URL
https://opencores.org/ocsvn/uart_fiber/uart_fiber/trunk
Subversion Repositories uart_fiber
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- This comparison shows the changes necessary to convert path
/uart_fiber
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/Version2/main.vhd
0,0 → 1,161
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library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.std_logic_unsigned.all; |
--use IEEE.NUMERIC_STD.ALL; |
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entity main is |
Port ( iCLK : in STD_LOGIC; |
RX : out STD_LOGIC; |
TX : in STD_LOGIC; |
optic_out : out STD_LOGIC; |
optic_in : in STD_LOGIC; |
setting : in STD_LOGIC_VECTOR(1 downto 0) |
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--baud_div1 : in STD_LOGIC_VECTOR(3 downto 0); |
--period1 : in STD_LOGIC_VECTOR(3 downto 0) |
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--RX2 : out STD_LOGIC; |
--TX2 : in STD_LOGIC; |
--optic_out2 : out STD_LOGIC; |
--optic_in2 : in STD_LOGIC; |
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--led1 : out STD_LOGIC; |
--led2 : out STD_LOGIC; |
--led3 : out STD_LOGIC; |
--led4 : out STD_LOGIC |
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); |
end main; |
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architecture Behavioral of main is |
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COMPONENT TX_to_spdif_full |
PORT( |
iCLK : IN std_logic; |
TX : IN std_logic; |
OPTIC_OUT : OUT std_logic; |
period01 : in STD_LOGIC_VECTOR(6 downto 0); |
periodA : in STD_LOGIC_VECTOR(6 downto 0); |
period10 : in STD_LOGIC_VECTOR(6 downto 0); |
period : in STD_LOGIC_VECTOR(6 downto 0); |
baud_div : in STD_LOGIC_VECTOR(6 downto 0) |
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); |
END COMPONENT; |
COMPONENT spdif_to_RX |
PORT( |
iCLK : IN std_logic; |
OPTIC_IN : IN std_logic; |
RX : OUT std_logic; |
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periodA : in STD_LOGIC_VECTOR(6 downto 0); |
period10 : in STD_LOGIC_VECTOR(6 downto 0) |
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); |
END COMPONENT; |
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COMPONENT q_period is |
PORT ( period : in STD_LOGIC_VECTOR (6 downto 0); |
period01 : out STD_LOGIC_VECTOR (6 downto 0); |
periodA : out STD_LOGIC_VECTOR (6 downto 0); |
period10 : out STD_LOGIC_VECTOR (6 downto 0) |
); |
END COMPONENT; |
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--signal nled1 : STD_LOGIC_VECTOR(3 downto 0); |
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--constant period : STD_LOGIC_VECTOR(6 downto 0) := ('0','1','0','1','0','0','0'); --40 |
--constant baud_div : STD_LOGIC_VECTOR(6 downto 0) := ('0','0','0','1','0','0','0'); --1 |
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signal period01 :STD_LOGIC_VECTOR(6 downto 0); |
signal periodA :STD_LOGIC_VECTOR(6 downto 0); |
signal period10 :STD_LOGIC_VECTOR(6 downto 0); |
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signal period : STD_LOGIC_VECTOR(6 downto 0);--normally 40 |
signal baud_div : STD_LOGIC_VECTOR(6 downto 0);--normally 1 |
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begin |
--led1<=not nled1(3); |
--led2<=not nled1(2); |
--led3<=not nled1(1); |
--led4<=not nled1(0); |
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--period<=((6 downto 4=>'0')&period1); |
--baud_div<=((6 downto 4=>'0')&baud_div1); |
process |
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begin |
if(setting=('0','0'))then |
period<=('0','1','0','1','0','0','0'); |
--period<=to_stdlogicvector("40"); |
baud_div<=('0','0','0','0','0','0','1'); |
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elsif (setting=('0','0'))then |
period<=('0','1','0','0','0','0','1'); |
baud_div<=('0','0','0','0','0','1','0'); |
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elsif (setting=('0','0'))then |
period<=('0','1','0','0','1','0','0'); |
baud_div<=('0','0','1','0','0','0','0'); |
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else |
period<=('0','1','0','0','0','1','0'); |
baud_div<=('0','0','0','1','1','1','0'); |
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end if; |
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end process; |
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q_period_inst:q_period |
Port map (period=>period, |
period01=>period01, |
periodA=>periodA, |
period10=>period10 |
); |
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TX_to_spdif_full_inst:TX_to_spdif_full |
Port map ( iCLK=> iCLK, |
TX => TX, |
optic_out => optic_out, |
period01=>period01, |
periodA=>periodA, |
period10=>period10, |
period=>period, |
baud_div=>baud_div |
); |
spdif_to_RX_inst:spdif_to_RX |
Port map ( iCLK=>iCLK, |
optic_in => optic_in, |
RX => RX, |
periodA=>periodA, |
period10=>period10 |
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); |
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end Behavioral; |
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