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URL https://opencores.org/ocsvn/uart_observer/uart_observer/trunk

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Rev 2 → Rev 3

/trunk/verilog/uart.v File deleted
/trunk/verilog/uart_observer.v
12,10 → 12,10
 
module uart_observer (
// clock, tested with 90 MHZ clock
input clk,
input CLK_I,
 
// The array of observables.
input wire [BITS-1:0] observables,
input wire [BITS-1:0] DAT_I,
// UART
input CTS, // "clear to send"
203,7 → 203,7
end
endtask
always @(posedge clk)
always @(posedge CLK_I)
begin :cl
// Need 781.25 (90000000 Hz to 115200 Hz)
if (divider > DIV_MAX)
210,7 → 210,7
begin
if (phase == 0 && ram_addr == 0)
begin
observables_reg = observables;
observables_reg = DAT_I;
if (observables_prev == observables_reg)
begin
r_reg <= 10'b1_1111_1111_1;
/trunk/verilog/uart_observer_demonstrator.v
0,0 → 1,110
/**
* Demonstrates the functionality of the UART observer. Shows the 64 bits of
* binary data that, in this demo, are derived from push buttons and dip switches on FPGA board.
*/
module uart_observer_demonstrator (
input USB_UART_TX_FPGA_RX_LS,
input USB_UART_CTS_I_B_LS,
input CLK_I,
input GPIO_SW_E,
input GPIO_SW_W,
input GPIO_SW_S,
input GPIO_SW_N,
input GPIO_SW_C,
input GPIO_DIP_SW0,
input GPIO_DIP_SW1,
input GPIO_DIP_SW2,
input GPIO_DIP_SW3,
 
output GPIO_LED_0,
output GPIO_LED_1,
output GPIO_LED_2,
output GPIO_LED_3,
output GPIO_LED_4,
output GPIO_LED_5,
output GPIO_LED_6,
output GPIO_LED_7,
output USB_UART_RX_FPGA_TX_LS,
output USB_UART_RTS_O_B_LS
);
 
// 64 bits we observe.
wire [63:0] observables;
 
// Observe the switches as example
// First byte
assign observables[0] = GPIO_SW_E;
assign observables[1] = GPIO_SW_W;
assign observables[2] = GPIO_SW_S;
assign observables[3] = GPIO_SW_N;
assign observables[4] = GPIO_SW_E;
assign observables[5] = GPIO_SW_W;
assign observables[6] = GPIO_SW_S;
assign observables[7] = GPIO_SW_N;
// Second
assign observables[8] = GPIO_SW_E;
assign observables[9] = GPIO_SW_W;
assign observables[10] = GPIO_SW_S;
assign observables[11] = GPIO_SW_N;
assign observables[12] = GPIO_SW_E;
assign observables[13] = GPIO_SW_W;
assign observables[14] = GPIO_SW_S;
assign observables[15] = GPIO_SW_N;
// Third
assign observables[16] = GPIO_DIP_SW0;
assign observables[17] = GPIO_DIP_SW1;
assign observables[18] = GPIO_DIP_SW2;
assign observables[19] = GPIO_DIP_SW3;
assign observables[20] = GPIO_DIP_SW3;
assign observables[21] = GPIO_DIP_SW2;
assign observables[22] = GPIO_DIP_SW1;
assign observables[23] = GPIO_DIP_SW0;
// Forth
assign observables[24] = GPIO_SW_E;
assign observables[25] = GPIO_SW_W;
assign observables[26] = GPIO_SW_S;
assign observables[27] = GPIO_SW_N;
assign observables[28] = GPIO_SW_E;
assign observables[29] = GPIO_SW_W;
assign observables[30] = GPIO_SW_S;
assign observables[31] = GPIO_SW_N;
assign observables[63] = GPIO_SW_C;
uart_observer #(.CLOCK_FREQ (90_000_000), .BAUDS(921600), .BITS(64) )
U0(
// Clock
.CLK_I(CLK_I),
// Values to observer
.DAT_I(observables),
// UART
.TXD(USB_UART_RX_FPGA_TX_LS), // data
.RTS(USB_UART_RTS_O_B_LS), // request to send
.CTS(USB_UART_CTS_I_B_LS) // clear to send
);
 
assign GPIO_LED_0 = observables[0];
assign GPIO_LED_1 = observables[1];
assign GPIO_LED_2 = observables[2];
assign GPIO_LED_3 = observables[3];
assign GPIO_LED_4 = observables[4];
endmodule
/trunk/xdc/xtra.xdc File deleted
/trunk/xdc/uart.xdc File deleted
/trunk/xdc/KCU116.xdc
0,0 → 1,77
# W12 RX Input LVCMOS18 USB_UART_TX 21 TXD Output
# W13 TX Output LVCMOS18 USB_UART_RX 20 RXD Input
# Y13 CTS Output LVCMOS18 USB_UART_CTS 18 CTS Input
# AA13 RTS Input LVCMOS18 USB_UART_RTS 19 RTS Output
 
#USB UART
set_property PACKAGE_PIN W13 [get_ports USB_UART_RX_FPGA_TX_LS]
set_property IOSTANDARD LVCMOS33 [get_ports USB_UART_RX_FPGA_TX_LS]
 
set_property PACKAGE_PIN W12 [get_ports USB_UART_TX_FPGA_RX_LS]
set_property IOSTANDARD LVCMOS33 [get_ports USB_UART_TX_FPGA_RX_LS]
 
set_property PACKAGE_PIN AA13 [get_ports USB_UART_RTS_O_B_LS]
set_property IOSTANDARD LVCMOS33 [get_ports USB_UART_RTS_O_B_LS]
 
set_property PACKAGE_PIN Y13 [get_ports USB_UART_CTS_I_B_LS]
set_property IOSTANDARD LVCMOS33 [get_ports USB_UART_CTS_I_B_LS]
 
#GPIO
 
#GPIO PB SWITCHES
set_property PACKAGE_PIN B11 [get_ports GPIO_SW_E]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_SW_E]
set_property PACKAGE_PIN A10 [get_ports GPIO_SW_N]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_SW_N]
set_property PACKAGE_PIN B10 [get_ports GPIO_SW_W]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_SW_W]
set_property PACKAGE_PIN A9 [get_ports GPIO_SW_C]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_SW_C]
set_property PACKAGE_PIN C11 [get_ports GPIO_SW_S]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_SW_S]
 
#GPIO DIP SWITCHES
set_property PACKAGE_PIN G11 [get_ports "GPIO_DIP_SW0"] ;
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW0"] ;
set_property PACKAGE_PIN H11 [get_ports "GPIO_DIP_SW1"] ;
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW1"] ;
set_property PACKAGE_PIN H9 [get_ports "GPIO_DIP_SW2"] ;
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW2"] ;
set_property PACKAGE_PIN J9 [get_ports "GPIO_DIP_SW3"] ;
set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW3"] ;
 
# LEDs
#GPIO LEDs
set_property PACKAGE_PIN C9 [get_ports GPIO_LED_0]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_0]
set_property PACKAGE_PIN D9 [get_ports GPIO_LED_1]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_1]
set_property PACKAGE_PIN E10 [get_ports GPIO_LED_2]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_2]
set_property PACKAGE_PIN E11 [get_ports GPIO_LED_3]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_3]
set_property PACKAGE_PIN F9 [get_ports GPIO_LED_4]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_4]
set_property PACKAGE_PIN F10 [get_ports GPIO_LED_5]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_5]
set_property PACKAGE_PIN G9 [get_ports GPIO_LED_6]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_6]
set_property PACKAGE_PIN G10 [get_ports GPIO_LED_7]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_7]
 
#CLOCKS
 
#create_clock -period 1000000.000 -name AM_CLOCK -waveform {0.000 500000.000} [get_ports CLK_125_P]
 
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets *]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets *]
 
# Forum clock (90.0 MHz single-ended 1.8V LVCMOS, series resistor coupled FPGA_EMCCLK, connected to XCKU5P FPGA U1 bank 65 dedicated EMCCLK input pin N21), works posedge
set_property PACKAGE_PIN N21 [get_ports CLK_I]
set_property IOSTANDARD LVCMOS18 [get_ports CLK_I]
 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_I_IBUF_inst/O]
 
create_clock -period 11.111 -name CLK_I -waveform {0.000 5.556} [get_ports CLK_I]
 
 

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