URL
https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk
Subversion Repositories udp_ip_stack
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/udp_ip_stack/tags/v2.0/rtl/vhdl/ml605
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Rev 10 → Rev 12
/IP_complete.vhd
0,0 → 1,272
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Peter Fall |
-- |
-- Create Date: 20:25:56 06/03/2011 |
-- Design Name: |
-- Module Name: IP_complete - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: Implements complete IP stack with ARP and MAC |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.axi.all; |
use work.ipv4_types.all; |
use work.arp_types.all; |
|
entity IP_complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
ip_tx : in ipv4_tx_type; -- IP tx cxns |
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission) |
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data |
ip_rx_start : out std_logic; -- indicates receipt of ip frame. |
ip_rx : out ipv4_rx_type; |
-- system signals |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
clk_out : out std_logic; |
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
-- GMII Interface |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end IP_complete; |
|
architecture structural of IP_complete is |
|
------------------------------------------------------------------------------ |
-- Component Declaration for the IP layer |
------------------------------------------------------------------------------ |
|
COMPONENT IP_complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- IP Layer signals |
ip_tx_start : in std_logic; |
ip_tx : in ipv4_tx_type; -- IP tx cxns |
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission) |
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data |
ip_rx_start : out std_logic; -- indicates receipt of ip frame. |
ip_rx : out ipv4_rx_type; |
-- system signals |
rx_clk : in STD_LOGIC; |
tx_clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in ip_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
-- MAC Transmitter |
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx |
mac_tx_tvalid : out std_logic; -- tdata is valid |
mac_tx_tready : in std_logic; -- mac is ready to accept data |
mac_tx_tfirst : out std_logic; -- indicates first byte of frame |
mac_tx_tlast : out std_logic; -- indicates last byte of frame |
-- MAC Receiver |
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received |
mac_rx_tvalid : in std_logic; -- indicates tdata is valid |
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : in std_logic -- indicates last byte of the trame |
); |
END COMPONENT; |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the MAC layer |
------------------------------------------------------------------------------ |
component mac_layer_v2_1 |
port ( |
-- System controls |
------------------ |
glbl_rst : in std_logic; -- asynchronous reset |
mac_reset : in std_logic; -- reset mac layer |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
|
-- MAC Transmitter (AXI-S) Interface |
--------------------------------------------- |
mac_tx_clock : out std_logic; -- data sampled on rising edge |
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx |
mac_tx_tvalid : in std_logic; -- tdata is valid |
mac_tx_tready : out std_logic; -- mac is ready to accept data |
mac_tx_tlast : in std_logic; -- indicates last byte of frame |
|
-- MAC Receiver (AXI-S) Interface |
------------------------------------------ |
mac_rx_clock : out std_logic; -- data valid on rising edge |
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received |
mac_rx_tvalid : out std_logic; -- indicates tdata is valid |
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : out std_logic; -- indicates last byte of the trame |
|
-- GMII Interface |
----------------- |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end component; |
|
--------------------------- |
-- Signals |
--------------------------- |
|
-- MAC RX bus |
signal mac_rx_clock : std_logic; |
signal mac_rx_tdata : std_logic_vector (7 downto 0); |
signal mac_rx_tvalid : std_logic; |
signal mac_rx_tready : std_logic; |
signal mac_rx_tlast : std_logic; |
-- MAC TX bus |
signal mac_tx_clock : std_logic; |
signal mac_tx_tdata : std_logic_vector (7 downto 0); |
signal mac_tx_tvalid : std_logic; |
signal mac_tx_tready : std_logic; |
signal mac_tx_tlast : std_logic; |
-- control signals |
signal mac_tx_tready_int : std_logic; |
signal mac_tx_granted_int : std_logic; |
|
begin |
|
clk_out <= mac_rx_clock; |
|
------------------------------------------------------------------------------ |
-- Instantiate the IP layer |
------------------------------------------------------------------------------ |
|
IP_layer : IP_complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
PORT MAP ( |
-- IP Layer signals |
ip_tx_start => ip_tx_start, |
ip_tx => ip_tx, |
ip_tx_result => ip_tx_result, |
ip_tx_data_out_ready => ip_tx_data_out_ready, |
ip_rx_start => ip_rx_start, |
ip_rx => ip_rx, |
-- system signals |
rx_clk => mac_rx_clock, |
tx_clk => mac_rx_clock, |
reset => reset, |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
control => control, |
-- status signals |
arp_pkt_count => arp_pkt_count, |
ip_pkt_count => ip_pkt_count, |
-- MAC Transmitter |
mac_tx_tready => mac_tx_tready_int, |
mac_tx_tvalid => mac_tx_tvalid, |
mac_tx_tfirst => open, |
mac_tx_tlast => mac_tx_tlast, |
mac_tx_tdata => mac_tx_tdata, |
-- MAC Receiver |
mac_rx_tdata => mac_rx_tdata, |
mac_rx_tvalid => mac_rx_tvalid, |
mac_rx_tready => mac_rx_tready, |
mac_rx_tlast => mac_rx_tlast |
); |
|
|
------------------------------------------------------------------------------ |
-- Instantiate the MAC layer |
------------------------------------------------------------------------------ |
mac_block : mac_layer_v2_1 |
Port map( |
-- System controls |
------------------ |
glbl_rst => reset, |
mac_reset => '0', |
clk_in_p => clk_in_p, |
clk_in_n => clk_in_n, |
|
-- MAC Transmitter (AXI-S) Interface |
--------------------------------------------- |
mac_tx_clock => mac_tx_clock, |
mac_tx_tdata => mac_tx_tdata, |
mac_tx_tvalid => mac_tx_tvalid, |
mac_tx_tready => mac_tx_tready_int, |
mac_tx_tlast => mac_tx_tlast, |
|
-- MAC Receiver (AXI-S) Interface |
------------------------------------------ |
mac_rx_clock => mac_rx_clock, |
mac_rx_tdata => mac_rx_tdata, |
mac_rx_tvalid => mac_rx_tvalid, |
mac_rx_tready => mac_rx_tready, |
mac_rx_tlast => mac_rx_tlast, |
|
-- GMII Interface |
----------------- |
phy_resetn => phy_resetn, |
gmii_txd => gmii_txd, |
gmii_tx_en => gmii_tx_en, |
gmii_tx_er => gmii_tx_er, |
gmii_tx_clk => gmii_tx_clk, |
gmii_rxd => gmii_rxd, |
gmii_rx_dv => gmii_rx_dv, |
gmii_rx_er => gmii_rx_er, |
gmii_rx_clk => gmii_rx_clk, |
gmii_col => gmii_col, |
gmii_crs => gmii_crs, |
mii_tx_clk => mii_tx_clk |
); |
|
end structural; |
|
/UDP_Complete.vhd
0,0 → 1,296
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 17:51:18 06/11/2011 |
-- Design Name: |
-- Module Name: UDP_Complete - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.02 - separated RX and TX clocks |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.axi.all; |
use work.ipv4_types.all; |
use work.arp_types.all; |
|
entity UDP_Complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
udp_txi : in udp_tx_type; -- UDP tx cxns |
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission) |
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data |
-- UDP RX signals |
udp_rx_start : out std_logic; -- indicates receipt of udp header |
udp_rxo : out udp_rx_type; |
-- IP RX signals |
ip_rx_hdr : out ipv4_rx_header_type; |
-- system signals |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
clk_out : out std_logic; |
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
-- GMII Interface |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end UDP_Complete; |
|
|
|
|
architecture structural of UDP_Complete is |
|
------------------------------------------------------------------------------ |
-- Component Declaration for UDP complete no mac |
------------------------------------------------------------------------------ |
|
COMPONENT UDP_Complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
udp_txi : in udp_tx_type; -- UDP tx cxns |
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission) |
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data |
-- UDP RX signals |
udp_rx_start : out std_logic; -- indicates receipt of udp header |
udp_rxo : out udp_rx_type; |
-- IP RX signals |
ip_rx_hdr : out ipv4_rx_header_type; |
-- system signals |
rx_clk : in STD_LOGIC; |
tx_clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
-- MAC Transmitter |
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx |
mac_tx_tvalid : out std_logic; -- tdata is valid |
mac_tx_tready : in std_logic; -- mac is ready to accept data |
mac_tx_tfirst : out std_logic; -- indicates first byte of frame |
mac_tx_tlast : out std_logic; -- indicates last byte of frame |
-- MAC Receiver |
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received |
mac_rx_tvalid : in std_logic; -- indicates tdata is valid |
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : in std_logic -- indicates last byte of the trame |
); |
END COMPONENT; |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the MAC layer |
------------------------------------------------------------------------------ |
component mac_v2_2 |
-- component xv6mac_straight |
port ( |
-- System controls |
------------------ |
glbl_rst : in std_logic; -- asynchronous reset |
mac_reset : in std_logic; -- reset mac layer |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
|
-- MAC Transmitter (AXI-S) Interface |
--------------------------------------------- |
mac_tx_clock : out std_logic; -- data sampled on rising edge |
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx |
mac_tx_tvalid : in std_logic; -- tdata is valid |
mac_tx_tready : out std_logic; -- mac is ready to accept data |
mac_tx_tlast : in std_logic; -- indicates last byte of frame |
|
-- MAC Receiver (AXI-S) Interface |
------------------------------------------ |
mac_rx_clock : out std_logic; -- data valid on rising edge |
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received |
mac_rx_tvalid : out std_logic; -- indicates tdata is valid |
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : out std_logic; -- indicates last byte of the trame |
|
-- GMII Interface |
----------------- |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end component; |
|
|
--------------------------- |
-- Signals |
--------------------------- |
|
-- MAC RX bus |
signal mac_rx_clock : std_logic; |
signal mac_rx_tdata : std_logic_vector (7 downto 0); |
signal mac_rx_tvalid : std_logic; |
signal mac_rx_tready : std_logic; |
signal mac_rx_tlast : std_logic; |
-- MAC TX bus |
signal mac_tx_clock : std_logic; |
signal mac_tx_tdata : std_logic_vector (7 downto 0); |
signal mac_tx_tvalid : std_logic; |
signal mac_tx_tready : std_logic; |
signal mac_tx_tlast : std_logic; |
-- control signals |
signal mac_tx_tready_int : std_logic; |
signal mac_tx_granted_int : std_logic; |
|
|
begin |
|
|
process (mac_tx_clock) |
begin |
-- output followers |
clk_out <= mac_tx_clock; |
end process; |
|
------------------------------------------------------------------------------ |
-- Instantiate the UDP layer |
------------------------------------------------------------------------------ |
|
udp_block: UDP_Complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
PORT MAP ( |
-- UDP TX signals |
udp_tx_start => udp_tx_start, |
udp_txi => udp_txi, |
udp_tx_result => udp_tx_result, |
udp_tx_data_out_ready => udp_tx_data_out_ready, |
-- UDP RX signals |
udp_rx_start => udp_rx_start, |
udp_rxo => udp_rxo, |
-- IP RX signals |
ip_rx_hdr => ip_rx_hdr, |
-- system signals |
rx_clk => mac_rx_clock, |
tx_clk => mac_tx_clock, |
reset => reset, |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
-- status signals |
arp_pkt_count => arp_pkt_count, |
ip_pkt_count => ip_pkt_count, |
control => control, |
-- MAC Transmitter |
mac_tx_tready => mac_tx_tready_int, |
mac_tx_tvalid => mac_tx_tvalid, |
mac_tx_tfirst => open, |
mac_tx_tlast => mac_tx_tlast, |
mac_tx_tdata => mac_tx_tdata, |
-- MAC Receiver |
mac_rx_tdata => mac_rx_tdata, |
mac_rx_tvalid => mac_rx_tvalid, |
mac_rx_tready => mac_rx_tready, |
mac_rx_tlast => mac_rx_tlast |
); |
|
|
------------------------------------------------------------------------------ |
-- Instantiate the MAC layer |
------------------------------------------------------------------------------ |
mac_block : mac_v2_2 |
-- mac_block : xv6mac_straight |
Port map( |
-- System controls |
------------------ |
glbl_rst => reset, |
mac_reset => '0', |
clk_in_p => clk_in_p, |
clk_in_n => clk_in_n, |
|
-- MAC Transmitter (AXI-S) Interface |
--------------------------------------------- |
mac_tx_clock => mac_tx_clock, |
mac_tx_tdata => mac_tx_tdata, |
mac_tx_tvalid => mac_tx_tvalid, |
mac_tx_tready => mac_tx_tready_int, |
mac_tx_tlast => mac_tx_tlast, |
|
-- MAC Receiver (AXI-S) Interface |
------------------------------------------ |
mac_rx_clock => mac_rx_clock, |
mac_rx_tdata => mac_rx_tdata, |
mac_rx_tvalid => mac_rx_tvalid, |
mac_rx_tready => mac_rx_tready, |
mac_rx_tlast => mac_rx_tlast, |
|
-- GMII Interface |
----------------- |
phy_resetn => phy_resetn, |
gmii_txd => gmii_txd, |
gmii_tx_en => gmii_tx_en, |
gmii_tx_er => gmii_tx_er, |
gmii_tx_clk => gmii_tx_clk, |
gmii_rxd => gmii_rxd, |
gmii_rx_dv => gmii_rx_dv, |
gmii_rx_er => gmii_rx_er, |
gmii_rx_clk => gmii_rx_clk, |
gmii_col => gmii_col, |
gmii_crs => gmii_crs, |
mii_tx_clk => mii_tx_clk |
); |
|
|
end structural; |
|
|
/UDP_integration_example.vhd
0,0 → 1,490
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 11:01:00 06/11/2011 |
-- Design Name: |
-- Module Name: UDP_integration_example - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.axi.all; |
use work.ipv4_types.all; |
use work.arp_types.all; |
|
entity UDP_integration_example is |
port ( |
-- System signals |
------------------ |
reset : in std_logic; -- asynchronous reset |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
|
-- System controls |
------------------ |
PBTX : in std_logic; |
PB_DO_SECOND_TX : in std_logic; |
DO_SECOND_TX_LED : out std_logic; |
UDP_RX : out std_logic; |
UDP_Start : out std_logic; |
PBTX_LED : out std_logic; |
TX_Started : out std_logic; |
TX_Completed : out std_logic; |
TX_RSLT_0 : out std_logic; |
TX_RSLT_1 : out std_logic; |
reset_leds : in std_logic; |
display : out std_logic_vector(7 downto 0); |
|
-- GMII Interface |
----------------- |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end UDP_integration_example; |
|
architecture Behavioral of UDP_integration_example is |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the complete UDP layer |
------------------------------------------------------------------------------ |
component UDP_Complete |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
udp_tx_start : in std_logic; -- indicates req to tx UDP |
udp_txi : in udp_tx_type; -- UDP tx cxns |
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission) |
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data |
-- UDP RX signals |
udp_rx_start : out std_logic; -- indicates receipt of udp header |
udp_rxo : out udp_rx_type; |
-- IP RX signals |
ip_rx_hdr : out ipv4_rx_header_type; |
-- system signals |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
clk_out : out std_logic; |
reset : in STD_LOGIC; |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
our_mac_address : in std_logic_vector (47 downto 0); |
control : in udp_control_type; |
-- status signals |
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us |
-- GMII Interface |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end component; |
|
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp; |
|
|
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR); |
type count_mode_type is (RST, INCR, HOLD); |
type set_clr_type is (SET, CLR, HOLD); |
type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD); |
|
-- system signals |
signal clk_int : std_logic; |
signal our_mac : STD_LOGIC_VECTOR (47 downto 0); |
signal our_ip : STD_LOGIC_VECTOR (31 downto 0); |
signal udp_tx_int : udp_tx_type; |
signal udp_tx_result_int : std_logic_vector (1 downto 0); |
signal udp_tx_data_out_ready_int : std_logic; |
signal udp_rx_int : udp_rx_type; |
signal udp_tx_start_int : std_logic; |
signal udp_rx_start_int : std_logic; |
signal arp_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0); |
signal ip_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0); |
signal ip_rx_hdr_int : ipv4_rx_header_type; |
|
-- state signals |
signal state : state_type; |
signal count : unsigned (7 downto 0); |
signal tx_hdr : udp_tx_header_type; |
signal tx_start_reg : std_logic; |
signal tx_started_reg : std_logic; |
signal tx_fin_reg : std_logic; |
signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first |
signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx |
|
-- control signals |
signal next_state : state_type; |
signal set_state : std_logic; |
signal set_count : count_mode_type; |
signal set_hdr : std_logic; |
signal set_tx_start : set_clr_type; |
signal set_last : std_logic; |
signal set_tx_started : set_clr_type; |
signal set_tx_fin : set_clr_type; |
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0); |
signal control_int : udp_control_type; |
signal set_second_tx : sec_tx_ctrl_type; |
|
begin |
|
process ( |
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, |
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int, |
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx, |
PB_DO_SECOND_TX, do_second_tx |
) |
begin |
-- set up our local addresses and default controls |
our_ip <= x"c0a80019"; -- 192.168.0.25 |
our_mac <= x"002320212223"; |
control_int.ip_controls.arp_controls.clear_cache <= '0'; |
|
-- determine RX good and error LEDs |
if udp_rx_int.hdr.is_valid = '1' then |
UDP_RX <= '1'; |
else |
UDP_RX <= '0'; |
end if; |
|
UDP_Start <= udp_rx_start_int; |
TX_Started <= tx_start_reg; --tx_started_reg; |
TX_Completed <= tx_fin_reg; |
TX_RSLT_0 <= udp_tx_result_int(0); |
TX_RSLT_1 <= udp_tx_result_int(1); |
DO_SECOND_TX_LED <= prime_second_tx; |
|
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0 |
display (7 downto 4) <= ip_pkt_count_int (3 downto 0); |
|
-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0); |
case state is |
when IDLE => display (3 downto 0) <= "0001"; |
when WAIT_RX_DONE => display (3 downto 0) <= "0010"; |
when DATA_OUT => display (3 downto 0) <= "0011"; |
when PAUSE => display (3 downto 0) <= "0100"; |
when CHECK_SECOND_TX => display (3 downto 0) <= "0101"; |
when SET_SEC_HDR => display (3 downto 0) <= "0110"; |
end case; |
|
end process; |
|
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received. |
|
-- TX response process - COMB |
tx_proc_combinatorial: process( |
-- inputs |
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int, |
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX, |
-- state |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx, |
-- controls |
next_state, set_state, set_count, set_hdr, set_tx_start, set_last, |
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx |
) |
begin |
-- set output_followers |
udp_tx_int.hdr <= tx_hdr; |
udp_tx_int.data.data_out_last <= set_last; |
udp_tx_start_int <= tx_start_reg; |
|
-- set control signal defaults |
next_state <= IDLE; |
set_state <= '0'; |
set_count <= HOLD; |
set_hdr <= '0'; |
set_tx_start <= HOLD; |
set_last <= '0'; |
set_tx_started <= HOLD; |
set_tx_fin <= HOLD; |
first_byte_rx <= (others => '0'); |
udp_tx_int.data.data_out <= (others => '0'); |
udp_tx_int.data.data_out_valid <= '0'; |
set_second_tx <= HOLD; |
|
if PB_DO_SECOND_TX = '1' then |
set_second_tx <= PRIME; |
end if; |
|
-- FSM |
case state is |
|
when IDLE => |
udp_tx_int.data.data_out_valid <= '0'; |
if udp_rx_start_int = '1' or PBTX = '1' then |
if udp_rx_start_int = '1' then |
first_byte_rx <= udp_rx_int.data.data_in; |
else |
first_byte_rx <= x"00"; |
end if; |
set_tx_fin <= CLR; |
set_count <= RST; |
set_hdr <= '1'; |
if udp_rx_int.data.data_in_last = '1' then |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
else |
next_state <= WAIT_RX_DONE; |
set_state <= '1'; |
end if; |
end if; |
|
when WAIT_RX_DONE => |
-- wait until RX pkt fully received |
if udp_rx_int.data.data_in_last = '1' then |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
end if; |
|
when DATA_OUT => |
if udp_tx_result_int = UDPTX_RESULT_ERR then |
-- have an error from the IP TX layer, clear down the TX |
set_tx_start <= CLR; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
set_second_tx <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
if udp_tx_result_int = UDPTX_RESULT_SENDING then |
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending |
end if; |
if ip_rx_hdr_int.is_broadcast = '1' then |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50"; |
else |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40"; |
end if; |
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int; |
if udp_tx_data_out_ready_int = '1' then |
if unsigned(count) = x"03" then |
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= PAUSE; |
set_state <= '1'; |
else |
set_count <= INCR; |
end if; |
end if; |
end if; |
|
when PAUSE => |
next_state <= CHECK_SECOND_TX; |
set_state <= '1'; |
|
|
when CHECK_SECOND_TX => |
if prime_second_tx = '1' then |
set_second_tx <= DO; |
next_state <= SET_SEC_HDR; |
set_state <= '1'; |
else |
set_second_tx <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
end if; |
|
when SET_SEC_HDR => |
set_hdr <= '1'; |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
|
end case; |
end process; |
|
|
|
-- TX response process - SEQ |
tx_proc_sequential: process(clk_int) |
begin |
if rising_edge(clk_int) then |
if reset = '1' then |
-- reset state variables |
state <= IDLE; |
count <= x"00"; |
tx_start_reg <= '0'; |
tx_hdr.dst_ip_addr <= (others => '0'); |
tx_hdr.dst_port <= (others => '0'); |
tx_hdr.src_port <= (others => '0'); |
tx_hdr.data_length <= (others => '0'); |
tx_hdr.checksum <= (others => '0'); |
tx_started_reg <= '0'; |
tx_fin_reg <= '0'; |
PBTX_LED <= '0'; |
do_second_tx <= '0'; |
prime_second_tx <= '0'; |
else |
PBTX_LED <= PBTX; |
|
-- Next rx_state processing |
if set_state = '1' then |
state <= next_state; |
else |
state <= state; |
end if; |
|
-- count processing |
case set_count is |
when RST => count <= x"00"; |
when INCR => count <= count + 1; |
when HOLD => count <= count; |
end case; |
|
-- set tx hdr |
if set_hdr = '1' then |
-- select the dst addr of the tx: |
-- if do_second_tx, to solaris box |
-- otherwise control according to first byte of received data: |
-- B = broadcast |
-- C = to dummy address to test timeout |
-- D to solaris box |
-- otherwise, direct to sender |
if do_second_tx = '1' then |
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5 |
elsif first_byte_rx = x"42" then |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr |
elsif first_byte_rx = x"43" then |
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout |
elsif first_byte_rx = x"44" then |
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5 |
else |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender |
end if; |
tx_hdr.dst_port <= udp_rx_int.hdr.src_port; |
tx_hdr.src_port <= udp_rx_int.hdr.dst_port; |
tx_hdr.data_length <= x"0004"; |
tx_hdr.checksum <= x"0000"; |
else |
tx_hdr <= tx_hdr; |
end if; |
|
-- set tx start signal |
case set_tx_start is |
when SET => tx_start_reg <= '1'; |
when CLR => tx_start_reg <= '0'; |
when HOLD => tx_start_reg <= tx_start_reg; |
end case; |
|
-- set tx started signal |
case set_tx_started is |
when SET => tx_started_reg <= '1'; |
when CLR => tx_started_reg <= '0'; |
when HOLD => tx_started_reg <= tx_started_reg; |
end case; |
|
-- set tx finished signal |
case set_tx_fin is |
when SET => tx_fin_reg <= '1'; |
when CLR => tx_fin_reg <= '0'; |
when HOLD => tx_fin_reg <= tx_fin_reg; |
end case; |
|
-- set do_second_tx |
case set_second_tx is |
when PRIME => |
prime_second_tx <= '1'; |
when DO => |
prime_second_tx <= '0'; |
do_second_tx <= '1'; |
when CLR => |
prime_second_tx <= '0'; |
do_second_tx <= '0'; |
when HOLD => |
prime_second_tx <= prime_second_tx; |
do_second_tx <= do_second_tx; |
end case; |
|
end if; |
end if; |
|
end process; |
|
|
|
------------------------------------------------------------------------------ |
-- Instantiate the UDP layer |
------------------------------------------------------------------------------ |
UDP_block : UDP_Complete |
generic map ( |
ARP_TIMEOUT => 10 -- timeout in seconds |
) |
PORT MAP ( |
-- UDP interface |
udp_tx_start => udp_tx_start_int, |
udp_txi => udp_tx_int, |
udp_tx_result => udp_tx_result_int, |
udp_tx_data_out_ready=> udp_tx_data_out_ready_int, |
udp_rx_start => udp_rx_start_int, |
udp_rxo => udp_rx_int, |
-- IP RX signals |
ip_rx_hdr => ip_rx_hdr_int, |
-- System interface |
clk_in_p => clk_in_p, |
clk_in_n => clk_in_n, |
clk_out => clk_int, |
reset => reset, |
our_ip_address => our_ip, |
our_mac_address => our_mac, |
control => control_int, |
-- status signals |
arp_pkt_count => arp_pkt_count_int, |
ip_pkt_count => ip_pkt_count_int, |
-- GMII Interface |
----------------- |
phy_resetn => phy_resetn, |
gmii_txd => gmii_txd, |
gmii_tx_en => gmii_tx_en, |
gmii_tx_er => gmii_tx_er, |
gmii_tx_clk => gmii_tx_clk, |
gmii_rxd => gmii_rxd, |
gmii_rx_dv => gmii_rx_dv, |
gmii_rx_er => gmii_rx_er, |
gmii_rx_clk => gmii_rx_clk, |
gmii_col => gmii_col, |
gmii_crs => gmii_crs, |
mii_tx_clk => mii_tx_clk |
); |
|
|
end Behavioral; |
|
/xv6mac_straight.vhd
0,0 → 1,463
-------------------------------------------------------------------------------- |
-- Project : low latency UDP |
-- File : xv6mac_straight |
-- Version : 0.0 |
------------------------------------------------------------------------------- |
-- |
-- |
-- Description: This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs |
-- |
-- |
-- |
-- --------------------------------------------------------------------- |
-- | EXAMPLE DESIGN WRAPPER | |
-- | --------------------------------------------------------| |
-- | |FIFO BLOCK WRAPPER | |
-- | | | |
-- | | | |
-- | | -----------------------------------------| |
-- | | | BLOCK LEVEL WRAPPER | |
-- | | | --------------------- | |
-- | | | | V6 EMAC CORE | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | | --------- | |
-- | | |->|->----------->|--|--->| Tx Tx |--| |--->| |
-- | | | | | | AXI-S PHY | | | | |
-- | | | | | | I/F I/F | | | | |
-- | | | | | | | | PHY | | |
-- | | | | | | | | I/F | | |
-- | | | | | | | | | | |
-- | | | | | | Rx Rx | | | | |
-- | | | | | | AX)-S PHY | | | | |
-- | | |<-|<-------------|----| I/F I/F |<-| |<---| |
-- | | | | | | | --------- | |
-- | -------- | | --------------------- | |
-- | | | | |
-- | | -----------------------------------------| |
-- | --------------------------------------------------------| |
-- --------------------------------------------------------------------- |
-- |
-------------------------------------------------------------------------------- |
|
library unisim; |
use unisim.vcomponents.all; |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
|
entity xv6mac_straight is |
port ( |
-- System controls |
------------------ |
glbl_rst : in std_logic; -- asynchronous reset |
mac_reset : in std_logic; -- reset mac layer |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
|
-- MAC Transmitter (AXI-S) Interface |
--------------------------------------------- |
mac_tx_clock : out std_logic; -- data sampled on rising edge |
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx |
mac_tx_tvalid : in std_logic; -- tdata is valid |
mac_tx_tready : out std_logic; -- mac is ready to accept data |
mac_tx_tlast : in std_logic; -- indicates last byte of frame |
|
-- MAC Receiver (AXI-S) Interface |
------------------------------------------ |
mac_rx_clock : out std_logic; -- data valid on rising edge |
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received |
mac_rx_tvalid : out std_logic; -- indicates tdata is valid |
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : out std_logic; -- indicates last byte of the trame |
|
-- GMII Interface |
----------------- |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end xv6mac_straight; |
|
architecture wrapper of xv6mac_straight is |
|
------------------------------------------------------------------------------ |
-- Component declaration for the internal mac layer |
------------------------------------------------------------------------------ |
component mac_layer_v2_2_block |
port( |
gtx_clk : in std_logic; |
|
-- Receiver Interface |
---------------------------- |
rx_statistics_vector : out std_logic_vector(27 downto 0); |
rx_statistics_valid : out std_logic; |
|
rx_mac_aclk : out std_logic; |
rx_reset : out std_logic; |
rx_axis_mac_tdata : out std_logic_vector(7 downto 0); |
rx_axis_mac_tvalid : out std_logic; |
rx_axis_mac_tlast : out std_logic; |
rx_axis_mac_tuser : out std_logic; |
|
-- Transmitter Interface |
------------------------------- |
tx_ifg_delay : in std_logic_vector(7 downto 0); |
tx_statistics_vector : out std_logic_vector(31 downto 0); |
tx_statistics_valid : out std_logic; |
|
tx_reset : out std_logic; |
tx_axis_mac_tdata : in std_logic_vector(7 downto 0); |
tx_axis_mac_tvalid : in std_logic; |
tx_axis_mac_tlast : in std_logic; |
tx_axis_mac_tuser : in std_logic; |
tx_axis_mac_tready : out std_logic; |
tx_collision : out std_logic; |
tx_retransmit : out std_logic; |
|
-- MAC Control Interface |
------------------------ |
pause_req : in std_logic; |
pause_val : in std_logic_vector(15 downto 0); |
|
-- Reference clock for IDELAYCTRL's |
refclk : in std_logic; |
|
-- GMII Interface |
----------------- |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
|
-- asynchronous reset |
----------------- |
glbl_rstn : in std_logic; |
rx_axi_rstn : in std_logic; |
tx_axi_rstn : in std_logic |
|
); |
end component; |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the Clock generator |
------------------------------------------------------------------------------ |
|
component clk_wiz_v2_2 |
port ( |
-- Clock in ports |
CLK_IN1_P : in std_logic; |
CLK_IN1_N : in std_logic; |
-- Clock out ports |
CLK_OUT1 : out std_logic; |
CLK_OUT2 : out std_logic; |
CLK_OUT3 : out std_logic; |
-- Status and control signals |
RESET : in std_logic; |
LOCKED : out std_logic |
); |
end component; |
|
|
------------------------------------------------------------------------------ |
-- Component declaration for the reset synchroniser |
------------------------------------------------------------------------------ |
component reset_sync_v2_2 |
port ( |
reset_in : in std_logic; -- Active high asynchronous reset |
enable : in std_logic; |
clk : in std_logic; -- clock to be sync'ed to |
reset_out : out std_logic -- "Synchronised" reset signal |
); |
end component; |
|
------------------------------------------------------------------------------ |
-- Component declaration for the synchroniser |
------------------------------------------------------------------------------ |
component sync_block_v2_2 |
port ( |
clk : in std_logic; |
data_in : in std_logic; |
data_out : out std_logic |
); |
end component; |
|
------------------------------------------------------------------------------ |
-- Constants used in this top level wrapper. |
------------------------------------------------------------------------------ |
constant BOARD_PHY_ADDR : std_logic_vector(7 downto 0) := "00000111"; |
|
|
------------------------------------------------------------------------------ |
-- internal signals used in this top level wrapper. |
------------------------------------------------------------------------------ |
|
-- example design clocks |
signal gtx_clk_bufg : std_logic; |
signal refclk_bufg : std_logic; |
signal rx_mac_aclk : std_logic; |
|
-- tx handshaking |
signal mac_tx_tready_int : std_logic; |
signal tx_full_reg : std_logic; |
signal tx_full_val : std_logic; |
signal tx_data_reg : std_logic_vector(7 downto 0); |
signal tx_last_reg : std_logic; |
signal set_tx_reg : std_logic; |
|
signal phy_resetn_int : std_logic; |
|
-- resets (and reset generation) |
signal local_chk_reset : std_logic; |
signal chk_reset_int : std_logic; |
signal chk_pre_resetn : std_logic := '0'; |
signal chk_resetn : std_logic := '0'; |
signal dcm_locked : std_logic; |
|
signal glbl_rst_int : std_logic; |
signal phy_reset_count : unsigned(5 downto 0); |
signal glbl_rst_intn : std_logic; |
|
-- pipeline register for RX signals |
signal rx_data_val : std_logic_vector(7 downto 0); |
signal rx_tvalid_val : std_logic; |
signal rx_tlast_val : std_logic; |
signal rx_data_reg : std_logic_vector(7 downto 0); |
signal rx_tvalid_reg : std_logic; |
signal rx_tlast_reg : std_logic; |
|
attribute keep : string; |
attribute keep of gtx_clk_bufg : signal is "true"; |
attribute keep of refclk_bufg : signal is "true"; |
attribute keep of mac_tx_tready_int : signal is "true"; |
attribute keep of tx_full_reg : signal is "true"; |
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------------------------------------------------------------------------------ |
-- Begin architecture |
------------------------------------------------------------------------------ |
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begin |
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combinatorial: process ( |
rx_data_reg, rx_tvalid_reg, rx_tlast_reg, |
mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg |
) |
begin |
-- output followers |
mac_rx_tdata <= rx_data_reg; |
mac_rx_tvalid <= rx_tvalid_reg; |
mac_rx_tlast <= rx_tlast_reg; |
mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int); -- if not full, we are ready to accept |
|
-- control defaults |
tx_full_val <= tx_full_reg; |
set_tx_reg <= '0'; |
|
-- tx handshaking logic |
if mac_tx_tvalid = '1' then |
tx_full_val <= '1'; |
set_tx_reg <= '1'; |
elsif mac_tx_tready_int = '1' then |
tx_full_val <= '0'; |
end if; |
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end process; |
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sequential: process(gtx_clk_bufg) |
begin |
if rising_edge(gtx_clk_bufg) then |
if chk_resetn = '0' then |
-- reset state variables |
rx_data_reg <= (others => '0'); |
rx_tvalid_reg <= '0'; |
rx_tlast_reg <= '0'; |
tx_full_reg <= '0'; |
tx_data_reg <= (others => '0'); |
tx_last_reg <= '0'; |
else |
-- register rx data |
rx_data_reg <= rx_data_val; |
rx_tvalid_reg <= rx_tvalid_val; |
rx_tlast_reg <= rx_tlast_val; |
|
-- process tx tvalid and tready |
tx_full_reg <= tx_full_val; |
if set_tx_reg = '1' then |
tx_data_reg <= mac_tx_tdata; |
tx_last_reg <= mac_tx_tlast; |
else |
tx_data_reg <= tx_data_reg; |
tx_last_reg <= tx_last_reg; |
end if; |
end if; |
end if; |
end process; |
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------------------------------------------------------------------------------ |
-- Instantiate the Tri-Mode EMAC Block wrapper |
------------------------------------------------------------------------------ |
v6emac_block : mac_layer_v2_2_block |
port map( |
gtx_clk => gtx_clk_bufg, |
|
-- Client Receiver Interface |
rx_statistics_vector => open, |
rx_statistics_valid => open, |
|
rx_mac_aclk => open, |
rx_reset => open, |
rx_axis_mac_tdata => rx_data_val, |
rx_axis_mac_tvalid => rx_tvalid_val, |
rx_axis_mac_tlast => rx_tlast_val, |
rx_axis_mac_tuser => open, |
|
-- Client Transmitter Interface |
tx_ifg_delay => x"00", |
tx_statistics_vector => open, |
tx_statistics_valid => open, |
|
tx_reset => open, |
tx_axis_mac_tdata => tx_data_reg, |
tx_axis_mac_tvalid => tx_full_reg, |
tx_axis_mac_tlast => tx_last_reg, |
tx_axis_mac_tuser => '0', |
tx_axis_mac_tready => mac_tx_tready_int, |
tx_collision => open, |
tx_retransmit => open, |
|
-- Flow Control |
pause_req => '0', |
pause_val => x"0000", |
|
-- Reference clock for IDELAYCTRL's |
refclk => refclk_bufg, |
|
-- GMII Interface |
gmii_txd => gmii_txd, |
gmii_tx_en => gmii_tx_en, |
gmii_tx_er => gmii_tx_er, |
gmii_tx_clk => gmii_tx_clk, |
gmii_rxd => gmii_rxd, |
gmii_rx_dv => gmii_rx_dv, |
gmii_rx_er => gmii_rx_er, |
gmii_rx_clk => gmii_rx_clk, |
|
-- asynchronous reset |
glbl_rstn => chk_resetn, |
rx_axi_rstn => '1', |
tx_axi_rstn => '1' |
); |
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------------------------------------------------------------------------------ |
-- Clock logic to generate required clocks from the 200MHz on board |
-- if 125MHz is available directly this can be removed |
------------------------------------------------------------------------------ |
clock_generator : clk_wiz_v2_2 |
port map ( |
-- Clock in ports |
CLK_IN1_P => clk_in_p, |
CLK_IN1_N => clk_in_n, |
-- Clock out ports |
CLK_OUT1 => gtx_clk_bufg, |
CLK_OUT2 => open, |
CLK_OUT3 => refclk_bufg, |
-- Status and control signals |
RESET => glbl_rst, |
LOCKED => dcm_locked |
); |
|
----------------- |
-- global reset |
glbl_reset_gen : reset_sync_v2_2 |
port map ( |
clk => gtx_clk_bufg, |
enable => dcm_locked, |
reset_in => glbl_rst, |
reset_out => glbl_rst_int |
); |
|
glbl_rst_intn <= not glbl_rst_int; |
|
-- generate the user side clocks |
mac_tx_clock <= gtx_clk_bufg; |
mac_rx_clock <= gtx_clk_bufg; |
|
------------------------------------------------------------------------------ |
-- Generate resets |
------------------------------------------------------------------------------ |
-- in each case the async reset is first captured and then synchronised |
|
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local_chk_reset <= glbl_rst or mac_reset; |
|
----------------- |
-- data check reset |
chk_reset_gen : reset_sync_v2_2 |
port map ( |
clk => gtx_clk_bufg, |
enable => dcm_locked, |
reset_in => local_chk_reset, |
reset_out => chk_reset_int |
); |
|
-- Create fully synchronous reset in the gtx clock domain. |
gen_chk_reset : process (gtx_clk_bufg) |
begin |
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then |
if chk_reset_int = '1' then |
chk_pre_resetn <= '0'; |
chk_resetn <= '0'; |
else |
chk_pre_resetn <= '1'; |
chk_resetn <= chk_pre_resetn; |
end if; |
end if; |
end process gen_chk_reset; |
|
|
----------------- |
-- PHY reset |
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles |
-- this is derived using the 125MHz available and a 6 bit counter |
gen_phy_reset : process (gtx_clk_bufg) |
begin |
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then |
if glbl_rst_intn = '0' then |
phy_resetn_int <= '0'; |
phy_reset_count <= (others => '0'); |
else |
if phy_reset_count /= "111111" then |
phy_reset_count <= phy_reset_count + "000001"; |
else |
phy_resetn_int <= '1'; |
end if; |
end if; |
end if; |
end process gen_phy_reset; |
|
phy_resetn <= phy_resetn_int; |
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end wrapper; |
/udp_constraints.ucf
0,0 → 1,83
CONFIG PART = xc6vlx240tff1156-1; |
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########## ML605 Board ########## |
NET clk_in_p LOC = J9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE; |
NET clk_in_n LOC = H9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE; |
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Net reset LOC = H10 |IOSTANDARD = LVCMOS15 |TIG; |
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# downgrade the Place:1153 error in the mapper |
NET "reset" CLOCK_DEDICATED_ROUTE = FALSE; |
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#### Module LEDs_8Bit constraints |
NET "display[0]" LOC = AC22; |
NET "display[1]" LOC = AC24; |
NET "display[2]" LOC = AE22; |
NET "display[3]" LOC = AE23; |
NET "display[4]" LOC = AB23; |
NET "display[5]" LOC = AG23; |
NET "display[6]" LOC = AE24; |
NET "display[7]" LOC = AD24; |
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NET PBTX_LED LOC = AD21; |
NET UDP_RX LOC = AH27; |
NET DO_SECOND_TX_LED LOC = AH28; |
NET TX_RSLT_0 LOC = AE21; |
NET TX_RSLT_1 LOC = AP24; |
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#### Module Push_Buttons_4Bit constraints |
NET PBTX LOC = H17; |
NET PB_DO_SECOND_TX LOC = A18; |
NET reset_leds LOC = G26; |
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#### Module DIP_Switches_4Bit constraints |
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Net phy_resetn LOC = AH13 |IOSTANDARD = LVCMOS25 |TIG; |
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Net gmii_rxd<7> LOC = AC13 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<6> LOC = AC12 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<5> LOC = AD11 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<4> LOC = AM12 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<3> LOC = AN12 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<2> LOC = AE14 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<1> LOC = AF14 |IOSTANDARD = LVCMOS25; |
Net gmii_rxd<0> LOC = AN13 |IOSTANDARD = LVCMOS25; |
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Net gmii_txd<7> LOC = AF11 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<6> LOC = AE11 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<5> LOC = AM10 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<4> LOC = AL10 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<3> LOC = AG11 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<2> LOC = AG10 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<1> LOC = AL11 |IOSTANDARD = LVCMOS25; |
Net gmii_txd<0> LOC = AM11 |IOSTANDARD = LVCMOS25; |
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Net gmii_col LOC = AK13 |IOSTANDARD = LVCMOS25; |
Net gmii_crs LOC = AL13 |IOSTANDARD = LVCMOS25; |
Net mii_tx_clk LOC = AD12 |IOSTANDARD = LVCMOS25; |
|
Net gmii_tx_en LOC = AJ10 |IOSTANDARD = LVCMOS25; |
Net gmii_tx_er LOC = AH10 |IOSTANDARD = LVCMOS25; |
Net gmii_tx_clk LOC = AH12 |IOSTANDARD = LVCMOS25; |
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Net gmii_rx_dv LOC = AM13 |IOSTANDARD = LVCMOS25; |
Net gmii_rx_er LOC = AG12 |IOSTANDARD = LVCMOS25; |
# P20 - GCLK7 |
Net gmii_rx_clk LOC = AP11 |IOSTANDARD = LVCMOS25; |
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NET "clk_in_p" TNM_NET = "clk_in_p"; |
TIMESPEC "TS_emac1_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps; |
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# Ethernet GTX_CLK high quality 125 MHz reference clock |
NET "*mac_block/gtx_clk_bufg" TNM_NET = "ref_gtx_clk"; |
TIMEGRP "emac1_clk_ref_gtx" = "ref_gtx_clk"; |
TIMESPEC TS_emac1_clk_ref_gtx = PERIOD "N/A" 8 ns HIGH 50%; |
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