OpenCores
URL https://opencores.org/ocsvn/usb11_phy_translation/usb11_phy_translation/trunk

Subversion Repositories usb11_phy_translation

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /usb11_phy_translation
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/trunk/usb_tx_phy.vhdl
40,8 → 40,17
-- // // --
-- /////////////////////////////////////////////////////////////////// --
--======================================================================================--
-- --
-- Change history --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | Vers. | Date | Autor | Comment | --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | 1.0 |04 Feb 2011| MN | Initial version | --
-- | 1.1 |23 Apr 2011| MN | Added missing 'rst' in process sensitivity lists | --
-- | | | | Added ELSE constructs in next_state process to | --
-- | | | | prevent an undesired latch implementation. | --
--======================================================================================--
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
66,7 → 75,7
 
signal hold_reg : std_logic_vector(7 downto 0);
signal ld_data : std_logic;
signal ld_data_d : std_logic;
signal ld_data_d : std_logic;
signal ld_eop_d : std_logic;
signal ld_sop_d : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
214,7 → 223,7
sft_done_e <= sft_done and not sft_done_r;
 
-- Out Data Hold Register
p_hold_reg: process (clk)
p_hold_reg: process (clk, rst)
begin
if rst ='0' then
hold_reg <= X"00";
391,22 → 400,35
case (state) is
when IDLE_STATE => if TxValid_i ='1' then
next_state <= SOP_STATE;
ELSE
next_state <= IDLE_STATE;
end if;
when SOP_STATE => if sft_done_e ='1' then
next_state <= DATA_STATE;
ELSE
next_state <= SOP_STATE;
end if;
when DATA_STATE => if data_done ='0' and sft_done_e ='1' then
next_state <= EOP1_STATE;
ELSE
next_state <= DATA_STATE;
end if;
when EOP1_STATE => if eop_done ='1' then
next_state <= EOP2_STATE;
ELSE
next_state <= EOP1_STATE;
end if;
when EOP2_STATE => if eop_done ='0' and fs_ce ='1' then
next_state <= WAIT_STATE;
ELSE
next_state <= EOP2_STATE;
end if;
when others => if fs_ce = '1' then --is WAIT_STATE
when WAIT_STATE => if fs_ce = '1' then
next_state <= IDLE_STATE;
ELSE
next_state <= WAIT_STATE;
end if;
when others => next_state <= IDLE_STATE;
end case;
end if;
end process;
/trunk/usb_rx_phy_60MHz.vhdl
41,6 → 41,16
-- // // --
-- /////////////////////////////////////////////////////////////////// --
--======================================================================================--
-- --
-- Change history --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | Vers. | Date | Autor | Comment | --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | 1.0 |04 Feb 2011| MN | Initial version | --
-- | 1.1 |23 Apr 2011| MN | Added missing 'rst' in process sensitivity lists. | --
-- | | | | Added ELSE construct in fs_next_state process to | --
-- | | | | prevent an undesired latch implementation. | --
--======================================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
121,7 → 131,7
end if;
end process;
 
p_sync_err: process (clk)
p_sync_err: process (clk, rst)
begin
if rst ='0' then
sync_err <= '0';
176,7 → 186,7
k <= not rxdp_s and rxdn_s;
se0 <= not rxdp_s and not rxdn_s;
 
p_se0_s: process (clk)
p_se0_s: process (clk, rst)
begin
if rst ='0' then
se0_s <= '0';
250,6 → 260,9
when FS_IDLE => if k ='1' and rx_en ='1' then -- 0
fs_next_state <= K1;
sync_err_d <= '0';
else
fs_next_state <= FS_IDLE;
sync_err_d <= '0';
end if;
when K1 => if j ='1' and rx_en ='1' then -- 1
fs_next_state <= J1;
331,7 → 344,7
end if;
end process;
 
p_rx_valid_r: process (clk)
p_rx_valid_r: process (clk, rst)
begin
if rst ='0' then
rx_valid_r <= '0';
348,7 → 361,7
-- NRZI Decoder --
--====================================================================================--
 
p_sd_r: process (clk)
p_sd_r: process (clk, rst)
begin
if rst ='0' then
sd_r <= '0';
395,7 → 408,7
 
drop_bit <= '1' when one_cnt ="110" else '0';
 
p_bit_stuff_err: process (clk) -- Bit Stuff Error
p_bit_stuff_err: process (clk, rst) -- Bit Stuff Error
begin
if rst ='0' then
bit_stuff_err <= '0';
408,7 → 421,7
-- Serial => Parallel converter --
--====================================================================================--
 
p_shift_en: process (clk)
p_shift_en: process (clk, rst)
begin
if rst ='0' then
shift_en <= '0';
458,7 → 471,7
end if;
end process;
 
p_rx_valid: process (clk)
p_rx_valid: process (clk, rst)
begin
if rst ='0' then
rx_valid <= '0';
474,7 → 487,7
end if;
end process;
 
p_byte_err: process (clk)
p_byte_err: process (clk, rst)
begin
if rst ='0' then
byte_err <= '0';
/trunk/usb_rx_phy.vhdl
40,6 → 40,16
-- // // --
-- /////////////////////////////////////////////////////////////////// --
--======================================================================================--
-- --
-- Change history --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | Vers. | Date | Autor | Comment | --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | 1.0 |04 Feb 2011| MN | Initial version | --
-- | 1.1 |23 Apr 2011| MN | Added 'rst' to most latched signals. | --
-- | | | | Added ELSE construct in fs_next_state process to | --
-- | | | | prevent an undesired latch implementation. | --
--======================================================================================--
 
library ieee;
use ieee.std_logic_1164.all;
123,9 → 133,11
end if;
end process;
 
p_sync_err: process (clk)
p_sync_err: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
sync_err <= '0';
elsif rising_edge(clk) then
sync_err <= not rx_active and sync_err_d;
end if;
end process;
176,9 → 188,11
k <= not rxdp_s and rxdn_s;
se0 <= not rxdp_s and not rxdn_s;
 
p_se0_s: process (clk)
p_se0_s: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
se0_s <= '0';
elsif rising_edge(clk) then
if fs_ce ='1' then
se0_s <= se0;
end if;
279,6 → 293,9
when FS_IDLE => if k ='1' and rx_en ='1' then -- 0
fs_next_state <= K1;
sync_err_d <= '0';
else
fs_next_state <= FS_IDLE;
sync_err_d <= '0';
end if;
when K1 => if j ='1' and rx_en ='1' then -- 1
fs_next_state <= J1;
360,9 → 377,11
end if;
end process;
 
p_rx_valid_r: process (clk)
p_rx_valid_r: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
rx_valid_r <= '0';
elsif rising_edge(clk) then
if rx_valid ='1' then
rx_valid_r <= '1';
elsif fs_ce ='1' then
375,9 → 394,11
-- NRZI Decoder --
--====================================================================================--
 
p_sd_r: process (clk)
p_sd_r: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
sd_r <= '0';
elsif rising_edge(clk) then
if fs_ce ='1' then
sd_r <= rxd_s;
end if;
420,9 → 441,11
 
drop_bit <= '1' when one_cnt ="110" else '0';
 
p_bit_stuff_err: process (clk) -- Bit Stuff Error
p_bit_stuff_err: process (clk, rst) -- Bit Stuff Error
begin
if rising_edge(clk) then
if rst ='0' then
bit_stuff_err <= '0';
elsif rising_edge(clk) then
bit_stuff_err <= drop_bit and sd_nrzi and fs_ce and not se0 and rx_active;
end if;
end process;
431,9 → 454,11
-- Serial => Parallel converter --
--====================================================================================--
 
p_shift_en: process (clk)
p_shift_en: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
shift_en <= '0';
elsif rising_edge(clk) then
if fs_ce ='1' then
shift_en <= synced_d or rx_active;
end if;
479,9 → 504,11
end if;
end process;
 
p_rx_valid: process (clk)
p_rx_valid: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
rx_valid <= '0';
elsif rising_edge(clk) then
rx_valid <= not drop_bit and rx_valid1 and fs_ce;
end if;
end process;
493,9 → 520,11
end if;
end process;
 
p_byte_err: process (clk)
p_byte_err: process (clk, rst)
begin
if rising_edge(clk) then
if rst ='0' then
byte_err <= '0';
elsif rising_edge(clk) then
byte_err <= se0 and not se0_r and (bit_cnt(1) or bit_cnt(2)) and rx_active;
end if;
end process;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.