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URL https://opencores.org/ocsvn/usb_dongle_fpga/usb_dongle_fpga/trunk

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    /usb_dongle_fpga/tags/HWVersion_1_0/src
    from Rev 5 to Rev 53
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Rev 5 → Rev 53

/led_sys/led_sys.vhd
0,0 → 1,169
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
-- bit 0,A
-- ----------
-- | |
-- | |
-- 5,F| | 1,B
-- | 6,G |
-- ----------
-- | |
-- | |
-- 4,E| | 2,C
-- | 3,D |
-- ----------
-- # 7,H
 
 
-- Select signal order
-- --- --- --- ---
-- | | | | | | | |
-- | | | | | | | |
-- --- --- --- ---
-- | | | | | | | |
-- | | | | | | | |
-- --- --- --- ---
-- sel(3) sel(2) sel(1) sel(0)
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
 
entity led_sys is --toplevel for led system
generic(
msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
);
port (
clk : in std_logic;
reset_n : in std_logic;
led_data_i : in std_logic_vector(15 downto 0); --binary data in
seg_out : out std_logic_vector(7 downto 0); --one segment out
sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
);
end led_sys;
 
architecture rtl of led_sys is
 
component led_coder
port (
led_data_i : in std_logic_vector(7 downto 0);
hi_seg : out std_logic_vector(7 downto 0);
lo_seg : out std_logic_vector(7 downto 0)
);
end component;
 
component byte_scan
port (
clk : in std_logic;
hi_seg_1 : in std_logic_vector(7 downto 0);
lo_seg_1 : in std_logic_vector(7 downto 0);
hi_seg_0 : in std_logic_vector(7 downto 0);
lo_seg_0 : in std_logic_vector(7 downto 0);
seg_out : out std_logic_vector(7 downto 0);
sel_out : out std_logic_vector(3 downto 0)
);
end component;
 
 
-- input signals
signal hi_seg1 : std_logic_vector(7 downto 0);
signal lo_seg1 : std_logic_vector(7 downto 0);
signal hi_seg0 : std_logic_vector(7 downto 0);
signal lo_seg0 : std_logic_vector(7 downto 0);
 
--data containing signals
signal data_hi_seg1 : std_logic_vector(7 downto 0);
signal data_lo_seg1 : std_logic_vector(7 downto 0);
signal data_hi_seg0 : std_logic_vector(7 downto 0);
signal data_lo_seg0 : std_logic_vector(7 downto 0);
 
--constant display
signal cons_hi_seg1 : std_logic_vector(7 downto 0);
signal cons_lo_seg1 : std_logic_vector(7 downto 0);
signal cons_hi_seg0 : std_logic_vector(7 downto 0);
signal cons_lo_seg0 : std_logic_vector(7 downto 0);
 
signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
 
begin -- rtl
---------------------------HGFEDCBA
cons_hi_seg1 <= msn_hib;--"01111111"; --8
cons_lo_seg1 <= lsn_hib;--"01111101"; --6
cons_hi_seg0 <= msn_lob;--"01011100"; -- small o
cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o
 
 
 
 
process (clk) --enable the scanning while in reset
begin -- process
if clk'event and clk = '0' then -- rising clock edge
disp_cnt <= disp_cnt + 1;
end if;
end process;
 
LED_CODE0: led_coder
port map(
led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0);
hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0);
lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0)
);
 
LED_CODE1: led_coder
port map(
led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0);
hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0);
lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0)
);
 
 
lo_seg1 <= data_hi_seg1 when reset_n='1' else cons_hi_seg1;
hi_seg1 <= data_lo_seg1 when reset_n='1' else cons_lo_seg1;
 
lo_seg0 <= data_hi_seg0 when reset_n='1' else cons_hi_seg0;
hi_seg0 <= data_lo_seg0 when reset_n='1' else cons_lo_seg0;
 
SCAN : byte_scan
port map(
clk => disp_cnt(15), -- in std_logic;
hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0);
lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0);
hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0);
lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0);
seg_out => seg_out, -- out std_logic_vector(7 downto 0);
sel_out => sel_out -- out std_logic_vector(3 downto 0)
);
 
 
 
 
end rtl;
/led_sys/byte_scan_mux.vhd
0,0 → 1,111
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
 
-- bit 0,A
-- ----------
-- | |
-- | |
-- 5,F| | 1,B
-- | 6,G |
-- ----------
-- | |
-- | |
-- 4,E| | 2,C
-- | 3,D |
-- ----------
-- # 7,H
 
 
-- Select signal order
-- --- --- --- ---
-- | | | | | | | |
-- | | | | | | | |
-- --- --- --- ---
-- | | | | | | | |
-- | | | | | | | |
-- --- --- --- ---
-- sel(3) sel(2) sel(1) sel(0)
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
 
entity byte_scan is
port (
clk : in std_logic;
hi_seg_1 : in std_logic_vector(7 downto 0);
lo_seg_1 : in std_logic_vector(7 downto 0);
hi_seg_0 : in std_logic_vector(7 downto 0);
lo_seg_0 : in std_logic_vector(7 downto 0);
seg_out : out std_logic_vector(7 downto 0);
sel_out : out std_logic_vector(3 downto 0)
);
end byte_scan;
 
architecture rtl of byte_scan is
 
signal sel_p : std_logic_vector(3 downto 0);
signal count : std_logic_vector(1 downto 0):="00";
signal hi_seg_1_3 : std_logic_vector(7 downto 0);
signal lo_seg_1_3 : std_logic_vector(7 downto 0);
signal hi_seg_0_2 : std_logic_vector(7 downto 0);
signal lo_seg_0_2 : std_logic_vector(7 downto 0);
 
begin -- rtl
 
 
hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3;
lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3;
hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2;
lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2;
 
seg_out <=hi_seg_1_3 when count="01" else
lo_seg_1_3 when count="10" else
hi_seg_0_2 when count="11" else
lo_seg_0_2 when count="00";
 
sel_out <= sel_p;
 
sel_p <= "1110" when count="00" else
"0111" when count="01" else
"1011" when count="10" else
"1101" when count="11";
 
 
 
 
process (clk) --enable the scanning while in reset (simulation will be incorrect)
begin -- process
if clk'event and clk = '1' then -- rising clock edge
count <= count + 1;
end if;
end process;
 
end rtl;
/led_sys/led_coder.vhd
0,0 → 1,112
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
-- bit 0,A
-- ----------
-- | |
-- | |
-- 5,F| | 1,B
-- | 6,G |
-- ----------
-- | |
-- | |
-- 4,E| | 2,C
-- | 3,D |
-- ----------
-- # 7,H
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
 
entity led_coder is
port (
led_data_i : in std_logic_vector(7 downto 0);
hi_seg : out std_logic_vector(7 downto 0);
lo_seg : out std_logic_vector(7 downto 0)
);
end led_coder;
 
architecture rtl of led_coder is
signal r_led_data : std_logic_vector(7 downto 0);
signal decoded_lo,decoded_hi : std_logic_vector(7 downto 0);
 
begin -- rtl
hi_seg <= decoded_hi;
lo_seg <= decoded_lo;
-- purpose: binary to led segments decoder
-- type : combinational
-- inputs : nibble,reset
-- outputs:
decode_nibble_lo: process (led_data_i)
begin -- process decode_nibble
case led_data_i(3 downto 0) is--HGFEDCBA
when "0000" => decoded_lo <= "00111111"; -- 0
when "0001" => decoded_lo <= "00000110"; -- 1
when "0010" => decoded_lo <= "01011011"; -- 2
when "0011" => decoded_lo <= "01001111"; -- 3
when "0100" => decoded_lo <= "01100110"; -- 4
when "0101" => decoded_lo <= "01101101"; -- 5
when "0110" => decoded_lo <= "01111101"; -- 6
when "0111" => decoded_lo <= "00000111"; -- 7
when "1000" => decoded_lo <= "01111111"; -- 8
when "1001" => decoded_lo <= "01101111"; -- 9
when "1010" => decoded_lo <= "01110111"; -- a
when "1011" => decoded_lo <= "01111100"; -- b
when "1100" => decoded_lo <= "00111001"; -- c
when "1101" => decoded_lo <= "01011110"; -- d
when "1110" => decoded_lo <= "01111001"; -- e
when others => decoded_lo <= "01110001"; -- f
end case;
end process decode_nibble_lo;
 
decode_nibble_hi: process (led_data_i)
begin -- process decode_nibble
case led_data_i(7 downto 4) is--HGFEDCBA
when "0000" => decoded_hi <= "00111111"; -- 0
when "0001" => decoded_hi <= "00000110"; -- 1
when "0010" => decoded_hi <= "01011011"; -- 2
when "0011" => decoded_hi <= "01001111"; -- 3
when "0100" => decoded_hi <= "01100110"; -- 4
when "0101" => decoded_hi <= "01101101"; -- 5
when "0110" => decoded_hi <= "01111101"; -- 6
when "0111" => decoded_hi <= "00000111"; -- 7
when "1000" => decoded_hi <= "01111111"; -- 8
when "1001" => decoded_hi <= "01101111"; -- 9
when "1010" => decoded_hi <= "01110111"; -- a
when "1011" => decoded_hi <= "01111100"; -- b
when "1100" => decoded_hi <= "00111001"; -- c
when "1101" => decoded_hi <= "01011110"; -- d
when "1110" => decoded_hi <= "01111001"; -- e
when others => decoded_hi <= "01110001"; -- f
end case;
end process decode_nibble_hi;
 
 
end rtl;
/lpc_proto/lpc_byte.vhd
0,0 → 1,247
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
 
entity lpc_iow is
port (
--system signals
lreset_n : in std_logic;
lclk : in std_logic;
--LPC bus from host
lad_i : in std_logic_vector(3 downto 0);
lad_o : out std_logic_vector(3 downto 0);
lad_oe : out std_logic;
lframe_n : in std_logic;
--memory interface
lpc_addr : out std_logic_vector(23 downto 0); --shared address
lpc_wr : out std_logic; --shared write not read
lpc_data_i : in std_logic_vector(7 downto 0);
lpc_data_o : out std_logic_vector(7 downto 0);
lpc_val : out std_logic;
lpc_ack : in std_logic
);
end lpc_iow;
 
architecture rtl of lpc_iow is
type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states
signal CS : state;
signal r_lad : std_logic_vector(3 downto 0);
signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
--adress 23 bits on flash
signal r_data : std_logic_vector(7 downto 0);
signal r_cnt : std_logic_vector(2 downto 0);
signal ext_sum : std_logic_vector(2 downto 0);
signal mem_nio : std_logic; -- memory not io cycle
signal data_valid : std_logic;
begin -- rtl
 
--Pass the whole LPC address to the system
lpc_addr <= r_addr(23 downto 0);
lpc_data_o<= r_data;
 
 
--this result is used in LPC process
ext_sum <= r_cnt + 1;
-- purpose: LPC IO write handler
-- type : sequential
-- inputs : lclk, lreset_n
-- outputs:
LPC: process (lclk, lreset_n)
begin -- process LPC
if lreset_n = '0' then -- asynchronous reset (active low)
CS<= RESETs;
lad_oe<='0';
data_valid <='1';
lad_o <="0000";
lpc_val <='0';
r_addr <= (others=>'0');
elsif lclk'event and lclk = '1' then -- rising clock edge
case CS is
when RESETs => ----------------------------------------------------------
lpc_wr <='0';
lpc_val <='0';
if lframe_n='0' then
CS <= STARTs;
r_lad <= lad_i;
else
CS <= RESETs;
end if;
when STARTs => ----------------------------------------------------------
if lframe_n = '0' then
r_lad <= lad_i;
CS <= STARTs;
elsif r_lad="0000" then
--must identify CYCTYPE
if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
--next 4 states must be address states
CS<=ADDRs;
mem_nio <= '0';
r_cnt <= "000";
elsif lad_i(3 downto 1)="010" then
CS<=ADDRs;
mem_nio <= '1';
r_cnt <= "000";
else
CS<= RESETs;
end if;
end if;
when ADDRs => -----------------------------------------------------------
case mem_nio is
when '0' => --IO write cycle
if r_cnt ="011" then
if r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" then
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt <= "000";
CS<=DATAs;
elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then --for debug switch
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt <= "000";
CS<=DATAs;
else
--not for this device
CS<=RESETs;
end if;
else
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt<=ext_sum;
CS<=ADDRs;
end if;
when '1' => --Memory read cycle
if r_cnt ="111" then
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt <= "000";
lpc_wr <='0'; --memory read mus accure
lpc_val <='1';
data_valid <='0';
CS<=TARs;
else
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt<=ext_sum;
CS<=ADDRs;
end if;
when others => null;
end case;
when DATAs => -----------------------------------------------------------
case mem_nio is
when '0' => --IO write cycle
if r_cnt ="001" then
r_data <= r_data(3 downto 0)&lad_i;
r_cnt <= "000";
lpc_wr <='1'; --IO write must accure
lpc_val <='1';
CS <= TARs;
else
r_data <= r_data(3 downto 0)&lad_i;
r_cnt<=ext_sum;
CS <= DATAs;
end if;
when '1' => --Memory read cycle
if r_cnt ="001" then
lad_o <= r_data(7 downto 4);
r_cnt <= "000";
CS <= LOCAL_TARs;
else
lad_o <= r_data(3 downto 0);
r_cnt<=ext_sum;
CS <= DATAs;
end if;
when others => null;
end case;
when TARs => ------------------------------------------------------------
if mem_nio = '1' and lpc_ack='1' and r_cnt ="001" then
r_data <= lpc_data_i;
lpc_val <='0';
data_valid <='1';
CS<= SYNCs;
r_cnt <= "000";
elsif lpc_ack='1' and r_cnt ="001" then
lad_o<="0000"; --added to avoid trouble
lpc_val <='0';
CS<= SYNCs;
r_cnt <= "000";
end if;
 
if r_cnt ="001" then
if lpc_ack='0' then
lad_o<="0110"; --added to avoid trouble
end if;
lad_oe<='1';
elsif lad_i="1111" then
r_cnt<=ext_sum;
lad_oe<='1';
lad_o<="1111"; --drive to F on the bus
CS <= TARs;
else
CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR
end if;
when SYNCs => -----------------------------------------------------------
case mem_nio is
when '0' => --IO write cycle
-- just passing r_lad on bus again
lad_o <= "1111";
CS <= LOCAL_TARs;
when '1' => --Memory read cycle
if data_valid ='1' then
lad_o <="0000";
CS <= DATAs;
else
if lpc_ack='1' then
r_data <= lpc_data_i;
data_valid <= '1';
lad_o<="0000"; --SYNC ok now
lpc_val <='0';
CS <= DATAs;
end if;
end if;
when others => null;
end case;
when LOCAL_TARs => ------------------------------------------------------
case mem_nio is
when '0' => --IO write cycle
lpc_wr <='0';
lad_oe <='0';
CS <= RESETs;
when '1' => --Memory read cycle
if r_cnt ="000" then
lad_o <= "1111";
r_cnt <= ext_sum;
else
lad_oe <= '0';
r_cnt <="000";
CS <= RESETs;
end if;
when others => null;
end case;
end case; -----------------------------------------------------------------
end if;
end process LPC;
 
end rtl;
/usb/usb2mem.vhd
0,0 → 1,326
--COMMAND STRUCTURE OF SERAL USB PROTOCOL
 
-- MSBYTE LSBYTE
 
-- DATA CODE
 
--Dongle internal command codes
-- 0x-- 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble)
-- 0xNN 0xCD --Get Data from flash (performs read from current address) NN count of words auto increment address
-- 0xAA 0xA0 --Addr LSByte write
-- 0xAA 0xA1 --Addr Byte write
-- 0xAA 0xA2 --Addr MSByte write
-- 0x-- 0x3F --NOP
 
--Flash operations codes
-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
-- 0x-- 0xD0 -- 0xD0 is flash confirm command
 
 
 
--write buffer sequence
-- ??? -- set address if needed
-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine
-- 0x-- 0xNN --0xNN is word count for flash ges directly to flash and is wordCount - 1
-- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum
-- ...
-- 0x-- 0xD0 -- 0xD0 is flash confirm command
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity usb2mem is
port (
clk25 : in std_logic;
reset_n : in std_logic;
-- mem Bus
mem_addr : out std_logic_vector(23 downto 0);
mem_do : out std_logic_vector(15 downto 0);
mem_di : in std_logic_vector(15 downto 0);
mem_wr : out std_logic;
mem_val : out std_logic;
mem_ack : in std_logic;
mem_cmd : out std_logic;
-- USB port
usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr : out std_logic; -- write performed on edge \ of signal
usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
usb_bd : inout std_logic_vector(7 downto 0) --bus data
);
end usb2mem;
 
architecture RTL of usb2mem is
 
 
 
type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s);
signal CS : state_type;
 
signal data_reg_i : std_logic_vector(15 downto 0);
signal data_reg_o : std_logic_vector(15 downto 0);
signal data_oe : std_logic; -- rx fifo empty (data redy if low)
signal usb_wr_d : std_logic; -- internal readable output state for write
signal addr_reg: std_logic_vector(23 downto 0);
 
--State machine
signal cmd_cnt : std_logic_vector(7 downto 0);
signal state_cnt : std_logic_vector(3 downto 0);
--shyncro to USB
signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
 
signal read_mode : std_logic;
signal write_mode : std_logic;
signal write_count : std_logic;
signal first_word : std_logic;
 
 
begin
 
--define internal command codes
internal_cmd <='1' when data_reg_i(7 downto 0) = x"C5" else
'1' when data_reg_i(7 downto 0) = x"CD" else
'1' when data_reg_i(7 downto 0) = x"A0" else
'1' when data_reg_i(7 downto 0) = x"A1" else
'1' when data_reg_i(7 downto 0) = x"A2" else
'1' when data_reg_i(7 downto 0) = x"3F" else
--These are spechial attention Flash commands
'1' when data_reg_i(7 downto 0) = x"E8" else
'0';
 
 
usb_wr <= usb_wr_d;
 
-- this goes to byte buffer for that reason send LSB first and MSB second
usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s else --LSB byte first
data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s else --MSB byte second
(others=>'Z');
 
 
process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
begin -- process
if reset_n='0' then
CS <= RESETs;
usb_rd_n <= '1';
usb_wr_d <= '0';
usb_txe_nd <= '1';
usb_rxf_nd <= '1';
data_oe <='0';
state_cnt <=(others=>'0'); --init command counter
mem_do <= (others=>'Z');
mem_addr <= (others=>'Z');
addr_reg <= (others=>'0');
mem_val <= '0';
mem_wr <='0';
mem_cmd <='0';
cmd_cnt <= (others=>'0');
read_mode <='0';
write_mode <='0';
write_count <='0';
first_word <='0';
elsif clk25'event and clk25 = '1' then -- rising clock edge
usb_txe_nd <= usb_txe_n;
usb_rxf_nd <= usb_rxf_n;
case CS is
when RESETs =>
if usb_rxf_nd='0' then
state_cnt <=(others=>'0'); --init command counter
data_oe <='0'; --we will read command in
CS <= RXCMD0s;
end if;
when RXCMD0s =>
if state_cnt="0000" then
usb_rd_n <='0'; -- set read low
state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
elsif state_cnt="0001" then
state_cnt <= state_cnt + 1;-- one wait cycle
elsif state_cnt="0010" then
state_cnt <= state_cnt + 1;-- now is ok
data_reg_i(15 downto 8) <= usb_bd; --get data form bus MSByte must come first
elsif state_cnt="0011" then
usb_rd_n <='1'; -- set read back to high
state_cnt <= state_cnt + 1;-- start wait
elsif state_cnt="0100" then
state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
elsif state_cnt="0101" then
state_cnt <= state_cnt + 1;-- wait
elsif state_cnt="0110" then
state_cnt <= state_cnt + 1;-- now is ok prob.
else
if usb_rxf_nd='0' then --wait untill next byte is available
state_cnt <=(others=>'0'); --init command counter
CS <= RXCMD1s;
end if;
end if;
when RXCMD1s =>
if state_cnt="0000" then
usb_rd_n <='0'; -- set read low
state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles)
elsif state_cnt="0001" then
state_cnt <= state_cnt + 1;-- one wait cycle
elsif state_cnt="0010" then
state_cnt <= state_cnt + 1;-- now is ok
data_reg_i(7 downto 0) <= usb_bd; --get data form bus LSByte must come last
elsif state_cnt="0011" then
state_cnt <= state_cnt + 1;-- now is ok
usb_rd_n <='1'; -- set read back to high
elsif state_cnt="0100" then
state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready)
elsif state_cnt="0101" then
state_cnt <= state_cnt + 1;-- wait
elsif state_cnt="0110" then
state_cnt <= state_cnt + 1;-- now is ok prob.
else
state_cnt <=(others=>'0'); --init command counter
CS <= INTERNs;
end if;
when INTERNs =>
if cmd_cnt=x"00" then
if data_reg_i(7 downto 0)=x"A0" then
addr_reg(7 downto 0)<= data_reg_i(15 downto 8);
CS <= RESETs; --go back to resets
elsif data_reg_i(7 downto 0)=x"A1" then
addr_reg(15 downto 8)<= data_reg_i(15 downto 8);
CS <= RESETs; --go back to resets
elsif data_reg_i(7 downto 0)=x"A2" then
addr_reg(23 downto 16)<= data_reg_i(15 downto 8);
CS <= RESETs; --go back to resets
elsif data_reg_i(7 downto 0)=x"3F" then
CS <= RESETs; --go back to resets --NOP command
elsif data_reg_i(7 downto 0)=x"C5" then
data_reg_o <=x"3210";
CS <= TXCMD0s;
elsif data_reg_i(7 downto 0)=x"CD" then
cmd_cnt <= data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now
CS <= VCIRDs; --go perform a read
read_mode <='1';
elsif data_reg_i(7 downto 0)=x"E8" then
--write_mode <='1';
write_count <='0';
first_word <='0';
cmd_cnt <= data_reg_i(15 downto 8) + 1; --+2 for direct count write +1
data_reg_i(15 downto 8)<=(others=>'0');
CS <= VCIWRs; --go perform a write
else
CS <= VCIWRs;
end if;
else
if cmd_cnt>x"00" then
cmd_cnt<= cmd_cnt - 1;
if write_count='0' then
write_count<='1';
elsif write_count='1' and first_word ='0' then
first_word <='1';
elsif write_count='1' and first_word ='1' then
addr_reg <= addr_reg + 1; --autoincrement address in in block mode
end if;
--if cmd_cnt>x"02" then --so not to increase too many times on write buffer
-- addr_reg <= addr_reg + 1; --autoincrement address in in block mode
--end if;
end if;
CS <= VCIWRs;
end if;
when VCIRDs => --flash read
mem_wr <='0'; --this is VCI write_not_read
mem_cmd <='0';
mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
mem_val <= '1';
if mem_ack='1' then
data_reg_o <= mem_di;
mem_wr <='0'; --this is VCI write_not_read
mem_cmd <='0';
mem_val <= '0';
CS <= TXCMD0s;
end if;
when VCIWRs => --flash write
mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address
mem_do <= data_reg_i; --USB data in will go to mem_out
mem_wr <='1'; --this is VCI write_not_read
mem_cmd <='1';
mem_val <= '1';
if mem_ack='1' then
mem_do <= (others=>'Z');
mem_wr <='0'; --this is VCI write_not_read
mem_cmd <='0';
mem_val <= '0';
if write_mode='0' then
CS <= RESETs;
--else --else if was 0xE8 must read and return XSR
-- write_mode <='0'; --XSR return will no follow clear this bit
-- CS <= VCIRDs;
end if;
end if;
when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first
if state_cnt="0000" then
if usb_txe_nd='0' then
usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
state_cnt <= state_cnt + 1;-- now is ok
end if;
elsif state_cnt="0010" then
data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
state_cnt <= state_cnt + 1;-- now is ok
elsif state_cnt="0011" then
usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
state_cnt <= state_cnt + 1;-- now is ok
elsif state_cnt="0100" then
state_cnt <= state_cnt + 1;-- now is ok
data_oe<='0';
elsif state_cnt="0111" then --must stay low at least 50ns
CS <= TXCMD1s;
state_cnt <= (others=>'0');
else
state_cnt <= state_cnt + 1;-- if intermediate cnt then count
end if;
when TXCMD1s =>
if state_cnt="0000" then
if usb_txe_nd='0' then
usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch
state_cnt <= state_cnt + 1;-- now is ok
end if;
elsif state_cnt="0010" then
data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before)
state_cnt <= state_cnt + 1;-- now is ok
elsif state_cnt="0011" then
usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns
state_cnt <= state_cnt + 1;-- now is ok
elsif state_cnt="0100" then
state_cnt <= state_cnt + 1;-- now is ok
data_oe<='0';
elsif state_cnt="0111" then --must stay low at least 50ns
if read_mode='0' then
CS <= RESETs;
elsif cmd_cnt="00" then --last word sent
addr_reg <= addr_reg + 1; --autoincrement address in read mode
read_mode <='0';
CS <= RESETs;
else
cmd_cnt<= cmd_cnt - 1;
addr_reg <= addr_reg + 1; --autoincrement address in read mode
CS <= VCIRDs; --more data to be read
end if;
state_cnt <= (others=>'0');
else
state_cnt <= state_cnt + 1;-- if intermediate cnt then count
end if;
when others => null;
end case;
end if;
end process;
 
 
 
end RTL;
 
/design_top/Copyright.txt
0,0 → 1,22
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
/design_top/lesser.txt
0,0 → 1,504
GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
 
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51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Libraries
 
If you develop a new library, and you want it to be of the greatest
possible use to the public, we recommend making it free software that
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safest to attach them to the start of each source file to most effectively
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modify it under the terms of the GNU Lesser General Public
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but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Ty Coon, President of Vice
 
That's all there is to it!
 
 
/design_top/design_top_thincandbg.vhd
0,0 → 1,451
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
 
-- Coding for seg_out(7:0)
--
-- bit 0,A
-- ----------
-- | |
-- | |
-- 5,F| | 1,B
-- | 6,G |
-- ----------
-- | |
-- | |
-- 4,E| | 2,C
-- | 3,D |
-- ----------
-- # 7,H
 
-- Revision history
--
-- Version 1.01
-- 15 oct 2006 version code 86 01 jyrit
-- Added IO write to address 0x0088 with commands F1 and F4 to
-- enable switching dongle to 4Meg mode for external reads
-- Changed USB interface to address all 4 Meg on any mode jumper configuration
--
-- Version 1.02
-- 04 dec 2006 version code 86 02 jyrit
-- Added listen only mode for mode pin configuration "00" to enable post code
-- spy mode (does not respond to external reads).
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity design_top is
port (
--system signals
sys_clk : in std_logic; --25 MHz clk
resetn : in std_logic;
hdr : out std_logic_vector(10 downto 0);
--alt_clk : out std_logic; --alternative clock from extention header
mode : in std_logic_vector(1 downto 0); --sel upper addr bits
--lpc slave interf
lad : inout std_logic_vector(3 downto 0);
lframe_n : in std_logic;
lreset_n : in std_logic;
lclk : in std_logic;
--led system
seg_out : out std_logic_vector(7 downto 0);
scn_seg : out std_logic_vector(3 downto 0);
led_green : out std_logic;
led_red : out std_logic;
--flash interface
fl_addr : out std_logic_vector(23 downto 0);
fl_ce_n : out std_logic; --chip select
fl_oe_n : out std_logic; --output enable for flash
fl_we_n : out std_logic; --write enable
fl_data : inout std_logic_vector(15 downto 0);
fl_rp_n : out std_logic; --reset signal
fl_sts : in std_logic; --status signal
--USB parallel interface
usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr : inout std_logic; -- write performed on edge \ of signal
usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
usb_rxf_n : in std_logic; -- rx fifo has data if low
usb_bd : inout std_logic_vector(7 downto 0) --bus data
);
end design_top;
 
 
 
architecture rtl of design_top is
 
component led_sys --toplevel for led system
generic(
msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
);
port (
clk : in std_logic;
reset_n : in std_logic;
led_data_i : in std_logic_vector(15 downto 0); --binary data in
seg_out : out std_logic_vector(7 downto 0); --one segment out
sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
);
end component;
 
 
component lpc_iow
port (
--system signals
lreset_n : in std_logic;
lclk : in std_logic;
--LPC bus from host
lad_i : in std_logic_vector(3 downto 0);
lad_o : out std_logic_vector(3 downto 0);
lad_oe : out std_logic;
lframe_n : in std_logic;
--memory interface
lpc_addr : out std_logic_vector(23 downto 0); --shared address
lpc_wr : out std_logic; --shared write not read
lpc_data_i : in std_logic_vector(7 downto 0);
lpc_data_o : out std_logic_vector(7 downto 0);
lpc_val : out std_logic;
lpc_ack : in std_logic
);
end component;
 
 
component flash_if
port (
clk : in std_logic;
reset_n : in std_logic;
--flash Bus
fl_addr : out std_logic_vector(23 downto 0);
fl_ce_n : out std_logic; --chip select
fl_oe_n : out std_logic; --output enable for flash
fl_we_n : out std_logic; --write enable
fl_data : inout std_logic_vector(15 downto 0);
fl_rp_n : out std_logic; --reset signal
fl_byte_n : out std_logic; --hold in byte mode
fl_sts : in std_logic; --status signal
-- mem Bus
mem_addr : in std_logic_vector(23 downto 0);
mem_do : out std_logic_vector(15 downto 0);
mem_di : in std_logic_vector(15 downto 0);
mem_wr : in std_logic; --write not read signal
mem_val : in std_logic;
mem_ack : out std_logic
);
end component;
 
 
component usb2mem
port (
clk25 : in std_logic;
reset_n : in std_logic;
-- mem Bus
mem_addr : out std_logic_vector(23 downto 0);
mem_do : out std_logic_vector(15 downto 0);
mem_di : in std_logic_vector(15 downto 0);
mem_wr : out std_logic;
mem_val : out std_logic;
mem_ack : in std_logic;
mem_cmd : out std_logic;
-- USB port
usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr : out std_logic; -- write performed on edge \ of signal
usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
usb_bd : inout std_logic_vector(7 downto 0) --bus data
);
end component;
 
 
 
--LED signals
signal data_to_disp : std_logic_vector(15 downto 0);
--END LED SIGNALS
 
--lpc signals
signal lad_i : std_logic_vector(3 downto 0);
signal lad_o : std_logic_vector(3 downto 0);
signal lad_oe : std_logic;
 
signal lpc_debug : std_logic_vector(31 downto 0);
signal lpc_addr : std_logic_vector(23 downto 0); --shared address
signal lpc_data_o : std_logic_vector(7 downto 0);
signal lpc_data_i : std_logic_vector(7 downto 0);
signal lpc_wr : std_logic; --shared write not read
signal lpc_ack : std_logic;
signal lpc_val : std_logic;
 
 
signal c25_lpc_val : std_logic;
signal c25_lpc_wr : std_logic; --shared write not read
signal c33_lpc_wr : std_logic; --for led debug data latching
 
--End lpc signals
 
--Flash signals
signal mem_addr : std_logic_vector(23 downto 0);
signal mem_do : std_logic_vector(15 downto 0);
signal mem_di : std_logic_vector(15 downto 0);
signal mem_wr : std_logic; --write not read signal
signal mem_val : std_logic;
signal mem_ack : std_logic;
 
signal c33_mem_ack : std_logic; --sync signal
 
 
 
signal fl_ce_n_w : std_logic; --chip select
signal fl_oe_n_w : std_logic; --output enable for flash
 
--END flash signals
 
--USB signals
signal umem_addr : std_logic_vector(23 downto 0);
signal umem_do : std_logic_vector(15 downto 0);
signal umem_wr : std_logic;
signal umem_val : std_logic;
signal umem_ack : std_logic;
signal umem_cmd : std_logic;
signal enable_4meg: std_logic;
--END USB signals
 
begin
 
 
 
--LED SUBSYSTEM START
 
data_to_disp <= x"86"&lpc_debug(7 downto 0); --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
 
--########################################--
--VERSION CONSTATNS
--########################################--
led_red <= enable_4meg;
 
LEDS: led_sys --toplevel for led system
generic map(
msn_hib => "01111111",--8 --Most signif. of hi byte
lsn_hib => "01111101",--6 --Least signif. of hi byte
msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
lsn_lob => "01011011" --2 --Least signif. of hi byte This is version code
)
port map(
clk => sys_clk , -- in std_logic;
reset_n => resetn, -- in std_logic;
led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
);
 
--LED SUBSYSTEM END
 
 
--MAIN DATAPATH CONNECTIONS
--LPC bus logic
lad_i <= lad;
lad <= lad_o when lad_oe='1' and mode/="00" else --mode "00" is post code spy mode
(others=>'Z');
 
--END LPC bus logic
 
LPCBUS : lpc_iow
port map(
--system signals
lreset_n => lreset_n, -- in std_logic;
lclk => lclk, -- in std_logic;
--LPC bus from host
lad_i => lad_i, -- in std_logic_vector(3 downto 0);
lad_o => lad_o, -- out std_logic_vector(3 downto 0);
lad_oe => lad_oe, -- out std_logic;
lframe_n => lframe_n, -- in std_logic;
--memory interface
lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
lpc_wr => lpc_wr, -- out std_logic; --shared write not read
lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
lpc_val => lpc_val, -- out std_logic;
lpc_ack => lpc_ack -- in std_logic
);
 
 
--memory data bus logic
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
(others=>'Z');
mem_di <= (others=>'Z') when c25_lpc_val='1' else
umem_do when umem_val='1' else
(others=>'Z');
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
umem_wr when umem_val='1' else
'0';
mem_val <= c25_lpc_val or umem_val;
 
umem_ack <= mem_ack when umem_val='1' else
'0';
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
mem_do(15 downto 8);
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
'1' when lpc_val='1' and lpc_wr='1' else
'0';
 
 
SYNC1: process (lclk, lreset_n) --c33
begin
if lclk'event and lclk = '1' then -- rising clock edge
c33_mem_ack <= mem_ack;
end if;
end process SYNC1;
SYNC2: process (sys_clk, resetn) --c25
begin
if sys_clk'event and sys_clk = '1' then -- rising clock edge
c25_lpc_val <= lpc_val;
c25_lpc_wr <= lpc_wr;
end if;
end process SYNC2;
 
 
LATCHled: process (lclk,lreset_n) --c33
begin
if lreset_n='0' then
lpc_debug(7 downto 0)<=(others=>'0');
enable_4meg <='0';
c33_lpc_wr <='0';
elsif lclk'event and lclk = '1' then -- rising clock edge
c33_lpc_wr <= lpc_wr; --just for debug delay
if c33_lpc_wr='0' and lpc_wr='1' then
lpc_debug(7 downto 0)<= lpc_data_o;
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"4F" then --Flash 4 Mega enable (LSN is first MSN is second)
enable_4meg <='1';
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"1F" then --Flash 1 Mega enalbe
enable_4meg <='0';
end if;
end if;
end if;
end process LATCHled;
 
 
--END memory data bus logic
fl_ce_n<= fl_ce_n_w;
fl_oe_n<= fl_oe_n_w;
 
FLASH : flash_if
port map(
clk => sys_clk, -- in std_logic;
reset_n => resetn, -- in std_logic;
--flash Bus
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
fl_we_n => fl_we_n, -- out std_logic; --write enable
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
fl_sts => fl_sts, -- in std_logic; --status signal
-- mem Bus
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
mem_wr => mem_wr, -- in std_logic; --write not read signal
mem_val => mem_val, -- in std_logic;
mem_ack => mem_ack -- out std_logic
);
 
--hdr(7 downto 0) <= umem_do(7 downto 0) when umem_ack='0' and umem_wr='1' else
-- umem_do(15 downto 8) when umem_ack='1' and umem_wr='1' else
-- mem_do(7 downto 0) when umem_wr='0' else
-- mem_do(15 downto 8);
--hdr(8)<= umem_wr;
--hdr(9)<= umem_val;
--hdr(10)<= umem_ack;
-- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
-- usb_wr : out std_logic; -- write performed on edge \ of signal
-- usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
-- usb_rxf_n : in std_logic; -- rx fifo has data if low
 
hdr(3 downto 0) <= lad_o when lad_oe='1' else
lad;
hdr(4)<= lframe_n;
hdr(5)<= lreset_n;
hdr(6)<= lclk;
hdr(7)<= lpc_ack;
 
--hdr(7 downto 0) <= lpc_data_o(7 downto 0);
 
hdr(8)<= lpc_val;
hdr(9)<= '1' when lpc_wr='1' and lpc_addr(7 downto 0)=x"88" else
'0';
hdr(10)<= resetn;
 
USB: usb2mem
port map(
clk25 => sys_clk, -- in std_logic;
reset_n => resetn, -- in std_logic;
-- mem Bus
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
mem_wr => umem_wr, -- out std_logic;
mem_val => umem_val, -- out std_logic;
mem_ack => umem_ack, -- in std_logic; --from flash
mem_cmd => umem_cmd, -- out std_logic;
-- USB port
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
);
 
 
--END MAIN DATAPATH CONNECTIONS
 
end rtl;
 
 
 
/flash/flsh_if.vhd
0,0 → 1,127
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity flash_if is
port (
clk : in std_logic;
reset_n : in std_logic;
--flash Bus
fl_addr : out std_logic_vector(23 downto 0);
fl_ce_n : out std_logic; --chip select (timing is very chip dependent)
fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent)
fl_we_n : out std_logic; --write enable (timing is very chip dependent)
fl_data : inout std_logic_vector(15 downto 0);
fl_rp_n : out std_logic; --reset signal
fl_byte_n : out std_logic; --hold in byte mode
fl_sts : in std_logic; --status signal
-- mem Bus
mem_addr : in std_logic_vector(23 downto 0);
mem_do : out std_logic_vector(15 downto 0);
mem_di : in std_logic_vector(15 downto 0);
mem_wr : in std_logic; --write not read signal
mem_val : in std_logic;
mem_ack : out std_logic
);
end flash_if;
 
architecture RTL of flash_if is
type state_type is (RESETs,FLREADs,FLWRITEs,WAITs);
signal CS : state_type;
signal fl_cnt : std_logic_vector(3 downto 0);
signal fl_oe_nd : std_logic; --output enable for flash
begin
 
fl_rp_n <= reset_n; --make flash reset
fl_addr <= mem_addr(23 downto 0);
fl_byte_n <= '0'; --all byte accesses
 
 
fl_oe_n<=fl_oe_nd;
fl_data <= mem_di when fl_oe_nd ='1' else
(others =>'Z');
 
 
RD: process (clk, reset_n)
begin -- process READ
if reset_n='0' then
fl_oe_nd <='1';
CS <= RESETs;
fl_cnt <= (others=>'0');
mem_do <= (others=>'0');
mem_ack <='0';
elsif clk'event and clk = '1' then -- rising clock edge
case CS is
when RESETs =>
mem_ack <='0';
fl_ce_n <= (not mem_val); --chipselect 4 flash
fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash
if mem_val='1' and mem_wr = '0' then --READ
fl_oe_nd <='0';
fl_cnt <= (others=>'0');
CS <= FLREADs;
elsif mem_val='1' and mem_wr = '1' then --WRITE
fl_oe_nd <='1';
fl_cnt <= (others=>'0');
CS <= FLWRITEs;
end if; --elsif mem_cmd
when FLREADs =>
fl_cnt <= fl_cnt + 1;
if fl_cnt=x"3" then --3 cycles later
mem_ack <='1';
mem_do <= fl_data; --registered is nicer
elsif fl_cnt=x"4" then --4 cycles later
mem_ack <='0';
fl_oe_nd <='1';
CS <= WAITs;
end if;
when FLWRITEs =>
fl_cnt <= fl_cnt + 1;
if fl_cnt=x"3" then --3 cycles later
mem_ack <='1';
elsif fl_cnt=x"4" then --4 cycles later
mem_ack <='0';
CS <= WAITs;
end if;
when WAITs =>
if mem_val='0' then -- wait untill val is removed
CS <= RESETs;
end if;
end case;
end if; --system
end process RD;
 
 
 
end RTL;
 

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