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/dongle_syn.pof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/dongle_syn.pof
dongle_syn.pof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: dongle_syn.pin =================================================================== --- dongle_syn.pin (nonexistent) +++ dongle_syn.pin (revision 53) @@ -0,0 +1,203 @@ + -- Copyright (C) 1991-2006 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. This pin can either be left unconnected or + -- connected to GND. Connecting this pin to GND will improve the + -- device's immunity to noise. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + --------------------------------------------------------------------------------- + +Quartus II Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition +CHIP "dongle_syn" ASSIGNED TO AN: EP1C6T144C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +seg_out[6] : 1 : output : LVCMOS : : 1 : Y +seg_out[0] : 2 : output : LVCMOS : : 1 : Y +seg_out[5] : 3 : output : LVCMOS : : 1 : Y +usb_rxf_n : 4 : input : LVCMOS : : 1 : Y +usb_txe_n : 5 : input : LVCMOS : : 1 : Y +usb_wr : 6 : bidir : LVCMOS : : 1 : Y +usb_rd_n : 7 : bidir : LVCMOS : : 1 : Y +VCCIO1 : 8 : power : : 3.3V : 1 : +GND : 9 : gnd : : : : +lclk : 10 : input : LVCMOS : : 1 : Y +mode[0] : 11 : input : LVCMOS : : 1 : Y +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 12 : input : LVCMOS : : 1 : N +DATA0 : 13 : input : : : 1 : +nCONFIG : 14 : : : : 1 : +VCCA_PLL1 : 15 : power : : 1.5V : : +GND+ : 16 : : : : 1 : +GND+ : 17 : : : : 1 : +GNDA_PLL1 : 18 : gnd : : : : +GNDG_PLL1 : 19 : gnd : : : : +nCEO : 20 : : : : 1 : +nCE : 21 : : : : 1 : +MSEL0 : 22 : : : : 1 : +MSEL1 : 23 : : : : 1 : +DCLK : 24 : bidir : : : 1 : +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 25 : input : LVCMOS : : 1 : N +mode[1] : 26 : input : LVCMOS : : 1 : Y +usb_bd[7] : 27 : bidir : LVCMOS : : 1 : Y +usb_bd[6] : 28 : bidir : LVCMOS : : 1 : Y +VCCIO1 : 29 : power : : 3.3V : 1 : +GND : 30 : gnd : : : : +usb_bd[5] : 31 : bidir : LVCMOS : : 1 : Y +usb_bd[4] : 32 : bidir : LVCMOS : : 1 : Y +usb_bd[3] : 33 : bidir : LVCMOS : : 1 : Y +usb_bd[2] : 34 : bidir : LVCMOS : : 1 : Y +usb_bd[1] : 35 : bidir : LVCMOS : : 1 : Y +usb_bd[0] : 36 : bidir : LVCMOS : : 1 : Y +fl_addr[23] : 37 : output : LVCMOS : : 4 : Y +fl_addr[1] : 38 : output : LVCMOS : : 4 : Y +fl_addr[2] : 39 : output : LVCMOS : : 4 : Y +fl_addr[3] : 40 : output : LVCMOS : : 4 : Y +fl_addr[4] : 41 : output : LVCMOS : : 4 : Y +fl_addr[5] : 42 : output : LVCMOS : : 4 : Y +GND : 43 : gnd : : : : +VCCIO4 : 44 : power : : 3.3V : 4 : +GND : 45 : gnd : : : : +VCCINT : 46 : power : : 1.5V : : +fl_addr[6] : 47 : output : LVCMOS : : 4 : Y +fl_addr[7] : 48 : output : LVCMOS : : 4 : Y +fl_addr[8] : 49 : output : LVCMOS : : 4 : Y +fl_addr[9] : 50 : output : LVCMOS : : 4 : Y +fl_ce_n : 51 : output : LVCMOS : : 4 : Y +fl_addr[10] : 52 : output : LVCMOS : : 4 : Y +fl_addr[11] : 53 : output : LVCMOS : : 4 : Y +GND : 54 : gnd : : : : +VCCINT : 55 : power : : 1.5V : : +fl_addr[12] : 56 : output : LVCMOS : : 4 : Y +fl_addr[13] : 57 : output : LVCMOS : : 4 : Y +fl_addr[14] : 58 : output : LVCMOS : : 4 : Y +fl_addr[15] : 59 : output : LVCMOS : : 4 : Y +fl_addr[16] : 60 : output : LVCMOS : : 4 : Y +fl_addr[17] : 61 : output : LVCMOS : : 4 : Y +fl_addr[18] : 62 : output : LVCMOS : : 4 : Y +GND : 63 : gnd : : : : +VCCINT : 64 : power : : 1.5V : : +GND : 65 : gnd : : : : +VCCIO4 : 66 : power : : 3.3V : 4 : +fl_addr[19] : 67 : output : LVCMOS : : 4 : Y +fl_addr[20] : 68 : output : LVCMOS : : 4 : Y +fl_addr[21] : 69 : output : LVCMOS : : 4 : Y +fl_addr[22] : 70 : output : LVCMOS : : 4 : Y +fl_addr[0] : 71 : output : LVCMOS : : 4 : Y +seg_out[7] : 72 : output : LVCMOS : : 4 : N +fl_rp_n : 73 : output : LVCMOS : : 3 : N +hdr[9] : 74 : bidir : LVCMOS : : 3 : Y +hdr[8] : 75 : bidir : LVCMOS : : 3 : Y +hdr[7] : 76 : bidir : LVCMOS : : 3 : Y +hdr[6] : 77 : bidir : LVCMOS : : 3 : Y +hdr[5] : 78 : bidir : LVCMOS : : 3 : Y +hdr[4] : 79 : bidir : LVCMOS : : 3 : Y +GND : 80 : gnd : : : : +VCCIO3 : 81 : power : : 3.3V : 3 : +hdr[3] : 82 : bidir : LVCMOS : : 3 : Y +hdr[2] : 83 : bidir : LVCMOS : : 3 : Y +hdr[1] : 84 : bidir : LVCMOS : : 3 : Y +hdr[0] : 85 : bidir : LVCMOS : : 3 : Y +CONF_DONE : 86 : : : : 3 : +nSTATUS : 87 : : : : 3 : +TCK : 88 : input : : : 3 : +TMS : 89 : input : : : 3 : +TDO : 90 : output : : : 3 : +GNDG_PLL2 : 91 : gnd : : : : +GND+ : 92 : : : : 3 : +sys_clk : 93 : input : LVCMOS : : 3 : Y +VCCA_PLL2 : 94 : power : : 1.5V : : +TDI : 95 : input : : : 3 : +lreset_n : 96 : input : LVCMOS : : 3 : Y +lad[0] : 97 : bidir : LVCMOS : : 3 : Y +lad[2] : 98 : bidir : LVCMOS : : 3 : Y +lad[1] : 99 : bidir : LVCMOS : : 3 : Y +lframe_n : 100 : input : LVCMOS : : 3 : Y +GND : 101 : gnd : : : : +VCCIO3 : 102 : power : : 3.3V : 3 : +lad[3] : 103 : bidir : LVCMOS : : 3 : Y +led_red : 104 : output : LVCMOS : : 3 : Y +led_green : 105 : output : LVCMOS : : 3 : Y +scn_seg[2] : 106 : output : LVCMOS : : 3 : Y +scn_seg[1] : 107 : output : LVCMOS : : 3 : Y +scn_seg[3] : 108 : output : LVCMOS : : 3 : Y +seg_out[1] : 109 : output : LVCMOS : : 2 : Y +seg_out[2] : 110 : output : LVCMOS : : 2 : Y +seg_out[4] : 111 : output : LVCMOS : : 2 : Y +seg_out[3] : 112 : output : LVCMOS : : 2 : Y +scn_seg[0] : 113 : output : LVCMOS : : 2 : Y +fl_we_n : 114 : output : LVCMOS : : 2 : Y +VCCIO2 : 115 : power : : 3.3V : 2 : +GND : 116 : gnd : : : : +VCCINT : 117 : power : : 1.5V : : +GND : 118 : gnd : : : : +fl_oe_n : 119 : output : LVCMOS : : 2 : Y +fl_sts : 120 : input : LVCMOS : : 2 : Y +fl_data[15] : 121 : bidir : LVCMOS : : 2 : Y +fl_data[7] : 122 : bidir : LVCMOS : : 2 : Y +fl_data[14] : 123 : bidir : LVCMOS : : 2 : Y +fl_data[6] : 124 : bidir : LVCMOS : : 2 : Y +fl_data[5] : 125 : bidir : LVCMOS : : 2 : Y +VCCINT : 126 : power : : 1.5V : : +GND : 127 : gnd : : : : +fl_data[13] : 128 : bidir : LVCMOS : : 2 : Y +fl_data[12] : 129 : bidir : LVCMOS : : 2 : Y +fl_data[4] : 130 : bidir : LVCMOS : : 2 : Y +fl_sts_en : 131 : output : LVCMOS : : 2 : Y +fl_data[11] : 132 : bidir : LVCMOS : : 2 : Y +fl_data[3] : 133 : bidir : LVCMOS : : 2 : Y +fl_data[10] : 134 : bidir : LVCMOS : : 2 : Y +VCCINT : 135 : power : : 1.5V : : +GND : 136 : gnd : : : : +VCCIO2 : 137 : power : : 3.3V : 2 : +GND : 138 : gnd : : : : +fl_data[2] : 139 : bidir : LVCMOS : : 2 : Y +fl_data[9] : 140 : bidir : LVCMOS : : 2 : Y +fl_data[1] : 141 : bidir : LVCMOS : : 2 : Y +fl_data[8] : 142 : bidir : LVCMOS : : 2 : Y +fl_data[0] : 143 : bidir : LVCMOS : : 2 : Y +resetn : 144 : input : LVCMOS : : 2 : Y Index: dongle_syn.qsf =================================================================== --- dongle_syn.qsf (nonexistent) +++ dongle_syn.qsf (revision 53) @@ -0,0 +1,167 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# dongle_syn_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name DEVICE EP1C6T144C8 +set_global_assignment -name TOP_LEVEL_ENTITY design_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:34:29 AUGUST 31, 2006" +set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1" +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" +set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_location_assignment PIN_71 -to fl_addr[0] +set_location_assignment PIN_38 -to fl_addr[1] +set_location_assignment PIN_39 -to fl_addr[2] +set_location_assignment PIN_40 -to fl_addr[3] +set_location_assignment PIN_41 -to fl_addr[4] +set_location_assignment PIN_42 -to fl_addr[5] +set_location_assignment PIN_47 -to fl_addr[6] +set_location_assignment PIN_48 -to fl_addr[7] +set_location_assignment PIN_49 -to fl_addr[8] +set_location_assignment PIN_50 -to fl_addr[9] +set_location_assignment PIN_52 -to fl_addr[10] +set_location_assignment PIN_53 -to fl_addr[11] +set_location_assignment PIN_56 -to fl_addr[12] +set_location_assignment PIN_57 -to fl_addr[13] +set_location_assignment PIN_58 -to fl_addr[14] +set_location_assignment PIN_59 -to fl_addr[15] +set_location_assignment PIN_60 -to fl_addr[16] +set_location_assignment PIN_61 -to fl_addr[17] +set_location_assignment PIN_62 -to fl_addr[18] +set_location_assignment PIN_67 -to fl_addr[19] +set_location_assignment PIN_68 -to fl_addr[20] +set_location_assignment PIN_69 -to fl_addr[21] +set_location_assignment PIN_70 -to fl_addr[22] +set_location_assignment PIN_37 -to fl_addr[23] +set_location_assignment PIN_51 -to fl_ce_n +set_location_assignment PIN_143 -to fl_data[0] +set_location_assignment PIN_141 -to fl_data[1] +set_location_assignment PIN_139 -to fl_data[2] +set_location_assignment PIN_133 -to fl_data[3] +set_location_assignment PIN_130 -to fl_data[4] +set_location_assignment PIN_125 -to fl_data[5] +set_location_assignment PIN_124 -to fl_data[6] +set_location_assignment PIN_122 -to fl_data[7] +set_location_assignment PIN_142 -to fl_data[8] +set_location_assignment PIN_140 -to fl_data[9] +set_location_assignment PIN_134 -to fl_data[10] +set_location_assignment PIN_132 -to fl_data[11] +set_location_assignment PIN_129 -to fl_data[12] +set_location_assignment PIN_128 -to fl_data[13] +set_location_assignment PIN_123 -to fl_data[14] +set_location_assignment PIN_121 -to fl_data[15] +set_location_assignment PIN_119 -to fl_oe_n +set_location_assignment PIN_120 -to fl_sts +set_location_assignment PIN_114 -to fl_we_n +set_location_assignment PIN_85 -to hdr[0] +set_location_assignment PIN_84 -to hdr[1] +set_location_assignment PIN_83 -to hdr[2] +set_location_assignment PIN_82 -to hdr[3] +set_location_assignment PIN_79 -to hdr[4] +set_location_assignment PIN_78 -to hdr[5] +set_location_assignment PIN_77 -to hdr[6] +set_location_assignment PIN_76 -to hdr[7] +set_location_assignment PIN_75 -to hdr[8] +set_location_assignment PIN_74 -to hdr[9] +set_location_assignment PIN_97 -to lad[0] +set_location_assignment PIN_99 -to lad[1] +set_location_assignment PIN_98 -to lad[2] +set_location_assignment PIN_103 -to lad[3] +set_location_assignment PIN_10 -to lclk +set_location_assignment PIN_105 -to led_green +set_location_assignment PIN_104 -to led_red +set_location_assignment PIN_100 -to lframe_n +set_location_assignment PIN_96 -to lreset_n +set_location_assignment PIN_144 -to resetn +set_location_assignment PIN_11 -to mode[0] +set_location_assignment PIN_26 -to mode[1] +set_location_assignment PIN_113 -to scn_seg[0] +set_location_assignment PIN_107 -to scn_seg[1] +set_location_assignment PIN_106 -to scn_seg[2] +set_location_assignment PIN_108 -to scn_seg[3] +set_location_assignment PIN_2 -to seg_out[0] +set_location_assignment PIN_109 -to seg_out[1] +set_location_assignment PIN_110 -to seg_out[2] +set_location_assignment PIN_112 -to seg_out[3] +set_location_assignment PIN_111 -to seg_out[4] +set_location_assignment PIN_3 -to seg_out[5] +set_location_assignment PIN_1 -to seg_out[6] +set_location_assignment PIN_93 -to sys_clk +set_location_assignment PIN_36 -to usb_bd[0] +set_location_assignment PIN_35 -to usb_bd[1] +set_location_assignment PIN_34 -to usb_bd[2] +set_location_assignment PIN_33 -to usb_bd[3] +set_location_assignment PIN_32 -to usb_bd[4] +set_location_assignment PIN_31 -to usb_bd[5] +set_location_assignment PIN_28 -to usb_bd[6] +set_location_assignment PIN_27 -to usb_bd[7] +set_location_assignment PIN_7 -to usb_rd_n +set_location_assignment PIN_4 -to usb_rxf_n +set_location_assignment PIN_5 -to usb_txe_n +set_location_assignment PIN_6 -to usb_wr +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1 +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVCMOS +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON +set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id for33 +set_global_assignment -name FMAX_REQUIREMENT "25 MHz" -section_id for25sys +set_instance_assignment -name IO_STANDARD LVCMOS -to lad[0] +set_instance_assignment -name IO_STANDARD LVCMOS -to lad[1] +set_instance_assignment -name IO_STANDARD LVCMOS -to lad[2] +set_instance_assignment -name IO_STANDARD LVCMOS -to lad[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to lad +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to fl_data +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hdr +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to usb_bd +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to fl_addr +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to fl_ce_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to fl_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to fl_rp_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to fl_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_green +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to led_red +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to scn_seg +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to seg_out +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to usb_rd_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to usb_wr +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdr[5] +set_global_assignment -name VHDL_FILE ../src/postcode_ser/fifo.vhd +set_global_assignment -name VHDL_FILE ../src/postcode_ser/pc_serializer.vhd +set_global_assignment -name VHDL_FILE ../src/usb/usb2mem.vhd +set_global_assignment -name VHDL_FILE ../src/lpc_proto/lpc_byte.vhd +set_global_assignment -name VHDL_FILE ../src/flash/flsh_if.vhd +set_global_assignment -name VHDL_FILE ../src/led_sys/led_coder.vhd +set_global_assignment -name VHDL_FILE ../src/led_sys/byte_scan_mux.vhd +set_global_assignment -name VHDL_FILE ../src/led_sys/led_sys.vhd +set_global_assignment -name VHDL_FILE ../src/design_top/design_top_thincandbg.vhd +set_global_assignment -name FMAX_REQUIREMENT "12.5 MHz" -section_id "design_top|pc_serializer:DBG|half_clk" +set_instance_assignment -name CLOCK_SETTINGS for33 -to for33 +set_instance_assignment -name CLOCK_SETTINGS for25sys -to for25sys +set_instance_assignment -name CLOCK_SETTINGS "design_top|pc_serializer:DBG|half_clk" -to "pc_serializer:DBG|half_clk" +set_location_assignment PIN_131 -to fl_sts_en \ No newline at end of file Index: dongle_syn.qws =================================================================== --- dongle_syn.qws (nonexistent) +++ dongle_syn.qws (revision 53) @@ -0,0 +1,86 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +ptn_Child4=Document-3 +ptn_Child5=Document-4 +ptn_Child6=Document-5 +ptn_Child7=Document-6 +ptn_Child8=Document-7 +ptn_Child9=Document-8 +ptn_Child10=Document-9 +ptn_Child11=Document-10 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=../src/lpc_proto/lpc_byte.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPOGAAAAAABJAAAAAAAEDAAAAAGDCAAAAA +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-1] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] +DocPathName=../src/led_sys/byte_scan_mux.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPJMAAAAAAHEAAAAAAMFEAAAAAHLBAAAAA +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-2] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] +DocPathName=../src/led_sys/led_coder.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPEGBAAAAADFAAAAAAHPEAAAAADMBAAAAA +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-3] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0] +DocPathName=../src/postcode_ser/pc_serializer.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPOGAAAAAABJAAAAAALLDAAAAAGECAAAAA +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-4] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-4.ViewFrame-0] +DocPathName=../src/usb/usb2mem.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPEIAAAAAAOKAAAAAABNDAAAAADGCAAAAA +IsActiveChildFrame=True +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-4.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-5] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-5.ViewFrame-0] +DocPathName=../src/design_top/design_top_thincandbg.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPGBAAAAAADCAAAAAAHIDAAAAAPKBAAAAA +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-5.ViewFrame-0.StateMap] +AFC_IN_REPORT=False +[ProjectWorkspace.Frames.ChildFrames.Document-6] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-6.ViewFrame-0] +DocPathName=../src/flash/flsh_if.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPEIAAAAAAOKAAAAAADAEAAAAADICAAAAA +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-6.ViewFrame-0.StateMap] +AFC_IN_REPORT=False Index: dongle_syn.cdf =================================================================== --- dongle_syn.cdf (nonexistent) +++ dongle_syn.cdf (revision 53) @@ -0,0 +1,13 @@ +/* Quartus II Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EPCS1) Path("") File("dongle_syn.pof") MfrSpec(OpMask(3) Child_OpMask(1 0)); + +ChainEnd; + +AlteraBegin; + ChainType(asc); +AlteraEnd; Index: dongle_syn.qpf =================================================================== --- dongle_syn.qpf (nonexistent) +++ dongle_syn.qpf (revision 53) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "6.0" +DATE = "13:34:29 August 31, 2006" + + +# Revisions + +PROJECT_REVISION = "dongle_syn" Index: dongle_syn_assignment_defaults.qdf =================================================================== --- dongle_syn_assignment_defaults.qdf (nonexistent) +++ dongle_syn_assignment_defaults.qdf (revision 53) @@ -0,0 +1,422 @@ +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_IO_BUFFER_CONVERSION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 +set_global_assignment -name DO_MIN_ANALYSIS -value OFF +set_global_assignment -name DO_MIN_TIMING Off +set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off +set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name IGNORE_CLOCK_SETTINGS Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS -value ON +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off +set_global_assignment -name ENABLE_CLOCK_LATENCY Off +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF -value ON +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE -value OFF +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_HCII_COMPARE Off +set_global_assignment -name HCII_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY On +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION On +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_USE_VOLTAGE NOMINAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" +set_global_assignment -name MUX_RESTRUCTURE AUTO +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL93 +set_global_assignment -name FAMILY Stratix +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name REMOVE_DUPLICATE_LOGIC On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME Off +set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO On +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION On +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name IGNORE_DUPLICATE_DESIGN_ENTITY Off +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1" +set_global_assignment -name IGNORE_TRANSLATE_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name ADV_NETLIST_OPT_METASTABLE_REGS 2 +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off +set_global_assignment -name INCREMENTAL_COMPILATION Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" +set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING Off +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT -value "AUTO FIT" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name DRC_REPORT_TOP_FANOUT On +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING On +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name SIGNALRACE_RULE_TRISTATE On +set_global_assignment -name SIGNALRACE_RULE_RESET_RACE On +set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES On +set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM On +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_CAT On +set_global_assignment -name CLK_RULE_COMB_CLOCK On +set_global_assignment -name CLK_RULE_INV_CLOCK On +set_global_assignment -name CLK_RULE_GATING_SCHEME On +set_global_assignment -name CLK_RULE_INPINS_CLKNET On +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES On +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name CLK_RULE_MIX_EDGES On +set_global_assignment -name RESET_CAT On +set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET On +set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET On +set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET On +set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN On +set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN On +set_global_assignment -name TIMING_CAT On +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE On +set_global_assignment -name NONSYNCHSTRUCT_CAT On +set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP On +set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP On +set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN On +set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK On +set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN On +set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR On +set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH On +set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED On +set_global_assignment -name SIGNALRACE_CAT On +set_global_assignment -name ACLK_CAT On +set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN On +set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN On +set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN On +set_global_assignment -name HCPY_CAT On +set_global_assignment -name HCPY_VREF_PINS On +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY -value OFF +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name DUTY_CYCLE 50 -section_id ? +set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? +set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 ns" -section_id ? +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?

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