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    /usb_dongle_fpga/tags/version_1_5/beh
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Rev 45 → Rev 53

/lpc_byte_test.vhd
0,0 → 1,207
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:11 10/09/2006
-- Design Name: lpc_iow
-- Module Name: C:/projects/USB_dongle/beh/lpc_byte_test.vhd
-- Project Name: simulation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: lpc_iow
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY lpc_byte_test_vhd IS
END lpc_byte_test_vhd;
 
ARCHITECTURE behavior OF lpc_byte_test_vhd IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lpc_iow
PORT(
lreset_n : IN std_logic;
lclk : IN std_logic;
lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
lena_reads : in std_logic; --enable read capabilities
lad_i : IN std_logic_vector(3 downto 0);
lframe_n : IN std_logic;
lpc_data_i : IN std_logic_vector(7 downto 0);
lpc_ack : IN std_logic;
lad_o : OUT std_logic_vector(3 downto 0);
lad_oe : OUT std_logic;
lpc_addr : OUT std_logic_vector(23 downto 0);
lpc_wr : OUT std_logic;
lpc_data_o : OUT std_logic_vector(7 downto 0);
lpc_val : OUT std_logic
);
END COMPONENT;
 
--Inputs
SIGNAL lreset_n : std_logic := '0';
SIGNAL lclk : std_logic := '0';
SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
SIGNAL lframe_n : std_logic := '1';
SIGNAL lpc_ack : std_logic := '0';
SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL lpc_data_i : std_logic_vector(7 downto 0) := (others=>'0');
 
--Outputs
SIGNAL lad_o : std_logic_vector(3 downto 0);
SIGNAL lad_oe : std_logic;
SIGNAL lpc_addr : std_logic_vector(23 downto 0);
SIGNAL lpc_wr : std_logic;
SIGNAL lpc_data_o : std_logic_vector(7 downto 0);
SIGNAL lpc_val : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: lpc_iow PORT MAP(
lreset_n => lreset_n,
lclk => lclk,
lena_mem_r=> lena_mem_r,
lena_reads => lena_reads,
lad_i => lad_i,
lad_o => lad_o,
lad_oe => lad_oe,
lframe_n => lframe_n,
lpc_addr => lpc_addr,
lpc_wr => lpc_wr,
lpc_data_i => lpc_data_i,
lpc_data_o => lpc_data_o,
lpc_val => lpc_val,
lpc_ack => lpc_ack
);
 
 
clocker : process is
begin
wait for 15 ns;
lclk <=not (lclk);
end process clocker;
 
 
VCI_ACK : process is
begin
wait until lpc_val='1';
wait for 100 ns;
lpc_ack <='1';
wait until lpc_val='0';
lpc_ack <='0';
end process VCI_ACK;
 
 
tb : PROCESS
BEGIN
 
-- Wait 100 ns for global reset to finish
wait for 500 ns;
lreset_n <='1';
-- Place stimulus here
wait until lclk='0'; --cycle 1
wait until lclk='1';
lad_i <="0000";
lframe_n <='0';
wait until lclk='0'; --cycle 2
wait until lclk='1';
lad_i <="0010"; --LPC IO write
lframe_n <='1';
wait until lclk='0'; --cycle 3
wait until lclk='1';
lad_i <=x"0"; --address nibble 1
wait until lclk='0'; --cycle 4
wait until lclk='1';
lad_i <=x"0"; --address nibble 2
wait until lclk='0'; --cycle 5
wait until lclk='1';
lad_i <=x"8"; --address nibble 3
wait until lclk='0'; --cycle 6
wait until lclk='1';
lad_i <=x"0"; --address nibble 4
wait until lclk='0'; --cycle 7
wait until lclk='1';
lad_i <=x"A"; --data nibble 1
wait until lclk='0'; --cycle 8
wait until lclk='1';
lad_i <=x"5"; --data nibble 2
wait until lclk='0'; --cycle 9
wait until lclk='1';
lad_i <=x"F"; --TAR 1
wait until lclk='0'; --cycle 10
wait until lclk='1';
if lad_oe='0' then --TAR 2
else
report "LPC error found on TAR cycle no 0xF on lad_o";
lframe_n <='0';
end if;
wait until lclk='0'; --cycle 11
wait until lclk='1';
wait until lad_o=x"6";
while(lad_o=x"6") loop
wait until lclk='0'; --cycle 11
wait until lclk='1';
end loop;
if (lad_o=x"0") and lad_oe='1' then --SYNC
else
report "LPC error found on SYNC cycle no 0x0 on lad_o";
lframe_n <='0';
end if;
wait until lclk='0'; --cycle 12
wait until lclk='1';
if (lad_o=x"F") and lad_oe='1' then --TARL 1
else
report "LPC error found on TAR_L cycle no 0xF on lad_o";
lframe_n <='0';
end if;
wait until lclk='0'; --cycle 13
wait until lclk='1';
lad_i <=x"F"; --TARL 2
lframe_n <='1';
wait; -- will wait forever
END PROCESS;
 
END;
/toplevel_usb_test.vhd
0,0 → 1,316
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:17:32 09/28/2006
-- Design Name: design_top
-- Module Name: C:/projects/USB_dongle/beh/toplevel_usb_test.vhd
-- Project Name: simulation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: design_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY toplevel_usb_test_vhd IS
END toplevel_usb_test_vhd;
 
ARCHITECTURE behavior OF toplevel_usb_test_vhd IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT design_top
PORT(
sys_clk : IN std_logic;
resetn : IN std_logic;
hdr : OUT std_logic_vector(10 downto 0);
alt_clk : IN std_logic;
mode : IN std_logic_vector(1 downto 0);
lreset_n : IN std_logic;
lclk : IN std_logic;
fl_sts : IN std_logic;
usb_txe_n : IN std_logic;
usb_rxf_n : IN std_logic;
lad : INOUT std_logic_vector(3 downto 0);
lframe_n : INOUT std_logic;
fl_data : INOUT std_logic_vector(15 downto 0);
usb_bd : INOUT std_logic_vector(7 downto 0);
seg_out : OUT std_logic_vector(7 downto 0);
scn_seg : OUT std_logic_vector(3 downto 0);
led_green : OUT std_logic;
led_red : OUT std_logic;
fl_addr : OUT std_logic_vector(23 downto 0);
fl_ce_n : OUT std_logic;
fl_oe_n : OUT std_logic;
fl_we_n : OUT std_logic;
fl_rp_n : OUT std_logic;
usb_rd_n : OUT std_logic;
usb_wr : OUT std_logic
);
END COMPONENT;
 
--Inputs
SIGNAL sys_clk : std_logic := '0';
SIGNAL resetn : std_logic := '0';
SIGNAL alt_clk : std_logic := '0';
SIGNAL lreset_n : std_logic := '0';
SIGNAL lclk : std_logic := '0';
SIGNAL fl_sts : std_logic := '0';
SIGNAL usb_txe_n : std_logic := '0';
SIGNAL usb_rxf_n : std_logic := '0';
SIGNAL hdr : std_logic_vector(10 downto 0);
SIGNAL mode : std_logic_vector(1 downto 0) := (others=>'0');
 
--BiDirs
SIGNAL lad : std_logic_vector(3 downto 0);
SIGNAL lframe_n : std_logic;
SIGNAL fl_data : std_logic_vector(15 downto 0);
SIGNAL usb_bd : std_logic_vector(7 downto 0);
 
--Outputs
SIGNAL seg_out : std_logic_vector(7 downto 0);
SIGNAL scn_seg : std_logic_vector(3 downto 0);
SIGNAL led_green : std_logic;
SIGNAL led_red : std_logic;
SIGNAL fl_addr : std_logic_vector(23 downto 0);
SIGNAL fl_ce_n : std_logic;
SIGNAL fl_oe_n : std_logic;
SIGNAL fl_we_n : std_logic;
SIGNAL fl_rp_n : std_logic;
SIGNAL usb_rd_n : std_logic;
SIGNAL usb_wr : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: design_top PORT MAP(
sys_clk => sys_clk,
resetn => resetn,
hdr => hdr,
alt_clk => alt_clk,
mode => mode,
lad => lad,
lframe_n => lframe_n,
lreset_n => lreset_n,
lclk => lclk,
seg_out => seg_out,
scn_seg => scn_seg,
led_green => led_green,
led_red => led_red,
fl_addr => fl_addr,
fl_ce_n => fl_ce_n,
fl_oe_n => fl_oe_n,
fl_we_n => fl_we_n,
fl_data => fl_data,
fl_rp_n => fl_rp_n,
fl_sts => fl_sts,
usb_rd_n => usb_rd_n,
usb_wr => usb_wr,
usb_txe_n => usb_txe_n,
usb_rxf_n => usb_rxf_n,
usb_bd => usb_bd
);
 
clocker : process is
begin
wait for 17 ns;
lclk <=not (lclk);
end process clocker;
clocker2 : process is
begin
wait for 20 ns;
sys_clk <=not (sys_clk);
end process clocker2;
 
 
tb : PROCESS
BEGIN
 
-- Wait 100 ns for global reset to finish
wait for 100 ns;
resetn <='1';
lreset_n <='1';
-- Status check COMMAND
usb_rxf_n <='0';
usb_bd <=x"00";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"C5";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A1 COMMAND
wait for 800 ns;
 
-- A0 COMMAND
usb_rxf_n <='0';
usb_bd <=x"02";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"A0";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A0 COMMAND
wait for 800 ns;
 
-- A1 COMMAND
usb_rxf_n <='0';
usb_bd <=x"00";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"A1";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A1 COMMAND
wait for 800 ns;
 
-- A2 COMMAND
usb_rxf_n <='0';
usb_bd <=x"00";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"A2";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A2 COMMAND
wait for 800 ns;
 
-- 98 COMMAND
usb_rxf_n <='0';
usb_bd <=x"00";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"98";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A2 COMMAND
wait for 800 ns;
-- CD COMMAND
usb_rxf_n <='0';
usb_bd <=x"01";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"CD";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END CD COMMAND
wait for 800 ns;
 
-- E8 COMMAND
usb_rxf_n <='0';
usb_bd <=x"01"; --this should mean 2 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"E8";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END E8 COMMAND
wait for 2000 ns;
-- SEND Data count to flash COMMAND
usb_rxf_n <='0';
usb_bd <=x"01"; --this should mean 2 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"00"; --count 00 means 1 word
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END COMMAND
wait for 800 ns;
 
-- SEND raw Data
usb_rxf_n <='0';
usb_bd <=x"CA"; --this should mean 1 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"FE"; --count 00 means 1 word
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END send data
wait for 800 ns;
-- SEND raw Data
usb_rxf_n <='0';
usb_bd <=x"BE"; --this should mean 1 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"CD"; --count 00 means 1 word
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END send data
wait for 800 ns;
wait; -- will wait forever
END PROCESS;
 
END;
/usb_mem_test.vhd
0,0 → 1,271
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:19:29 09/28/2006
-- Design Name: usb2mem
-- Module Name: C:/projects/USB_dongle/beh/usb_mem_test.vhd
-- Project Name: simulation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: usb2mem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY usb_mem_test_vhd IS
END usb_mem_test_vhd;
 
ARCHITECTURE behavior OF usb_mem_test_vhd IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT usb2mem
PORT(
clk25 : IN std_logic;
reset_n : IN std_logic;
mem_di : IN std_logic_vector(15 downto 0);
mem_ack : IN std_logic;
usb_txe_n : IN std_logic;
usb_rxf_n : IN std_logic;
usb_bd : INOUT std_logic_vector(7 downto 0);
mem_addr : OUT std_logic_vector(23 downto 0);
mem_do : OUT std_logic_vector(15 downto 0);
mem_wr : OUT std_logic;
mem_val : OUT std_logic;
mem_cmd : OUT std_logic;
usb_rd_n : OUT std_logic;
usb_wr : OUT std_logic
);
END COMPONENT;
 
--Inputs
SIGNAL clk25 : std_logic := '0';
SIGNAL reset_n : std_logic := '0';
SIGNAL mem_ack : std_logic := '0';
SIGNAL usb_txe_n : std_logic := '0';
SIGNAL usb_rxf_n : std_logic := '1';
SIGNAL mem_di : std_logic_vector(15 downto 0) := x"3210";
 
--BiDirs
SIGNAL usb_bd : std_logic_vector(7 downto 0);
 
--Outputs
SIGNAL mem_addr : std_logic_vector(23 downto 0);
SIGNAL mem_do : std_logic_vector(15 downto 0);
SIGNAL mem_wr : std_logic;
SIGNAL mem_val : std_logic;
SIGNAL mem_cmd : std_logic;
SIGNAL usb_rd_n : std_logic;
SIGNAL usb_wr : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: usb2mem PORT MAP(
clk25 => clk25,
reset_n => reset_n,
mem_addr => mem_addr,
mem_do => mem_do,
mem_di => mem_di,
mem_wr => mem_wr,
mem_val => mem_val,
mem_ack => mem_ack,
mem_cmd => mem_cmd,
usb_rd_n => usb_rd_n,
usb_wr => usb_wr,
usb_txe_n => usb_txe_n,
usb_rxf_n => usb_rxf_n,
usb_bd => usb_bd
);
 
clocker : process is
begin
wait for 20 ns;
clk25 <=not (clk25);
end process clocker;
 
 
VCI_ACK : process is
begin
wait until mem_val='1';
wait for 100 ns;
mem_ack <='1';
wait until mem_val='0';
mem_ack <='0';
end process VCI_ACK;
 
 
tb : PROCESS
BEGIN
 
-- Wait 100 ns for global reset to finish
wait for 100 ns;
reset_n <='1';
-- STATUS CHECK COMMAND
usb_rxf_n <='0';
usb_bd <=x"C5";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END STATUS CHECK COMMAND
wait for 800 ns;
 
-- A0 COMMAND
usb_rxf_n <='0';
usb_bd <=x"02";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"A0";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A0 COMMAND
wait for 800 ns;
 
-- A1 COMMAND
usb_rxf_n <='0';
usb_bd <=x"00";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"A1";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A1 COMMAND
wait for 800 ns;
 
-- A2 COMMAND
usb_rxf_n <='0';
usb_bd <=x"00";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"A2";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END A2 COMMAND
wait for 800 ns;
-- CD COMMAND
usb_rxf_n <='0';
usb_bd <=x"01";
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"CD";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END CD COMMAND
wait for 800 ns;
 
-- E8 COMMAND
usb_rxf_n <='0';
usb_bd <=x"01"; --this should mean 2 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"E8";
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END E8 COMMAND
wait for 2000 ns;
-- SEND Data count to flash COMMAND
usb_rxf_n <='0';
usb_bd <=x"01"; --this should mean 2 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"00"; --count 00 means 1 word
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END COMMAND
wait for 800 ns;
 
-- SEND raw Data
usb_rxf_n <='0';
usb_bd <=x"CA"; --this should mean 1 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"FE"; --count 00 means 1 word
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END send data
wait for 800 ns;
-- SEND raw Data
usb_rxf_n <='0';
usb_bd <=x"BE"; --this should mean 1 word to write
wait until usb_rd_n='0'; --wait to go low --first read
wait until usb_rd_n='1'; --wait to go low
wait for 20 ns;
usb_bd <=x"CD"; --count 00 means 1 word
wait until usb_rd_n='0'; --wait to go low --second read
wait until usb_rd_n='1'; --wait to go low
usb_bd <=(others=>'Z');
usb_rxf_n <='1';
-- END send data
wait for 800 ns;
wait; -- will wait forever
END PROCESS;
 
END;

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