URL
https://opencores.org/ocsvn/usb_dongle_fpga/usb_dongle_fpga/trunk
Subversion Repositories usb_dongle_fpga
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- This comparison shows the changes necessary to convert path
/usb_dongle_fpga/tags/version_1_5/src/led_sys
- from Rev 45 to Rev 53
- ↔ Reverse comparison
Rev 45 → Rev 53
/led_sys.vhd
0,0 → 1,169
------------------------------------------------------------------ |
-- Universal dongle board source code |
-- |
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee> |
-- |
-- This source code is free hardware; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
-- License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- |
-- This source code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public |
-- License along with this library; if not, write to the Free Software |
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
-- |
-- |
-- The complete text of the GNU Lesser General Public License can be found in |
-- the file 'lesser.txt'. |
|
|
-- bit 0,A |
-- ---------- |
-- | | |
-- | | |
-- 5,F| | 1,B |
-- | 6,G | |
-- ---------- |
-- | | |
-- | | |
-- 4,E| | 2,C |
-- | 3,D | |
-- ---------- |
-- # 7,H |
|
|
-- Select signal order |
-- --- --- --- --- |
-- | | | | | | | | |
-- | | | | | | | | |
-- --- --- --- --- |
-- | | | | | | | | |
-- | | | | | | | | |
-- --- --- --- --- |
-- sel(3) sel(2) sel(1) sel(0) |
|
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.std_logic_arith.all; |
|
|
entity led_sys is --toplevel for led system |
generic( |
msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte |
lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte |
msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte |
lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte |
); |
port ( |
clk : in std_logic; |
reset_n : in std_logic; |
led_data_i : in std_logic_vector(15 downto 0); --binary data in |
seg_out : out std_logic_vector(7 downto 0); --one segment out |
sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low |
); |
end led_sys; |
|
architecture rtl of led_sys is |
|
component led_coder |
port ( |
led_data_i : in std_logic_vector(7 downto 0); |
hi_seg : out std_logic_vector(7 downto 0); |
lo_seg : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component byte_scan |
port ( |
clk : in std_logic; |
hi_seg_1 : in std_logic_vector(7 downto 0); |
lo_seg_1 : in std_logic_vector(7 downto 0); |
hi_seg_0 : in std_logic_vector(7 downto 0); |
lo_seg_0 : in std_logic_vector(7 downto 0); |
seg_out : out std_logic_vector(7 downto 0); |
sel_out : out std_logic_vector(3 downto 0) |
); |
end component; |
|
|
-- input signals |
signal hi_seg1 : std_logic_vector(7 downto 0); |
signal lo_seg1 : std_logic_vector(7 downto 0); |
signal hi_seg0 : std_logic_vector(7 downto 0); |
signal lo_seg0 : std_logic_vector(7 downto 0); |
|
--data containing signals |
signal data_hi_seg1 : std_logic_vector(7 downto 0); |
signal data_lo_seg1 : std_logic_vector(7 downto 0); |
signal data_hi_seg0 : std_logic_vector(7 downto 0); |
signal data_lo_seg0 : std_logic_vector(7 downto 0); |
|
--constant display |
signal cons_hi_seg1 : std_logic_vector(7 downto 0); |
signal cons_lo_seg1 : std_logic_vector(7 downto 0); |
signal cons_hi_seg0 : std_logic_vector(7 downto 0); |
signal cons_lo_seg0 : std_logic_vector(7 downto 0); |
|
signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation |
|
begin -- rtl |
---------------------------HGFEDCBA |
cons_hi_seg1 <= msn_hib;--"01111111"; --8 |
cons_lo_seg1 <= lsn_hib;--"01111101"; --6 |
cons_hi_seg0 <= msn_lob;--"01011100"; -- small o |
cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o |
|
|
|
|
process (clk) --enable the scanning while in reset |
begin -- process |
if clk'event and clk = '0' then -- rising clock edge |
disp_cnt <= disp_cnt + 1; |
end if; |
end process; |
|
LED_CODE0: led_coder |
port map( |
led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0); |
hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0); |
lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0) |
); |
|
LED_CODE1: led_coder |
port map( |
led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0); |
hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0); |
lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0) |
); |
|
|
lo_seg1 <= data_hi_seg1 when reset_n='1' else cons_hi_seg1; |
hi_seg1 <= data_lo_seg1 when reset_n='1' else cons_lo_seg1; |
|
lo_seg0 <= data_hi_seg0 when reset_n='1' else cons_hi_seg0; |
hi_seg0 <= data_lo_seg0 when reset_n='1' else cons_lo_seg0; |
|
SCAN : byte_scan |
port map( |
clk => disp_cnt(15), -- in std_logic; |
hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0); |
lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0); |
hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0); |
lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0); |
seg_out => seg_out, -- out std_logic_vector(7 downto 0); |
sel_out => sel_out -- out std_logic_vector(3 downto 0) |
); |
|
|
|
|
end rtl; |
/byte_scan_mux.vhd
0,0 → 1,111
------------------------------------------------------------------ |
-- Universal dongle board source code |
-- |
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee> |
-- |
-- This source code is free hardware; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
-- License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- |
-- This source code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public |
-- License along with this library; if not, write to the Free Software |
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
-- |
-- |
-- The complete text of the GNU Lesser General Public License can be found in |
-- the file 'lesser.txt'. |
|
|
|
-- bit 0,A |
-- ---------- |
-- | | |
-- | | |
-- 5,F| | 1,B |
-- | 6,G | |
-- ---------- |
-- | | |
-- | | |
-- 4,E| | 2,C |
-- | 3,D | |
-- ---------- |
-- # 7,H |
|
|
-- Select signal order |
-- --- --- --- --- |
-- | | | | | | | | |
-- | | | | | | | | |
-- --- --- --- --- |
-- | | | | | | | | |
-- | | | | | | | | |
-- --- --- --- --- |
-- sel(3) sel(2) sel(1) sel(0) |
|
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.std_logic_arith.all; |
|
|
entity byte_scan is |
port ( |
clk : in std_logic; |
hi_seg_1 : in std_logic_vector(7 downto 0); |
lo_seg_1 : in std_logic_vector(7 downto 0); |
hi_seg_0 : in std_logic_vector(7 downto 0); |
lo_seg_0 : in std_logic_vector(7 downto 0); |
seg_out : out std_logic_vector(7 downto 0); |
sel_out : out std_logic_vector(3 downto 0) |
); |
end byte_scan; |
|
architecture rtl of byte_scan is |
|
signal sel_p : std_logic_vector(3 downto 0); |
signal count : std_logic_vector(1 downto 0):="00"; |
signal hi_seg_1_3 : std_logic_vector(7 downto 0); |
signal lo_seg_1_3 : std_logic_vector(7 downto 0); |
signal hi_seg_0_2 : std_logic_vector(7 downto 0); |
signal lo_seg_0_2 : std_logic_vector(7 downto 0); |
|
begin -- rtl |
|
|
hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3; |
lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3; |
hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2; |
lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2; |
|
|
seg_out <=hi_seg_1_3 when count="01" else |
lo_seg_1_3 when count="10" else |
hi_seg_0_2 when count="11" else |
lo_seg_0_2 when count="00"; |
|
sel_out <= sel_p; |
|
sel_p <= "1110" when count="00" else |
"0111" when count="01" else |
"1011" when count="10" else |
"1101" when count="11"; |
|
|
|
|
process (clk) --enable the scanning while in reset (simulation will be incorrect) |
begin -- process |
if clk'event and clk = '1' then -- rising clock edge |
count <= count + 1; |
end if; |
end process; |
|
end rtl; |
/led_coder.vhd
0,0 → 1,112
------------------------------------------------------------------ |
-- Universal dongle board source code |
-- |
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee> |
-- |
-- This source code is free hardware; you can redistribute it and/or |
-- modify it under the terms of the GNU Lesser General Public |
-- License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- |
-- This source code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public |
-- License along with this library; if not, write to the Free Software |
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
-- |
-- |
-- The complete text of the GNU Lesser General Public License can be found in |
-- the file 'lesser.txt'. |
|
|
-- bit 0,A |
-- ---------- |
-- | | |
-- | | |
-- 5,F| | 1,B |
-- | 6,G | |
-- ---------- |
-- | | |
-- | | |
-- 4,E| | 2,C |
-- | 3,D | |
-- ---------- |
-- # 7,H |
|
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.std_logic_arith.all; |
|
|
entity led_coder is |
port ( |
led_data_i : in std_logic_vector(7 downto 0); |
hi_seg : out std_logic_vector(7 downto 0); |
lo_seg : out std_logic_vector(7 downto 0) |
); |
end led_coder; |
|
architecture rtl of led_coder is |
signal r_led_data : std_logic_vector(7 downto 0); |
signal decoded_lo,decoded_hi : std_logic_vector(7 downto 0); |
|
begin -- rtl |
hi_seg <= decoded_hi; |
lo_seg <= decoded_lo; |
|
-- purpose: binary to led segments decoder |
-- type : combinational |
-- inputs : nibble,reset |
-- outputs: |
decode_nibble_lo: process (led_data_i) |
begin -- process decode_nibble |
case led_data_i(3 downto 0) is--HGFEDCBA |
when "0000" => decoded_lo <= "00111111"; -- 0 |
when "0001" => decoded_lo <= "00000110"; -- 1 |
when "0010" => decoded_lo <= "01011011"; -- 2 |
when "0011" => decoded_lo <= "01001111"; -- 3 |
when "0100" => decoded_lo <= "01100110"; -- 4 |
when "0101" => decoded_lo <= "01101101"; -- 5 |
when "0110" => decoded_lo <= "01111101"; -- 6 |
when "0111" => decoded_lo <= "00000111"; -- 7 |
when "1000" => decoded_lo <= "01111111"; -- 8 |
when "1001" => decoded_lo <= "01101111"; -- 9 |
when "1010" => decoded_lo <= "01110111"; -- a |
when "1011" => decoded_lo <= "01111100"; -- b |
when "1100" => decoded_lo <= "00111001"; -- c |
when "1101" => decoded_lo <= "01011110"; -- d |
when "1110" => decoded_lo <= "01111001"; -- e |
when others => decoded_lo <= "01110001"; -- f |
end case; |
end process decode_nibble_lo; |
|
decode_nibble_hi: process (led_data_i) |
begin -- process decode_nibble |
case led_data_i(7 downto 4) is--HGFEDCBA |
when "0000" => decoded_hi <= "00111111"; -- 0 |
when "0001" => decoded_hi <= "00000110"; -- 1 |
when "0010" => decoded_hi <= "01011011"; -- 2 |
when "0011" => decoded_hi <= "01001111"; -- 3 |
when "0100" => decoded_hi <= "01100110"; -- 4 |
when "0101" => decoded_hi <= "01101101"; -- 5 |
when "0110" => decoded_hi <= "01111101"; -- 6 |
when "0111" => decoded_hi <= "00000111"; -- 7 |
when "1000" => decoded_hi <= "01111111"; -- 8 |
when "1001" => decoded_hi <= "01101111"; -- 9 |
when "1010" => decoded_hi <= "01110111"; -- a |
when "1011" => decoded_hi <= "01111100"; -- b |
when "1100" => decoded_hi <= "00111001"; -- c |
when "1101" => decoded_hi <= "01011110"; -- d |
when "1110" => decoded_hi <= "01111001"; -- e |
when others => decoded_hi <= "01110001"; -- f |
end case; |
end process decode_nibble_hi; |
|
|
end rtl; |