URL
https://opencores.org/ocsvn/usb_dongle_fpga/usb_dongle_fpga/trunk
Subversion Repositories usb_dongle_fpga
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb_dongle_fpga/tags/version_1_5/src/postcode_ser
- from Rev 45 to Rev 53
- ↔ Reverse comparison
Rev 45 → Rev 53
/fifo_waveforms.html
0,0 → 1,13
<html> |
<head> |
<title>Sample Waveforms for fifo.vhd </title> |
</head> |
<body> |
<h2><CENTER>Sample behavioral waveforms for design file fifo.vhd </CENTER></h2> |
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design fifo.vhd. The design fifo.vhd has a depth of 8192 words of 8 bits each. The output of the fifo is registered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P> |
<CENTER><img src=fifo_wave0.jpg> </CENTER> |
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P> |
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P> |
<P></P> |
</body> |
</html> |
/fifo_inst.vhd
0,0 → 1,12
fifo_inst : fifo PORT MAP ( |
aclr => aclr_sig, |
clock => clock_sig, |
data => data_sig, |
rdreq => rdreq_sig, |
wrreq => wrreq_sig, |
almost_full => almost_full_sig, |
empty => empty_sig, |
full => full_sig, |
q => q_sig, |
usedw => usedw_sig |
); |
/fifo.cmp
0,0 → 1,30
--Copyright (C) 1991-2006 Altera Corporation |
--Your use of Altera Corporation's design tools, logic functions |
--and other software and tools, and its AMPP partner logic |
--functions, and any output files any of the foregoing |
--(including device programming or simulation files), and any |
--associated documentation or information are expressly subject |
--to the terms and conditions of the Altera Program License |
--Subscription Agreement, Altera MegaCore Function License |
--Agreement, or other applicable license agreement, including, |
--without limitation, that your use is for the sole purpose of |
--programming logic devices manufactured by Altera and sold by |
--Altera or its authorized distributors. Please refer to the |
--applicable agreement for further details. |
|
|
component fifo |
PORT |
( |
aclr : IN STD_LOGIC ; |
clock : IN STD_LOGIC ; |
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); |
rdreq : IN STD_LOGIC ; |
wrreq : IN STD_LOGIC ; |
almost_full : OUT STD_LOGIC ; |
empty : OUT STD_LOGIC ; |
full : OUT STD_LOGIC ; |
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); |
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0) |
); |
end component; |
/fifo.vhd
0,0 → 1,201
-- megafunction wizard: %LPM_FIFO+% |
-- GENERATION: STANDARD |
-- VERSION: WM1.0 |
-- MODULE: scfifo |
|
-- ============================================================ |
-- File Name: fifo.vhd |
-- Megafunction Name(s): |
-- scfifo |
-- ============================================================ |
-- ************************************************************ |
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
-- |
-- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition |
-- ************************************************************ |
|
|
--Copyright (C) 1991-2006 Altera Corporation |
--Your use of Altera Corporation's design tools, logic functions |
--and other software and tools, and its AMPP partner logic |
--functions, and any output files any of the foregoing |
--(including device programming or simulation files), and any |
--associated documentation or information are expressly subject |
--to the terms and conditions of the Altera Program License |
--Subscription Agreement, Altera MegaCore Function License |
--Agreement, or other applicable license agreement, including, |
--without limitation, that your use is for the sole purpose of |
--programming logic devices manufactured by Altera and sold by |
--Altera or its authorized distributors. Please refer to the |
--applicable agreement for further details. |
|
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
LIBRARY altera_mf; |
USE altera_mf.all; |
|
ENTITY fifo IS |
PORT |
( |
aclr : IN STD_LOGIC ; |
clock : IN STD_LOGIC ; |
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); |
rdreq : IN STD_LOGIC ; |
wrreq : IN STD_LOGIC ; |
almost_full : OUT STD_LOGIC ; |
empty : OUT STD_LOGIC ; |
full : OUT STD_LOGIC ; |
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); |
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0) |
); |
END fifo; |
|
|
ARCHITECTURE SYN OF fifo IS |
|
SIGNAL sub_wire0 : STD_LOGIC ; |
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (12 DOWNTO 0); |
SIGNAL sub_wire2 : STD_LOGIC ; |
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); |
SIGNAL sub_wire4 : STD_LOGIC ; |
|
|
|
COMPONENT scfifo |
GENERIC ( |
add_ram_output_register : STRING; |
almost_full_value : NATURAL; |
intended_device_family : STRING; |
lpm_numwords : NATURAL; |
lpm_showahead : STRING; |
lpm_type : STRING; |
lpm_width : NATURAL; |
lpm_widthu : NATURAL; |
overflow_checking : STRING; |
underflow_checking : STRING; |
use_eab : STRING |
); |
PORT ( |
almost_full : OUT STD_LOGIC ; |
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); |
rdreq : IN STD_LOGIC ; |
empty : OUT STD_LOGIC ; |
aclr : IN STD_LOGIC ; |
clock : IN STD_LOGIC ; |
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); |
wrreq : IN STD_LOGIC ; |
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); |
full : OUT STD_LOGIC |
); |
END COMPONENT; |
|
BEGIN |
almost_full <= sub_wire0; |
usedw <= sub_wire1(12 DOWNTO 0); |
empty <= sub_wire2; |
q <= sub_wire3(7 DOWNTO 0); |
full <= sub_wire4; |
|
scfifo_component : scfifo |
GENERIC MAP ( |
add_ram_output_register => "ON", |
almost_full_value => 8000, |
intended_device_family => "Cyclone", |
lpm_numwords => 8192, |
lpm_showahead => "OFF", |
lpm_type => "scfifo", |
lpm_width => 8, |
lpm_widthu => 13, |
overflow_checking => "ON", |
underflow_checking => "ON", |
use_eab => "ON" |
) |
PORT MAP ( |
rdreq => rdreq, |
aclr => aclr, |
clock => clock, |
wrreq => wrreq, |
data => data, |
almost_full => sub_wire0, |
usedw => sub_wire1, |
empty => sub_wire2, |
q => sub_wire3, |
full => sub_wire4 |
); |
|
|
|
END SYN; |
|
-- ============================================================ |
-- CNX file retrieval info |
-- ============================================================ |
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" |
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" |
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1" |
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "8000" |
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" |
-- Retrieval info: PRIVATE: Clock NUMERIC "0" |
-- Retrieval info: PRIVATE: Depth NUMERIC "8192" |
-- Retrieval info: PRIVATE: Empty NUMERIC "1" |
-- Retrieval info: PRIVATE: Full NUMERIC "1" |
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" |
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" |
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" |
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" |
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" |
-- Retrieval info: PRIVATE: Optimize NUMERIC "1" |
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
-- Retrieval info: PRIVATE: UsedW NUMERIC "1" |
-- Retrieval info: PRIVATE: Width NUMERIC "8" |
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" |
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" |
-- Retrieval info: PRIVATE: rsFull NUMERIC "1" |
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" |
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" |
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" |
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" |
-- Retrieval info: PRIVATE: wsFull NUMERIC "1" |
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" |
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON" |
-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "8000" |
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" |
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192" |
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" |
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" |
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13" |
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
-- Retrieval info: CONSTANT: USE_EAB STRING "ON" |
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr |
-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full |
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock |
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] |
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty |
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full |
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] |
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq |
-- Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0] |
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq |
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 |
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 |
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 |
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 |
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 |
-- Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0 |
-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 |
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_waveforms.html TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wave*.jpg FALSE |
/fifo_wave0.jpg
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
fifo_wave0.jpg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pc_serializer.vhd
===================================================================
--- pc_serializer.vhd (nonexistent)
+++ pc_serializer.vhd (revision 53)
@@ -0,0 +1,327 @@
+------------------------------------------------------------------
+-- Universal dongle board source code
+--
+-- Copyright (C) 2006 Artec Design
+--
+-- This source code is free hardware; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+--
+-- This source code is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+--
+--
+-- The complete text of the GNU Lesser General Public License can be found in
+-- the file 'lesser.txt'.
+
+
+
+----------------------------------------------------------------------------------
+-- Company: ArtecDesign
+-- Engineer: Jüri Toomessoo
+--
+-- Create Date: 12:57:23 28/02/2008
+-- Design Name: Postcode serial pipe Hardware
+-- Module Name: pc_serializer - rtl
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pc_serializer is
+ Port ( --system signals
+ sys_clk : in STD_LOGIC;
+ resetn : in STD_LOGIC;
+ --postcode data port
+ dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
+ dbg_wr : in STD_LOGIC; --write not read
+ dbg_full : out STD_LOGIC; --write not read
+ dbg_almost_full : out STD_LOGIC;
+ dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
+ --debug USB port
+ dbg_usb_mode_en: in std_logic; -- enable this debug mode
+ dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
+ dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
+ dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
+);
+
+end pc_serializer;
+
+architecture rtl of pc_serializer is
+
+ component fifo
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
+
+ );
+ end component;
+
+
+
+ --type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
+ signal CS : std_logic_vector(8 downto 0);--state;
+ signal RETS : std_logic_vector(8 downto 0); --state;
+ signal next_char : std_logic_vector(7 downto 0); --bus data
+ signal ascii_char : std_logic_vector(7 downto 0); --bus data
+ signal in_nibble : std_logic_vector(3 downto 0); --bus data
+ signal usb_send_char : std_logic_vector(7 downto 0); --bus data
+
+ signal count : std_logic_vector(3 downto 0); --internal counter
+ signal dly_count : std_logic_vector(15 downto 0); --internal counter
+ signal dbg_wr_pulse : std_logic; --active reset
+ signal dbg_wrd : std_logic; --active reset
+ signal dbg_wr_len : std_logic; --active reset
+ signal usb_send : std_logic; --active reset
+
+
+ signal rdreq_sig : std_logic; --active reset
+ signal empty_sig : std_logic; --active reset
+ signal full_sig : std_logic; --active reset
+ signal almost_full : std_logic; --active reset
+
+ signal q_sig : std_logic_vector(7 downto 0); --bus data
+
+ signal reset : std_logic; --active reset
+ signal half_clk : std_logic; --active reset
+
+
+ --RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
+ constant RESETs: std_logic_vector(8 downto 0) := "000000001"; -- char /n
+ constant HEXMARKs: std_logic_vector(8 downto 0) := "000000010"; -- char /n
+ constant MSNIBBLEs: std_logic_vector(8 downto 0) := "000000100"; -- char /n
+ constant LSNIBBLEs: std_logic_vector(8 downto 0) := "000001000"; -- char /n
+ constant LINEFDs: std_logic_vector(8 downto 0) := "000010000"; -- char /n
+ constant CRs: std_logic_vector(8 downto 0) := "000100000"; -- char /n
+ constant START_WRITEs: std_logic_vector(8 downto 0):= "001000000"; -- char /n
+ constant WAITs: std_logic_vector(8 downto 0) := "010000000"; -- char /n
+ constant END_WRITEs: std_logic_vector(8 downto 0) := "100000000"; -- char /n
+
+
+ constant CHAR_LF : std_logic_vector(7 downto 0):= x"0A"; -- char /n
+ constant CHAR_CR : std_logic_vector(7 downto 0):= x"0D"; -- char /n
+ constant CHAR_SP : std_logic_vector(7 downto 0):= x"20"; -- space
+ constant CHAR_ux : std_logic_vector(7 downto 0):= x"58"; -- fifo full hex marker --upper case x
+ constant CHAR_x : std_logic_vector(7 downto 0):= x"78"; -- regular hex marker
+ constant CHAR_0 : std_logic_vector(7 downto 0):= x"30";
+ constant CHAR_1 : std_logic_vector(7 downto 0):= x"31";
+ constant CHAR_2 : std_logic_vector(7 downto 0):= x"32";
+ constant CHAR_3 : std_logic_vector(7 downto 0):= x"33";
+ constant CHAR_4 : std_logic_vector(7 downto 0):= x"34";
+ constant CHAR_5 : std_logic_vector(7 downto 0):= x"35";
+ constant CHAR_6 : std_logic_vector(7 downto 0):= x"36";
+ constant CHAR_7 : std_logic_vector(7 downto 0):= x"37";
+ constant CHAR_8 : std_logic_vector(7 downto 0):= x"38";
+ constant CHAR_9 : std_logic_vector(7 downto 0):= x"39";
+ constant CHAR_a : std_logic_vector(7 downto 0):= x"41";
+ constant CHAR_b : std_logic_vector(7 downto 0):= x"42";
+ constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
+ constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
+ constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
+ constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
+
+
+
+begin
+
+ ascii_char <=CHAR_0 when in_nibble = x"0" else
+ CHAR_1 when in_nibble = x"1" else
+ CHAR_2 when in_nibble = x"2" else
+ CHAR_3 when in_nibble = x"3" else
+ CHAR_4 when in_nibble = x"4" else
+ CHAR_5 when in_nibble = x"5" else
+ CHAR_6 when in_nibble = x"6" else
+ CHAR_7 when in_nibble = x"7" else
+ CHAR_8 when in_nibble = x"8" else
+ CHAR_9 when in_nibble = x"9" else
+ CHAR_a when in_nibble = x"a" else
+ CHAR_b when in_nibble = x"b" else
+ CHAR_c when in_nibble = x"c" else
+ CHAR_d when in_nibble = x"d" else
+ CHAR_e when in_nibble = x"e" else
+ CHAR_f when in_nibble = x"f";
+
+
+
+ dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else
+ (others=>'Z');
+
+ dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else
+ 'Z';
+
+ SER_SM: process (sys_clk,resetn)
+ begin -- process
+
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ if resetn='0' then --active low reset
+ CS<= RESETs;
+ in_nibble <= (others=>'0');
+ usb_send_char <= (others=>'0');
+ dly_count<= (others=>'0');
+ usb_send <='0';
+ RETS <= RESETs;
+ rdreq_sig <='0';
+ count<= (others=>'1');
+ else
+ case CS is
+ when RESETs => ----------------------------------------------------------
+
+ if empty_sig ='0' and dbg_usb_txe_n='0' and dbg_usb_mode_en='1' then --is, can and may send
+ rdreq_sig <='1';
+ count <= count + 1;
+ RETS <= HEXMARKs;
+ dly_count <= x"000F";
+ CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
+ else
+ usb_send <='0';
+ rdreq_sig <='0';
+ CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
+ end if;
+ when HEXMARKs => ----------------------------------------------------------
+ rdreq_sig <='0'; --data will be ready on output 'till next read request
+ --if almost_full='0' then
+ usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
+ --else
+ -- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
+ --end if;
+ in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
+ RETS <= MSNIBBLEs;
+ CS <= START_WRITEs;
+ when MSNIBBLEs => ----------------------------------------------------------
+ usb_send_char <= ascii_char; --put MS nibble to output
+ in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
+ RETS <= LSNIBBLEs;
+ CS <= START_WRITEs;
+ when LSNIBBLEs => ----------------------------------------------------------
+ usb_send_char <= ascii_char; --put MS nibble to output
+ if count = x"f" then
+ RETS <= CRs;
+ else
+ RETS <= LINEFDs;
+ end if;
+ CS <= START_WRITEs;
+ when CRs => ----------------------------------------------------------
+ --if count = x"f" then
+ usb_send_char <= CHAR_CR; --put line feed
+ --else
+ -- usb_send_char <= CHAR_SP; --put space
+ --end if;
+ RETS <= LINEFDs;
+ CS <= START_WRITEs;
+ when LINEFDs => ----------------------------------------------------------
+ if count = x"f" then
+ usb_send_char <= CHAR_LF; --put line feed
+ else
+ usb_send_char <= CHAR_SP; --put space
+ end if;
+ RETS <= RESETs;
+ CS <= START_WRITEs;
+
+ when START_WRITEs => ----------------------------------------------------------
+ if dly_count /= x"0004" then
+ if dbg_usb_txe_n='0' then
+ usb_send <='1';
+ dly_count <= dly_count + 1;
+ else
+ usb_send <='0'; --remove send signal when txe is falsely asserted
+ end if;
+ else
+ usb_send <='0';
+ CS <= WAITs;
+ end if;
+ when WAITs => ----------------------------------------------------------
+ usb_send <='0';
+ CS <= END_WRITEs;
+ when END_WRITEs => ----------------------------------------------------------
+ rdreq_sig <='0'; --used as intermeadiate cheat state when exiting resets
+ if dly_count /= x"000F" then
+ if dbg_usb_txe_n='0' then
+ dly_count <= dly_count + 1;
+ end if;
+ else
+ dly_count <= (others=>'0');
+ CS <= RETS;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process SER_SM;
+
+
+ SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
+ begin -- process
+ if sys_clk'event and sys_clk = '1' then -- rising clock edge
+ if resetn='0' then --active low reset
+ dbg_wr_pulse <='0';
+ dbg_wr_len <='0';
+ dbg_wrd <='0';
+ else
+ dbg_wrd <= dbg_wr;
+ if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
+ dbg_wr_pulse <='1';
+ else
+ dbg_wr_pulse <='0';
+ end if;
+ end if;
+ end if;
+ end process SYNCER;
+
+
+ reset <= not resetn;
+ dbg_full <= full_sig;
+ dbg_almost_full<= almost_full;
+ fifo_inst : fifo PORT MAP (
+ --system signals
+ aclr => reset,
+ clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
+ -- push interface
+ data => dbg_data,
+ wrreq => dbg_wr_pulse,
+ almost_full => almost_full,
+ usedw => dbg_usedw,
+ --pop interface
+ rdreq => rdreq_sig,
+ empty => empty_sig,
+ full => full_sig,
+ q => q_sig
+ );
+
+
+
+
+end rtl;
+
Index: fifo.bsf
===================================================================
--- fifo.bsf (nonexistent)
+++ fifo.bsf (revision 53)
@@ -0,0 +1,107 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 160)
+ (text "fifo" (rect 72 1 90 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 144 25 156)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+ (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 160 32)
+ (output)
+ (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "q[7..0]" (rect 111 26 141 39)(font "Arial" (font_size 8)))
+ (line (pt 160 32)(pt 144 32)(line_width 3))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "almost_full" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+ (text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 1))
+ )
+ (port
+ (pt 160 88)
+ (output)
+ (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+ (text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8)))
+ (line (pt 160 88)(pt 144 88)(line_width 1))
+ )
+ (port
+ (pt 160 104)
+ (output)
+ (text "usedw[12..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+ (text "usedw[12..0]" (rect 77 98 136 111)(font "Arial" (font_size 8)))
+ (line (pt 160 104)(pt 144 104)(line_width 3))
+ )
+ (drawing
+ (text "8 bits x 8192 words" (rect 63 132 144 144)(font "Arial" ))
+ (text "almost_full at 8000" (rect 64 122 144 134)(font "Arial" ))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 144)(line_width 1))
+ (line (pt 144 144)(pt 16 144)(line_width 1))
+ (line (pt 16 144)(pt 16 16)(line_width 1))
+ (line (pt 16 116)(pt 144 116)(line_width 1))
+ (line (pt 16 90)(pt 22 96)(line_width 1))
+ (line (pt 22 96)(pt 16 102)(line_width 1))
+ )
+)