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Rev 45 → Rev 53

/lpc_proto/lpc_byte.vhd
0,0 → 1,303
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
 
entity lpc_iow is
port (
--system signals
lreset_n : in std_logic;
lclk : in std_logic;
lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
lena_reads : in std_logic; --enable read capabilities
--LPC bus from host
lad_i : in std_logic_vector(3 downto 0);
lad_o : out std_logic_vector(3 downto 0);
lad_oe : out std_logic;
lframe_n : in std_logic;
--memory interface
lpc_addr : out std_logic_vector(23 downto 0); --shared address
lpc_wr : out std_logic; --shared write not read
lpc_data_i : in std_logic_vector(7 downto 0);
lpc_data_o : out std_logic_vector(7 downto 0);
lpc_val : out std_logic;
lpc_ack : in std_logic
);
end lpc_iow;
 
architecture rtl of lpc_iow is
type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states
type cycle is (LPC_IO_W,LPC_MEM_R,LPC_FW_R); -- simple LPC bus cycle types
 
signal CS : state;
signal r_lad : std_logic_vector(3 downto 0);
signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
--adress 23 bits on flash
signal r_data : std_logic_vector(7 downto 0);
signal r_cnt : std_logic_vector(2 downto 0);
signal cycle_type : cycle;
--signal r_fw_msize : std_logic_vector(3 downto 0);
 
 
signal data_valid : std_logic;
 
signal lad_rising_o : std_logic_vector(3 downto 0);
signal lad_rising_oe : std_logic;
 
constant START_FW_READ : std_logic_vector(3 downto 0):="1101";
constant START_LPC : std_logic_vector(3 downto 0):="0000";
constant IDSEL_FW_BOOT : std_logic_vector(3 downto 0):="0000"; --0000 is boot device on ThinCan
constant MSIZE_FW_1B : std_logic_vector(3 downto 0):="0000"; --0000 is 1 byte read
constant SYNC_OK : std_logic_vector(3 downto 0):="0000"; --sync done
constant SYNC_WAIT : std_logic_vector(3 downto 0):="0101"; --sync wait device holds the bus
constant SYNC_LWAIT : std_logic_vector(3 downto 0):="0110"; --sync long wait expected device holds the bus
constant TAR_OK : std_logic_vector(3 downto 0):="1111"; --accepted tar constant for master and slave
 
 
 
 
begin -- rtl
 
lad_o<= lad_rising_o;
lad_oe <= lad_rising_oe;
 
 
--Pass the whole LPC address to the system
lpc_addr <= r_addr(23 downto 0);
lpc_data_o<= r_data;
 
 
 
-- purpose: LPC IO write/LPC MEM read/LPC FW read handler
-- type : sequential
-- inputs : lclk, lreset_n
-- outputs:
LPC: process (lclk, lreset_n)
begin -- process LPC
if lreset_n = '0' then -- asynchronous reset (active low)
CS<= RESETs;
lad_rising_oe<='0';
data_valid <='1';
lad_rising_o<="0000";
lpc_val <='0';
lpc_wr <='0';
r_lad <= (others=>'0');
cycle_type <= LPC_IO_W; --initial value
r_addr <= (others=>'0');
r_cnt <= (others=>'0');
elsif lclk'event and lclk = '1' then -- rising clock edge
case CS is
when RESETs => ----------------------------------------------------------
lpc_wr <='0';
lpc_val <='0';
if lframe_n='0' then
CS <= STARTs;
r_lad <= lad_i;
else
CS <= RESETs;
end if;
when STARTs => ----------------------------------------------------------
if lframe_n = '0' then
r_lad <= lad_i; -- latch lad state for next cycle
CS <= STARTs;
elsif r_lad = START_LPC then
--must identify CYCTYPE
if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
--next 4 states must be address states
CS<=ADDRs;
cycle_type <= LPC_IO_W;
r_cnt <= "000";
elsif lad_i(3 downto 1)="010" and lena_mem_r='1' and lena_reads='1' then --MEM READ ALLOWED
CS<=ADDRs;
cycle_type <= LPC_MEM_R;
r_cnt <= "000";
else
CS<= RESETs;
end if;
elsif r_lad = START_FW_READ then --FW READ is always allowed
if lad_i = IDSEL_FW_BOOT and lena_reads='1' then
CS<=ADDRs;
cycle_type <= LPC_FW_R;
r_cnt <= "000";
else
CS<= RESETs;
end if;
end if;
when ADDRs => -----------------------------------------------------------
case cycle_type is
when LPC_IO_W => --IO write cycle
if r_cnt ="011" then
if r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" then
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt <= "000";
CS<=DATAs;
elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then --for debug switch
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt <= "000";
CS<=DATAs;
else
--not for this device
CS<=RESETs;
end if;
else
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt<=r_cnt + 1;
CS<=ADDRs;
end if;
when LPC_MEM_R => --Memory read cycle
if r_cnt ="111" then
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt <= "000";
lpc_wr <='0'; --memory read mus accure
lpc_val <='1';
data_valid <='0';
CS<=TARs;
else
r_addr<= r_addr(27 downto 0)&lad_i;
r_cnt<=r_cnt + 1;
CS<=ADDRs;
end if;
when LPC_FW_R => --Firmware read
if r_cnt ="111" then
--r_fw_msize <= lad_i; --8'th cycle on FW read is mem size
r_cnt <= "000";
lpc_wr <='0'; --memory read must accure
lpc_val <='1';
data_valid <='0';
if lad_i = MSIZE_FW_1B then
CS<=TARs;
else
--over byte fw read not supported
CS<=RESETs;
end if;
else
r_addr<= r_addr(27 downto 0)&lad_i; --28 bit address is given
r_cnt<=r_cnt + 1;
CS<=ADDRs;
end if;
when others => null;
end case;
when DATAs => -----------------------------------------------------------
case cycle_type is
when LPC_IO_W => --IO write cycle
if r_cnt ="001" then
r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
r_cnt <= "000";
lpc_wr <='1'; --IO write must accure
lpc_val <='1';
CS <= TARs;
else
r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
r_cnt<=r_cnt + 1;
CS <= DATAs;
end if;
when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
if r_cnt ="001" then
lad_rising_o<= r_data(7 downto 4);
r_cnt <= "000";
CS <= LOCAL_TARs;
else
lad_rising_o<= r_data(3 downto 0);
r_cnt<=r_cnt + 1;
CS <= DATAs;
end if;
when others => null;
end case;
when TARs => ------------------------------------------------------------
if cycle_type /= LPC_IO_W and lpc_ack='1' and r_cnt ="001" then --if mem_read or fr_read
r_data <= lpc_data_i;
lpc_val <='0';
data_valid <='1';
CS<= SYNCs;
r_cnt <= "000";
elsif lpc_ack='1' and r_cnt ="001" then
lad_rising_o<=SYNC_OK; --added to avoid trouble as SYNC is OK allready
lpc_val <='0';
CS<= SYNCs;
r_cnt <= "000";
end if;
 
if r_cnt ="001" then
if lpc_ack='0' then
lad_rising_o <= SYNC_LWAIT; --added to avoid trouble
end if;
lad_rising_oe<='1';
elsif lad_i = TAR_OK then
r_cnt<=r_cnt + 1;
--lad_rising_oe<='1'; --BUG fix by LPC stanard TAR cycle part 2 must be tri-stated by host and device
lad_rising_o <= TAR_OK; --drive to F on the bus
CS <= TARs;
else
CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR
end if;
when SYNCs => -----------------------------------------------------------
case cycle_type is
when LPC_IO_W => --IO write cycle
-- just passing r_lad on bus again
lad_rising_o<= TAR_OK;
CS <= LOCAL_TARs;
when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
if data_valid ='1' then
lad_rising_o<=SYNC_OK;
CS <= DATAs;
else
if lpc_ack='1' then
r_data <= lpc_data_i;
data_valid <= '1';
lad_rising_o<=SYNC_OK; --SYNC ok now
lpc_val <='0';
CS <= DATAs;
end if;
end if;
when others => null;
end case;
when LOCAL_TARs => ------------------------------------------------------
case cycle_type is
when LPC_IO_W => --IO write cycle
lpc_wr <='0';
lad_rising_oe <='0';
CS <= RESETs;
when LPC_MEM_R | LPC_FW_R => --Memory read cycle
if r_cnt ="000" then
lad_rising_o<= TAR_OK;
r_cnt <= r_cnt + 1;
else
lad_rising_oe <= '0';
r_cnt <="000";
CS <= RESETs;
end if;
when others => null;
end case;
end case; -----------------------------------------------------------------
end if;
end process LPC;
 
end rtl;
/design_top/design_top_thincandbg.vhd
0,0 → 1,535
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
 
 
 
-- Coding for seg_out(7:0)
--
-- bit 0,A
-- ----------
-- | |
-- | |
-- 5,F| | 1,B
-- | 6,G |
-- ----------
-- | |
-- | |
-- 4,E| | 2,C
-- | 3,D |
-- ----------
-- # 7,H
 
-- Revision history
--
-- Version 1.01
-- 15 oct 2006 version code 86 01 jyrit
-- Added IO write to address 0x0088 with commands F1 and F4 to
-- enable switching dongle to 4Meg mode for external reads
-- Changed USB interface to address all 4 Meg on any mode jumper configuration
--
-- Version 1.02
-- 04 dec 2006 version code 86 02 jyrit
-- Added listen only mode for mode pin configuration "00" to enable post code
-- spy mode (does not respond to external reads).
 
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity design_top is
port (
--system signals
sys_clk : in std_logic; --25 MHz clk
resetn : in std_logic;
hdr : inout std_logic_vector(9 downto 0);
--alt_clk : out std_logic;
mode : in std_logic_vector(1 downto 0); --sel upper addr bits
--lpc slave interf
lad : inout std_logic_vector(3 downto 0);
lframe_n : in std_logic;
lreset_n : in std_logic;
lclk : in std_logic;
--led system
seg_out : out std_logic_vector(7 downto 0);
scn_seg : out std_logic_vector(3 downto 0);
led_green : out std_logic;
led_red : out std_logic;
--flash interface
fl_addr : out std_logic_vector(23 downto 0);
fl_ce_n : out std_logic; --chip select
fl_oe_n : out std_logic; --output enable for flash
fl_we_n : out std_logic; --write enable
fl_data : inout std_logic_vector(15 downto 0);
fl_rp_n : out std_logic; --reset signal
fl_sts : in std_logic; --status signal
fl_sts_en : out std_logic; --enable status signal wiht highZ out
--USB parallel interface
usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr : inout std_logic; -- write performed on edge \ of signal
usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
usb_rxf_n : in std_logic; -- rx fifo has data if low
usb_bd : inout std_logic_vector(7 downto 0) --bus data
);
end design_top;
 
 
 
architecture rtl of design_top is
 
component led_sys --toplevel for led system
generic(
msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
);
port (
clk : in std_logic;
reset_n : in std_logic;
led_data_i : in std_logic_vector(15 downto 0); --binary data in
seg_out : out std_logic_vector(7 downto 0); --one segment out
sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
);
end component;
 
 
component lpc_iow
port (
--system signals
lreset_n : in std_logic;
lclk : in std_logic;
lena_mem_r : in std_logic; --enable full adress range covering memory read block
lena_reads : in std_logic; --enable read capabilities
--LPC bus from host
lad_i : in std_logic_vector(3 downto 0);
lad_o : out std_logic_vector(3 downto 0);
lad_oe : out std_logic;
lframe_n : in std_logic;
--memory interface
lpc_addr : out std_logic_vector(23 downto 0); --shared address
lpc_wr : out std_logic; --shared write not read
lpc_data_i : in std_logic_vector(7 downto 0);
lpc_data_o : out std_logic_vector(7 downto 0);
lpc_val : out std_logic;
lpc_ack : in std_logic
);
end component;
 
 
component flash_if
port (
clk : in std_logic;
reset_n : in std_logic;
--flash Bus
fl_addr : out std_logic_vector(23 downto 0);
fl_ce_n : out std_logic; --chip select
fl_oe_n : out std_logic; --output enable for flash
fl_we_n : out std_logic; --write enable
fl_data : inout std_logic_vector(15 downto 0);
fl_rp_n : out std_logic; --reset signal
fl_byte_n : out std_logic; --hold in byte mode
fl_sts : in std_logic; --status signal
-- mem Bus
mem_addr : in std_logic_vector(23 downto 0);
mem_do : out std_logic_vector(15 downto 0);
mem_di : in std_logic_vector(15 downto 0);
mem_wr : in std_logic; --write not read signal
mem_val : in std_logic;
mem_ack : out std_logic
);
end component;
 
 
component usb2mem
port (
clk25 : in std_logic;
reset_n : in std_logic;
dongle_ver: in std_logic_vector(15 downto 0);
-- mem Bus
mem_busy_n: in std_logic;
mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads)
mem_addr : out std_logic_vector(23 downto 0);
mem_do : out std_logic_vector(15 downto 0);
mem_di : in std_logic_vector(15 downto 0);
mem_wr : out std_logic;
mem_val : out std_logic;
mem_ack : in std_logic;
mem_cmd : out std_logic;
-- USB port
usb_mode_en: in std_logic; -- enable this block
usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr : out std_logic; -- write performed on edge \ of signal
usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
usb_bd : inout std_logic_vector(7 downto 0) --bus data
);
end component;
 
component pc_serializer
Port ( --system signals
sys_clk : in STD_LOGIC;
resetn : in STD_LOGIC;
--postcode data port
dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
dbg_wr : in STD_LOGIC; --write not read
dbg_full : out STD_LOGIC; --write not read
dbg_almost_full : out STD_LOGIC;
dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
--debug USB port
dbg_usb_mode_en: in std_logic; -- enable this debug mode
dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
);
end component;
 
 
--LED signals
signal data_to_disp : std_logic_vector(15 downto 0);
--END LED SIGNALS
 
--lpc signals
signal lad_i : std_logic_vector(3 downto 0);
signal lad_o : std_logic_vector(3 downto 0);
signal lad_oe : std_logic;
 
signal lpc_debug : std_logic_vector(31 downto 0);
signal lpc_debug_cnt : std_logic_vector(15 downto 0);
signal lpc_addr : std_logic_vector(23 downto 0); --shared address
signal lpc_data_o : std_logic_vector(7 downto 0);
signal lpc_data_i : std_logic_vector(7 downto 0);
signal lpc_wr : std_logic; --shared write not read
signal lpc_ack : std_logic;
signal lpc_val : std_logic;
signal lena_mem_r : std_logic; --enable full adress range covering memory read block
signal lena_reads : std_logic; --enable/disables all read capabilty to make the device post code capturer
 
signal c25_lpc_val : std_logic;
signal c25_lpc_wr : std_logic; --shared write not read
signal c25_lpc_wr_long : std_logic; --for led debug data latching
 
signal c33_lpc_wr_long : std_logic; --for led debug data latching
signal c33_lpc_wr : std_logic; --for led debug data latching
signal c33_lpc_wr_wait: std_logic; --for led debug data latching
signal c33_lpc_wr_waitd: std_logic; --for led debug data latching
signal c33_wr_cnt : std_logic_vector(23 downto 0); --for led debug data latching
 
 
--End lpc signals
 
--Flash signals
signal mem_addr : std_logic_vector(23 downto 0);
signal mem_do : std_logic_vector(15 downto 0);
signal mem_di : std_logic_vector(15 downto 0);
signal mem_wr : std_logic; --write not read signal
signal mem_val : std_logic;
signal mem_ack : std_logic;
 
signal c33_mem_ack : std_logic; --sync signal
 
 
 
signal fl_ce_n_w : std_logic; --chip select
signal fl_oe_n_w : std_logic; --output enable for flash
 
--END flash signals
 
--USB signals
signal dbg_data : STD_LOGIC_VECTOR (7 downto 0);
signal c25_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
signal c33_dbg_addr_d : STD_LOGIC_VECTOR (7 downto 0);
 
signal dbg_wr : STD_LOGIC; --write not read
signal dbg_full : STD_LOGIC; --write not read
signal dbg_almost_full : STD_LOGIC;
signal dbg_usedw : STD_LOGIC_VECTOR (12 DOWNTO 0);
 
signal dbg_usb_mode_en : std_logic;
signal usb_mode_en : std_logic;
signal mem_idle : std_logic;
signal umem_addr : std_logic_vector(23 downto 0);
signal umem_do : std_logic_vector(15 downto 0);
signal umem_wr : std_logic;
signal umem_val : std_logic;
signal umem_ack : std_logic;
signal umem_cmd : std_logic;
signal enable_4meg: std_logic;
signal dongle_con_n : std_logic;
 
constant dongle_ver : std_logic_vector(15 downto 0):=x"8605";
--END USB signals
 
begin
 
--GPIO PINS START
fl_sts_en <='Z';
 
hdr(1) <= dongle_con_n;
--hdr(1) <= fl_sts when resetn='1' else
-- '0';
 
--when jumper on then mem read and firmware read enabled else only firmware read
hdr(0) <= 'Z';
lena_mem_r <= not hdr(0); -- disabled if jumper is not on header pins 1-2
 
-- jumper on pins 5,6 then postcode only mode (no mem device)
hdr(2) <= '0'; --create low pin for jumper pair 5-6 (this pin is 6 on J1 header)
lena_reads <= hdr(3) and mem_idle and (not dongle_con_n); -- disabled if jumper is on (jumper makes it a postcode only device) paired with hdr(2) pins 5,6 and when usb control is not accessing flash
 
 
-- when jumper on pins 7,8 then post code capture mode enabled
hdr(4)<= '0';
dbg_usb_mode_en <= not hdr(5); --weak pullup on hdr(5) paired with hdr(4)
usb_mode_en <= not dbg_usb_mode_en;
 
--GPIO PINS END
 
--LED SUBSYSTEM START
data_to_disp <= x"86"&lpc_debug(7 downto 0) when usb_mode_en='1' else --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
"000"&dbg_usedw; --show tx fifo state on leds when postcode capture mode
--########################################--
--VERSION CONSTATNS
--########################################--
led_red <= enable_4meg;
 
LEDS: led_sys --toplevel for led system
generic map(
msn_hib => "01111111",--8 --Most signif. of hi byte
lsn_hib => "01111101",--6 --Least signif. of hi byte
msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
--lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
--lsn_lob => "01100110" --4 --Least signif. of hi byte This is version code
lsn_lob => "01101101" --5 --sync with dongle version const. Least signif. of hi byte This is version code
)
port map(
clk => sys_clk , -- in std_logic;
reset_n => resetn, -- in std_logic;
led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
);
 
--LED SUBSYSTEM END
 
 
--MAIN DATAPATH CONNECTIONS
--LPC bus logic
lad_i <= lad;
lad <= lad_o when lad_oe='1' else
(others=>'Z');
 
--END LPC bus logic
 
LPCBUS : lpc_iow
port map(
--system signals
lreset_n => lreset_n, -- in std_logic;
lclk => lclk, -- in std_logic;
lena_mem_r => lena_mem_r, --: in std_logic; --enable full adress range covering memory read block
lena_reads => lena_reads, -- : in std_logic; --enable read capabilities, : in std_logic; --enable read capabilities
--LPC bus from host
lad_i => lad_i, -- in std_logic_vector(3 downto 0);
lad_o => lad_o, -- out std_logic_vector(3 downto 0);
lad_oe => lad_oe, -- out std_logic;
lframe_n => lframe_n, -- in std_logic;
--memory interface
lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
lpc_wr => lpc_wr, -- out std_logic; --shared write not read
lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
lpc_val => lpc_val, -- out std_logic;
lpc_ack => lpc_ack -- in std_logic
);
 
 
--memory data bus logic
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
(others=>'Z');
mem_di <= (others=>'Z') when c25_lpc_val='1' else
umem_do when umem_val='1' else
(others=>'Z');
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
umem_wr when umem_val='1' else
'0';
mem_val <= c25_lpc_val or umem_val;
 
umem_ack <= mem_ack when umem_val='1' else
'0';
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
mem_do(15 downto 8);
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
(not dbg_almost_full) when lpc_val='1' and lpc_wr='1' else
'0';
 
 
SYNC1: process (lclk, lreset_n) --c33
begin
if lclk'event and lclk = '1' then -- rising clock edge
c33_mem_ack <= mem_ack;
end if;
end process SYNC1;
dbg_data <= lpc_debug(7 downto 0);
SYNC2: process (sys_clk) --c25
begin
if sys_clk'event and sys_clk = '1' then -- rising clock edge
c25_lpc_val <= lpc_val; --syncro two clock domains
c25_lpc_wr <= c33_lpc_wr; --syncro two clock domains
c25_dbg_addr_d <= c33_dbg_addr_d; --syncro two clock domains
if usb_mode_en ='0' and c25_dbg_addr_d=x"80" then --don't fill fifo in regular mode
dbg_wr<= c25_lpc_wr; --c33_lpc_wr_wait;--c33_lpc_wr_wait;
else
dbg_wr<='0'; --write never rises when usb_mode_en = 1
end if;
end if;
end process SYNC2;
 
 
LATCHled: process (lclk,lreset_n) --c33
begin
if lreset_n='0' then
lpc_debug(7 downto 0)<=(others=>'0');
c33_dbg_addr_d <=(others=>'0');
enable_4meg <='0';
c33_lpc_wr <='0';
dongle_con_n <='0'; -- pin 3 in GPIO make it toggleable
elsif lclk'event and lclk = '1' then -- rising clock edge
c33_lpc_wr <= lpc_wr;
if c33_lpc_wr='0' and lpc_wr='1' then
c33_dbg_addr_d <= lpc_addr(7 downto 0);
lpc_debug(7 downto 0)<= lpc_data_o;
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F4" then --Flash 4 Mega enable (LSN is first MSN is second)
enable_4meg <='1';
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"F1" then --Flash 1 Mega enalbe
enable_4meg <='0';
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D1" then --Set Dongle not attached signal
dongle_con_n <='1'; -- pin 3 in GPIO make it 1
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"D0" then --Set Dongle attached signal
dongle_con_n <='0'; -- pin 3 in GPIO make it 1
end if;
end if;
end if;
end process LATCHled;
 
 
--END memory data bus logic
fl_ce_n<= fl_ce_n_w;
fl_oe_n<= fl_oe_n_w;
 
FLASH : flash_if
port map(
clk => sys_clk, -- in std_logic;
reset_n => resetn, -- in std_logic;
--flash Bus
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
fl_we_n => fl_we_n, -- out std_logic; --write enable
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
fl_sts => fl_sts, -- in std_logic; --status signal
-- mem Bus
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
mem_wr => mem_wr, -- in std_logic; --write not read signal
mem_val => mem_val, -- in std_logic;
mem_ack => mem_ack -- out std_logic
);
 
 
USB: usb2mem
port map(
clk25 => sys_clk, -- in std_logic;
reset_n => resetn, -- in std_logic;
dongle_ver => dongle_ver,
-- mem Bus
mem_busy_n=> fl_sts, --check flash status before starting new command on flash
mem_idle => mem_idle,
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
mem_wr => umem_wr, -- out std_logic;
mem_val => umem_val, -- out std_logic;
mem_ack => umem_ack, -- in std_logic; --from flash
mem_cmd => umem_cmd, -- out std_logic;
-- USB port
usb_mode_en => usb_mode_en,
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
);
 
 
DBG : pc_serializer
port map ( --system signals
sys_clk => sys_clk, -- in STD_LOGIC;
resetn => resetn, -- in STD_LOGIC;
--postcode data port
dbg_data => dbg_data, -- in STD_LOGIC_VECTOR (7 downto 0);
dbg_wr => dbg_wr, -- in STD_LOGIC; --write not read
dbg_full => dbg_full,--: out STD_LOGIC; --write not read
dbg_almost_full => dbg_almost_full,
dbg_usedw => dbg_usedw,
 
--debug USB port
dbg_usb_mode_en=> dbg_usb_mode_en, -- in std_logic; -- enable this debug mode
dbg_usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
dbg_usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo not full (redy for new data if low)
dbg_usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
);
 
 
--END MAIN DATAPATH CONNECTIONS
 
end rtl;
 
 
 
/design_top/Copyright.txt
0,0 → 1,22
------------------------------------------------------------------
-- Universal dongle board source code
--
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
--
-- This source code is free hardware; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This source code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The complete text of the GNU Lesser General Public License can be found in
-- the file 'lesser.txt'.
/design_top/lesser.txt
0,0 → 1,504
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FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
 
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Libraries
 
If you develop a new library, and you want it to be of the greatest
possible use to the public, we recommend making it free software that
everyone can redistribute and change. You can do so by permitting
redistribution under these terms (or, alternatively, under the terms of the
ordinary General Public License).
 
To apply these terms, attach the following notices to the library. It is
safest to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least the
"copyright" line and a pointer to where the full notice is found.
 
<one line to give the library's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
 
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
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License along with this library; if not, write to the Free Software
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Also add information on how to contact you by electronic and paper mail.
 
You should also get your employer (if you work as a programmer) or your
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library `Frob' (a library for tweaking knobs) written by James Random Hacker.
 
<signature of Ty Coon>, 1 April 1990
Ty Coon, President of Vice
 
That's all there is to it!
 
 
/postcode_ser/fifo_waveforms.html
0,0 → 1,13
<html>
<head>
<title>Sample Waveforms for fifo.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file fifo.vhd </CENTER></h2>
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design fifo.vhd. The design fifo.vhd has a depth of 8192 words of 8 bits each. The output of the fifo is registered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=fifo_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<P></P>
</body>
</html>
/postcode_ser/fifo_inst.vhd
0,0 → 1,12
fifo_inst : fifo PORT MAP (
aclr => aclr_sig,
clock => clock_sig,
data => data_sig,
rdreq => rdreq_sig,
wrreq => wrreq_sig,
almost_full => almost_full_sig,
empty => empty_sig,
full => full_sig,
q => q_sig,
usedw => usedw_sig
);
/postcode_ser/fifo.cmp
0,0 → 1,30
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component fifo
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
almost_full : OUT STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
);
end component;
/postcode_ser/fifo.vhd
0,0 → 1,201
-- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
 
-- ============================================================
-- File Name: fifo.vhd
-- Megafunction Name(s):
-- scfifo
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY fifo IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
almost_full : OUT STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
);
END fifo;
 
 
ARCHITECTURE SYN OF fifo IS
 
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
 
 
 
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
almost_full_value : NATURAL;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
almost_full : OUT STD_LOGIC ;
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
full : OUT STD_LOGIC
);
END COMPONENT;
 
BEGIN
almost_full <= sub_wire0;
usedw <= sub_wire1(12 DOWNTO 0);
empty <= sub_wire2;
q <= sub_wire3(7 DOWNTO 0);
full <= sub_wire4;
 
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
almost_full_value => 8000,
intended_device_family => "Cyclone",
lpm_numwords => 8192,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 13,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
rdreq => rdreq,
aclr => aclr,
clock => clock,
wrreq => wrreq,
data => data,
almost_full => sub_wire0,
usedw => sub_wire1,
empty => sub_wire2,
q => sub_wire3,
full => sub_wire4
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "8000"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "8192"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "1"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0]
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0
-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wave*.jpg FALSE
/postcode_ser/fifo_wave0.jpg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/postcode_ser/fifo_wave0.jpg
postcode_ser/fifo_wave0.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: postcode_ser/pc_serializer.vhd =================================================================== --- postcode_ser/pc_serializer.vhd (nonexistent) +++ postcode_ser/pc_serializer.vhd (revision 53) @@ -0,0 +1,327 @@ +------------------------------------------------------------------ +-- Universal dongle board source code +-- +-- Copyright (C) 2006 Artec Design +-- +-- This source code is free hardware; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This source code is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The complete text of the GNU Lesser General Public License can be found in +-- the file 'lesser.txt'. + + + +---------------------------------------------------------------------------------- +-- Company: ArtecDesign +-- Engineer: Jüri Toomessoo +-- +-- Create Date: 12:57:23 28/02/2008 +-- Design Name: Postcode serial pipe Hardware +-- Module Name: pc_serializer - rtl +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity pc_serializer is + Port ( --system signals + sys_clk : in STD_LOGIC; + resetn : in STD_LOGIC; + --postcode data port + dbg_data : in STD_LOGIC_VECTOR (7 downto 0); + dbg_wr : in STD_LOGIC; --write not read + dbg_full : out STD_LOGIC; --write not read + dbg_almost_full : out STD_LOGIC; + dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0); + --debug USB port + dbg_usb_mode_en: in std_logic; -- enable this debug mode + dbg_usb_wr : out std_logic; -- write performed on edge \ of signal + dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low) + dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data +); + +end pc_serializer; + +architecture rtl of pc_serializer is + + component fifo + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + almost_full : OUT STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0) + + ); + end component; + + + + --type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo + signal CS : std_logic_vector(8 downto 0);--state; + signal RETS : std_logic_vector(8 downto 0); --state; + signal next_char : std_logic_vector(7 downto 0); --bus data + signal ascii_char : std_logic_vector(7 downto 0); --bus data + signal in_nibble : std_logic_vector(3 downto 0); --bus data + signal usb_send_char : std_logic_vector(7 downto 0); --bus data + + signal count : std_logic_vector(3 downto 0); --internal counter + signal dly_count : std_logic_vector(15 downto 0); --internal counter + signal dbg_wr_pulse : std_logic; --active reset + signal dbg_wrd : std_logic; --active reset + signal dbg_wr_len : std_logic; --active reset + signal usb_send : std_logic; --active reset + + + signal rdreq_sig : std_logic; --active reset + signal empty_sig : std_logic; --active reset + signal full_sig : std_logic; --active reset + signal almost_full : std_logic; --active reset + + signal q_sig : std_logic_vector(7 downto 0); --bus data + + signal reset : std_logic; --active reset + signal half_clk : std_logic; --active reset + + + --RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs + constant RESETs: std_logic_vector(8 downto 0) := "000000001"; -- char /n + constant HEXMARKs: std_logic_vector(8 downto 0) := "000000010"; -- char /n + constant MSNIBBLEs: std_logic_vector(8 downto 0) := "000000100"; -- char /n + constant LSNIBBLEs: std_logic_vector(8 downto 0) := "000001000"; -- char /n + constant LINEFDs: std_logic_vector(8 downto 0) := "000010000"; -- char /n + constant CRs: std_logic_vector(8 downto 0) := "000100000"; -- char /n + constant START_WRITEs: std_logic_vector(8 downto 0):= "001000000"; -- char /n + constant WAITs: std_logic_vector(8 downto 0) := "010000000"; -- char /n + constant END_WRITEs: std_logic_vector(8 downto 0) := "100000000"; -- char /n + + + constant CHAR_LF : std_logic_vector(7 downto 0):= x"0A"; -- char /n + constant CHAR_CR : std_logic_vector(7 downto 0):= x"0D"; -- char /n + constant CHAR_SP : std_logic_vector(7 downto 0):= x"20"; -- space + constant CHAR_ux : std_logic_vector(7 downto 0):= x"58"; -- fifo full hex marker --upper case x + constant CHAR_x : std_logic_vector(7 downto 0):= x"78"; -- regular hex marker + constant CHAR_0 : std_logic_vector(7 downto 0):= x"30"; + constant CHAR_1 : std_logic_vector(7 downto 0):= x"31"; + constant CHAR_2 : std_logic_vector(7 downto 0):= x"32"; + constant CHAR_3 : std_logic_vector(7 downto 0):= x"33"; + constant CHAR_4 : std_logic_vector(7 downto 0):= x"34"; + constant CHAR_5 : std_logic_vector(7 downto 0):= x"35"; + constant CHAR_6 : std_logic_vector(7 downto 0):= x"36"; + constant CHAR_7 : std_logic_vector(7 downto 0):= x"37"; + constant CHAR_8 : std_logic_vector(7 downto 0):= x"38"; + constant CHAR_9 : std_logic_vector(7 downto 0):= x"39"; + constant CHAR_a : std_logic_vector(7 downto 0):= x"41"; + constant CHAR_b : std_logic_vector(7 downto 0):= x"42"; + constant CHAR_c : std_logic_vector(7 downto 0):= x"43"; + constant CHAR_d : std_logic_vector(7 downto 0):= x"44"; + constant CHAR_e : std_logic_vector(7 downto 0):= x"45"; + constant CHAR_f : std_logic_vector(7 downto 0):= x"46"; + + + +begin + + ascii_char <=CHAR_0 when in_nibble = x"0" else + CHAR_1 when in_nibble = x"1" else + CHAR_2 when in_nibble = x"2" else + CHAR_3 when in_nibble = x"3" else + CHAR_4 when in_nibble = x"4" else + CHAR_5 when in_nibble = x"5" else + CHAR_6 when in_nibble = x"6" else + CHAR_7 when in_nibble = x"7" else + CHAR_8 when in_nibble = x"8" else + CHAR_9 when in_nibble = x"9" else + CHAR_a when in_nibble = x"a" else + CHAR_b when in_nibble = x"b" else + CHAR_c when in_nibble = x"c" else + CHAR_d when in_nibble = x"d" else + CHAR_e when in_nibble = x"e" else + CHAR_f when in_nibble = x"f"; + + + + dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else + (others=>'Z'); + + dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else + 'Z'; + + SER_SM: process (sys_clk,resetn) + begin -- process + + if sys_clk'event and sys_clk = '1' then -- rising clock edge + if resetn='0' then --active low reset + CS<= RESETs; + in_nibble <= (others=>'0'); + usb_send_char <= (others=>'0'); + dly_count<= (others=>'0'); + usb_send <='0'; + RETS <= RESETs; + rdreq_sig <='0'; + count<= (others=>'1'); + else + case CS is + when RESETs => ---------------------------------------------------------- + + if empty_sig ='0' and dbg_usb_txe_n='0' and dbg_usb_mode_en='1' then --is, can and may send + rdreq_sig <='1'; + count <= count + 1; + RETS <= HEXMARKs; + dly_count <= x"000F"; + CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data + else + usb_send <='0'; + rdreq_sig <='0'; + CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data + end if; + when HEXMARKs => ---------------------------------------------------------- + rdreq_sig <='0'; --data will be ready on output 'till next read request + --if almost_full='0' then + usb_send_char <= CHAR_x; --show fifo full status to user by hex x case + --else + -- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case + --end if; + in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder + RETS <= MSNIBBLEs; + CS <= START_WRITEs; + when MSNIBBLEs => ---------------------------------------------------------- + usb_send_char <= ascii_char; --put MS nibble to output + in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder + RETS <= LSNIBBLEs; + CS <= START_WRITEs; + when LSNIBBLEs => ---------------------------------------------------------- + usb_send_char <= ascii_char; --put MS nibble to output + if count = x"f" then + RETS <= CRs; + else + RETS <= LINEFDs; + end if; + CS <= START_WRITEs; + when CRs => ---------------------------------------------------------- + --if count = x"f" then + usb_send_char <= CHAR_CR; --put line feed + --else + -- usb_send_char <= CHAR_SP; --put space + --end if; + RETS <= LINEFDs; + CS <= START_WRITEs; + when LINEFDs => ---------------------------------------------------------- + if count = x"f" then + usb_send_char <= CHAR_LF; --put line feed + else + usb_send_char <= CHAR_SP; --put space + end if; + RETS <= RESETs; + CS <= START_WRITEs; + + when START_WRITEs => ---------------------------------------------------------- + if dly_count /= x"0004" then + if dbg_usb_txe_n='0' then + usb_send <='1'; + dly_count <= dly_count + 1; + else + usb_send <='0'; --remove send signal when txe is falsely asserted + end if; + else + usb_send <='0'; + CS <= WAITs; + end if; + when WAITs => ---------------------------------------------------------- + usb_send <='0'; + CS <= END_WRITEs; + when END_WRITEs => ---------------------------------------------------------- + rdreq_sig <='0'; --used as intermeadiate cheat state when exiting resets + if dly_count /= x"000F" then + if dbg_usb_txe_n='0' then + dly_count <= dly_count + 1; + end if; + else + dly_count <= (others=>'0'); + CS <= RETS; + end if; + when others => null; + end case; + end if; + end if; + end process SER_SM; + + + SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse + begin -- process + if sys_clk'event and sys_clk = '1' then -- rising clock edge + if resetn='0' then --active low reset + dbg_wr_pulse <='0'; + dbg_wr_len <='0'; + dbg_wrd <='0'; + else + dbg_wrd <= dbg_wr; + if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write + dbg_wr_pulse <='1'; + else + dbg_wr_pulse <='0'; + end if; + end if; + end if; + end process SYNCER; + + + reset <= not resetn; + dbg_full <= full_sig; + dbg_almost_full<= almost_full; + fifo_inst : fifo PORT MAP ( + --system signals + aclr => reset, + clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns + -- push interface + data => dbg_data, + wrreq => dbg_wr_pulse, + almost_full => almost_full, + usedw => dbg_usedw, + --pop interface + rdreq => rdreq_sig, + empty => empty_sig, + full => full_sig, + q => q_sig + ); + + + + +end rtl; + Index: postcode_ser/fifo.bsf =================================================================== --- postcode_ser/fifo.bsf (nonexistent) +++ postcode_ser/fifo.bsf (revision 53) @@ -0,0 +1,107 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 160) + (text "fifo" (rect 72 1 90 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 144 25 156)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 111 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "almost_full" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 160 88) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 144 88)(line_width 1)) + ) + (port + (pt 160 104) + (output) + (text "usedw[12..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) + (text "usedw[12..0]" (rect 77 98 136 111)(font "Arial" (font_size 8))) + (line (pt 160 104)(pt 144 104)(line_width 3)) + ) + (drawing + (text "8 bits x 8192 words" (rect 63 132 144 144)(font "Arial" )) + (text "almost_full at 8000" (rect 64 122 144 134)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 144)(line_width 1)) + (line (pt 144 144)(pt 16 144)(line_width 1)) + (line (pt 16 144)(pt 16 16)(line_width 1)) + (line (pt 16 116)(pt 144 116)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) Index: usb/usb2mem.vhd =================================================================== --- usb/usb2mem.vhd (nonexistent) +++ usb/usb2mem.vhd (revision 53) @@ -0,0 +1,362 @@ +--COMMAND STRUCTURE OF SERAL USB PROTOCOL + +-- MSBYTE LSBYTE + +-- DATA CODE + +--Dongle internal command codes +-- 0x-- 0xC5 --Get Status data is don't care (must return) 0x3210 (3 is the MSNibble) +-- 0xNN 0xCD --Get Data from flash (performs read from current address) NN count of words auto increment address +-- 0xAA 0xA0 --Addr LSByte write +-- 0xAA 0xA1 --Addr Byte write +-- 0xAA 0xA2 --Addr MSByte write +-- 0x-- 0x3F --NOP + +--Flash operations codes +-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine +-- 0x-- 0xD0 -- 0xD0 is flash confirm command + + + +--write buffer sequence +-- ??? -- set address if needed +-- 0xNN 0xE8 --Write to buffer returns extended satus NN is word count for USB machine +-- 0x-- 0xNN --0xNN is word count for flash ges directly to flash and is wordCount - 1 +-- 0xDD 0xDD --N+1 times data expected 0xF + 1 is the maximum +-- ... +-- 0x-- 0xD0 -- 0xD0 is flash confirm command + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +entity usb2mem is + port ( + clk25 : in std_logic; + reset_n : in std_logic; + dongle_ver: in std_logic_vector(15 downto 0); + -- mem Bus + mem_busy_n : in std_logic; + mem_idle : out std_logic; -- '1' if controller is idle (flash is safe for LPC reads) + mem_addr : out std_logic_vector(23 downto 0); + mem_do : out std_logic_vector(15 downto 0); + mem_di : in std_logic_vector(15 downto 0); + mem_wr : out std_logic; + mem_val : out std_logic; + mem_ack : in std_logic; + mem_cmd : out std_logic; + -- USB port + usb_mode_en: in std_logic; -- enable this block + usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip) + usb_wr : out std_logic; -- write performed on edge \ of signal + usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low) + usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low) + usb_bd : inout std_logic_vector(7 downto 0) --bus data + ); +end usb2mem; + + +architecture RTL of usb2mem is + + + + + type state_type is (RESETs,RXCMD0s,RXCMD1s,DECODEs,INTERNs,VCIRDs,VCIWRs,TXCMD0s,TXCMD1s,STS_WAITs); + signal CS : state_type; + + signal data_reg_i : std_logic_vector(15 downto 0); + signal data_reg_o : std_logic_vector(15 downto 0); + signal data_oe : std_logic; -- rx fifo empty (data redy if low) + signal usb_wr_d : std_logic; -- internal readable output state for write + signal addr_reg: std_logic_vector(23 downto 0); + + --State machine + signal cmd_cnt : std_logic_vector(15 downto 0); + signal state_cnt : std_logic_vector(3 downto 0); + --shyncro to USB + signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low) + signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low) + signal internal_cmd : std_logic; -- rx fifo empty (data redy if low) + + signal read_mode : std_logic; + signal write_mode : std_logic; + signal write_count : std_logic; + signal first_word : std_logic; + signal mem_busy_nd : std_logic; + + + +begin + +--define internal command codes +internal_cmd <='1' when data_reg_i(7 downto 0) = x"C5" else + '1' when data_reg_i(7 downto 0) = x"CD" else + '1' when data_reg_i(7 downto 0) = x"A0" else + '1' when data_reg_i(7 downto 0) = x"A1" else + '1' when data_reg_i(7 downto 0) = x"A2" else + '1' when data_reg_i(7 downto 0) = x"3F" else + --These are spechial attention Flash commands + '1' when data_reg_i(7 downto 0) = x"E8" else + '0'; + + +usb_wr <= usb_wr_d when usb_mode_en='1' else + 'Z'; + + +-- this goes to byte buffer for that reason send LSB first and MSB second +usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first + data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else --MSB byte second + (others=>'Z'); + + +process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect) +begin -- process + if reset_n='0' then + CS <= RESETs; + usb_rd_n <= '1'; + usb_wr_d <= '0'; + usb_txe_nd <= '1'; + usb_rxf_nd <= '1'; + data_oe <='0'; + state_cnt <=(others=>'0'); --init command counter + mem_do <= (others=>'Z'); + mem_addr <= (others=>'Z'); + addr_reg <= (others=>'0'); + mem_val <= '0'; + mem_wr <='0'; + mem_cmd <='0'; + cmd_cnt <= (others=>'0'); + read_mode <='0'; + write_mode <='0'; + write_count <='0'; + first_word <='0'; + mem_idle <='1'; --set idle + mem_busy_nd <='1'; + elsif clk25'event and clk25 = '1' then -- rising clock edge + usb_txe_nd <= usb_txe_n; --syncronize + usb_rxf_nd <= usb_rxf_n; --syncronize + mem_busy_nd <=mem_busy_n; --syncronize + case CS is + when RESETs => + if usb_rxf_nd='0' and usb_mode_en='1' and mem_busy_nd='1' then + state_cnt <=(others=>'0'); --init command counter + data_oe <='0'; --we will read command in + mem_idle <='0'; --set busy untill return here + CS <= RXCMD0s; + elsif mem_busy_nd='1' then + mem_idle <='1'; --set idle when here + end if; + when RXCMD0s => + if state_cnt="0000" then + usb_rd_n <='0'; -- set read low + state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles) + elsif state_cnt="0001" then + state_cnt <= state_cnt + 1;-- one wait cycle + elsif state_cnt="0010" then + state_cnt <= state_cnt + 1;-- now is ok + data_reg_i(15 downto 8) <= usb_bd; --get data form bus MSByte must come first + elsif state_cnt="0011" then + usb_rd_n <='1'; -- set read back to high + state_cnt <= state_cnt + 1;-- start wait + elsif state_cnt="0100" then + state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready) + elsif state_cnt="0101" then + state_cnt <= state_cnt + 1;-- wait + elsif state_cnt="0110" then + state_cnt <= state_cnt + 1;-- now is ok prob. + else + if usb_rxf_nd='0' then --wait untill next byte is available + state_cnt <=(others=>'0'); --init command counter + CS <= RXCMD1s; + end if; + end if; + when RXCMD1s => + if state_cnt="0000" then + usb_rd_n <='0'; -- set read low + state_cnt <= state_cnt + 1;-- must be min 50ns long (two cycles) + elsif state_cnt="0001" then + state_cnt <= state_cnt + 1;-- one wait cycle + elsif state_cnt="0010" then + state_cnt <= state_cnt + 1;-- now is ok + data_reg_i(7 downto 0) <= usb_bd; --get data form bus LSByte must come last + elsif state_cnt="0011" then + state_cnt <= state_cnt + 1;-- now is ok + usb_rd_n <='1'; -- set read back to high + elsif state_cnt="0100" then + state_cnt <= state_cnt + 1;-- wait (the usb_rxf_n toggles after each read and next data is not ready) + elsif state_cnt="0101" then + state_cnt <= state_cnt + 1;-- wait + elsif state_cnt="0110" then + state_cnt <= state_cnt + 1;-- now is ok prob. + else + state_cnt <=(others=>'0'); --init command counter + CS <= INTERNs; + end if; + when INTERNs => + if cmd_cnt=x"0000" then + if data_reg_i(7 downto 0)=x"A0" then + addr_reg(7 downto 0)<= data_reg_i(15 downto 8); + CS <= RESETs; --go back to resets + elsif data_reg_i(7 downto 0)=x"A1" then + addr_reg(15 downto 8)<= data_reg_i(15 downto 8); + CS <= RESETs; --go back to resets + elsif data_reg_i(7 downto 0)=x"A2" then + addr_reg(23 downto 16)<= data_reg_i(15 downto 8); + CS <= RESETs; --go back to resets + elsif data_reg_i(7 downto 0)=x"3F" then + CS <= RESETs; --go back to resets --NOP command + elsif data_reg_i(7 downto 0)=x"C5" then + if (data_reg_i(15 downto 8))=x"00" then + data_reg_o <=x"3210"; + else + data_reg_o <=dongle_ver; + end if; + CS <= TXCMD0s; + elsif data_reg_i(7 downto 0)=x"CD" then + if (data_reg_i(15 downto 8))=x"00" then --64K word read coming + cmd_cnt <= (others=>'1'); --64K word count + else + cmd_cnt <= x"00"&data_reg_i(15 downto 8) - 1; -- -1 as one read will be done right now (cmd_cnt words) + end if; + CS <= VCIRDs; --go perform a read + read_mode <='1'; + elsif data_reg_i(7 downto 0)=x"E8" then + --write_mode <='1'; + write_count <='0'; + first_word <='0'; + cmd_cnt <= x"00"&data_reg_i(15 downto 8) + 1; --+2 for direct count write +1 + data_reg_i(15 downto 8)<=(others=>'0'); + CS <= VCIWRs; --go perform a write + else + CS <= VCIWRs; + end if; + else + if cmd_cnt>x"0000" then + cmd_cnt<= cmd_cnt - 1; + if write_count='0' then + write_count<='1'; + elsif write_count='1' and first_word ='0' then + first_word <='1'; + elsif write_count='1' and first_word ='1' then + addr_reg <= addr_reg + 1; --autoincrement address in in block mode + end if; + --if cmd_cnt>x"02" then --so not to increase too many times on write buffer + -- addr_reg <= addr_reg + 1; --autoincrement address in in block mode + --end if; + end if; + CS <= VCIWRs; + end if; + when VCIRDs => --flash read + mem_wr <='0'; --this is VCI write_not_read + mem_cmd <='0'; + mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address + mem_val <= '1'; + if mem_ack='1' then + data_reg_o <= mem_di; + mem_wr <='0'; --this is VCI write_not_read + mem_cmd <='0'; + mem_val <= '0'; + CS <= TXCMD0s; + end if; + when VCIWRs => --flash write + mem_addr <= addr_reg(22 downto 0)&'0'; --translate byte address to word address + mem_do <= data_reg_i; --USB data in will go to mem_out + mem_wr <='1'; --this is VCI write_not_read + mem_cmd <='1'; + mem_val <= '1'; + if mem_ack='1' then + mem_do <= (others=>'Z'); + mem_wr <='0'; --this is VCI write_not_read + mem_cmd <='0'; + mem_val <= '0'; + --if write_mode='0' then + + if cmd_cnt=x"0000" then --if flash command and not data + state_cnt <=(others=>'0'); --init command counter + CS <= STS_WAITs; + else + CS <= RESETs; + end if; + --else --else if was 0xE8 must read and return XSR + -- write_mode <='0'; --XSR return will no follow clear this bit + -- CS <= VCIRDs; + --end if; + end if; + when TXCMD0s => --transmit over USB what ever is in data_reg_o MSB first + + if state_cnt="0000" then + if usb_txe_nd='0' then + usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch + state_cnt <= state_cnt + 1;-- now is ok + end if; + elsif state_cnt="0010" then + data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before) + state_cnt <= state_cnt + 1;-- now is ok + elsif state_cnt="0011" then + usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns + state_cnt <= state_cnt + 1;-- now is ok + elsif state_cnt="0100" then + state_cnt <= state_cnt + 1;-- now is ok + data_oe<='0'; + elsif state_cnt="0111" then --must stay low at least 50ns + CS <= TXCMD1s; + state_cnt <= (others=>'0'); + else + state_cnt <= state_cnt + 1;-- if intermediate cnt then count + end if; + + when TXCMD1s => + + if state_cnt="0000" then + if usb_txe_nd='0' then + usb_wr_d<='1'; -- data is mux'ed by state and data_oe in the beginning of arch + state_cnt <= state_cnt + 1;-- now is ok + end if; + elsif state_cnt="0010" then + data_oe<='1'; --this is to put data on bus befora falling edge of wr (max 20ns before) + state_cnt <= state_cnt + 1;-- now is ok + elsif state_cnt="0011" then + usb_wr_d<='0'; --falling edge performs write must be high for atleast 50ns + state_cnt <= state_cnt + 1;-- now is ok + elsif state_cnt="0100" then + state_cnt <= state_cnt + 1;-- now is ok + data_oe<='0'; + elsif state_cnt="0111" then --must stay low at least 50ns + if read_mode='0' then + CS <= RESETs; + elsif cmd_cnt="0000" then --last word sent + addr_reg <= addr_reg + 1; --autoincrement address in read mode + read_mode <='0'; + CS <= RESETs; + else + cmd_cnt<= cmd_cnt - 1; + addr_reg <= addr_reg + 1; --autoincrement address in read mode + CS <= VCIRDs; --more data to be read + end if; + state_cnt <= (others=>'0'); + else + state_cnt <= state_cnt + 1;-- if intermediate cnt then count + end if; + when STS_WAITs => + if mem_busy_nd='0' then + CS <= RESETs; --now it's ok to go here + else + state_cnt <= state_cnt + 1; + if state_cnt="1111" then + --sts cant take longer than 500 ns to go low + CS <= RESETs; --time out go to resets anyway + end if; + end if; + when others => null; + end case; + end if; +end process; + + + +end RTL; + Index: led_sys/led_sys.vhd =================================================================== --- led_sys/led_sys.vhd (nonexistent) +++ led_sys/led_sys.vhd (revision 53) @@ -0,0 +1,169 @@ +------------------------------------------------------------------ +-- Universal dongle board source code +-- +-- Copyright (C) 2006 Artec Design +-- +-- This source code is free hardware; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This source code is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The complete text of the GNU Lesser General Public License can be found in +-- the file 'lesser.txt'. + + +-- bit 0,A +-- ---------- +-- | | +-- | | +-- 5,F| | 1,B +-- | 6,G | +-- ---------- +-- | | +-- | | +-- 4,E| | 2,C +-- | 3,D | +-- ---------- +-- # 7,H + + +-- Select signal order +-- --- --- --- --- +-- | | | | | | | | +-- | | | | | | | | +-- --- --- --- --- +-- | | | | | | | | +-- | | | | | | | | +-- --- --- --- --- +-- sel(3) sel(2) sel(1) sel(0) + + + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +entity led_sys is --toplevel for led system + generic( + msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte + lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte + msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte + lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte + ); + port ( + clk : in std_logic; + reset_n : in std_logic; + led_data_i : in std_logic_vector(15 downto 0); --binary data in + seg_out : out std_logic_vector(7 downto 0); --one segment out + sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low + ); +end led_sys; + +architecture rtl of led_sys is + +component led_coder + port ( + led_data_i : in std_logic_vector(7 downto 0); + hi_seg : out std_logic_vector(7 downto 0); + lo_seg : out std_logic_vector(7 downto 0) + ); +end component; + +component byte_scan + port ( + clk : in std_logic; + hi_seg_1 : in std_logic_vector(7 downto 0); + lo_seg_1 : in std_logic_vector(7 downto 0); + hi_seg_0 : in std_logic_vector(7 downto 0); + lo_seg_0 : in std_logic_vector(7 downto 0); + seg_out : out std_logic_vector(7 downto 0); + sel_out : out std_logic_vector(3 downto 0) + ); +end component; + + +-- input signals +signal hi_seg1 : std_logic_vector(7 downto 0); +signal lo_seg1 : std_logic_vector(7 downto 0); +signal hi_seg0 : std_logic_vector(7 downto 0); +signal lo_seg0 : std_logic_vector(7 downto 0); + +--data containing signals +signal data_hi_seg1 : std_logic_vector(7 downto 0); +signal data_lo_seg1 : std_logic_vector(7 downto 0); +signal data_hi_seg0 : std_logic_vector(7 downto 0); +signal data_lo_seg0 : std_logic_vector(7 downto 0); + +--constant display +signal cons_hi_seg1 : std_logic_vector(7 downto 0); +signal cons_lo_seg1 : std_logic_vector(7 downto 0); +signal cons_hi_seg0 : std_logic_vector(7 downto 0); +signal cons_lo_seg0 : std_logic_vector(7 downto 0); + +signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation + +begin -- rtl +---------------------------HGFEDCBA +cons_hi_seg1 <= msn_hib;--"01111111"; --8 +cons_lo_seg1 <= lsn_hib;--"01111101"; --6 +cons_hi_seg0 <= msn_lob;--"01011100"; -- small o +cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o + + + + +process (clk) --enable the scanning while in reset +begin -- process + if clk'event and clk = '0' then -- rising clock edge + disp_cnt <= disp_cnt + 1; + end if; +end process; + +LED_CODE0: led_coder + port map( + led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0); + hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0); + lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0) + ); + +LED_CODE1: led_coder + port map( + led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0); + hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0); + lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0) + ); + + +lo_seg1 <= data_hi_seg1 when reset_n='1' else cons_hi_seg1; +hi_seg1 <= data_lo_seg1 when reset_n='1' else cons_lo_seg1; + +lo_seg0 <= data_hi_seg0 when reset_n='1' else cons_hi_seg0; +hi_seg0 <= data_lo_seg0 when reset_n='1' else cons_lo_seg0; + +SCAN : byte_scan + port map( + clk => disp_cnt(15), -- in std_logic; + hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0); + lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0); + hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0); + lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0); + seg_out => seg_out, -- out std_logic_vector(7 downto 0); + sel_out => sel_out -- out std_logic_vector(3 downto 0) + ); + + + + +end rtl; Index: led_sys/byte_scan_mux.vhd =================================================================== --- led_sys/byte_scan_mux.vhd (nonexistent) +++ led_sys/byte_scan_mux.vhd (revision 53) @@ -0,0 +1,111 @@ +------------------------------------------------------------------ +-- Universal dongle board source code +-- +-- Copyright (C) 2006 Artec Design +-- +-- This source code is free hardware; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This source code is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The complete text of the GNU Lesser General Public License can be found in +-- the file 'lesser.txt'. + + + +-- bit 0,A +-- ---------- +-- | | +-- | | +-- 5,F| | 1,B +-- | 6,G | +-- ---------- +-- | | +-- | | +-- 4,E| | 2,C +-- | 3,D | +-- ---------- +-- # 7,H + + +-- Select signal order +-- --- --- --- --- +-- | | | | | | | | +-- | | | | | | | | +-- --- --- --- --- +-- | | | | | | | | +-- | | | | | | | | +-- --- --- --- --- +-- sel(3) sel(2) sel(1) sel(0) + + + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +entity byte_scan is + port ( + clk : in std_logic; + hi_seg_1 : in std_logic_vector(7 downto 0); + lo_seg_1 : in std_logic_vector(7 downto 0); + hi_seg_0 : in std_logic_vector(7 downto 0); + lo_seg_0 : in std_logic_vector(7 downto 0); + seg_out : out std_logic_vector(7 downto 0); + sel_out : out std_logic_vector(3 downto 0) + ); +end byte_scan; + +architecture rtl of byte_scan is + +signal sel_p : std_logic_vector(3 downto 0); +signal count : std_logic_vector(1 downto 0):="00"; +signal hi_seg_1_3 : std_logic_vector(7 downto 0); +signal lo_seg_1_3 : std_logic_vector(7 downto 0); +signal hi_seg_0_2 : std_logic_vector(7 downto 0); +signal lo_seg_0_2 : std_logic_vector(7 downto 0); + +begin -- rtl + + +hi_seg_1_3 <= hi_seg_1; -- when sel_hib_n ='1' else hi_seg_3; +lo_seg_1_3 <= lo_seg_1; --when sel_hib_n ='1' else lo_seg_3; +hi_seg_0_2 <= hi_seg_0; --when sel_hib_n ='1' else hi_seg_2; +lo_seg_0_2 <= lo_seg_0; --when sel_hib_n ='1' else lo_seg_2; + + +seg_out <=hi_seg_1_3 when count="01" else + lo_seg_1_3 when count="10" else + hi_seg_0_2 when count="11" else + lo_seg_0_2 when count="00"; + +sel_out <= sel_p; + +sel_p <= "1110" when count="00" else + "0111" when count="01" else + "1011" when count="10" else + "1101" when count="11"; + + + + +process (clk) --enable the scanning while in reset (simulation will be incorrect) +begin -- process + if clk'event and clk = '1' then -- rising clock edge + count <= count + 1; + end if; +end process; + +end rtl; Index: led_sys/led_coder.vhd =================================================================== --- led_sys/led_coder.vhd (nonexistent) +++ led_sys/led_coder.vhd (revision 53) @@ -0,0 +1,112 @@ +------------------------------------------------------------------ +-- Universal dongle board source code +-- +-- Copyright (C) 2006 Artec Design +-- +-- This source code is free hardware; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This source code is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The complete text of the GNU Lesser General Public License can be found in +-- the file 'lesser.txt'. + + +-- bit 0,A +-- ---------- +-- | | +-- | | +-- 5,F| | 1,B +-- | 6,G | +-- ---------- +-- | | +-- | | +-- 4,E| | 2,C +-- | 3,D | +-- ---------- +-- # 7,H + + + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +entity led_coder is + port ( + led_data_i : in std_logic_vector(7 downto 0); + hi_seg : out std_logic_vector(7 downto 0); + lo_seg : out std_logic_vector(7 downto 0) + ); +end led_coder; + +architecture rtl of led_coder is +signal r_led_data : std_logic_vector(7 downto 0); +signal decoded_lo,decoded_hi : std_logic_vector(7 downto 0); + +begin -- rtl +hi_seg <= decoded_hi; +lo_seg <= decoded_lo; + + -- purpose: binary to led segments decoder + -- type : combinational + -- inputs : nibble,reset + -- outputs: + decode_nibble_lo: process (led_data_i) + begin -- process decode_nibble + case led_data_i(3 downto 0) is--HGFEDCBA + when "0000" => decoded_lo <= "00111111"; -- 0 + when "0001" => decoded_lo <= "00000110"; -- 1 + when "0010" => decoded_lo <= "01011011"; -- 2 + when "0011" => decoded_lo <= "01001111"; -- 3 + when "0100" => decoded_lo <= "01100110"; -- 4 + when "0101" => decoded_lo <= "01101101"; -- 5 + when "0110" => decoded_lo <= "01111101"; -- 6 + when "0111" => decoded_lo <= "00000111"; -- 7 + when "1000" => decoded_lo <= "01111111"; -- 8 + when "1001" => decoded_lo <= "01101111"; -- 9 + when "1010" => decoded_lo <= "01110111"; -- a + when "1011" => decoded_lo <= "01111100"; -- b + when "1100" => decoded_lo <= "00111001"; -- c + when "1101" => decoded_lo <= "01011110"; -- d + when "1110" => decoded_lo <= "01111001"; -- e + when others => decoded_lo <= "01110001"; -- f + end case; + end process decode_nibble_lo; + + decode_nibble_hi: process (led_data_i) + begin -- process decode_nibble + case led_data_i(7 downto 4) is--HGFEDCBA + when "0000" => decoded_hi <= "00111111"; -- 0 + when "0001" => decoded_hi <= "00000110"; -- 1 + when "0010" => decoded_hi <= "01011011"; -- 2 + when "0011" => decoded_hi <= "01001111"; -- 3 + when "0100" => decoded_hi <= "01100110"; -- 4 + when "0101" => decoded_hi <= "01101101"; -- 5 + when "0110" => decoded_hi <= "01111101"; -- 6 + when "0111" => decoded_hi <= "00000111"; -- 7 + when "1000" => decoded_hi <= "01111111"; -- 8 + when "1001" => decoded_hi <= "01101111"; -- 9 + when "1010" => decoded_hi <= "01110111"; -- a + when "1011" => decoded_hi <= "01111100"; -- b + when "1100" => decoded_hi <= "00111001"; -- c + when "1101" => decoded_hi <= "01011110"; -- d + when "1110" => decoded_hi <= "01111001"; -- e + when others => decoded_hi <= "01110001"; -- f + end case; + end process decode_nibble_hi; + + +end rtl; Index: flash/flsh_if.vhd =================================================================== --- flash/flsh_if.vhd (nonexistent) +++ flash/flsh_if.vhd (revision 53) @@ -0,0 +1,127 @@ +------------------------------------------------------------------ +-- Universal dongle board source code +-- +-- Copyright (C) 2006 Artec Design +-- +-- This source code is free hardware; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This source code is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The complete text of the GNU Lesser General Public License can be found in +-- the file 'lesser.txt'. + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + +entity flash_if is + port ( + clk : in std_logic; + reset_n : in std_logic; + --flash Bus + fl_addr : out std_logic_vector(23 downto 0); + fl_ce_n : out std_logic; --chip select (timing is very chip dependent) + fl_oe_n : out std_logic; --output enable for flash (timing is very chip dependent) + fl_we_n : out std_logic; --write enable (timing is very chip dependent) + fl_data : inout std_logic_vector(15 downto 0); + fl_rp_n : out std_logic; --reset signal + fl_byte_n : out std_logic; --hold in byte mode + fl_sts : in std_logic; --status signal + -- mem Bus + mem_addr : in std_logic_vector(23 downto 0); + mem_do : out std_logic_vector(15 downto 0); + mem_di : in std_logic_vector(15 downto 0); + + mem_wr : in std_logic; --write not read signal + mem_val : in std_logic; + mem_ack : out std_logic + ); +end flash_if; + + +architecture RTL of flash_if is + type state_type is (RESETs,FLREADs,FLWRITEs,WAITs); + signal CS : state_type; + signal fl_cnt : std_logic_vector(3 downto 0); + signal fl_oe_nd : std_logic; --output enable for flash +begin + +fl_rp_n <= reset_n; --make flash reset +fl_addr <= mem_addr(23 downto 0); +fl_byte_n <= '0'; --all byte accesses + + +fl_oe_n<=fl_oe_nd; +fl_data <= mem_di when fl_oe_nd ='1' else + (others =>'Z'); + + + +RD: process (clk, reset_n) +begin -- process READ + if reset_n='0' then + fl_oe_nd <='1'; + CS <= RESETs; + fl_cnt <= (others=>'0'); + mem_do <= (others=>'0'); + mem_ack <='0'; + elsif clk'event and clk = '1' then -- rising clock edge + case CS is + when RESETs => + mem_ack <='0'; + fl_ce_n <= (not mem_val); --chipselect 4 flash + fl_we_n <= (not (mem_val and mem_wr)); --write enable 4 flash + if mem_val='1' and mem_wr = '0' then --READ + fl_oe_nd <='0'; + fl_cnt <= (others=>'0'); + CS <= FLREADs; + elsif mem_val='1' and mem_wr = '1' then --WRITE + fl_oe_nd <='1'; + fl_cnt <= (others=>'0'); + CS <= FLWRITEs; + end if; --elsif mem_cmd + when FLREADs => + fl_cnt <= fl_cnt + 1; + if fl_cnt=x"3" then --3 cycles later + mem_ack <='1'; + mem_do <= fl_data; --registered is nicer + elsif fl_cnt=x"4" then --4 cycles later + mem_ack <='0'; + fl_oe_nd <='1'; + CS <= WAITs; + end if; + when FLWRITEs => + fl_cnt <= fl_cnt + 1; + if fl_cnt=x"3" then --3 cycles later + mem_ack <='1'; + elsif fl_cnt=x"4" then --4 cycles later + mem_ack <='0'; + CS <= WAITs; + end if; + when WAITs => + if mem_val='0' then -- wait untill val is removed + CS <= RESETs; + end if; + end case; + + end if; --system +end process RD; + + + + +end RTL; +

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