URL
https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk
Subversion Repositories usb_fpga_1_11
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb_fpga_1_11/trunk/examples/usb-fpga-1.11/1.11b/intraffic
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/InTraffic.java
1,6 → 1,6
/*! |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB FPGA Module 1.11 |
Copyright (C) 2009-2010 ZTEX e.K. |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11b |
Copyright (C) 2009-2011 ZTEX GmbH. |
http://www.ztex.de |
|
This program is free software; you can redistribute it and/or modify |
/intraffic.c
1,6 → 1,6
/*! |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB FPGA Module 1.11 |
Copyright (C) 2009-2010 ZTEX e.K. |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11b |
Copyright (C) 2009-2011 ZTEX GmbH. |
http://www.ztex.de |
|
This program is free software; you can redistribute it and/or modify |
/fpga/intraffic.ucf
13,8 → 13,8
NET "SLOE" LOC = "T3" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2 |
NET "CONT" LOC = "R11" | IOSTANDARD = LVCMOS33 ; # PA3 |
NET "FIFOADR0" LOC = "T10" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4 |
NET "FIFOADR1" LOC = "H14" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5 |
NET "PKTEND" LOC = "H13" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6 |
NET "FIFOADR1" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5 |
NET "PKTEND" LOC = "T11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6 |
# NET "PA7" LOC = "H11" | IOSTANDARD = LVCMOS33 ; |
|
NET "FD<0>" LOC = "C16" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; |
/fpga/intraffic.ise
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/fpga/intraffic.xise
97,7 → 97,7
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="EDIF" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/> |