OpenCores

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/memtest.bit

memtest.bit Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: ipcore_dir/mem0_xmdf.tcl =================================================================== --- ipcore_dir/mem0_xmdf.tcl (revision 5) +++ ipcore_dir/mem0_xmdf.tcl (nonexistent) @@ -1,78 +0,0 @@ -# The package naming convention is _xmdf -package provide mem0_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::mem0_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::mem0_xmdf::xmdfInit { instance } { - # Variable containing name of library into which module is compiled - # Recommendation: - # Required - utilities_xmdf::xmdfSetData $instance Module Attributes Name mem0 -} -# ::mem0_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::mem0_xmdf::xmdfApplyParams { instance } { - -set fcount 0 - # Array containing libraries that are assumed to exist - # Examples include unisim and xilinxcorelib - # Optional - # In this example, we assume that the unisim library will - # be magically - # available to the simulation and synthesis tool - utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library - utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim - incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/iodrp_controller.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/iodrp_mcb_controller.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mcb_raw_wrapper.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mcb_soft_calibration.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mcb_soft_calibration_top.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mem0.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/memc3_infrastructure.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/memc3_wrapper.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/par/mem0.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module mem0 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams Index: ipcore_dir/dcm0_xmdf.tcl =================================================================== --- ipcore_dir/dcm0_xmdf.tcl (revision 5) +++ ipcore_dir/dcm0_xmdf.tcl (nonexistent) @@ -1,160 +0,0 @@ -# The package naming convention is _xmdf -package provide dcm0_xmdf 1.0 - -# This includes some utilities that support common XMDF operations -package require utilities_xmdf - -# Define a namespace for this package. The name of the name space -# is _xmdf -namespace eval ::dcm0_xmdf { -# Use this to define any statics -} - -# Function called by client to rebuild the params and port arrays -# Optional when the use context does not require the param or ports -# arrays to be available. -proc ::dcm0_xmdf::xmdfInit { instance } { -# Variable containg name of library into which module is compiled -# Recommendation: -# Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name dcm0 -} -# ::dcm0_xmdf::xmdfInit - -# Function called by client to fill in all the xmdf* data variables -# based on the current settings of the parameters -proc ::dcm0_xmdf::xmdfApplyParams { instance } { - -set fcount 0 -# Array containing libraries that are assumed to exist -# Examples include unisim and xilinxcorelib -# Optional -# In this example, we assume that the unisim library will -# be magically -# available to the simulation and synthesis tool -utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library -utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/clk_wiz_readme.txt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/dcm0.ucf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/doc/clk_wiz_ds709.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/doc/clk_wiz_gsg521.pdf -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/example_design/dcm0_exdes.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/example_design/dcm0_exdes.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/implement.bat -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/implement.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/xst.prj -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/xst.scr -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/dcm0_tb.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/dcm0_tb.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simcmds.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_isim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_mti.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_ncsim.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_vcs.sh -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/ucli_commands.key -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/vcs_session.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/wave.do -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/wave.sv -utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.asy -utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.ejp -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.v -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.veo -utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.vhd -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.vho -utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.xco -utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0_xmdf.tcl -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount - -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module dcm0 -incr fcount - -} - -# ::gen_comp_name_xmdf::xmdfApplyParams Index: ipcore_dir/dcm0.vhd =================================================================== --- ipcore_dir/dcm0.vhd (revision 5) +++ ipcore_dir/dcm0.vhd (nonexistent) @@ -1,160 +0,0 @@ --- file: dcm0.vhd --- --- DISCLAIMER OF LIABILITY --- --- This file contains proprietary and confidential information of --- Xilinx, Inc. ("Xilinx"), that is distributed under a license --- from Xilinx, and may be used, copied and/or disclosed only --- pursuant to the terms of a valid license agreement with Xilinx. --- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION --- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER --- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT --- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, --- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx --- does not warrant that functions included in the Materials will --- meet the requirements of Licensee, or that the operation of the --- Materials will be uninterrupted or error-free, or that defects --- in the Materials will be corrected. Furthermore, Xilinx does --- not warrant or make any representations regarding use, or the --- results of the use, of the Materials in terms of correctness, --- accuracy, reliability or otherwise. --- --- Xilinx products are not designed or intended to be fail-safe, --- or for use in any application requiring fail-safe performance, --- such as life-support or safety devices or systems, Class III --- medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could --- lead to death, personal injury or severe property or --- environmental damage (individually and collectively, "critical --- applications"). Customer assumes the sole risk and liability --- of any use of Xilinx products in critical applications, --- subject only to applicable laws and regulations governing --- limitations on product liability. --- --- Copyright 2008, 2009 Xilinx, Inc. --- All rights reserved. --- --- This disclaimer and copyright notice must be retained as part --- of this file at all times. --- ------------------------------------------------------------------------------- --- User entered comments ------------------------------------------------------------------------------- --- None --- ------------------------------------------------------------------------------- --- Output Output Phase Duty Cycle Pk-to-Pk Phase --- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) ------------------------------------------------------------------------------- --- CLK_OUT1 200.000 0.000 N/A 217.125 N/A --- CLK_OUT2 50.000 0.000 N/A 207.125 N/A --- ------------------------------------------------------------------------------- --- Input Clock Input Freq (MHz) Input Jitter (UI) ------------------------------------------------------------------------------- --- primary 48.000 0.010 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -entity dcm0 is -port - (-- Clock in ports - CLK_IN1 : in std_logic; - -- Clock out ports - CLK_OUT1 : out std_logic; - CLK_OUT2 : out std_logic; - -- Status and control signals - RESET : in std_logic; - LOCKED : out std_logic; - CLK_VALID : out std_logic - ); -end dcm0; - -architecture xilinx of dcm0 is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm0,clk_wiz_v1_4,{component_name=dcm0,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,diff_ext_feedback=false,primtype_sel=DCM_CLKGEN,num_out_clk=2,clkin1_period=20.83333,clkin2_period=20.83333,use_power_down=false}"; - -- Input clock buffering / unused connectors - signal clkin1 : std_logic; - -- Output clock buffering / unused connectors - signal clkfx : std_logic; - signal clkfx180_unused : std_logic; - signal clkfxdv : std_logic; - signal clkfbout : std_logic; - -- Dynamic programming unused signals - signal progdone_unused : std_logic; - signal locked_internal : std_logic; - signal status_internal : std_logic_vector(2 downto 1); - -begin - - - -- Input buffering - -------------------------------------- - clkin1_buf : IBUFG - port map - (O => clkin1, - I => CLK_IN1); - - - -- Clocking primitive - -------------------------------------- - -- Instantiation of the DCM primitive - -- * Unused inputs are tied off - -- * Unused outputs are labeled unused - dcm_clkgen_inst: DCM_CLKGEN - generic map - (CLKFXDV_DIVIDE => 4, - CLKFX_DIVIDE => 6, - CLKFX_MULTIPLY => 25, - SPREAD_SPECTRUM => "NONE", - STARTUP_WAIT => FALSE, - CLKIN_PERIOD => 20.83333, - CLKFX_MD_MAX => 0.000) - port map - -- Input clock - (CLKIN => clkin1, - -- Output clocks - CLKFX => clkfx, - CLKFX180 => clkfx180_unused, - CLKFXDV => clkfxdv, - -- Ports for dynamic phase shift - PROGCLK => '0', - PROGEN => '0', - PROGDATA => '0', - PROGDONE => progdone_unused, - -- Other control and status signals - FREEZEDCM => '0', - LOCKED => locked_internal, - STATUS => status_internal, - RST => RESET); - - LOCKED <= locked_internal; - CLK_VALID <= ( locked_internal and ( not status_internal(2) ) ); - - -- Output buffering - ------------------------------------- - - - clkout1_buf : AUTOBUF - generic map - (BUFFER_TYPE => "BUFG") - port map - (O => CLK_OUT1, - I => clkfx); - - - clkout2_buf : AUTOBUF - generic map - (BUFFER_TYPE => "BUFG") - port map - (O => CLK_OUT2, - I => clkfxdv); -end xilinx;

ipcore_dir/dcm0.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd (nonexistent) @@ -1,1384 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version: %version --- \ \ Application: MIG --- / / Filename: mcb_soft_calibration.vhd --- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:38 $ --- \ \ / \ Date Created: Mon Feb 9 2009 --- \___\/\___\ --- ---Device: Spartan6 ---Design Name: DDR/DDR2/DDR3/LPDDR ---Purpose: Xilinx reference design for MCB Soft --- Calibration ---Reference: --- --- Revision: Date: Comment --- 1.0: 2/06/09: Initial version for MIG wrapper. --- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working --- correctly) --- 1.2: 2/12/09: Many other changes. --- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within --- STATE --- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE --- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. --- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. --- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets --- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to --- RST_DELAY. --- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least --- 16 clocks. Added PNSKEW option. --- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. --- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. --- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced --- with 8bit TARGET_DQS_DELAY which --- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL. --- Changed DQS_COUNT* to DQS_DELAY*. --- Changed MCB_SYSRST port back to wire (from reg). --- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG) --- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. --- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; --- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) --- 3.4: 03/04/10: Recoded the RST_Reg logic. --- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) --- 3.6 03/10/10: Improvements to Reset logic. --- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . --- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL). --- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. - --- End Revision ---********************************************************************************** - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - USE ieee.numeric_std.all; - -entity mcb_soft_calibration is - generic ( - C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets - SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration - SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration - SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration - C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value - -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY - -- (Quarter, etc) - C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented - C_MEM_TYPE : string := "DDR" - - - ); - port ( - UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB - -- CLK pins - RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST - DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB - -- hard calib complete) - PLL_LOCK : in std_logic; -- Lock signal from PLL - SELFREFRESH_REQ : in std_logic; - SELFREFRESH_MCB_MODE : in std_logic; - SELFREFRESH_MCB_REQ : out std_logic; - SELFREFRESH_MODE : out std_logic; - IODRP_ADD : out std_logic; -- IODRP ADD port - IODRP_SDI : out std_logic; -- IODRP SDI port - RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground - RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port - RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port - ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally - ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port - ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port - MCB_UIADD : out std_logic; -- to MCB's UIADD port - MCB_UISDI : out std_logic; -- to MCB's UISDI port - MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) - MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete - MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive - MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) - MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used - -- during IODRP2_MCB writes). Currently just trasnparent - MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) - MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port - MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block - MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state - MCB_UIDQLOWERDEC : out std_logic := '0'; - MCB_UIDQLOWERINC : out std_logic := '0'; - MCB_UIDQUPPERDEC : out std_logic := '0'; - MCB_UIDQUPPERINC : out std_logic := '0'; - MCB_UILDQSDEC : out std_logic := '0'; - MCB_UILDQSINC : out std_logic := '0'; - MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in - -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. - MCB_UIUDQSDEC : out std_logic := '0'; - MCB_UIUDQSINC : out std_logic := '0'; - MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high - MCB_UICMD : out std_logic; - MCB_UICMDIN : out std_logic; - MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); - MCB_UODATA : in std_logic_vector(7 downto 0); - MCB_UODATAVALID : in std_logic; - MCB_UOCMDREADY : in std_logic; - MCB_UO_CAL_START : in std_logic; - MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB - Max_Value : out std_logic_vector(7 downto 0); - CKE_Train : out std_logic - ); -end entity mcb_soft_calibration; - -architecture trans of mcb_soft_calibration is - - constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1'); - constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0'); - constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1'); - constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0'); - constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1'); - constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0'); - constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1'); - constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0'); - constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1'); - constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0'); - constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1'); - constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0'); - constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1'); - constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0'); - constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1'); - constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0'); - constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1'); - constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0'); - constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1'); - constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0'); - constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1'); - constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0'); - constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1'); - constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0'); - constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1'); - constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0'); - constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1'); - constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0'); - constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1'); - constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0'); - constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1'); - constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0'); - - constant START : std_logic_vector(5 downto 0) := "000000"; - constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001"; - constant WAIT1 : std_logic_vector(5 downto 0) := "000010"; - constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011"; - constant WAIT2 : std_logic_vector(5 downto 0) := "000100"; - constant INC_PTERM : std_logic_vector(5 downto 0) := "000101"; - constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110"; - constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111"; - constant WAIT3 : std_logic_vector(5 downto 0) := "001000"; - constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001"; - constant WAIT4 : std_logic_vector(5 downto 0) := "001010"; - constant INC_NTERM : std_logic_vector(5 downto 0) := "001011"; - constant SKEW : std_logic_vector(5 downto 0) := "001100"; - constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101"; - constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110"; - constant WAIT5 : std_logic_vector(5 downto 0) := "001111"; - constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000"; - constant WAIT6 : std_logic_vector(5 downto 0) := "010001"; - constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "010010"; - constant WAIT7 : std_logic_vector(5 downto 0) := "010011"; - constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "010100"; - constant WAIT8 : std_logic_vector(5 downto 0) := "010101"; - constant RST_DELAY : std_logic_vector(5 downto 0) := "010110"; - constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "010111"; - constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "011000"; - constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "011001"; - constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "011010"; - constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "011011"; - constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "011100"; - constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "011101"; - constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "011110"; - constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "011111"; - constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "100000"; - constant START_DYN_CAL : std_logic_vector(5 downto 0) := "100001"; - constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "100010"; - constant WAIT9 : std_logic_vector(5 downto 0) := "100011"; - constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "100100"; - constant WAIT10 : std_logic_vector(5 downto 0) := "100101"; - constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "100110"; - constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "100111"; - constant INCREMENT : std_logic_vector(5 downto 0) := "101000"; - constant DECREMENT : std_logic_vector(5 downto 0) := "101001"; - constant DONE : std_logic_vector(5 downto 0) := "101010"; - - constant RZQ : std_logic_vector(1 downto 0) := "00"; - constant ZIO : std_logic_vector(1 downto 0) := "01"; - constant MCB_PORT : std_logic_vector(1 downto 0) := "11"; - constant WRITE_MODE : std_logic := '0'; - constant READ_MODE : std_logic := '1'; - - -- IOI Registers - constant NoOp : std_logic_vector(7 downto 0) := "00000000"; - constant DelayControl : std_logic_vector(7 downto 0) := "00000001"; - constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010"; - constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011"; - constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100"; - constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101"; - constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110"; - constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111"; - constant MaxValue : std_logic_vector(7 downto 0) := "00001000"; - - -- IOB Registers - constant PDrive : std_logic_vector(7 downto 0) := "10000000"; - constant PTerm : std_logic_vector(7 downto 0) := "10000001"; - constant NDrive : std_logic_vector(7 downto 0) := "10000010"; - constant NTerm : std_logic_vector(7 downto 0) := "10000011"; - constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100"; - constant LVDSControl : std_logic_vector(7 downto 0) := "10000101"; - constant MiscControl : std_logic_vector(7 downto 0) := "10000110"; - constant InputControl : std_logic_vector(7 downto 0) := "10000111"; - constant TestReadback : std_logic_vector(7 downto 0) := "10001000"; - --- No multi/divide is required when a 55 ohm resister is used on RZQ --- localparam MULT = 1; --- localparam DIV = 1; --- use 7/4 scaling factor when the 100 ohm RZQ is used - constant MULT : integer := 7; - constant DIV : integer := 4; - - constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required - constant PSKEW_MULT : integer := 9; - constant PSKEW_DIV : integer := 8; - constant NSKEW_MULT : integer := 7; - constant NSKEW_DIV : integer := 8; - - constant DQS_NUMERATOR : integer := 3; - constant DQS_DENOMINATOR : integer := 8; - constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03"; - -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, - -- 3 for three eighths - - constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000"; - constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := C_MEM_TZQINIT_MAXCNT + RST_CNT; - - constant IN_TERM_PASS : std_logic := '0'; - constant DYN_CAL_PASS : std_logic := '1'; - - component iodrp_mcb_controller is - port ( - memcell_address : in std_logic_vector(7 downto 0); - write_data : in std_logic_vector(7 downto 0); - read_data : out std_logic_vector(7 downto 0); - rd_not_write : in std_logic; - cmd_valid : in std_logic; - rdy_busy_n : out std_logic; - use_broadcast : in std_logic; - drp_ioi_addr : in std_logic_vector(4 downto 0); - sync_rst : in std_logic; - DRP_CLK : in std_logic; - DRP_CS : out std_logic; - DRP_SDI : out std_logic; - DRP_ADD : out std_logic; - DRP_BKST : out std_logic; - DRP_SDO : in std_logic; - MCB_UIREAD : out std_logic - ); - end component; - - component iodrp_controller is - port ( - memcell_address : in std_logic_vector(7 downto 0); - write_data : in std_logic_vector(7 downto 0); - read_data : out std_logic_vector(7 downto 0); - rd_not_write : in std_logic; - cmd_valid : in std_logic; - rdy_busy_n : out std_logic; - use_broadcast : in std_logic; - sync_rst : in std_logic; - DRP_CLK : in std_logic; - DRP_CS : out std_logic; - DRP_SDI : out std_logic; - DRP_ADD : out std_logic; - DRP_BKST : out std_logic; - DRP_SDO : in std_logic - ); - end component; - - signal P_Term : std_logic_vector(5 downto 0) := "000000"; - signal N_Term : std_logic_vector(6 downto 0) := "0000000"; - signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000"; - signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000"; - - signal STATE : std_logic_vector(5 downto 0) := START; - signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0); - signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0); - signal Active_IODRP : std_logic_vector(1 downto 0); - signal IODRPCTRLR_R_WB : std_logic := '0'; - signal IODRPCTRLR_CMD_VALID : std_logic := '0'; - signal IODRPCTRLR_USE_BKST : std_logic := '0'; - signal MCB_CMD_VALID : std_logic := '0'; - signal MCB_USE_BKST : std_logic := '0'; - signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's - -- SYSRST pin (MCB_SYSRST) - signal IODRP_SDO : std_logic; - signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000"; - signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit - signal counter_en : std_logic := '0'; -- counter enable for "count" - signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done - signal START_BROADCAST : std_logic := '1'; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - - -- state machine will wait for this to be high - signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000"; - signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays - signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if - -- the Max Value changes by more than the threshold - signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with - -- latency on UOREFRSHFLAG) - signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with - -- latency on UOREFRSHFLAG) - signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0); - signal IODRPCTRLR_RDY_BUSY_N : std_logic; - signal IODRP_CS : std_logic; - signal MCB_READ_DATA : std_logic_vector(7 downto 0); - signal RST_reg : std_logic; - signal Block_Reset : std_logic; - signal MCB_UODATAVALID_U : std_logic; - - signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place - signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read - signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up - signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read - signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn - - signal RstCounter : std_logic_vector(9 downto 0) := (others => '0'); - signal rst_tmp : std_logic; - signal LastPass_DynCal : std_logic; - signal First_In_Term_Done : std_logic; - signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay - signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay - - signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE - -- parameter = "CALIBRATION" - signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays - signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays - signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the - -- one-time or dynamic parameters are 1 - signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either - -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION - signal Quarter_Max_Value : std_logic_vector(7 downto 0); - signal Half_Max_Value : std_logic_vector(7 downto 0); - signal PLL_LOCK_R1 : std_logic; - signal PLL_LOCK_R2 : std_logic; - signal MCB_RDY_BUSY_N : std_logic; - - signal SELFREFRESH_REQ_R1 : std_logic; - signal SELFREFRESH_REQ_R2 : std_logic; - signal SELFREFRESH_REQ_R3 : std_logic; - signal SELFREFRESH_MCB_MODE_R1 : std_logic; - signal SELFREFRESH_MCB_MODE_R2 : std_logic; - signal SELFREFRESH_MCB_MODE_R3 : std_logic; - signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic; - signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic; - signal START_DYN_CAL_STATE_R1 : std_logic; - signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic; - - -- Declare intermediate signals for referenced outputs - signal IODRP_ADD_xilinx0 : std_logic; - signal IODRP_SDI_xilinx1 : std_logic; - signal MCB_UIADD_xilinx2 : std_logic; - signal MCB_UISDI_xilinx11 : std_logic; - signal MCB_UICS_xilinx6 : std_logic; - signal MCB_UIBROADCAST_xilinx4 : std_logic; - signal MCB_UIADDR_xilinx3 : std_logic_vector(4 downto 0); - signal MCB_UIDONECAL_xilinx7 : std_logic; - signal MCB_UIREAD_xilinx10 : std_logic; - signal SELFREFRESH_MODE_xilinx11 : std_logic; - signal Max_Value_int : std_logic_vector(7 downto 0); - signal Rst_condition1 : std_logic; - signal Rst_condition2 : std_logic; - signal non_violating_rst : std_logic; - signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0); - -- This function multiplies by a constant MULT and then divides by the DIV constant - function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is - variable Result : integer := 0; - variable temp : std_logic_vector(14 downto 0) := "000000000000000"; - begin - for count in 0 to (MULT-1) loop - temp := temp + ("0000000" & Input); - end loop; - Result := (to_integer(unsigned(temp))) / (DIV); - temp := std_logic_vector(to_unsigned(Result,15)); - return temp(7 downto 0); - end function Mult_Divide; - - attribute syn_preserve : boolean; - attribute syn_preserve of P_Term : signal is TRUE; - attribute syn_preserve of N_Term : signal is TRUE; - attribute syn_preserve of P_Term_Prev : signal is TRUE; - attribute syn_preserve of N_Term_Prev : signal is TRUE; - attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE; - attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE; - attribute syn_preserve of Max_Value_Previous : signal is TRUE; - attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE; - - attribute iob : string; - attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE"; - -begin - - Max_Value <= Max_Value_int; - -- Drive referenced outputs - IODRP_ADD <= IODRP_ADD_xilinx0; - IODRP_SDI <= IODRP_SDI_xilinx1; - MCB_UIADD <= MCB_UIADD_xilinx2; - MCB_UISDI <= MCB_UISDI_xilinx11; - MCB_UICS <= MCB_UICS_xilinx6; - MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4; - MCB_UIADDR <= MCB_UIADDR_xilinx3; - MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7; - MCB_UIREAD <= MCB_UIREAD_xilinx10; - SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11; - - Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG); - Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous; - Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1)); - Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int; - Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1)); - CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1 - Half_Max_Value <= ('0' & Max_Value_int(7 downto 1)); - Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2)); - DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here - DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here - SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; - -- skip dynamic input termination if either the one-time or dynamic parameters are 1 - SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; - -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION - - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then - DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high - else - DONE_SOFTANDHARD_CAL <= '0'; - end if; - end if; - end process; - - iodrp_controller_inst : iodrp_controller - port map ( - memcell_address => IODRPCTRLR_MEMCELL_ADDR, - write_data => IODRPCTRLR_WRITE_DATA, - read_data => IODRPCTRLR_READ_DATA, - rd_not_write => IODRPCTRLR_R_WB, - cmd_valid => IODRPCTRLR_CMD_VALID, - rdy_busy_n => IODRPCTRLR_RDY_BUSY_N, - use_broadcast => '0', - sync_rst => RST_reg, - DRP_CLK => UI_CLK, - DRP_CS => IODRP_CS, - DRP_SDI => IODRP_SDI_xilinx1, - DRP_ADD => IODRP_ADD_xilinx0, - DRP_SDO => IODRP_SDO, - DRP_BKST => open - ); - - iodrp_mcb_controller_inst : iodrp_mcb_controller - port map ( - memcell_address => IODRPCTRLR_MEMCELL_ADDR, - write_data => IODRPCTRLR_WRITE_DATA, - read_data => MCB_READ_DATA, - rd_not_write => IODRPCTRLR_R_WB, - cmd_valid => MCB_CMD_VALID, - rdy_busy_n => MCB_RDY_BUSY_N, - use_broadcast => MCB_USE_BKST, - drp_ioi_addr => MCB_UIADDR_xilinx3, - sync_rst => RST_reg, - DRP_CLK => UI_CLK, - DRP_CS => MCB_UICS_xilinx6, - DRP_SDI => MCB_UISDI_xilinx11, - DRP_ADD => MCB_UIADD_xilinx2, - DRP_BKST => MCB_UIBROADCAST_xilinx4, - DRP_SDO => MCB_UOSDO, - MCB_UIREAD => MCB_UIREAD_xilinx10 - ); - - init_sequence: if (C_SIMULATION = "FALSE") generate - process (UI_CLK, RST) begin - if (RST = '1') then - WAIT_200us_COUNTER <= (others => '0'); - elsif (UI_CLK'event and UI_CLK = '1') then - if (WAIT_200us_COUNTER(15) = '1') then - WAIT_200us_COUNTER <= WAIT_200us_COUNTER; - else - WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1'; - end if; - end if; - end process; - end generate; - - init_sequence_skip: if (C_SIMULATION = "TRUE") generate - WAIT_200us_COUNTER <= X"FFFF"; - end generate; - - - gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate - process (UI_CLK, RST) begin - if (RST = '1') then - CKE_Train <= '0'; - elsif (UI_CLK'event and UI_CLK = '1') then - if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then - CKE_Train <= '0'; - elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then - CKE_Train <= '1'; - end if; - end if; - end process; - end generate ; - - gen_CKE_Train_b: if (C_MEM_TYPE /= "DDR2") generate - process (UI_CLK) begin - if (UI_CLK'event and UI_CLK = '1') then - CKE_Train <= '0'; - end if; - end process; - end generate ; - ---******************************************** --- PLL_LOCK and RST signals ---******************************************** - MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's - -- SYSRST pin (MCB_SYSRST) - rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND - - process (UI_CLK, rst_tmp, RST) begin - if (rst_tmp = '1') then - Block_Reset <= '0'; - RstCounter <= (others => '0'); - elsif (RST = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets -- to DDR3) - Block_Reset <= '0'; - RstCounter <= (others => '0'); - elsif (UI_CLK'event and UI_CLK = '1') then - Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state - if (Pre_SYSRST = '1') then - RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10 - else - if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute - Block_Reset <= '1'; -- STATE won't exit RST_DELAY state - RstCounter <= RstCounter + "1"; -- and Rst_Counter increments - end if; - end if; - end if; - end process; - - non_violating_rst <= RST and Rst_condition1; - process (UI_CLK) begin - if (UI_CLK'event and UI_CLK = '1') then - if (RstCounter >= TZQINIT_MAXCNT) then - Rst_condition1 <= '1'; - else - Rst_condition1 <= '0'; - end if; - end if; - end process; - - - - process (UI_CLK) begin - if (UI_CLK'event and UI_CLK = '1') then - - if (RstCounter < RST_CNT) then - Rst_condition2 <= '1'; - else - Rst_condition2 <= '0'; - end if; - end if; - end process; - - process (UI_CLK, non_violating_rst) begin - if (non_violating_rst = '1') then - RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND - elsif (UI_CLK'event and UI_CLK = '1') then - if (WAIT_200us_COUNTER(15) = '0') then - RST_reg <= '0'; - else - RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long - end if; - end if; - end process; - - ---******************************************** --- SUSPEND Logic ---******************************************** - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 - SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; - SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; - SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; - - -- SELFREFRESH_REQ is clocked by user's application clock - SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; - SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; - SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; - - PLL_LOCK_R1 <= PLL_LOCK; - PLL_LOCK_R2 <= PLL_LOCK_R1; - - end if; - end process; - --- SELFREFRESH should only be deasserted after PLL_LOCK is asserted. --- This is to make sure MCB get a locked sys_2x_clk before exiting --- SELFREFRESH mode. - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if (RST = '1') then - SELFREFRESH_MCB_REQ <= '0'; - elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R1 = '0') and (STATE = START_DYN_CAL)) then - SELFREFRESH_MCB_REQ <= '0'; - elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R1 = '1')) then - SELFREFRESH_MCB_REQ <= '1'; - end if; - end if; - end process; - - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if (RST = '1') then - WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; - elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then - WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1'; - elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then - -- START_DYN_CAL is next state - WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0'; - end if; - end if; - end process; - --- Need to detect when SM entering START_DYN_CAL - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if (RST = '1') then - PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; - START_DYN_CAL_STATE_R1 <= '0'; - else - -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle - PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; - if (STATE = START_DYN_CAL) then - START_DYN_CAL_STATE_R1 <= '1'; - else - START_DYN_CAL_STATE_R1 <= '0'; - end if; - if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then - PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1'; - elsif ((STATE = START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '0')) then - PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0'; - end if; - end if; - end if; - end process; - --- SELFREFRESH_MCB_MODE deasserted status is hold off --- until Soft_Calib has at least done one loop of DQS update. - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if (RST = '1') then - SELFREFRESH_MODE_xilinx11 <= '0'; - elsif (SELFREFRESH_MCB_MODE_R2 = '1') then - SELFREFRESH_MODE_xilinx11 <= '1'; - elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then - SELFREFRESH_MODE_xilinx11 <= '0'; - end if; - end if; - end process; - ---******************************************** ---Comparitor for Dynamic Calibration circuit ---******************************************** - Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0'; - Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0'; - ---********************************************************************************************* ---Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal ---********************************************************************************************* - process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if (RST_reg = '1') then - count <= "000000"; - elsif (counter_en = '1') then - count <= count + "000001"; - else - count <= "000000"; - end if; - end if; - end process; - ---********************************************************************************************* --- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide ---********************************************************************************************* - process (UI_CLK, MCB_UODATAVALID) - begin - if(MCB_UODATAVALID = '1') then - MCB_UODATAVALID_U <= '1'; - elsif(UI_CLK'event and UI_CLK = '1') then - MCB_UODATAVALID_U <= MCB_UODATAVALID; - end if; - end process; - ---************************************************************************************************************** ---Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) ---************************************************************************************************************** - process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO) - begin - case Active_IODRP is - when RZQ => - RZQ_IODRP_CS <= IODRP_CS; - ZIO_IODRP_CS <= '0'; - IODRP_SDO <= RZQ_IODRP_SDO; - when ZIO => - RZQ_IODRP_CS <= '0'; - ZIO_IODRP_CS <= IODRP_CS; - IODRP_SDO <= ZIO_IODRP_SDO; - when MCB_PORT => - RZQ_IODRP_CS <= '0'; - ZIO_IODRP_CS <= '0'; - IODRP_SDO <= '0'; - when others => - RZQ_IODRP_CS <= '0'; - ZIO_IODRP_CS <= '0'; - IODRP_SDO <= '0'; - end case; - end process; - ---****************************************************************** ---State Machine's Always block / Case statement for Next State Logic --- ---The WAIT1,2,etc states were required after every state where the ---DRP controller was used to do a write to the IODRPs - this is because ---there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller ---sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added ---soley for the purpose of reducing power, particularly on RZQ as ---that pin is expected to have a permanent external resistor to gnd. ---****************************************************************** - NEXT_STATE_LOGIC: process (UI_CLK) - begin - if (UI_CLK'event and UI_CLK = '1') then - if (RST_reg = '1') then -- Synchronous reset - MCB_CMD_VALID <= '0'; - MCB_UIADDR_xilinx3 <= "00000"; -- take control of UI/UO port - MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal. - MCB_UIDONECAL_xilinx7 <= '0'; - MCB_USE_BKST <= '0'; - MCB_UIDRPUPDATE <= '1'; - Pre_SYSRST <= '1'; -- keeps MCB in reset - IODRPCTRLR_CMD_VALID <= '0'; - IODRPCTRLR_MEMCELL_ADDR <= NoOp; - IODRPCTRLR_WRITE_DATA <= "00000000"; - IODRPCTRLR_R_WB <= WRITE_MODE; - IODRPCTRLR_USE_BKST <= '0'; - P_Term <= "000000"; - N_Term <= "0000000"; - P_Term_Prev <= "000000"; - N_Term_Prev <= "0000000"; - Active_IODRP <= RZQ; - MCB_UILDQSINC <= '0'; --no inc or dec - MCB_UIUDQSINC <= '0'; --no inc or dec - MCB_UILDQSDEC <= '0'; --no inc or dec - MCB_UIUDQSDEC <= '0'; - counter_en <= '0'; --flag that the First Dynamic Calibration completed - First_Dyn_Cal_Done <= '0'; - Max_Value_int <= "00000000"; - Max_Value_Previous <= "00000000"; - STATE <= START; - DQS_DELAY <= "00000000"; - DQS_DELAY_INITIAL <= "00000000"; - TARGET_DQS_DELAY <= "00000000"; - LastPass_DynCal <= IN_TERM_PASS; - First_In_Term_Done <= '0'; - MCB_UICMD <= '0'; - MCB_UICMDIN <= '0'; - MCB_UIDQCOUNT <= "0000"; - counter_inc <= "00000000"; - counter_dec <= "00000000"; - else - counter_en <= '0'; - IODRPCTRLR_CMD_VALID <= '0'; - IODRPCTRLR_MEMCELL_ADDR <= NoOp; - IODRPCTRLR_R_WB <= READ_MODE; - IODRPCTRLR_USE_BKST <= '0'; - MCB_CMD_VALID <= '0'; --no inc or dec - MCB_UILDQSINC <= '0'; --no inc or dec - MCB_UIUDQSINC <= '0'; --no inc or dec - MCB_UILDQSDEC <= '0'; --no inc or dec - MCB_UIUDQSDEC <= '0'; - MCB_USE_BKST <= '0'; - MCB_UICMDIN <= '0'; - DQS_DELAY <= DQS_DELAY; - TARGET_DQS_DELAY <= TARGET_DQS_DELAY; - - case STATE is - when START => --h00 - MCB_UICMDEN <= '1'; -- take control of UI/UO port - MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal. - P_Term <= "000000"; - N_Term <= "0000000"; - Pre_SYSRST <= '1'; -- keeps MCB in reset - LastPass_DynCal <= IN_TERM_PASS; - if (SKIP_IN_TERM_CAL = 1) then - STATE <= WRITE_CALIBRATE; - elsif (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= LOAD_RZQ_NTERM; - else - STATE <= START; - end if; - --*************************** - -- IOB INPUT TERMINATION CAL - --*************************** - when LOAD_RZQ_NTERM => --h01 - Active_IODRP <= RZQ; - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= NTerm; - IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); - IODRPCTRLR_R_WB <= WRITE_MODE; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= LOAD_RZQ_NTERM; - else - STATE <= WAIT1; - end if; - - when WAIT1 => --h02 - if (IODRPCTRLR_RDY_BUSY_N = '0') then - STATE <= WAIT1; - else - STATE <= LOAD_RZQ_PTERM; - end if; - - when LOAD_RZQ_PTERM => --h03 - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= PTerm; - IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); - IODRPCTRLR_R_WB <= WRITE_MODE; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= LOAD_RZQ_PTERM; - else - STATE <= WAIT2; - end if; - - when WAIT2 => --h04 - if (IODRPCTRLR_RDY_BUSY_N = '0') then - STATE <= WAIT2; - elsif ((RZQ_IN = '1') or (P_Term = "111111")) then - STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM - else - STATE <= INC_PTERM; - end if; - - when INC_PTERM => --h05 - P_Term <= P_Term + "000001"; - STATE <= LOAD_RZQ_PTERM; - - when MULTIPLY_DIVIDE => -- h06 - P_Term <= Mult_Divide(("00" & P_Term),MULT,DIV)(5 downto 0); - STATE <= LOAD_ZIO_PTERM; - - when LOAD_ZIO_PTERM => --h07 - Active_IODRP <= ZIO; - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= PTerm; - IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); - IODRPCTRLR_R_WB <= WRITE_MODE; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= LOAD_ZIO_PTERM; - else - STATE <= WAIT3; - end if; - - when WAIT3 => --h08 - if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then - STATE <= WAIT3; - else - STATE <= LOAD_ZIO_NTERM; - end if; - - when LOAD_ZIO_NTERM => --h09 - Active_IODRP <= ZIO; - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= NTerm; - IODRPCTRLR_WRITE_DATA <= ('0' & N_Term); - IODRPCTRLR_R_WB <= WRITE_MODE; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= LOAD_ZIO_NTERM; - else - STATE <= WAIT4; - end if; - - when WAIT4 => --h0A - if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then - STATE <= WAIT4; - elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then - if (PNSKEW = '1') then - STATE <= SKEW; - else - STATE <= WAIT_FOR_START_BROADCAST; - end if; - else - STATE <= INC_NTERM; - end if; - - when INC_NTERM => --h0B - N_Term <= N_Term + "0000001"; - STATE <= LOAD_ZIO_NTERM; - - when SKEW => -- h0C - P_Term <= Mult_Divide(("00" & P_Term), PSKEW_MULT, PSKEW_DIV)(5 downto 0); - N_Term <= Mult_Divide(('0' & N_Term), NSKEW_MULT, NSKEW_DIV)(6 downto 0); - STATE <= WAIT_FOR_START_BROADCAST; - - when WAIT_FOR_START_BROADCAST => --h0D - Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while - -- keeping the MCB in calibration mode - Active_IODRP <= MCB_PORT; - if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then - if (P_Term /= P_Term_Prev) then - STATE <= BROADCAST_PTERM; - P_Term_Prev <= P_Term; - elsif (N_Term /= N_Term_Prev) then - N_Term_Prev <= N_Term; - STATE <= BROADCAST_NTERM; - else - STATE <= OFF_RZQ_PTERM; - end if; - else - STATE <= WAIT_FOR_START_BROADCAST; - end if; - - when BROADCAST_PTERM => --h0E - IODRPCTRLR_MEMCELL_ADDR <= PTerm; - IODRPCTRLR_WRITE_DATA <= ("00" & P_Term); - IODRPCTRLR_R_WB <= WRITE_MODE; - MCB_CMD_VALID <= '1'; - MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through - MCB_USE_BKST <= '1'; - if (MCB_RDY_BUSY_N = '1') then - STATE <= BROADCAST_PTERM; - else - STATE <= WAIT5; - end if; - - when WAIT5 => --h0F - if ((not(MCB_RDY_BUSY_N)) = '1') then - STATE <= WAIT5; - elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term - if (MCB_UOREFRSHFLAG = '1')then - MCB_UIDRPUPDATE <= '1'; - if (N_Term /= N_Term_Prev) then - N_Term_Prev <= N_Term; - STATE <= BROADCAST_NTERM; - else - STATE <= OFF_RZQ_PTERM; - end if; - else - STATE <= WAIT5; -- wait for a Refresh cycle - end if; - else - N_Term_Prev <= N_Term; - STATE <= BROADCAST_NTERM; - end if; - - when BROADCAST_NTERM => -- h10 - IODRPCTRLR_MEMCELL_ADDR <= NTerm; - IODRPCTRLR_WRITE_DATA <= ("0" & N_Term); - IODRPCTRLR_R_WB <= WRITE_MODE; - MCB_CMD_VALID <= '1'; - MCB_USE_BKST <= '1'; - MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through - if (MCB_RDY_BUSY_N = '1') then - STATE <= BROADCAST_NTERM; - else - STATE <= WAIT6; - end if; - - when WAIT6 => -- h11 - if (MCB_RDY_BUSY_N = '0') then - STATE <= WAIT6; - elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term - if (MCB_UOREFRSHFLAG = '1')then - MCB_UIDRPUPDATE <= '1'; - STATE <= OFF_RZQ_PTERM; - else - STATE <= WAIT6; -- wait for a Refresh cycle - end if; - else - STATE <= OFF_RZQ_PTERM; - end if; - - when OFF_RZQ_PTERM => -- h12 - Active_IODRP <= RZQ; - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= PTerm; - IODRPCTRLR_WRITE_DATA <= "00000000"; - IODRPCTRLR_R_WB <= WRITE_MODE; - P_Term <= "000000"; - N_Term <= "0000000"; - MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= OFF_RZQ_PTERM; - else - STATE <= WAIT7; - end if; - - when WAIT7 => -- h13 - if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then - STATE <= WAIT7; - else - STATE <= OFF_ZIO_NTERM; - end if; - - when OFF_ZIO_NTERM => -- h14 - Active_IODRP <= ZIO; - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= NTerm; - IODRPCTRLR_WRITE_DATA <= "00000000"; - IODRPCTRLR_R_WB <= WRITE_MODE; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= OFF_ZIO_NTERM; - else - STATE <= WAIT8; - end if; - - when WAIT8 => -- h15 - if (IODRPCTRLR_RDY_BUSY_N = '0') then - STATE <= WAIT8; - else - if (First_In_Term_Done = '1') then - STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning - else - STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ - end if; - end if; - - when RST_DELAY => -- h16 - MCB_UICMDEN <= '0'; -- release control of UI/UO port - if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? - STATE <= RST_DELAY; - else - STATE <= START_DYN_CAL_PRE; - end if; - ---*************************** ---DYNAMIC CALIBRATION PORTION ---*************************** - when START_DYN_CAL_PRE => -- h17 - LastPass_DynCal <= IN_TERM_PASS; - MCB_UICMDEN <= '0'; -- release UICMDEN - MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. - Pre_SYSRST <= '1'; -- SYSRST pulse - if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION - STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually - else - STATE <= WAIT_FOR_UODONE; - end if; - - when WAIT_FOR_UODONE => -- h18 - Pre_SYSRST <= '0'; -- SYSRST pulse - if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration - MCB_UICMDEN <= '1'; -- grab UICMDEN - DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); - STATE <= LDQS_WRITE_POS_INDELAY; - else - STATE <= WAIT_FOR_UODONE; - end if; - - when LDQS_WRITE_POS_INDELAY => -- h19 - IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; - IODRPCTRLR_R_WB <= WRITE_MODE; - IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; - MCB_UIADDR_xilinx3 <= IOI_LDQS_CLK; - MCB_CMD_VALID <= '1'; - if (MCB_RDY_BUSY_N = '1') then - STATE <= LDQS_WRITE_POS_INDELAY; - else - STATE <= LDQS_WAIT1; - end if; - - when LDQS_WAIT1 => -- h1A - if (MCB_RDY_BUSY_N = '0')then - STATE <= LDQS_WAIT1; - else - STATE <= LDQS_WRITE_NEG_INDELAY; - end if; - - when LDQS_WRITE_NEG_INDELAY => -- h1B - IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; - IODRPCTRLR_R_WB <= WRITE_MODE; - IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; - MCB_UIADDR_xilinx3 <= IOI_LDQS_CLK; - MCB_CMD_VALID <= '1'; - if (MCB_RDY_BUSY_N = '1')then - STATE <= LDQS_WRITE_NEG_INDELAY; - else - STATE <= LDQS_WAIT2; - end if; - - when LDQS_WAIT2 => -- 7'h1C - if(MCB_RDY_BUSY_N = '0')then - STATE <= LDQS_WAIT2; - else - STATE <= UDQS_WRITE_POS_INDELAY; - end if; - - when UDQS_WRITE_POS_INDELAY => -- 7'h1D - IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; - IODRPCTRLR_R_WB <= WRITE_MODE; - IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; - MCB_UIADDR_xilinx3 <= IOI_UDQS_CLK; - MCB_CMD_VALID <= '1'; - if (MCB_RDY_BUSY_N = '1')then - STATE <= UDQS_WRITE_POS_INDELAY; - else - STATE <= UDQS_WAIT1; - end if; - - when UDQS_WAIT1 => -- 7'h1E - if (MCB_RDY_BUSY_N = '0')then - STATE <= UDQS_WAIT1; - else - STATE <= UDQS_WRITE_NEG_INDELAY; - end if; - - when UDQS_WRITE_NEG_INDELAY => -- 7'h1F - IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; - IODRPCTRLR_R_WB <= WRITE_MODE; - IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; - MCB_UIADDR_xilinx3 <= IOI_UDQS_CLK; - MCB_CMD_VALID <= '1'; - if (MCB_RDY_BUSY_N = '1')then - STATE <= UDQS_WRITE_NEG_INDELAY; - else - STATE <= UDQS_WAIT2; - end if; - - when UDQS_WAIT2 => -- 7'h20 - if (MCB_RDY_BUSY_N = '0')then - STATE <= UDQS_WAIT2; - else - DQS_DELAY <= DQS_DELAY_INITIAL; - TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; - STATE <= START_DYN_CAL; - end if; - - when START_DYN_CAL => -- h21 - Pre_SYSRST <= '0'; -- SYSRST not driven - counter_inc <= (others => '0'); - counter_dec <= (others => '0'); - if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then - STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE - elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then - --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration - -- Alternate between Dynamic Input Termination and Dynamic Tuning routines - if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then - LastPass_DynCal <= IN_TERM_PASS; - STATE <= LOAD_RZQ_NTERM; - else - LastPass_DynCal <= DYN_CAL_PASS; - STATE <= WRITE_CALIBRATE; - end if; - else - STATE <= START_DYN_CAL; - end if; - - when WRITE_CALIBRATE => -- h22 - Pre_SYSRST <= '0'; - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= DelayControl; - IODRPCTRLR_WRITE_DATA <= "00100000"; - IODRPCTRLR_R_WB <= WRITE_MODE; - Active_IODRP <= RZQ; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= WRITE_CALIBRATE; - else - STATE <= WAIT9; - end if; - - when WAIT9 => -- h23 - counter_en <= '1'; - if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE - STATE <= WAIT9; - else - STATE <= READ_MAX_VALUE; - end if; - - when READ_MAX_VALUE => -- h24 - IODRPCTRLR_CMD_VALID <= '1'; - IODRPCTRLR_MEMCELL_ADDR <= MaxValue; - IODRPCTRLR_R_WB <= READ_MODE; - Max_Value_Previous <= Max_Value_int; - if (IODRPCTRLR_RDY_BUSY_N = '1') then - STATE <= READ_MAX_VALUE; - else - STATE <= WAIT10; - end if; - - when WAIT10 => -- h25 - if (IODRPCTRLR_RDY_BUSY_N = '0') then - STATE <= WAIT10; - else - Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller - if (First_In_Term_Done = '0') then - STATE <= RST_DELAY; - First_In_Term_Done <= '1'; - else - STATE <= ANALYZE_MAX_VALUE; - end if; - end if; - - when ANALYZE_MAX_VALUE => -- h26 only do a Inc or Dec during a REFRESH cycle. - if (First_Dyn_Cal_Done = '0')then - STATE <= FIRST_DYN_CAL; - elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then - STATE <= DECREMENT; -- May need to Decrement - TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); - -- DQS_COUNT_VIRTUAL updated (could be negative value) - elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then - STATE <= INCREMENT; -- May need to Increment - TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR); - else - Max_Value_int <= Max_Value_Previous; - STATE <= START_DYN_CAL; - end if; - - when FIRST_DYN_CAL => -- h27 - First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed - STATE <= START_DYN_CAL; - - when INCREMENT => -- h28 - STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH - MCB_UILDQSINC <= '0'; -- Default case: no inc or dec - MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec - MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec - MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec - case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, - when "101" => - counter_inc <= counter_inc + '1'; - STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle - if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then - -- if not at the upper limit yet, and you've waited 4 clks, increment - MCB_UILDQSINC <= '1'; - MCB_UIUDQSINC <= '1'; - DQS_DELAY <= DQS_DELAY + '1'; - end if; - when "100" => - if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then - STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH - end if; - when others => - STATE <= START_DYN_CAL; - end case; - - when DECREMENT => -- h29 - STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH - MCB_UILDQSINC <= '0'; -- Default case: no inc or dec - MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec - MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec - MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec - if (DQS_DELAY /= "00000000") then - case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, - when "011" => - counter_dec <= counter_dec + '1'; - STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle - if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then - -- if not at the lower limit, and you've waited 4 clks, decrement - MCB_UILDQSDEC <= '1'; -- decrement - MCB_UIUDQSDEC <= '1'; -- decrement - DQS_DELAY <= DQS_DELAY - '1'; -- SBS - end if; - when "010" => - if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement - STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH - end if; - when others => - STATE <= START_DYN_CAL; - end case; - end if; - - when DONE => -- h2A - Pre_SYSRST <= '0'; -- SYSRST cleared - MCB_UICMDEN <= '0'; -- release UICMDEN - STATE <= DONE; - - when others => - MCB_UICMDEN <= '0'; -- release UICMDEN - MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize. - Pre_SYSRST <= '0'; -- SYSRST not driven - IODRPCTRLR_CMD_VALID <= '0'; - IODRPCTRLR_MEMCELL_ADDR <= "00000000"; - IODRPCTRLR_WRITE_DATA <= "00000000"; - IODRPCTRLR_R_WB <= '0'; - IODRPCTRLR_USE_BKST <= '0'; - P_Term <= "000000"; - N_Term <= "0000000"; - Active_IODRP <= ZIO; - Max_Value_Previous <= "00000000"; - MCB_UILDQSINC <= '0'; -- no inc or dec - MCB_UIUDQSINC <= '0'; -- no inc or dec - MCB_UILDQSDEC <= '0'; -- no inc or dec - MCB_UIUDQSDEC <= '0'; -- no inc or dec - counter_en <= '0'; - First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed - Max_Value_int <= Max_Value_int; - STATE <= START; - end case; - end if; - end if; - end process; - -end architecture trans; - -

ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd (nonexistent) @@ -1,372 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version: %version --- \ \ Application: MIG --- / / Filename: iodrp_controller.vhd --- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $ --- \ \ / \ Date Created: Mon Feb 9 2009 --- \___\/\___\ --- ---Device: Spartan6 ---Design Name: DDR/DDR2/DDR3/LPDDR ---Purpose: Xilinx reference design for IODRP controller for v0.9 device --- ---Reference: --- --- Revision: Date: Comment --- 1.0: 02/06/09: Initial version for MIG wrapper. --- 1.1: 02/01/09: updates to indentations. --- 1.2: 02/12/09: changed non-blocking assignments to blocking ones --- for state machine always block. Also, assigned --- intial value to load_shift_n to avoid latch --- End Revision ---******************************************************************************* - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - -entity iodrp_controller is - --output to IODRP SDI pin - --input from IODRP SDO pin - - -- Register where memcell_address is captured during the READY state - -- Register which stores the write data until it is ready to be shifted out - -- The shift register which shifts out SDO and shifts in SDI. - -- This register is loaded before the address or data phase, but continues - -- to shift for a writeback of read data - -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO - -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg - -- The counter for which bit is being shifted during address or data phase - -- This is set after the first address phase has executed - - -- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate; - - -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg - -- added so that DRP_SDI output is only active when DRP_CS is active - - port ( - memcell_address : in std_logic_vector(7 downto 0); - write_data : in std_logic_vector(7 downto 0); - read_data : out std_logic_vector(7 downto 0); - rd_not_write : in std_logic; - cmd_valid : in std_logic; - rdy_busy_n : out std_logic; - use_broadcast : in std_logic; - sync_rst : in std_logic; - DRP_CLK : in std_logic; - DRP_CS : out std_logic; - DRP_SDI : out std_logic; - DRP_ADD : out std_logic; - DRP_BKST : out std_logic; - DRP_SDO : in std_logic - ); -end entity iodrp_controller; - -architecture trans of iodrp_controller is - - - constant READY : std_logic_vector(2 downto 0) := "000"; - constant DECIDE : std_logic_vector(2 downto 0) := "001"; - constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010"; - constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011"; - constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100"; - constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101"; - constant DATA_PHASE : std_logic_vector(2 downto 0) := "110"; - constant ALMOST_READY : std_logic_vector(2 downto 0) := "111"; - - constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; - constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; - constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; - constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; - constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; - constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; - constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; - constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; - constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; - constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; - constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; - constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; - constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; - constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; - constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; - constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; - constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; - constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; - constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; - constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; - - - - - signal memcell_addr_reg : std_logic_vector(7 downto 0); - signal data_reg : std_logic_vector(7 downto 0); - signal shift_through_reg : std_logic_vector(7 downto 0); - signal load_shift_n : std_logic; - signal addr_data_sel_n : std_logic; - signal bit_cnt : std_logic_vector(2 downto 0); - signal rd_not_write_reg : std_logic; - signal AddressPhase : std_logic; - signal capture_read_data : std_logic; - signal state : std_logic_vector(2 downto 0); - signal nextstate : std_logic_vector(2 downto 0); - signal data_out_mux : std_logic_vector(7 downto 0); - signal DRP_SDI_pre : std_logic; - - signal ALMOST_READY_ST : std_logic; - signal ADDR_PHASE_ST : std_logic; - signal BIT_CNT7 : std_logic; - signal ADDR_PHASE_ST1 : std_logic; - signal DATA_PHASE_ST : std_logic; - - signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); -begin - --synthesis translate_off - --- process (state) --- begin --- case state is --- when READY => --- state_ascii <= "READY"; --- when DECIDE => --- state_ascii <= "DECIDE"; --- when ADDR_PHASE => --- state_ascii <= "ADDR_PHASE"; --- when ADDR_TO_DATA_GAP => --- state_ascii <= "ADDR_TO_DATA_GAP"; --- when ADDR_TO_DATA_GAP2 => --- state_ascii <= "ADDR_TO_DATA_GAP2"; --- when ADDR_TO_DATA_GAP3 => --- state_ascii <= "ADDR_TO_DATA_GAP3"; --- when DATA_PHASE => --- state_ascii <= "DATA_PHASE"; --- when ALMOST_READY => -- case(state) --- state_ascii <= "ALMOST_READY"; --- when others => --- null; --- end case; --- end process; - - --synthesis translate_on - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (state = READY) then - memcell_addr_reg <= memcell_address; - data_reg <= write_data; - rd_not_write_reg <= rd_not_write; - end if; - end if; - end process; - - - rdy_busy_n <= '1' when (state = READY) else '0'; - - data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else - data_reg; - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - shift_through_reg <= "00000000"; - else - if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first - shift_through_reg <= data_out_mux; - else - shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1)); - end if; - end if; - end if; - end process; - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then - bit_cnt <= bit_cnt + "001"; - else - bit_cnt <= "000"; - end if; - end if; - end process; - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - -- capture_read_data <= 1'b0; - read_data <= "00000000"; - else - -- capture_read_data <= (state == DATA_PHASE); - -- if(capture_read_data) - if (state = ALMOST_READY) then - -- else - -- read_data <= read_data; - read_data <= shift_through_reg; - end if; - end if; - end if; - end process; - - ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0'; - ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; - BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - AddressPhase <= '0'; - else - if (AddressPhase = '1') then - -- Keep it set until we finish the cycle - AddressPhase <= AddressPhase and (not ALMOST_READY_ST); - else - -- set the address phase when ever we finish the address phase - AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); - end if; - end if; - end if; - end process; - -ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; -DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - DRP_ADD <= ADDR_PHASE_ST1; - DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST; - if (state = READY) then - DRP_BKST <= use_broadcast; - end if; - end if; - end process; - - - -- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance - -- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance - DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data - - process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7) - begin - addr_data_sel_n <= '0'; - load_shift_n <= '0'; - case state is - when READY => - if (cmd_valid = '1') then - nextstate <= DECIDE; - else - nextstate <= READY; - end if; - when DECIDE => - load_shift_n <= '1'; - addr_data_sel_n <= '1'; - nextstate <= ADDR_PHASE; - -- After the second pass go to end of statemachine - -- execute a second address phase for the read access. - when ADDR_PHASE => - if (BIT_CNT7 = '1') then - if (rd_not_write_reg = '1') then - if (AddressPhase = '1') then - nextstate <= ALMOST_READY; - else - nextstate <= DECIDE; - end if; - else - nextstate <= ADDR_TO_DATA_GAP; - end if; - else - nextstate <= ADDR_PHASE; - end if; - when ADDR_TO_DATA_GAP => - load_shift_n <= '1'; - nextstate <= ADDR_TO_DATA_GAP2; - when ADDR_TO_DATA_GAP2 => - load_shift_n <= '1'; - nextstate <= ADDR_TO_DATA_GAP3; - when ADDR_TO_DATA_GAP3 => - load_shift_n <= '1'; - nextstate <= DATA_PHASE; - when DATA_PHASE => - if (BIT_CNT7 = '1') then - nextstate <= ALMOST_READY; - else - nextstate <= DATA_PHASE; - end if; - when ALMOST_READY => - nextstate <= READY; - when others => - nextstate <= READY; - end case; - end process; - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - state <= READY; - else - state <= nextstate; - end if; - end if; - end process; - - -end architecture trans; - -

ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ipcore_dir/mem0/user_design/rtl/mem0.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/mem0.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/mem0.vhd (nonexistent) @@ -1,832 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.5 --- \ \ Application : MIG --- / / Filename : mem0.vhd --- /___/ /\ Date Last Modified : $Date: 2010/05/18 11:08:59 $ --- \ \ / \ Date Created : Jul 03 2009 --- \___\/\___\ --- ---Device : Spartan-6 ---Design Name : DDR/DDR2/DDR3/LPDDR ---Purpose : This is the design top level. which instantiates top wrapper, --- test bench top and infrastructure modules. ---Reference : ---Revision History : ---***************************************************************************** -library ieee; -use ieee.std_logic_1164.all; -entity mem0 is -generic - ( - C3_P0_MASK_SIZE : integer := 4; - C3_P0_DATA_PORT_SIZE : integer := 32; - C3_P1_MASK_SIZE : integer := 4; - C3_P1_DATA_PORT_SIZE : integer := 32; - C3_MEMCLK_PERIOD : integer := 5000; - C3_RST_ACT_LOW : integer := 0; - C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; - C3_CALIB_SOFT_IP : string := "TRUE"; - C3_SIMULATION : string := "FALSE"; - DEBUG_EN : integer := 0; - C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; - C3_NUM_DQ_PINS : integer := 16; - C3_MEM_ADDR_WIDTH : integer := 13; - C3_MEM_BANKADDR_WIDTH : integer := 2 - ); - - port - ( - - mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); - mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); - mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); - mcb3_dram_cke : out std_logic; - mcb3_dram_ras_n : out std_logic; - mcb3_dram_cas_n : out std_logic; - mcb3_dram_we_n : out std_logic; - mcb3_dram_dm : out std_logic; - mcb3_dram_udqs : inout std_logic; - mcb3_rzq : inout std_logic; - mcb3_dram_udm : out std_logic; - c3_sys_clk : in std_logic; - c3_sys_rst_n : in std_logic; - c3_calib_done : out std_logic; - c3_clk0 : out std_logic; - c3_rst0 : out std_logic; - mcb3_dram_dqs : inout std_logic; - mcb3_dram_ck : out std_logic; - mcb3_dram_ck_n : out std_logic; - c3_p0_cmd_clk : in std_logic; - c3_p0_cmd_en : in std_logic; - c3_p0_cmd_instr : in std_logic_vector(2 downto 0); - c3_p0_cmd_bl : in std_logic_vector(5 downto 0); - c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0); - c3_p0_cmd_empty : out std_logic; - c3_p0_cmd_full : out std_logic; - c3_p0_wr_clk : in std_logic; - c3_p0_wr_en : in std_logic; - c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0); - c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); - c3_p0_wr_full : out std_logic; - c3_p0_wr_empty : out std_logic; - c3_p0_wr_count : out std_logic_vector(6 downto 0); - c3_p0_wr_underrun : out std_logic; - c3_p0_wr_error : out std_logic; - c3_p0_rd_clk : in std_logic; - c3_p0_rd_en : in std_logic; - c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); - c3_p0_rd_full : out std_logic; - c3_p0_rd_empty : out std_logic; - c3_p0_rd_count : out std_logic_vector(6 downto 0); - c3_p0_rd_overflow : out std_logic; - c3_p0_rd_error : out std_logic; - c3_p1_cmd_clk : in std_logic; - c3_p1_cmd_en : in std_logic; - c3_p1_cmd_instr : in std_logic_vector(2 downto 0); - c3_p1_cmd_bl : in std_logic_vector(5 downto 0); - c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0); - c3_p1_cmd_empty : out std_logic; - c3_p1_cmd_full : out std_logic; - c3_p1_wr_clk : in std_logic; - c3_p1_wr_en : in std_logic; - c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0); - c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); - c3_p1_wr_full : out std_logic; - c3_p1_wr_empty : out std_logic; - c3_p1_wr_count : out std_logic_vector(6 downto 0); - c3_p1_wr_underrun : out std_logic; - c3_p1_wr_error : out std_logic; - c3_p1_rd_clk : in std_logic; - c3_p1_rd_en : in std_logic; - c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); - c3_p1_rd_full : out std_logic; - c3_p1_rd_empty : out std_logic; - c3_p1_rd_count : out std_logic_vector(6 downto 0); - c3_p1_rd_overflow : out std_logic; - c3_p1_rd_error : out std_logic; - c3_p2_cmd_clk : in std_logic; - c3_p2_cmd_en : in std_logic; - c3_p2_cmd_instr : in std_logic_vector(2 downto 0); - c3_p2_cmd_bl : in std_logic_vector(5 downto 0); - c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0); - c3_p2_cmd_empty : out std_logic; - c3_p2_cmd_full : out std_logic; - c3_p2_wr_clk : in std_logic; - c3_p2_wr_en : in std_logic; - c3_p2_wr_mask : in std_logic_vector(3 downto 0); - c3_p2_wr_data : in std_logic_vector(31 downto 0); - c3_p2_wr_full : out std_logic; - c3_p2_wr_empty : out std_logic; - c3_p2_wr_count : out std_logic_vector(6 downto 0); - c3_p2_wr_underrun : out std_logic; - c3_p2_wr_error : out std_logic; - c3_p3_cmd_clk : in std_logic; - c3_p3_cmd_en : in std_logic; - c3_p3_cmd_instr : in std_logic_vector(2 downto 0); - c3_p3_cmd_bl : in std_logic_vector(5 downto 0); - c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0); - c3_p3_cmd_empty : out std_logic; - c3_p3_cmd_full : out std_logic; - c3_p3_rd_clk : in std_logic; - c3_p3_rd_en : in std_logic; - c3_p3_rd_data : out std_logic_vector(31 downto 0); - c3_p3_rd_full : out std_logic; - c3_p3_rd_empty : out std_logic; - c3_p3_rd_count : out std_logic_vector(6 downto 0); - c3_p3_rd_overflow : out std_logic; - c3_p3_rd_error : out std_logic; - c3_p4_cmd_clk : in std_logic; - c3_p4_cmd_en : in std_logic; - c3_p4_cmd_instr : in std_logic_vector(2 downto 0); - c3_p4_cmd_bl : in std_logic_vector(5 downto 0); - c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0); - c3_p4_cmd_empty : out std_logic; - c3_p4_cmd_full : out std_logic; - c3_p4_wr_clk : in std_logic; - c3_p4_wr_en : in std_logic; - c3_p4_wr_mask : in std_logic_vector(3 downto 0); - c3_p4_wr_data : in std_logic_vector(31 downto 0); - c3_p4_wr_full : out std_logic; - c3_p4_wr_empty : out std_logic; - c3_p4_wr_count : out std_logic_vector(6 downto 0); - c3_p4_wr_underrun : out std_logic; - c3_p4_wr_error : out std_logic; - c3_p5_cmd_clk : in std_logic; - c3_p5_cmd_en : in std_logic; - c3_p5_cmd_instr : in std_logic_vector(2 downto 0); - c3_p5_cmd_bl : in std_logic_vector(5 downto 0); - c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0); - c3_p5_cmd_empty : out std_logic; - c3_p5_cmd_full : out std_logic; - c3_p5_rd_clk : in std_logic; - c3_p5_rd_en : in std_logic; - c3_p5_rd_data : out std_logic_vector(31 downto 0); - c3_p5_rd_full : out std_logic; - c3_p5_rd_empty : out std_logic; - c3_p5_rd_count : out std_logic_vector(6 downto 0); - c3_p5_rd_overflow : out std_logic; - c3_p5_rd_error : out std_logic - ); -end mem0; - -architecture arc of mem0 is - - -component memc3_infrastructure is - generic ( - C_MEMCLK_PERIOD : integer; - C_RST_ACT_LOW : integer; - C_INPUT_CLK_TYPE : string; - C_CLKOUT0_DIVIDE : integer; - C_CLKOUT1_DIVIDE : integer; - C_CLKOUT2_DIVIDE : integer; - C_CLKOUT3_DIVIDE : integer; - C_CLKFBOUT_MULT : integer; - C_DIVCLK_DIVIDE : integer - - ); - port ( - sys_clk_p : in std_logic; - sys_clk_n : in std_logic; - sys_clk : in std_logic; - sys_rst_n : in std_logic; - clk0 : out std_logic; - rst0 : out std_logic; - async_rst : out std_logic; - sysclk_2x : out std_logic; - sysclk_2x_180 : out std_logic; - pll_ce_0 : out std_logic; - pll_ce_90 : out std_logic; - pll_lock : out std_logic; - mcb_drp_clk : out std_logic - - ); - end component; - - -component memc3_wrapper is - generic ( - C_MEMCLK_PERIOD : integer; - C_CALIB_SOFT_IP : string; - C_SIMULATION : string; - C_P0_MASK_SIZE : integer; - C_P0_DATA_PORT_SIZE : integer; - C_P1_MASK_SIZE : integer; - C_P1_DATA_PORT_SIZE : integer; - C_ARB_NUM_TIME_SLOTS : integer; - C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0); - C_MEM_TRAS : integer; - C_MEM_TRCD : integer; - C_MEM_TREFI : integer; - C_MEM_TRFC : integer; - C_MEM_TRP : integer; - C_MEM_TWR : integer; - C_MEM_TRTP : integer; - C_MEM_TWTR : integer; - C_MEM_ADDR_ORDER : string; - C_NUM_DQ_PINS : integer; - C_MEM_TYPE : string; - C_MEM_DENSITY : string; - C_MEM_BURST_LEN : integer; - C_MEM_CAS_LATENCY : integer; - C_MEM_ADDR_WIDTH : integer; - C_MEM_BANKADDR_WIDTH : integer; - C_MEM_NUM_COL_BITS : integer; - C_MEM_DDR1_2_ODS : string; - C_MEM_DDR2_RTT : string; - C_MEM_DDR2_DIFF_DQS_EN : string; - C_MEM_DDR2_3_PA_SR : string; - C_MEM_DDR2_3_HIGH_TEMP_SR : string; - C_MEM_DDR3_CAS_LATENCY : integer; - C_MEM_DDR3_ODS : string; - C_MEM_DDR3_RTT : string; - C_MEM_DDR3_CAS_WR_LATENCY : integer; - C_MEM_DDR3_AUTO_SR : string; - C_MEM_DDR3_DYN_WRT_ODT : string; - C_MEM_MOBILE_PA_SR : string; - C_MEM_MDDR_ODS : string; - C_MC_CALIB_BYPASS : string; - C_MC_CALIBRATION_MODE : string; - C_MC_CALIBRATION_DELAY : string; - C_SKIP_IN_TERM_CAL : integer; - C_SKIP_DYNAMIC_CAL : integer; - C_LDQSP_TAP_DELAY_VAL : integer; - C_LDQSN_TAP_DELAY_VAL : integer; - C_UDQSP_TAP_DELAY_VAL : integer; - C_UDQSN_TAP_DELAY_VAL : integer; - C_DQ0_TAP_DELAY_VAL : integer; - C_DQ1_TAP_DELAY_VAL : integer; - C_DQ2_TAP_DELAY_VAL : integer; - C_DQ3_TAP_DELAY_VAL : integer; - C_DQ4_TAP_DELAY_VAL : integer; - C_DQ5_TAP_DELAY_VAL : integer; - C_DQ6_TAP_DELAY_VAL : integer; - C_DQ7_TAP_DELAY_VAL : integer; - C_DQ8_TAP_DELAY_VAL : integer; - C_DQ9_TAP_DELAY_VAL : integer; - C_DQ10_TAP_DELAY_VAL : integer; - C_DQ11_TAP_DELAY_VAL : integer; - C_DQ12_TAP_DELAY_VAL : integer; - C_DQ13_TAP_DELAY_VAL : integer; - C_DQ14_TAP_DELAY_VAL : integer; - C_DQ15_TAP_DELAY_VAL : integer - ); - port ( - mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); - mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); - mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); - mcb3_dram_cke : out std_logic; - mcb3_dram_ras_n : out std_logic; - mcb3_dram_cas_n : out std_logic; - mcb3_dram_we_n : out std_logic; - mcb3_dram_dm : out std_logic; - mcb3_dram_udqs : inout std_logic; - mcb3_rzq : inout std_logic; - mcb3_dram_udm : out std_logic; - calib_done : out std_logic; - async_rst : in std_logic; - sysclk_2x : in std_logic; - sysclk_2x_180 : in std_logic; - pll_ce_0 : in std_logic; - pll_ce_90 : in std_logic; - pll_lock : in std_logic; - mcb_drp_clk : in std_logic; - mcb3_dram_dqs : inout std_logic; - mcb3_dram_ck : out std_logic; - mcb3_dram_ck_n : out std_logic; - p0_cmd_clk : in std_logic; - p0_cmd_en : in std_logic; - p0_cmd_instr : in std_logic_vector(2 downto 0); - p0_cmd_bl : in std_logic_vector(5 downto 0); - p0_cmd_byte_addr : in std_logic_vector(29 downto 0); - p0_cmd_empty : out std_logic; - p0_cmd_full : out std_logic; - p0_wr_clk : in std_logic; - p0_wr_en : in std_logic; - p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); - p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); - p0_wr_full : out std_logic; - p0_wr_empty : out std_logic; - p0_wr_count : out std_logic_vector(6 downto 0); - p0_wr_underrun : out std_logic; - p0_wr_error : out std_logic; - p0_rd_clk : in std_logic; - p0_rd_en : in std_logic; - p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); - p0_rd_full : out std_logic; - p0_rd_empty : out std_logic; - p0_rd_count : out std_logic_vector(6 downto 0); - p0_rd_overflow : out std_logic; - p0_rd_error : out std_logic; - p1_cmd_clk : in std_logic; - p1_cmd_en : in std_logic; - p1_cmd_instr : in std_logic_vector(2 downto 0); - p1_cmd_bl : in std_logic_vector(5 downto 0); - p1_cmd_byte_addr : in std_logic_vector(29 downto 0); - p1_cmd_empty : out std_logic; - p1_cmd_full : out std_logic; - p1_wr_clk : in std_logic; - p1_wr_en : in std_logic; - p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); - p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); - p1_wr_full : out std_logic; - p1_wr_empty : out std_logic; - p1_wr_count : out std_logic_vector(6 downto 0); - p1_wr_underrun : out std_logic; - p1_wr_error : out std_logic; - p1_rd_clk : in std_logic; - p1_rd_en : in std_logic; - p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); - p1_rd_full : out std_logic; - p1_rd_empty : out std_logic; - p1_rd_count : out std_logic_vector(6 downto 0); - p1_rd_overflow : out std_logic; - p1_rd_error : out std_logic; - p2_cmd_clk : in std_logic; - p2_cmd_en : in std_logic; - p2_cmd_instr : in std_logic_vector(2 downto 0); - p2_cmd_bl : in std_logic_vector(5 downto 0); - p2_cmd_byte_addr : in std_logic_vector(29 downto 0); - p2_cmd_empty : out std_logic; - p2_cmd_full : out std_logic; - p2_wr_clk : in std_logic; - p2_wr_en : in std_logic; - p2_wr_mask : in std_logic_vector(3 downto 0); - p2_wr_data : in std_logic_vector(31 downto 0); - p2_wr_full : out std_logic; - p2_wr_empty : out std_logic; - p2_wr_count : out std_logic_vector(6 downto 0); - p2_wr_underrun : out std_logic; - p2_wr_error : out std_logic; - p3_cmd_clk : in std_logic; - p3_cmd_en : in std_logic; - p3_cmd_instr : in std_logic_vector(2 downto 0); - p3_cmd_bl : in std_logic_vector(5 downto 0); - p3_cmd_byte_addr : in std_logic_vector(29 downto 0); - p3_cmd_empty : out std_logic; - p3_cmd_full : out std_logic; - p3_rd_clk : in std_logic; - p3_rd_en : in std_logic; - p3_rd_data : out std_logic_vector(31 downto 0); - p3_rd_full : out std_logic; - p3_rd_empty : out std_logic; - p3_rd_count : out std_logic_vector(6 downto 0); - p3_rd_overflow : out std_logic; - p3_rd_error : out std_logic; - p4_cmd_clk : in std_logic; - p4_cmd_en : in std_logic; - p4_cmd_instr : in std_logic_vector(2 downto 0); - p4_cmd_bl : in std_logic_vector(5 downto 0); - p4_cmd_byte_addr : in std_logic_vector(29 downto 0); - p4_cmd_empty : out std_logic; - p4_cmd_full : out std_logic; - p4_wr_clk : in std_logic; - p4_wr_en : in std_logic; - p4_wr_mask : in std_logic_vector(3 downto 0); - p4_wr_data : in std_logic_vector(31 downto 0); - p4_wr_full : out std_logic; - p4_wr_empty : out std_logic; - p4_wr_count : out std_logic_vector(6 downto 0); - p4_wr_underrun : out std_logic; - p4_wr_error : out std_logic; - p5_cmd_clk : in std_logic; - p5_cmd_en : in std_logic; - p5_cmd_instr : in std_logic_vector(2 downto 0); - p5_cmd_bl : in std_logic_vector(5 downto 0); - p5_cmd_byte_addr : in std_logic_vector(29 downto 0); - p5_cmd_empty : out std_logic; - p5_cmd_full : out std_logic; - p5_rd_clk : in std_logic; - p5_rd_en : in std_logic; - p5_rd_data : out std_logic_vector(31 downto 0); - p5_rd_full : out std_logic; - p5_rd_empty : out std_logic; - p5_rd_count : out std_logic_vector(6 downto 0); - p5_rd_overflow : out std_logic; - p5_rd_error : out std_logic; - selfrefresh_enter : in std_logic; - selfrefresh_mode : out std_logic - - ); - end component; - - - - - - - constant C3_CLKOUT0_DIVIDE : integer := 2; - constant C3_CLKOUT1_DIVIDE : integer := 2; - constant C3_CLKOUT2_DIVIDE : integer := 16; - constant C3_CLKOUT3_DIVIDE : integer := 8; - constant C3_CLKFBOUT_MULT : integer := 4; - constant C3_DIVCLK_DIVIDE : integer := 1; - constant C3_ARB_NUM_TIME_SLOTS : integer := 12; - constant C3_ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := o"012345"; - constant C3_ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := o"123450"; - constant C3_ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := o"234501"; - constant C3_ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := o"345012"; - constant C3_ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := o"450123"; - constant C3_ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := o"501234"; - constant C3_ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := o"012345"; - constant C3_ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := o"123450"; - constant C3_ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := o"234501"; - constant C3_ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := o"345012"; - constant C3_ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := o"450123"; - constant C3_ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := o"501234"; - constant C3_MEM_TRAS : integer := 40000; - constant C3_MEM_TRCD : integer := 15000; - constant C3_MEM_TREFI : integer := 7800000; - constant C3_MEM_TRFC : integer := 70000; - constant C3_MEM_TRP : integer := 15000; - constant C3_MEM_TWR : integer := 15000; - constant C3_MEM_TRTP : integer := 7500; - constant C3_MEM_TWTR : integer := 2; - constant C3_MEM_TYPE : string := "DDR"; - constant C3_MEM_DENSITY : string := "512Mb"; - constant C3_MEM_BURST_LEN : integer := 4; - constant C3_MEM_CAS_LATENCY : integer := 3; - constant C3_MEM_NUM_COL_BITS : integer := 10; - constant C3_MEM_DDR1_2_ODS : string := "FULL"; - constant C3_MEM_DDR2_RTT : string := "50OHMS"; - constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; - constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; - constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; - constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; - constant C3_MEM_DDR3_ODS : string := "DIV6"; - constant C3_MEM_DDR3_RTT : string := "DIV2"; - constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; - constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; - constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; - constant C3_MEM_MOBILE_PA_SR : string := "FULL"; - constant C3_MEM_MDDR_ODS : string := "FULL"; - constant C3_MC_CALIB_BYPASS : string := "NO"; - constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; - constant C3_MC_CALIBRATION_DELAY : string := "HALF"; - constant C3_SKIP_IN_TERM_CAL : integer := 1; - constant C3_SKIP_DYNAMIC_CAL : integer := 0; - constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; - constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; - constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; - constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; - constant C3_DQ0_TAP_DELAY_VAL : integer := 0; - constant C3_DQ1_TAP_DELAY_VAL : integer := 0; - constant C3_DQ2_TAP_DELAY_VAL : integer := 0; - constant C3_DQ3_TAP_DELAY_VAL : integer := 0; - constant C3_DQ4_TAP_DELAY_VAL : integer := 0; - constant C3_DQ5_TAP_DELAY_VAL : integer := 0; - constant C3_DQ6_TAP_DELAY_VAL : integer := 0; - constant C3_DQ7_TAP_DELAY_VAL : integer := 0; - constant C3_DQ8_TAP_DELAY_VAL : integer := 0; - constant C3_DQ9_TAP_DELAY_VAL : integer := 0; - constant C3_DQ10_TAP_DELAY_VAL : integer := 0; - constant C3_DQ11_TAP_DELAY_VAL : integer := 0; - constant C3_DQ12_TAP_DELAY_VAL : integer := 0; - constant C3_DQ13_TAP_DELAY_VAL : integer := 0; - constant C3_DQ14_TAP_DELAY_VAL : integer := 0; - constant C3_DQ15_TAP_DELAY_VAL : integer := 0; - - signal c3_sys_clk_p : std_logic; - signal c3_sys_clk_n : std_logic; - signal c3_async_rst : std_logic; - signal c3_sysclk_2x : std_logic; - signal c3_sysclk_2x_180 : std_logic; - signal c3_pll_ce_0 : std_logic; - signal c3_pll_ce_90 : std_logic; - signal c3_pll_lock : std_logic; - signal c3_mcb_drp_clk : std_logic; - signal c3_cmp_error : std_logic; - signal c3_cmp_data_valid : std_logic; - signal c3_vio_modify_enable : std_logic; - signal c3_error_status : std_logic_vector(127 downto 0); - signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); - signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); - signal c3_cmp_data : std_logic_vector(31 downto 0); - signal c3_selfrefresh_enter : std_logic; - signal c3_selfrefresh_mode : std_logic; - - - -begin - - -c3_sys_clk_p <= '0'; -c3_sys_clk_n <= '0'; - -memc3_infrastructure_inst : memc3_infrastructure - -generic map - ( - C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, - C_RST_ACT_LOW => C3_RST_ACT_LOW, - C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, - C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, - C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, - C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, - C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, - C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, - C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE - ) -port map - ( - sys_clk_p => c3_sys_clk_p, - sys_clk_n => c3_sys_clk_n, - sys_clk => c3_sys_clk, - sys_rst_n => c3_sys_rst_n, - clk0 => c3_clk0, - rst0 => c3_rst0, - async_rst => c3_async_rst, - sysclk_2x => c3_sysclk_2x, - sysclk_2x_180 => c3_sysclk_2x_180, - pll_ce_0 => c3_pll_ce_0, - pll_ce_90 => c3_pll_ce_90, - pll_lock => c3_pll_lock, - mcb_drp_clk => c3_mcb_drp_clk - ); - - --- wrapper instantiation - memc3_wrapper_inst : memc3_wrapper - -generic map - ( - C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, - C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, - C_SIMULATION => C3_SIMULATION, - C_P0_MASK_SIZE => C3_P0_MASK_SIZE, - C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, - C_P1_MASK_SIZE => C3_P1_MASK_SIZE, - C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, - C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, - C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, - C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, - C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, - C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, - C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, - C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, - C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, - C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, - C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, - C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, - C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, - C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, - C_MEM_TRAS => C3_MEM_TRAS, - C_MEM_TRCD => C3_MEM_TRCD, - C_MEM_TREFI => C3_MEM_TREFI, - C_MEM_TRFC => C3_MEM_TRFC, - C_MEM_TRP => C3_MEM_TRP, - C_MEM_TWR => C3_MEM_TWR, - C_MEM_TRTP => C3_MEM_TRTP, - C_MEM_TWTR => C3_MEM_TWTR, - C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, - C_NUM_DQ_PINS => C3_NUM_DQ_PINS, - C_MEM_TYPE => C3_MEM_TYPE, - C_MEM_DENSITY => C3_MEM_DENSITY, - C_MEM_BURST_LEN => C3_MEM_BURST_LEN, - C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, - C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, - C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, - C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, - C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, - C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, - C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, - C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, - C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, - C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, - C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, - C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, - C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, - C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, - C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT, - C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, - C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, - C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, - C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, - C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, - C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, - C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, - C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, - C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, - C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, - C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, - C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, - C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, - C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, - C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, - C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, - C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, - C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, - C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, - C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, - C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, - C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, - C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, - C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, - C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, - C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, - C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL - ) -port map -( - mcb3_dram_dq => mcb3_dram_dq, - mcb3_dram_a => mcb3_dram_a, - mcb3_dram_ba => mcb3_dram_ba, - mcb3_dram_cke => mcb3_dram_cke, - mcb3_dram_ras_n => mcb3_dram_ras_n, - mcb3_dram_cas_n => mcb3_dram_cas_n, - mcb3_dram_we_n => mcb3_dram_we_n, - mcb3_dram_dm => mcb3_dram_dm, - mcb3_dram_udqs => mcb3_dram_udqs, - mcb3_rzq => mcb3_rzq, - mcb3_dram_udm => mcb3_dram_udm, - calib_done => c3_calib_done, - async_rst => c3_async_rst, - sysclk_2x => c3_sysclk_2x, - sysclk_2x_180 => c3_sysclk_2x_180, - pll_ce_0 => c3_pll_ce_0, - pll_ce_90 => c3_pll_ce_90, - pll_lock => c3_pll_lock, - mcb_drp_clk => c3_mcb_drp_clk, - mcb3_dram_dqs => mcb3_dram_dqs, - mcb3_dram_ck => mcb3_dram_ck, - mcb3_dram_ck_n => mcb3_dram_ck_n, - p0_cmd_clk => c3_p0_cmd_clk, - p0_cmd_en => c3_p0_cmd_en, - p0_cmd_instr => c3_p0_cmd_instr, - p0_cmd_bl => c3_p0_cmd_bl, - p0_cmd_byte_addr => c3_p0_cmd_byte_addr, - p0_cmd_empty => c3_p0_cmd_empty, - p0_cmd_full => c3_p0_cmd_full, - p0_wr_clk => c3_p0_wr_clk, - p0_wr_en => c3_p0_wr_en, - p0_wr_mask => c3_p0_wr_mask, - p0_wr_data => c3_p0_wr_data, - p0_wr_full => c3_p0_wr_full, - p0_wr_empty => c3_p0_wr_empty, - p0_wr_count => c3_p0_wr_count, - p0_wr_underrun => c3_p0_wr_underrun, - p0_wr_error => c3_p0_wr_error, - p0_rd_clk => c3_p0_rd_clk, - p0_rd_en => c3_p0_rd_en, - p0_rd_data => c3_p0_rd_data, - p0_rd_full => c3_p0_rd_full, - p0_rd_empty => c3_p0_rd_empty, - p0_rd_count => c3_p0_rd_count, - p0_rd_overflow => c3_p0_rd_overflow, - p0_rd_error => c3_p0_rd_error, - p1_cmd_clk => c3_p1_cmd_clk, - p1_cmd_en => c3_p1_cmd_en, - p1_cmd_instr => c3_p1_cmd_instr, - p1_cmd_bl => c3_p1_cmd_bl, - p1_cmd_byte_addr => c3_p1_cmd_byte_addr, - p1_cmd_empty => c3_p1_cmd_empty, - p1_cmd_full => c3_p1_cmd_full, - p1_wr_clk => c3_p1_wr_clk, - p1_wr_en => c3_p1_wr_en, - p1_wr_mask => c3_p1_wr_mask, - p1_wr_data => c3_p1_wr_data, - p1_wr_full => c3_p1_wr_full, - p1_wr_empty => c3_p1_wr_empty, - p1_wr_count => c3_p1_wr_count, - p1_wr_underrun => c3_p1_wr_underrun, - p1_wr_error => c3_p1_wr_error, - p1_rd_clk => c3_p1_rd_clk, - p1_rd_en => c3_p1_rd_en, - p1_rd_data => c3_p1_rd_data, - p1_rd_full => c3_p1_rd_full, - p1_rd_empty => c3_p1_rd_empty, - p1_rd_count => c3_p1_rd_count, - p1_rd_overflow => c3_p1_rd_overflow, - p1_rd_error => c3_p1_rd_error, - p2_cmd_clk => c3_p2_cmd_clk, - p2_cmd_en => c3_p2_cmd_en, - p2_cmd_instr => c3_p2_cmd_instr, - p2_cmd_bl => c3_p2_cmd_bl, - p2_cmd_byte_addr => c3_p2_cmd_byte_addr, - p2_cmd_empty => c3_p2_cmd_empty, - p2_cmd_full => c3_p2_cmd_full, - p2_wr_clk => c3_p2_wr_clk, - p2_wr_en => c3_p2_wr_en, - p2_wr_mask => c3_p2_wr_mask, - p2_wr_data => c3_p2_wr_data, - p2_wr_full => c3_p2_wr_full, - p2_wr_empty => c3_p2_wr_empty, - p2_wr_count => c3_p2_wr_count, - p2_wr_underrun => c3_p2_wr_underrun, - p2_wr_error => c3_p2_wr_error, - p3_cmd_clk => c3_p3_cmd_clk, - p3_cmd_en => c3_p3_cmd_en, - p3_cmd_instr => c3_p3_cmd_instr, - p3_cmd_bl => c3_p3_cmd_bl, - p3_cmd_byte_addr => c3_p3_cmd_byte_addr, - p3_cmd_empty => c3_p3_cmd_empty, - p3_cmd_full => c3_p3_cmd_full, - p3_rd_clk => c3_p3_rd_clk, - p3_rd_en => c3_p3_rd_en, - p3_rd_data => c3_p3_rd_data, - p3_rd_full => c3_p3_rd_full, - p3_rd_empty => c3_p3_rd_empty, - p3_rd_count => c3_p3_rd_count, - p3_rd_overflow => c3_p3_rd_overflow, - p3_rd_error => c3_p3_rd_error, - p4_cmd_clk => c3_p4_cmd_clk, - p4_cmd_en => c3_p4_cmd_en, - p4_cmd_instr => c3_p4_cmd_instr, - p4_cmd_bl => c3_p4_cmd_bl, - p4_cmd_byte_addr => c3_p4_cmd_byte_addr, - p4_cmd_empty => c3_p4_cmd_empty, - p4_cmd_full => c3_p4_cmd_full, - p4_wr_clk => c3_p4_wr_clk, - p4_wr_en => c3_p4_wr_en, - p4_wr_mask => c3_p4_wr_mask, - p4_wr_data => c3_p4_wr_data, - p4_wr_full => c3_p4_wr_full, - p4_wr_empty => c3_p4_wr_empty, - p4_wr_count => c3_p4_wr_count, - p4_wr_underrun => c3_p4_wr_underrun, - p4_wr_error => c3_p4_wr_error, - p5_cmd_clk => c3_p5_cmd_clk, - p5_cmd_en => c3_p5_cmd_en, - p5_cmd_instr => c3_p5_cmd_instr, - p5_cmd_bl => c3_p5_cmd_bl, - p5_cmd_byte_addr => c3_p5_cmd_byte_addr, - p5_cmd_empty => c3_p5_cmd_empty, - p5_cmd_full => c3_p5_cmd_full, - p5_rd_clk => c3_p5_rd_clk, - p5_rd_en => c3_p5_rd_en, - p5_rd_data => c3_p5_rd_data, - p5_rd_full => c3_p5_rd_full, - p5_rd_empty => c3_p5_rd_empty, - p5_rd_count => c3_p5_rd_count, - p5_rd_overflow => c3_p5_rd_overflow, - p5_rd_error => c3_p5_rd_error, - selfrefresh_enter => c3_selfrefresh_enter, - selfrefresh_mode => c3_selfrefresh_mode -); - - - - - - end arc; Index: ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd (nonexistent) @@ -1,409 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version: %version --- \ \ Application: MIG --- / / Filename: mcb_soft_calibration_top.vhd --- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:38 $ --- \ \ / \ Date Created: Mon Feb 9 2009 --- \___\/\___\ --- ---Device: Spartan6 ---Design Name: DDR/DDR2/DDR3/LPDDR ---Purpose: Xilinx reference design top-level simulation --- wrapper file for input termination calibration ---Reference: --- --- Revision: Date: Comment --- 1.0: 2/06/09: Initial version for MIG wrapper. --- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset --- 1.2: 6/06/09: Removed MCB_UIDQCOUNT. --- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port --- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets --- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration --- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration --- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin. --- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait . --- End Revision ---********************************************************************************** - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; -library unisim; -use unisim.vcomponents.all; - -entity mcb_soft_calibration_top is - generic ( - C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets - C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, - -- and does dynamic recal, - -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* - -- no dynamic recal will be done - SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration - SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration - SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration - C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented - C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design - - ); - port ( - UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock - RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for - -- IODRP (sub)controller - IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's - DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high - -- (MCB hard calib complete) - PLL_LOCK : in std_logic; -- Lock signal from PLL - SELFREFRESH_REQ : in std_logic; - SELFREFRESH_MCB_MODE : in std_logic; - SELFREFRESH_MCB_REQ : out std_logic; - SELFREFRESH_MODE : out std_logic; - MCB_UIADD : out std_logic; -- to MCB's UIADD port - MCB_UISDI : out std_logic; -- to MCB's UISDI port - MCB_UOSDO : in std_logic; - MCB_UODONECAL : in std_logic; - MCB_UOREFRSHFLAG : in std_logic; - MCB_UICS : out std_logic; - MCB_UIDRPUPDATE : out std_logic; - MCB_UIBROADCAST : out std_logic; - MCB_UIADDR : out std_logic_vector(4 downto 0); - MCB_UICMDEN : out std_logic; - MCB_UIDONECAL : out std_logic; - MCB_UIDQLOWERDEC : out std_logic; - MCB_UIDQLOWERINC : out std_logic; - MCB_UIDQUPPERDEC : out std_logic; - MCB_UIDQUPPERINC : out std_logic; - MCB_UILDQSDEC : out std_logic; - MCB_UILDQSINC : out std_logic; - MCB_UIREAD : out std_logic; - MCB_UIUDQSDEC : out std_logic; - MCB_UIUDQSINC : out std_logic; - MCB_RECAL : out std_logic; - MCB_SYSRST : out std_logic; - - MCB_UICMD : out std_logic; - MCB_UICMDIN : out std_logic; - MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); - MCB_UODATA : in std_logic_vector(7 downto 0); - MCB_UODATAVALID : in std_logic; - MCB_UOCMDREADY : in std_logic; - MCB_UO_CAL_START : in std_logic; - RZQ_PIN : inout std_logic; - ZIO_PIN : inout std_logic; - CKE_Train : out std_logic - - ); -end entity mcb_soft_calibration_top; - -architecture trans of mcb_soft_calibration_top is - -component mcb_soft_calibration is - generic ( - C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets - SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration - SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration - SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration - C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value - -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY - -- (Quarter, etc) - - C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented - C_MEM_TYPE : string := "DDR" - ); - port ( - UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB - -- CLK pins - RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST - DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB - -- hard calib complete) - PLL_LOCK : in std_logic; -- Lock signal from PLL - SELFREFRESH_REQ : in std_logic; - SELFREFRESH_MCB_MODE : in std_logic; - SELFREFRESH_MCB_REQ : out std_logic; - SELFREFRESH_MODE : out std_logic; - IODRP_ADD : out std_logic; -- IODRP ADD port - IODRP_SDI : out std_logic; -- IODRP SDI port - RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground - RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port - RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port - ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally - ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port - ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port - MCB_UIADD : out std_logic; -- to MCB's UIADD port - MCB_UISDI : out std_logic; -- to MCB's UISDI port - MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) - MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete - MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive - MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) - MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used - -- during IODRP2_MCB writes). Currently just trasnparent - MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) - MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port - MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block - MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state - MCB_UIDQLOWERDEC : out std_logic := '0'; - MCB_UIDQLOWERINC : out std_logic := '0'; - MCB_UIDQUPPERDEC : out std_logic := '0'; - MCB_UIDQUPPERINC : out std_logic := '0'; - MCB_UILDQSDEC : out std_logic := '0'; - MCB_UILDQSINC : out std_logic := '0'; - MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in - -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. - MCB_UIUDQSDEC : out std_logic := '0'; - MCB_UIUDQSINC : out std_logic := '0'; - MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high - MCB_UICMD : out std_logic; - MCB_UICMDIN : out std_logic; - MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); - MCB_UODATA : in std_logic_vector(7 downto 0); - MCB_UODATAVALID : in std_logic; - MCB_UOCMDREADY : in std_logic; - MCB_UO_CAL_START : in std_logic; - MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB - Max_Value : out std_logic_vector(7 downto 0); - CKE_Train : out std_logic - - ); -end component; - - signal IODRP_ADD : std_logic; - signal IODRP_SDI : std_logic; - signal RZQ_IODRP_SDO : std_logic; - signal RZQ_IODRP_CS : std_logic; - signal ZIO_IODRP_SDO : std_logic; - signal ZIO_IODRP_CS : std_logic; - signal IODRP_SDO : std_logic; - signal IODRP_CS : std_logic; - signal IODRP_BKST : std_logic; - signal RZQ_ZIO_ODATAIN : std_logic; - signal RZQ_ZIO_TRISTATE : std_logic; - signal RZQ_TOUT : std_logic; - signal ZIO_TOUT : std_logic; - signal Max_Value : std_logic_vector(7 downto 0); - - signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground - signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally - signal RZQ_OUT : std_logic; - signal ZIO_OUT : std_logic; - - -- Declare intermediate signals for referenced outputs - signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic; - signal MCB_UIADD_xilinx3 : std_logic; - signal MCB_UISDI_xilinx17 : std_logic; - signal MCB_UICS_xilinx7 : std_logic; - signal MCB_UIDRPUPDATE_xilinx13 : std_logic; - signal MCB_UIBROADCAST_xilinx5 : std_logic; - signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0); - signal MCB_UICMDEN_xilinx6 : std_logic; - signal MCB_UIDONECAL_xilinx8 : std_logic; - signal MCB_UIDQLOWERDEC_xilinx9 : std_logic; - signal MCB_UIDQLOWERINC_xilinx10 : std_logic; - signal MCB_UIDQUPPERDEC_xilinx11 : std_logic; - signal MCB_UIDQUPPERINC_xilinx12 : std_logic; - signal MCB_UILDQSDEC_xilinx14 : std_logic; - signal MCB_UILDQSINC_xilinx15 : std_logic; - signal MCB_UIREAD_xilinx16 : std_logic; - signal MCB_UIUDQSDEC_xilinx18 : std_logic; - signal MCB_UIUDQSINC_xilinx19 : std_logic; - signal MCB_RECAL_xilinx1 : std_logic; - signal MCB_SYSRST_xilinx2 : std_logic; -begin - -- Drive referenced outputs - DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0; - MCB_UIADD <= MCB_UIADD_xilinx3; - MCB_UISDI <= MCB_UISDI_xilinx17; - MCB_UICS <= MCB_UICS_xilinx7; - MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13; - MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5; - MCB_UIADDR <= MCB_UIADDR_xilinx4; - MCB_UICMDEN <= MCB_UICMDEN_xilinx6; - MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8; - MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9; - MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10; - MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11; - MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12; - MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14; - MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15; - MCB_UIREAD <= MCB_UIREAD_xilinx16; - MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18; - MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19; - MCB_RECAL <= MCB_RECAL_xilinx1; - MCB_SYSRST <= MCB_SYSRST_xilinx2; - - RZQ_ZIO_ODATAIN <= not(RST); - RZQ_ZIO_TRISTATE <= not(RST); - IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ - - - mcb_soft_calibration_inst : mcb_soft_calibration - generic map ( - C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT, - C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, - SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL, - SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL, - SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM, - C_SIMULATION => C_SIMULATION, - C_MEM_TYPE => C_MEM_TYPE - - ) - port map ( - UI_CLK => UI_CLK, - RST => RST, - PLL_LOCK => PLL_LOCK, - SELFREFRESH_REQ => SELFREFRESH_REQ, - SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE, - SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ, - SELFREFRESH_MODE => SELFREFRESH_MODE, - DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0, - IODRP_ADD => IODRP_ADD, - IODRP_SDI => IODRP_SDI, - RZQ_IN => RZQ_IN, - RZQ_IODRP_SDO => RZQ_IODRP_SDO, - RZQ_IODRP_CS => RZQ_IODRP_CS, - ZIO_IN => ZIO_IN, - ZIO_IODRP_SDO => ZIO_IODRP_SDO, - ZIO_IODRP_CS => ZIO_IODRP_CS, - MCB_UIADD => MCB_UIADD_xilinx3, - MCB_UISDI => MCB_UISDI_xilinx17, - MCB_UOSDO => MCB_UOSDO, - MCB_UODONECAL => MCB_UODONECAL, - MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG, - MCB_UICS => MCB_UICS_xilinx7, - MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13, - MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5, - MCB_UIADDR => MCB_UIADDR_xilinx4, - MCB_UICMDEN => MCB_UICMDEN_xilinx6, - MCB_UIDONECAL => MCB_UIDONECAL_xilinx8, - MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9, - MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10, - MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11, - MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12, - MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14, - MCB_UILDQSINC => MCB_UILDQSINC_xilinx15, - MCB_UIREAD => MCB_UIREAD_xilinx16, - MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18, - MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19, - MCB_RECAL => MCB_RECAL_xilinx1, - MCB_UICMD => MCB_UICMD, - MCB_UICMDIN => MCB_UICMDIN, - MCB_UIDQCOUNT => MCB_UIDQCOUNT, - MCB_UODATA => MCB_UODATA, - MCB_UODATAVALID => MCB_UODATAVALID, - MCB_UOCMDREADY => MCB_UOCMDREADY, - MCB_UO_CAL_START => MCB_UO_CAL_START, - mcb_sysrst => MCB_SYSRST_xilinx2, - Max_Value => Max_Value, - CKE_Train => CKE_Train - ); - - IOBUF_RZQ : IOBUF - port map ( - o => RZQ_IN, - io => RZQ_PIN, - i => RZQ_OUT, - t => RZQ_TOUT - ); - - IODRP2_RZQ : IODRP2 - port map ( - dataout => open, - dataout2 => open, - dout => RZQ_OUT, - sdo => RZQ_IODRP_SDO, - tout => RZQ_TOUT, - add => IODRP_ADD, - bkst => IODRP_BKST, - clk => UI_CLK, - cs => RZQ_IODRP_CS, - idatain => RZQ_IN, - ioclk0 => IOCLK, - ioclk1 => '1', - odatain => RZQ_ZIO_ODATAIN, - sdi => IODRP_SDI, - t => RZQ_ZIO_TRISTATE - ); - - - gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and - (SKIP_IN_TERM_CAL = 0)) generate - - IOBUF_ZIO : IOBUF - port map ( - o => ZIO_IN, - io => ZIO_PIN, - i => ZIO_OUT, - t => ZIO_TOUT - ); - - IODRP2_ZIO : IODRP2 - port map ( - dataout => open, - dataout2 => open, - dout => ZIO_OUT, - sdo => ZIO_IODRP_SDO, - tout => ZIO_TOUT, - add => IODRP_ADD, - bkst => IODRP_BKST, - clk => UI_CLK, - cs => ZIO_IODRP_CS, - idatain => ZIO_IN, - ioclk0 => IOCLK, - ioclk1 => '1', - odatain => RZQ_ZIO_ODATAIN, - sdi => IODRP_SDI, - t => RZQ_ZIO_TRISTATE - ); - end generate; - -end architecture trans; - -

ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd (nonexistent) @@ -1,310 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.5 --- \ \ Application : MIG --- / / Filename : memc3_infrastructure.vhd --- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $ --- \ \ / \ Date Created : Jul 03 2009 --- \___\/\___\ --- ---Device : Spartan-6 ---Design Name : DDR/DDR2/DDR3/LPDDR ---Purpose : Clock generation/distribution and reset synchronization ---Reference : ---Revision History : ---***************************************************************************** -library ieee; -use ieee.std_logic_1164.all; -library unisim; -use unisim.vcomponents.all; - -entity memc3_infrastructure is -generic - ( - C_MEMCLK_PERIOD : integer := 2500; - C_RST_ACT_LOW : integer := 1; - C_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; - C_CLKOUT0_DIVIDE : integer := 2; - C_CLKOUT1_DIVIDE : integer := 2; - C_CLKOUT2_DIVIDE : integer := 16; - C_CLKOUT3_DIVIDE : integer := 8; - C_CLKFBOUT_MULT : integer := 4; - C_DIVCLK_DIVIDE : integer := 1 - - ); -port -( - sys_clk_p : in std_logic; - sys_clk_n : in std_logic; - sys_clk : in std_logic; - sys_rst_n : in std_logic; - clk0 : out std_logic; - rst0 : out std_logic; - async_rst : out std_logic; - sysclk_2x : out std_logic; - sysclk_2x_180 : out std_logic; - mcb_drp_clk : out std_logic; - pll_ce_0 : out std_logic; - pll_ce_90 : out std_logic; - pll_lock : out std_logic - -); -end entity; -architecture syn of memc3_infrastructure is - - -- # of clock cycles to delay deassertion of reset. Needs to be a fairly - -- high number not so much for metastability protection, but to give time - -- for reset (i.e. stable clock cycles) to propagate through all state - -- machines and to all control signals (i.e. not all control signals have - -- resets, instead they rely on base state logic being reset, and the effect - -- of that reset propagating through the logic). Need this because we may not - -- be getting stable clock cycles while reset asserted (i.e. since reset - -- depends on PLL/DCM lock status) - - constant RST_SYNC_NUM : integer := 25; - constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0; - constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000; - - - signal clk_2x_0 : std_logic; - signal clk_2x_180 : std_logic; - signal clk0_bufg : std_logic; - signal clk0_bufg_in : std_logic; - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; - signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; - signal locked : std_logic; - signal bufpll_mcb_locked : std_logic; - signal mcb_drp_clk_sig : std_logic; - - attribute max_fanout : string; - attribute syn_maxfan : integer; - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; - attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - -begin - - sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n; - clk0 <= clk0_bufg; - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - - diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate - --*********************************************************************** - -- Differential input clock input buffers - --*********************************************************************** - u_ibufg_sys_clk : IBUFGDS - generic map ( - DIFF_TERM => TRUE - ) - port map ( - I => sys_clk_p, - IB => sys_clk_n, - O => sys_clk_ibufg - ); - end generate; - - - se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate - --*********************************************************************** - -- SINGLE_ENDED input clock input buffers - --*********************************************************************** - u_ibufg_sys_clk : IBUFG - port map ( - I => sys_clk, - O => sys_clk_ibufg - ); - end generate; - - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** - - u_pll_adv : PLL_ADV - generic map - ( - BANDWIDTH => "OPTIMIZED", - CLKIN1_PERIOD => CLK_PERIOD_NS, - CLKIN2_PERIOD => CLK_PERIOD_NS, - CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE, - CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE, - CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE, - CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE, - CLKOUT4_DIVIDE => 1, - CLKOUT5_DIVIDE => 1, - CLKOUT0_PHASE => 0.000, - CLKOUT1_PHASE => 180.000, - CLKOUT2_PHASE => 0.000, - CLKOUT3_PHASE => 0.000, - CLKOUT4_PHASE => 0.000, - CLKOUT5_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT2_DUTY_CYCLE => 0.500, - CLKOUT3_DUTY_CYCLE => 0.500, - CLKOUT4_DUTY_CYCLE => 0.500, - CLKOUT5_DUTY_CYCLE => 0.500, - COMPENSATION => "INTERNAL", - DIVCLK_DIVIDE => C_DIVCLK_DIVIDE, - CLKFBOUT_MULT => C_CLKFBOUT_MULT, - CLKFBOUT_PHASE => 0.0, - REF_JITTER => 0.005000 - ) - port map - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', - CLKIN1 => sys_clk_ibufg, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DWE => '0', - REL => '0', - RST => sys_rst, - CLKFBDCM => open, - CLKFBOUT => clkfbout_clkfbin, - CLKOUTDCM0 => open, - CLKOUTDCM1 => open, - CLKOUTDCM2 => open, - CLKOUTDCM3 => open, - CLKOUTDCM4 => open, - CLKOUTDCM5 => open, - CLKOUT0 => clk_2x_0, - CLKOUT1 => clk_2x_180, - CLKOUT2 => clk0_bufg_in, - CLKOUT3 => mcb_drp_clk_bufg_in, - CLKOUT4 => open, - CLKOUT5 => open, - DO => open, - DRDY => open, - LOCKED => locked - ); - - U_BUFG_CLK0 : BUFG - port map - ( - O => clk0_bufg, - I => clk0_bufg_in - ); - - U_BUFG_CLK1 : BUFG - port map ( - O => mcb_drp_clk_sig, - I => mcb_drp_clk_bufg_in - ); - - process (clk0_bufg, sys_rst) - begin - if (clk0_bufg'event and clk0_bufg = '1') then - if(sys_rst = '1') then - powerup_pll_locked <= '0'; - elsif (bufpll_mcb_locked = '1') then - powerup_pll_locked <= '1'; - end if; - end if; - end process; - - --*************************************************************************** - -- Reset synchronization - -- NOTES: - -- 1. shut down the whole operation if the PLL hasn't yet locked (and - -- by inference, this means that external sys_rst has been asserted - - -- PLL deasserts LOCKED as soon as sys_rst asserted) - -- 2. asynchronously assert reset. This was we can assert reset even if - -- there is no clock (needed for things like 3-stating output buffers). - -- reset deassertion is synchronous. - -- 3. asynchronous reset only look at pll_lock from PLL during power up. After - -- power up and pll_lock is asserted, the powerup_pll_locked will be asserted - -- forever until sys_rst is asserted again. PLL will lose lock when FPGA - -- enters suspend mode. We don't want reset to MCB get - -- asserted in the application that needs suspend feature. - --*************************************************************************** - - rst_tmp <= sys_rst or not(powerup_pll_locked); - - async_rst <= rst_tmp; - -process (clk0_bufg, rst_tmp) - begin - if (rst_tmp = '1') then - rst0_sync_r <= (others => '1'); - elsif (rising_edge(clk0_bufg)) then - rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0) - end if; - end process; - - rst0 <= rst0_sync_r(RST_SYNC_NUM-1); - - -BUFPLL_MCB_INST : BUFPLL_MCB -port map -( IOCLK0 => sysclk_2x, - IOCLK1 => sysclk_2x_180, - LOCKED => locked, - GCLK => mcb_drp_clk_sig, - SERDESSTROBE0 => pll_ce_0, - SERDESSTROBE1 => pll_ce_90, - PLLIN0 => clk_2x_0, - PLLIN1 => clk_2x_180, - LOCK => bufpll_mcb_locked - ); - -end architecture syn; - Index: ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd (nonexistent) @@ -1,502 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version: %version --- \ \ Application: MIG --- / / Filename: iodrp_mcb_controller.vhd --- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $ --- \ \ / \ Date Created: Mon Feb 9 2009 --- \___\/\___\ --- ---Device: Spartan6 ---Design Name: DDR/DDR2/DDR3/LPDDR ---Purpose: Xilinx reference design for IODRP controller for v0.9 device --- ---Reference: --- --- Revision: Date: Comment --- 1.0: 03/19/09: Initial version for IODRP_MCB read operations. --- 1.1: 04/03/09: SLH - Added left shift for certain IOI's --- End Revision ---******************************************************************************* - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - -entity iodrp_mcb_controller is - --output to IODRP SDI pin - --input from IODRP SDO pin - - -- Register where memcell_address is captured during the READY state - -- Register which stores the write data until it is ready to be shifted out - -- The shift register which shifts out SDO and shifts in SDI. - -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data - -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO - -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg - -- The counter for which bit is being shifted during address or data phase - -- This is set after the first address phase has executed - - -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg - --added so that DRP_SDI output is only active when DRP_CS is active - port ( - memcell_address : in std_logic_vector(7 downto 0); - write_data : in std_logic_vector(7 downto 0); - read_data : out std_logic_vector(7 downto 0); - rd_not_write : in std_logic; - cmd_valid : in std_logic; - rdy_busy_n : out std_logic; - use_broadcast : in std_logic; - drp_ioi_addr : in std_logic_vector(4 downto 0); - sync_rst : in std_logic; - DRP_CLK : in std_logic; - DRP_CS : out std_logic; - DRP_SDI : out std_logic; - DRP_ADD : out std_logic; - DRP_BKST : out std_logic; - DRP_SDO : in std_logic; - MCB_UIREAD : out std_logic - ); -end entity iodrp_mcb_controller; - -architecture trans of iodrp_mcb_controller is - - constant READY : std_logic_vector(3 downto 0) := "0000"; - constant DECIDE : std_logic_vector(3 downto 0) := "0001"; - constant ADDR_PHASE : std_logic_vector(3 downto 0) := "0010"; - constant ADDR_TO_DATA_GAP : std_logic_vector(3 downto 0) := "0011"; - constant ADDR_TO_DATA_GAP2 : std_logic_vector(3 downto 0) := "0100"; - constant ADDR_TO_DATA_GAP3 : std_logic_vector(3 downto 0) := "0101"; - constant DATA_PHASE : std_logic_vector(3 downto 0) := "0110"; - constant ALMOST_READY : std_logic_vector(3 downto 0) := "0111"; - constant ALMOST_READY2 : std_logic_vector(3 downto 0) := "1001"; - constant ALMOST_READY3 : std_logic_vector(3 downto 0) := "1010"; - - constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001"; - constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000"; - constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011"; - constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010"; - constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101"; - constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100"; - constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111"; - constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110"; - constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001"; - constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000"; - constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011"; - constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010"; - constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101"; - constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100"; - constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111"; - constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110"; - constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101"; - constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100"; - constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111"; - constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110"; - - - signal memcell_addr_reg : std_logic_vector(7 downto 0); - signal data_reg : std_logic_vector(7 downto 0); - signal shift_through_reg : std_logic_vector(8 downto 0); - signal load_shift_n : std_logic; - signal addr_data_sel_n : std_logic; - signal bit_cnt : std_logic_vector(2 downto 0); - signal rd_not_write_reg : std_logic; - signal AddressPhase : std_logic; - signal DRP_CS_pre : std_logic; - signal extra_cs : std_logic; - signal state : std_logic_vector(3 downto 0); - signal nextstate : std_logic_vector(3 downto 0); - signal data_out : std_logic_vector(8 downto 0); - signal data_out_mux : std_logic_vector(8 downto 0); - signal DRP_SDI_pre : std_logic; - - --synthesis translate_off - signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0); - -- case(state) - --synthesis translate_on - - -- The changes below are to compensate for an issue with 1.0 silicon. - -- It may still be necessary to add a clock cycle to the ADD and CS signals - - --`define DRP_v1_0_FIX // Uncomment out this line for synthesis - - procedure shift_n_expand( - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(8 downto 0)) is - - variable data_out_xilinx2 : std_logic_vector(8 downto 0); - begin - if ((data_in(0)) = '1') then - data_out_xilinx2(1 downto 0) := "11"; - else - - data_out_xilinx2(1 downto 0) := "00"; - end if; - if (data_in(1 downto 0) = "10") then - data_out_xilinx2(2 downto 1) := "11"; - else - - data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1)); - end if; - if (data_in(2 downto 1) = "10") then - data_out_xilinx2(3 downto 2) := "11"; - else - - data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2)); - end if; - if (data_in(3 downto 2) = "10") then - data_out_xilinx2(4 downto 3) := "11"; - else - - data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3)); - end if; - if (data_in(4 downto 3) = "10") then - data_out_xilinx2(5 downto 4) := "11"; - else - - data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4)); - end if; - if (data_in(5 downto 4) = "10") then - data_out_xilinx2(6 downto 5) := "11"; - else - - data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5)); - end if; - if (data_in(6 downto 5) = "10") then - data_out_xilinx2(7 downto 6) := "11"; - else - - data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6)); - end if; - if (data_in(7 downto 6) = "10") then - data_out_xilinx2(8 downto 7) := "11"; - else - data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7)); - end if; - end shift_n_expand; - - - -- Declare intermediate signals for referenced outputs - signal DRP_CS_xilinx1 : std_logic; - signal DRP_ADD_xilinx0 : std_logic; - - signal ALMOST_READY2_ST : std_logic; - signal ADDR_PHASE_ST : std_logic; - signal BIT_CNT7 : std_logic; - signal ADDR_PHASE_ST1 : std_logic; - signal DATA_PHASE_ST : std_logic; - -begin - -- Drive referenced outputs - DRP_CS <= DRP_CS_xilinx1; - DRP_ADD <= DRP_ADD_xilinx0; - - --- process (state) --- begin --- case state is --- when READY => --- state_ascii <= "READY"; --- when DECIDE => --- state_ascii <= "DECIDE"; --- when ADDR_PHASE => --- state_ascii <= "ADDR_PHASE"; --- when ADDR_TO_DATA_GAP => --- state_ascii <= "ADDR_TO_DATA_GAP"; --- when ADDR_TO_DATA_GAP2 => --- state_ascii <= "ADDR_TO_DATA_GAP2"; --- when ADDR_TO_DATA_GAP3 => --- state_ascii <= "ADDR_TO_DATA_GAP3"; --- when DATA_PHASE => --- state_ascii <= "DATA_PHASE"; --- when ALMOST_READY => --- state_ascii <= "ALMOST_READY"; --- when ALMOST_READY2 => --- state_ascii <= "ALMOST_READY2"; --- when ALMOST_READY3 => --- state_ascii <= "ALMOST_READY3"; --- when others => --- null; --- end case; --- end process; - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (state = READY) then - memcell_addr_reg <= memcell_address; - data_reg <= write_data; - rd_not_write_reg <= rd_not_write; - end if; - end if; - end process; - - rdy_busy_n <= '1' when state = READY else '0'; - - process (drp_ioi_addr, data_out) - begin - - case drp_ioi_addr is - when IOI_DQ0 => - data_out_mux <= data_out; - when IOI_DQ1 => - data_out_mux <= data_out; - when IOI_DQ2 => - data_out_mux <= data_out; - when IOI_DQ3 => - data_out_mux <= data_out; - when IOI_DQ4 => - data_out_mux <= data_out; - when IOI_DQ5 => - data_out_mux <= data_out; - when IOI_DQ6 => - data_out_mux <= data_out; - when IOI_DQ7 => - data_out_mux <= data_out; - when IOI_DQ8 => - data_out_mux <= data_out; - when IOI_DQ9 => - data_out_mux <= data_out; - when IOI_DQ10 => - data_out_mux <= data_out; - when IOI_DQ11 => - data_out_mux <= data_out; - when IOI_DQ12 => - data_out_mux <= data_out; - when IOI_DQ13 => - data_out_mux <= data_out; - when IOI_DQ14 => - data_out_mux <= data_out; - when IOI_DQ15 => - data_out_mux <= data_out; - when IOI_UDQS_CLK => - data_out_mux <= data_out; - when IOI_UDQS_PIN => - data_out_mux <= data_out; - when IOI_LDQS_CLK => - data_out_mux <= data_out; - when IOI_LDQS_PIN => - data_out_mux <= data_out; - when others => - data_out_mux <= data_out; - end case; - end process; - - - data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else - ('0' & data_reg); - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - shift_through_reg <= "000000000"; - else - if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first - shift_through_reg <= data_out_mux; - else - shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1)); - end if; - end if; - end if; - end process; - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then - bit_cnt <= bit_cnt + "001"; - else - bit_cnt <= "000"; - end if; - end if; - end process; - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - read_data <= "00000000"; - else - if (state = ALMOST_READY3) then - read_data <= shift_through_reg(7 downto 0); - end if; - end if; - end if; - end process; - - ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0'; - ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0'; - BIT_CNT7 <= '1' when bit_cnt = "111" else '0'; - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - AddressPhase <= '0'; - else - if (AddressPhase = '1') then - -- Keep it set until we finish the cycle - AddressPhase <= AddressPhase and (not ALMOST_READY2_ST); - else - -- set the address phase when ever we finish the address phase - AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7); - end if; - end if; - end if; - end process; - -ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0'; -DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0'; - - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - DRP_ADD_xilinx0 <= ADDR_PHASE_ST1; - -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); - DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST; - MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg; - if (state = READY) then - DRP_BKST <= use_broadcast; - end if; - end if; - end process; - - - DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance - '0'; - DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance - DRP_SDI_pre; - - process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase) - begin - addr_data_sel_n <= '0'; - load_shift_n <= '0'; - case state is - when READY => - load_shift_n <= '0'; - if (cmd_valid = '1') then - nextstate <= DECIDE; - else - nextstate <= READY; - end if; - when DECIDE => - load_shift_n <= '1'; - addr_data_sel_n <= '1'; - nextstate <= ADDR_PHASE; - -- After the second pass go to end of statemachine - -- execute a second address phase for the alternative access method. - when ADDR_PHASE => - load_shift_n <= '0'; - if (BIT_CNT7 = '1') then - if (('1' and rd_not_write_reg) = '1') then - if (AddressPhase = '1') then - nextstate <= ALMOST_READY; - else - nextstate <= DECIDE; - end if; - else - nextstate <= ADDR_TO_DATA_GAP; - end if; - else - nextstate <= ADDR_PHASE; - end if; - when ADDR_TO_DATA_GAP => - load_shift_n <= '1'; - nextstate <= ADDR_TO_DATA_GAP2; - when ADDR_TO_DATA_GAP2 => - load_shift_n <= '1'; - nextstate <= ADDR_TO_DATA_GAP3; - when ADDR_TO_DATA_GAP3 => - load_shift_n <= '1'; - nextstate <= DATA_PHASE; - when DATA_PHASE => - load_shift_n <= '0'; - if (BIT_CNT7 = '1') then - nextstate <= ALMOST_READY; - else - nextstate <= DATA_PHASE; - end if; - when ALMOST_READY => - load_shift_n <= '0'; - nextstate <= ALMOST_READY2; - when ALMOST_READY2 => - load_shift_n <= '0'; - nextstate <= ALMOST_READY3; - when ALMOST_READY3 => - load_shift_n <= '0'; - nextstate <= READY; - when others => - load_shift_n <= '0'; - nextstate <= READY; - end case; - end process; - - - process (DRP_CLK) - begin - if (DRP_CLK'event and DRP_CLK = '1') then - if (sync_rst = '1') then - state <= READY; - else - state <= nextstate; - end if; - end if; - end process; - - -end architecture trans; - -

ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.bak.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.bak.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.bak.vhd (nonexistent) @@ -1,281 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.5 --- \ \ Application : MIG --- / / Filename : memc3_infrastructure.vhd --- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $ --- \ \ / \ Date Created : Jul 03 2009 --- \___\/\___\ --- ---Device : Spartan-6 ---Design Name : DDR/DDR2/DDR3/LPDDR ---Purpose : Clock generation/distribution and reset synchronization ---Reference : ---Revision History : ---***************************************************************************** -library ieee; -use ieee.std_logic_1164.all; -library unisim; -use unisim.vcomponents.all; - -entity memc3_infrastructure is -generic - ( - C_MEMCLK_PERIOD : integer := 2500; - C_RST_ACT_LOW : integer := 1; - C_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; - C_CLKOUT0_DIVIDE : integer := 2; - C_CLKOUT1_DIVIDE : integer := 2; - C_CLKOUT2_DIVIDE : integer := 16; - C_CLKOUT3_DIVIDE : integer := 8; - C_CLKFBOUT_MULT : integer := 4; - C_DIVCLK_DIVIDE : integer := 1 - - ); -port -( - sys_clk_p : in std_logic; - sys_clk_n : in std_logic; - sys_clk : in std_logic; - sys_rst_n : in std_logic; - clk0 : out std_logic; - rst0 : out std_logic; - async_rst : out std_logic; - sysclk_2x : out std_logic; - sysclk_2x_180 : out std_logic; - mcb_drp_clk : out std_logic; - pll_ce_0 : out std_logic; - pll_ce_90 : out std_logic; - pll_lock : out std_logic - -); -end entity; -architecture syn of memc3_infrastructure is - - -- # of clock cycles to delay deassertion of reset. Needs to be a fairly - -- high number not so much for metastability protection, but to give time - -- for reset (i.e. stable clock cycles) to propagate through all state - -- machines and to all control signals (i.e. not all control signals have - -- resets, instead they rely on base state logic being reset, and the effect - -- of that reset propagating through the logic). Need this because we may not - -- be getting stable clock cycles while reset asserted (i.e. since reset - -- depends on PLL/DCM lock status) - - constant RST_SYNC_NUM : integer := 25; - constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0; - constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000; - - - signal clk_2x_0 : std_logic; - signal clk_2x_180 : std_logic; - signal clk0_bufg : std_logic; - signal clk0_bufg_in : std_logic; - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; - signal locked : std_logic; - signal bufpll_mcb_locked : std_logic; - signal mcb_drp_clk_sig : std_logic; - - attribute max_fanout : string; - attribute syn_maxfan : integer; - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; - -begin - - sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n; - clk0 <= clk0_bufg; - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** - - u_pll_adv : PLL_ADV - generic map - ( - BANDWIDTH => "OPTIMIZED", - CLKIN1_PERIOD => CLK_PERIOD_NS, - CLKIN2_PERIOD => CLK_PERIOD_NS, - CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE, - CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE, - CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE, - CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE, - CLKOUT4_DIVIDE => 1, - CLKOUT5_DIVIDE => 1, - CLKOUT0_PHASE => 0.000, - CLKOUT1_PHASE => 180.000, - CLKOUT2_PHASE => 0.000, - CLKOUT3_PHASE => 0.000, - CLKOUT4_PHASE => 0.000, - CLKOUT5_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT2_DUTY_CYCLE => 0.500, - CLKOUT3_DUTY_CYCLE => 0.500, - CLKOUT4_DUTY_CYCLE => 0.500, - CLKOUT5_DUTY_CYCLE => 0.500, - COMPENSATION => "INTERNAL", - DIVCLK_DIVIDE => C_DIVCLK_DIVIDE, - CLKFBOUT_MULT => C_CLKFBOUT_MULT, - CLKFBOUT_PHASE => 0.0, - REF_JITTER => 0.005000 - ) - port map - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', - CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DWE => '0', - REL => '0', - RST => sys_rst, - CLKFBDCM => open, - CLKFBOUT => clkfbout_clkfbin, - CLKOUTDCM0 => open, - CLKOUTDCM1 => open, - CLKOUTDCM2 => open, - CLKOUTDCM3 => open, - CLKOUTDCM4 => open, - CLKOUTDCM5 => open, - CLKOUT0 => clk_2x_0, - CLKOUT1 => clk_2x_180, - CLKOUT2 => clk0_bufg_in, - CLKOUT3 => mcb_drp_clk_bufg_in, - CLKOUT4 => open, - CLKOUT5 => open, - DO => open, - DRDY => open, - LOCKED => locked - ); - - U_BUFG_CLK0 : BUFG - port map - ( - O => clk0_bufg, - I => clk0_bufg_in - ); - - U_BUFG_CLK1 : BUFG - port map ( - O => mcb_drp_clk_sig, - I => mcb_drp_clk_bufg_in - ); - - process (clk0_bufg, sys_rst) - begin - if (clk0_bufg'event and clk0_bufg = '1') then - if(sys_rst = '1') then - powerup_pll_locked <= '0'; - elsif (bufpll_mcb_locked = '1') then - powerup_pll_locked <= '1'; - end if; - end if; - end process; - - --*************************************************************************** - -- Reset synchronization - -- NOTES: - -- 1. shut down the whole operation if the PLL hasn't yet locked (and - -- by inference, this means that external sys_rst has been asserted - - -- PLL deasserts LOCKED as soon as sys_rst asserted) - -- 2. asynchronously assert reset. This was we can assert reset even if - -- there is no clock (needed for things like 3-stating output buffers). - -- reset deassertion is synchronous. - -- 3. asynchronous reset only look at pll_lock from PLL during power up. After - -- power up and pll_lock is asserted, the powerup_pll_locked will be asserted - -- forever until sys_rst is asserted again. PLL will lose lock when FPGA - -- enters suspend mode. We don't want reset to MCB get - -- asserted in the application that needs suspend feature. - --*************************************************************************** - - rst_tmp <= sys_rst or not(powerup_pll_locked); - - async_rst <= rst_tmp; - -process (clk0_bufg, rst_tmp) - begin - if (rst_tmp = '1') then - rst0_sync_r <= (others => '1'); - elsif (rising_edge(clk0_bufg)) then - rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0) - end if; - end process; - - rst0 <= rst0_sync_r(RST_SYNC_NUM-1); - - -BUFPLL_MCB_INST : BUFPLL_MCB -port map -( IOCLK0 => sysclk_2x, - IOCLK1 => sysclk_2x_180, - LOCKED => locked, - GCLK => mcb_drp_clk_sig, - SERDESSTROBE0 => pll_ce_0, - SERDESSTROBE1 => pll_ce_90, - PLLIN0 => clk_2x_0, - PLLIN1 => clk_2x_180, - LOCK => bufpll_mcb_locked - ); - -end architecture syn; - Index: ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd (nonexistent) @@ -1,1022 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.5 --- \ \ Application : MIG --- / / Filename : memc3_wrapper.vhd --- /___/ /\ Date Last Modified : $Date: 2010/06/04 11:24:37 $ --- \ \ / \ Date Created : Jul 03 2009 --- \___\/\___\ --- ---Device : Spartan-6 ---Design Name : DDR/DDR2/DDR3/LPDDR ---Purpose : This module instantiates mcb_raw_wrapper module. ---Reference : ---Revision History : ---***************************************************************************** -library ieee; -use ieee.std_logic_1164.all; - -entity memc3_wrapper is -generic ( - - C_MEMCLK_PERIOD : integer := 2500; - C_P0_MASK_SIZE : integer := 4; - C_P0_DATA_PORT_SIZE : integer := 32; - C_P1_MASK_SIZE : integer := 4; - C_P1_DATA_PORT_SIZE : integer := 32; - - C_ARB_NUM_TIME_SLOTS : integer := 12; - C_ARB_TIME_SLOT_0 : bit_vector := "000"; - C_ARB_TIME_SLOT_1 : bit_vector := "000"; - C_ARB_TIME_SLOT_2 : bit_vector := "000"; - C_ARB_TIME_SLOT_3 : bit_vector := "000"; - C_ARB_TIME_SLOT_4 : bit_vector := "000"; - C_ARB_TIME_SLOT_5 : bit_vector := "000"; - C_ARB_TIME_SLOT_6 : bit_vector := "000"; - C_ARB_TIME_SLOT_7 : bit_vector := "000"; - C_ARB_TIME_SLOT_8 : bit_vector := "000"; - C_ARB_TIME_SLOT_9 : bit_vector := "000"; - C_ARB_TIME_SLOT_10 : bit_vector := "000"; - C_ARB_TIME_SLOT_11 : bit_vector := "000"; - - C_MEM_TRAS : integer := 45000; - C_MEM_TRCD : integer := 12500; - C_MEM_TREFI : integer := 7800000; - C_MEM_TRFC : integer := 127500; - C_MEM_TRP : integer := 12500; - C_MEM_TWR : integer := 15000; - C_MEM_TRTP : integer := 7500; - C_MEM_TWTR : integer := 7500; - - C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN"; - C_MEM_TYPE : string :="DDR2"; - C_MEM_DENSITY : string :="1Gb"; - C_NUM_DQ_PINS : integer := 4; - C_MEM_BURST_LEN : integer := 8; - C_MEM_CAS_LATENCY : integer := 5; - C_MEM_ADDR_WIDTH : integer := 14; - C_MEM_BANKADDR_WIDTH : integer := 3; - C_MEM_NUM_COL_BITS : integer := 11; - - C_MEM_DDR1_2_ODS : string := "FULL"; - C_MEM_DDR2_RTT : string := "50OHMS"; - C_MEM_DDR2_DIFF_DQS_EN : string := "YES"; - C_MEM_DDR2_3_PA_SR : string := "FULL"; - C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; - - C_MEM_DDR3_CAS_LATENCY : integer:= 7; - C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5; - C_MEM_DDR3_ODS : string := "DIV6"; - C_MEM_DDR3_RTT : string := "DIV2"; - C_MEM_DDR3_AUTO_SR : string := "ENABLED"; - C_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; - C_MEM_MOBILE_PA_SR : string := "FULL"; - C_MEM_MDDR_ODS : string := "FULL"; - - C_MC_CALIB_BYPASS : string := "NO"; - C_LDQSP_TAP_DELAY_VAL : integer := 0; - C_UDQSP_TAP_DELAY_VAL : integer := 0; - C_LDQSN_TAP_DELAY_VAL : integer := 0; - C_UDQSN_TAP_DELAY_VAL : integer := 0; - C_DQ0_TAP_DELAY_VAL : integer := 0; - C_DQ1_TAP_DELAY_VAL : integer := 0; - C_DQ2_TAP_DELAY_VAL : integer := 0; - C_DQ3_TAP_DELAY_VAL : integer := 0; - C_DQ4_TAP_DELAY_VAL : integer := 0; - C_DQ5_TAP_DELAY_VAL : integer := 0; - C_DQ6_TAP_DELAY_VAL : integer := 0; - C_DQ7_TAP_DELAY_VAL : integer := 0; - C_DQ8_TAP_DELAY_VAL : integer := 0; - C_DQ9_TAP_DELAY_VAL : integer := 0; - C_DQ10_TAP_DELAY_VAL : integer := 0; - C_DQ11_TAP_DELAY_VAL : integer := 0; - C_DQ12_TAP_DELAY_VAL : integer := 0; - C_DQ13_TAP_DELAY_VAL : integer := 0; - C_DQ14_TAP_DELAY_VAL : integer := 0; - C_DQ15_TAP_DELAY_VAL : integer := 0; - - - C_SKIP_IN_TERM_CAL : integer := 0; - C_SKIP_DYNAMIC_CAL : integer := 0; - - C_SIMULATION : string := "FALSE"; - C_MC_CALIBRATION_MODE : string := "CALIBRATION"; - C_MC_CALIBRATION_DELAY : string := "QUARTER"; - C_CALIB_SOFT_IP : string := "TRUE" - - - ); - port - ( - - -- high-speed PLL clock interface - sysclk_2x : in std_logic; - sysclk_2x_180 : in std_logic; - pll_ce_0 : in std_logic; - pll_ce_90 : in std_logic; - pll_lock : in std_logic; - async_rst : in std_logic; - - --User Port0 Interface Signals - - p0_cmd_clk : in std_logic; - p0_cmd_en : in std_logic; - p0_cmd_instr : in std_logic_vector(2 downto 0) ; - p0_cmd_bl : in std_logic_vector(5 downto 0) ; - p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ; - p0_cmd_empty : out std_logic; - p0_cmd_full : out std_logic; - - -- Data Wr Port signals - p0_wr_clk : in std_logic; - p0_wr_en : in std_logic; - p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ; - p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ; - p0_wr_full : out std_logic; - p0_wr_empty : out std_logic; - p0_wr_count : out std_logic_vector(6 downto 0) ; - p0_wr_underrun : out std_logic; - p0_wr_error : out std_logic; - - --Data Rd Port signals - p0_rd_clk : in std_logic; - p0_rd_en : in std_logic; - p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ; - p0_rd_full : out std_logic; - p0_rd_empty : out std_logic; - p0_rd_count : out std_logic_vector(6 downto 0) ; - p0_rd_overflow : out std_logic; - p0_rd_error : out std_logic; - - --User Port1 Interface Signals - - p1_cmd_clk : in std_logic; - p1_cmd_en : in std_logic; - p1_cmd_instr : in std_logic_vector(2 downto 0) ; - p1_cmd_bl : in std_logic_vector(5 downto 0) ; - p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ; - p1_cmd_empty : out std_logic; - p1_cmd_full : out std_logic; - - -- Data Wr Port signals - p1_wr_clk : in std_logic; - p1_wr_en : in std_logic; - p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ; - p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ; - p1_wr_full : out std_logic; - p1_wr_empty : out std_logic; - p1_wr_count : out std_logic_vector(6 downto 0) ; - p1_wr_underrun : out std_logic; - p1_wr_error : out std_logic; - - --Data Rd Port signals - p1_rd_clk : in std_logic; - p1_rd_en : in std_logic; - p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ; - p1_rd_full : out std_logic; - p1_rd_empty : out std_logic; - p1_rd_count : out std_logic_vector(6 downto 0) ; - p1_rd_overflow : out std_logic; - p1_rd_error : out std_logic; - - --User Port2 Interface Signals - - p2_cmd_clk : in std_logic; - p2_cmd_en : in std_logic; - p2_cmd_instr : in std_logic_vector(2 downto 0) ; - p2_cmd_bl : in std_logic_vector(5 downto 0) ; - p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ; - p2_cmd_empty : out std_logic; - p2_cmd_full : out std_logic; - - --Data Wr Port signals - p2_wr_clk : in std_logic; - p2_wr_en : in std_logic; - p2_wr_mask : in std_logic_vector(3 downto 0) ; - p2_wr_data : in std_logic_vector(31 downto 0) ; - p2_wr_full : out std_logic; - p2_wr_empty : out std_logic; - p2_wr_count : out std_logic_vector(6 downto 0) ; - p2_wr_underrun : out std_logic; - p2_wr_error : out std_logic; - - --User Port3 Interface Signals - - p3_cmd_clk : in std_logic; - p3_cmd_en : in std_logic; - p3_cmd_instr : in std_logic_vector(2 downto 0) ; - p3_cmd_bl : in std_logic_vector(5 downto 0) ; - p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ; - p3_cmd_empty : out std_logic; - p3_cmd_full : out std_logic; - - --Data Rd Port signals - p3_rd_clk : in std_logic; - p3_rd_en : in std_logic; - p3_rd_data : out std_logic_vector(31 downto 0) ; - p3_rd_full : out std_logic; - p3_rd_empty : out std_logic; - p3_rd_count : out std_logic_vector(6 downto 0) ; - p3_rd_overflow : out std_logic; - p3_rd_error : out std_logic; - - --User Port4 Interface Signals - - p4_cmd_clk : in std_logic; - p4_cmd_en : in std_logic; - p4_cmd_instr : in std_logic_vector(2 downto 0) ; - p4_cmd_bl : in std_logic_vector(5 downto 0) ; - p4_cmd_byte_addr : in std_logic_vector(29 downto 0) ; - p4_cmd_empty : out std_logic; - p4_cmd_full : out std_logic; - - --Data Wr Port signals - p4_wr_clk : in std_logic; - p4_wr_en : in std_logic; - p4_wr_mask : in std_logic_vector(3 downto 0) ; - p4_wr_data : in std_logic_vector(31 downto 0) ; - p4_wr_full : out std_logic; - p4_wr_empty : out std_logic; - p4_wr_count : out std_logic_vector(6 downto 0) ; - p4_wr_underrun : out std_logic; - p4_wr_error : out std_logic; - - --User Port5 Interface Signals - - p5_cmd_clk : in std_logic; - p5_cmd_en : in std_logic; - p5_cmd_instr : in std_logic_vector(2 downto 0) ; - p5_cmd_bl : in std_logic_vector(5 downto 0) ; - p5_cmd_byte_addr : in std_logic_vector(29 downto 0) ; - p5_cmd_empty : out std_logic; - p5_cmd_full : out std_logic; - - --Data Rd Port signals - p5_rd_clk : in std_logic; - p5_rd_en : in std_logic; - p5_rd_data : out std_logic_vector(31 downto 0) ; - p5_rd_full : out std_logic; - p5_rd_empty : out std_logic; - p5_rd_count : out std_logic_vector(6 downto 0) ; - p5_rd_overflow : out std_logic; - p5_rd_error : out std_logic; - - - - -- memory interface signals - mcb3_dram_ck : out std_logic; - mcb3_dram_ck_n : out std_logic; - mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0); - mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0); - mcb3_dram_ras_n : out std_logic; - mcb3_dram_cas_n : out std_logic; - mcb3_dram_we_n : out std_logic; - mcb3_dram_cke : out std_logic; - mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0); - mcb3_dram_dqs : inout std_logic; - - -mcb3_dram_udqs : inout std_logic; -mcb3_dram_udm : out std_logic; - - - -mcb3_dram_dm : out std_logic; - - mcb3_rzq : inout std_logic; - - - -- Calibration signals - mcb_drp_clk : in std_logic; - calib_done : out std_logic; - selfrefresh_enter : in std_logic; - selfrefresh_mode : out std_logic - - ); -end entity; -architecture acch of memc3_wrapper is -component mcb_raw_wrapper IS - GENERIC ( - - C_MEMCLK_PERIOD : integer; - C_PORT_ENABLE : std_logic_vector(5 downto 0); - C_MEM_ADDR_ORDER : string; - C_ARB_NUM_TIME_SLOTS : integer; - C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0); - C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0); - C_PORT_CONFIG : string; - - - C_MEM_TRAS : integer; - C_MEM_TRCD : integer; - C_MEM_TREFI : integer; - C_MEM_TRFC : integer; - C_MEM_TRP : integer; - C_MEM_TWR : integer; - C_MEM_TRTP : integer; - C_MEM_TWTR : integer; - - C_NUM_DQ_PINS : integer; - C_MEM_TYPE : string; - C_MEM_DENSITY : string; - C_MEM_BURST_LEN : integer; - - C_MEM_CAS_LATENCY : integer; - C_MEM_ADDR_WIDTH : integer; - C_MEM_BANKADDR_WIDTH : integer; - C_MEM_NUM_COL_BITS : integer; - - C_MEM_DDR3_CAS_LATENCY : integer; - C_MEM_MOBILE_PA_SR : string; - C_MEM_DDR1_2_ODS : string; - C_MEM_DDR3_ODS : string; - C_MEM_DDR2_RTT : string; - C_MEM_DDR3_RTT : string; - C_MEM_MDDR_ODS : string; - - C_MEM_DDR2_DIFF_DQS_EN : string; - C_MEM_DDR2_3_PA_SR : string; - C_MEM_DDR3_CAS_WR_LATENCY : integer; - - C_MEM_DDR3_AUTO_SR : string; - C_MEM_DDR2_3_HIGH_TEMP_SR : string; - C_MEM_DDR3_DYN_WRT_ODT : string; - - C_MC_CALIB_BYPASS : string; - C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0); - C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0); - C_CALIB_SOFT_IP : string; - C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0); - C_MC_CALIBRATION_CLK_DIV : integer; - C_MC_CALIBRATION_MODE : string; - C_MC_CALIBRATION_DELAY : string; - - LDQSP_TAP_DELAY_VAL : integer; - UDQSP_TAP_DELAY_VAL : integer; - LDQSN_TAP_DELAY_VAL : integer; - UDQSN_TAP_DELAY_VAL : integer; - DQ0_TAP_DELAY_VAL : integer; - DQ1_TAP_DELAY_VAL : integer; - DQ2_TAP_DELAY_VAL : integer; - DQ3_TAP_DELAY_VAL : integer; - DQ4_TAP_DELAY_VAL : integer; - DQ5_TAP_DELAY_VAL : integer; - DQ6_TAP_DELAY_VAL : integer; - DQ7_TAP_DELAY_VAL : integer; - DQ8_TAP_DELAY_VAL : integer; - DQ9_TAP_DELAY_VAL : integer; - DQ10_TAP_DELAY_VAL : integer; - DQ11_TAP_DELAY_VAL : integer; - DQ12_TAP_DELAY_VAL : integer; - DQ13_TAP_DELAY_VAL : integer; - DQ14_TAP_DELAY_VAL : integer; - DQ15_TAP_DELAY_VAL : integer; - - C_P0_MASK_SIZE : integer; - C_P0_DATA_PORT_SIZE : integer; - C_P1_MASK_SIZE : integer; - C_P1_DATA_PORT_SIZE : integer; - - C_SIMULATION : string ; - C_SKIP_IN_TERM_CAL : integer; - C_SKIP_DYNAMIC_CAL : integer; - C_SKIP_DYN_IN_TERM : integer; - - C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) - ); - PORT ( - -- HIGH-SPEED PLL clock interface - - sysclk_2x : in std_logic; - sysclk_2x_180 : in std_logic; - pll_ce_0 : in std_logic; - pll_ce_90 : in std_logic; - pll_lock : in std_logic; - sys_rst : in std_logic; - - p0_arb_en : in std_logic; - p0_cmd_clk : in std_logic; - p0_cmd_en : in std_logic; - p0_cmd_instr : in std_logic_vector(2 DOWNTO 0); - p0_cmd_bl : in std_logic_vector(5 DOWNTO 0); - p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); - p0_cmd_empty : out std_logic; - p0_cmd_full : out std_logic; - p0_wr_clk : in std_logic; - p0_wr_en : in std_logic; - p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0); - p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0); - p0_wr_full : out std_logic; - p0_wr_empty : out std_logic; - p0_wr_count : out std_logic_vector(6 DOWNTO 0); - p0_wr_underrun : out std_logic; - p0_wr_error : out std_logic; - p0_rd_clk : in std_logic; - p0_rd_en : in std_logic; - p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0); - p0_rd_full : out std_logic; - p0_rd_empty : out std_logic; - p0_rd_count : out std_logic_vector(6 DOWNTO 0); - p0_rd_overflow : out std_logic; - p0_rd_error : out std_logic; - p1_arb_en : in std_logic; - p1_cmd_clk : in std_logic; - p1_cmd_en : in std_logic; - p1_cmd_instr : in std_logic_vector(2 DOWNTO 0); - p1_cmd_bl : in std_logic_vector(5 DOWNTO 0); - p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); - p1_cmd_empty : out std_logic; - p1_cmd_full : out std_logic; - p1_wr_clk : in std_logic; - p1_wr_en : in std_logic; - p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0); - p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0); - p1_wr_full : out std_logic; - p1_wr_empty : out std_logic; - p1_wr_count : out std_logic_vector(6 DOWNTO 0); - p1_wr_underrun : out std_logic; - p1_wr_error : out std_logic; - p1_rd_clk : in std_logic; - p1_rd_en : in std_logic; - p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0); - p1_rd_full : out std_logic; - p1_rd_empty : out std_logic; - p1_rd_count : out std_logic_vector(6 DOWNTO 0); - p1_rd_overflow : out std_logic; - p1_rd_error : out std_logic; - p2_arb_en : in std_logic; - p2_cmd_clk : in std_logic; - p2_cmd_en : in std_logic; - p2_cmd_instr : in std_logic_vector(2 DOWNTO 0); - p2_cmd_bl : in std_logic_vector(5 DOWNTO 0); - p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); - p2_cmd_empty : out std_logic; - p2_cmd_full : out std_logic; - p2_wr_clk : in std_logic; - p2_wr_en : in std_logic; - p2_wr_mask : in std_logic_vector(3 DOWNTO 0); - p2_wr_data : in std_logic_vector(31 DOWNTO 0); - p2_wr_full : out std_logic; - p2_wr_empty : out std_logic; - p2_wr_count : out std_logic_vector(6 DOWNTO 0); - p2_wr_underrun : out std_logic; - p2_wr_error : out std_logic; - p2_rd_clk : in std_logic; - p2_rd_en : in std_logic; - p2_rd_data : out std_logic_vector(31 DOWNTO 0); - p2_rd_full : out std_logic; - p2_rd_empty : out std_logic; - p2_rd_count : out std_logic_vector(6 DOWNTO 0); - p2_rd_overflow : out std_logic; - p2_rd_error : out std_logic; - p3_arb_en : in std_logic; - p3_cmd_clk : in std_logic; - p3_cmd_en : in std_logic; - p3_cmd_instr : in std_logic_vector(2 DOWNTO 0); - p3_cmd_bl : in std_logic_vector(5 DOWNTO 0); - p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); - p3_cmd_empty : out std_logic; - p3_cmd_full : out std_logic; - p3_wr_clk : in std_logic; - p3_wr_en : in std_logic; - p3_wr_mask : in std_logic_vector(3 DOWNTO 0); - p3_wr_data : in std_logic_vector(31 DOWNTO 0); - p3_wr_full : out std_logic; - p3_wr_empty : out std_logic; - p3_wr_count : out std_logic_vector(6 DOWNTO 0); - p3_wr_underrun : out std_logic; - p3_wr_error : out std_logic; - p3_rd_clk : in std_logic; - p3_rd_en : in std_logic; - p3_rd_data : out std_logic_vector(31 DOWNTO 0); - p3_rd_full : out std_logic; - p3_rd_empty : out std_logic; - p3_rd_count : out std_logic_vector(6 DOWNTO 0); - p3_rd_overflow : out std_logic; - p3_rd_error : out std_logic; - p4_arb_en : in std_logic; - p4_cmd_clk : in std_logic; - p4_cmd_en : in std_logic; - p4_cmd_instr : in std_logic_vector(2 DOWNTO 0); - p4_cmd_bl : in std_logic_vector(5 DOWNTO 0); - p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); - p4_cmd_empty : out std_logic; - p4_cmd_full : out std_logic; - p4_wr_clk : in std_logic; - p4_wr_en : in std_logic; - p4_wr_mask : in std_logic_vector(3 DOWNTO 0); - p4_wr_data : in std_logic_vector(31 DOWNTO 0); - p4_wr_full : out std_logic; - p4_wr_empty : out std_logic; - p4_wr_count : out std_logic_vector(6 DOWNTO 0); - p4_wr_underrun : out std_logic; - p4_wr_error : out std_logic; - p4_rd_clk : in std_logic; - p4_rd_en : in std_logic; - p4_rd_data : out std_logic_vector(31 DOWNTO 0); - p4_rd_full : out std_logic; - p4_rd_empty : out std_logic; - p4_rd_count : out std_logic_vector(6 DOWNTO 0); - p4_rd_overflow : out std_logic; - p4_rd_error : out std_logic; - p5_arb_en : in std_logic; - p5_cmd_clk : in std_logic; - p5_cmd_en : in std_logic; - p5_cmd_instr : in std_logic_vector(2 DOWNTO 0); - p5_cmd_bl : in std_logic_vector(5 DOWNTO 0); - p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); - p5_cmd_empty : out std_logic; - p5_cmd_full : out std_logic; - p5_wr_clk : in std_logic; - p5_wr_en : in std_logic; - p5_wr_mask : in std_logic_vector(3 DOWNTO 0); - p5_wr_data : in std_logic_vector(31 DOWNTO 0); - p5_wr_full : out std_logic; - p5_wr_empty : out std_logic; - p5_wr_count : out std_logic_vector(6 DOWNTO 0); - p5_wr_underrun : out std_logic; - p5_wr_error : out std_logic; - p5_rd_clk : in std_logic; - p5_rd_en : in std_logic; - p5_rd_data : out std_logic_vector(31 DOWNTO 0); - p5_rd_full : out std_logic; - p5_rd_empty : out std_logic; - p5_rd_count : out std_logic_vector(6 DOWNTO 0); - p5_rd_overflow : out std_logic; - p5_rd_error : out std_logic; - - mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0); - mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0); - mcbx_dram_ras_n : out std_logic; - mcbx_dram_cas_n : out std_logic; - mcbx_dram_we_n : out std_logic; - mcbx_dram_cke : out std_logic; - mcbx_dram_clk : out std_logic; - mcbx_dram_clk_n : out std_logic; - mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0); - mcbx_dram_dqs : inout std_logic; - mcbx_dram_dqs_n : inout std_logic; - mcbx_dram_udqs : inout std_logic; - mcbx_dram_udqs_n : inout std_logic; - mcbx_dram_udm : out std_logic; - mcbx_dram_ldm : out std_logic; - mcbx_dram_odt : out std_logic; - mcbx_dram_ddr3_rst : out std_logic; - calib_recal : in std_logic; - rzq : inout std_logic; - zio : inout std_logic; - ui_read : in std_logic; - ui_add : in std_logic; - ui_cs : in std_logic; - ui_clk : in std_logic; - ui_sdi : in std_logic; - ui_addr : in std_logic_vector(4 DOWNTO 0); - ui_broadcast : in std_logic; - ui_drp_update : in std_logic; - ui_done_cal : in std_logic; - ui_cmd : in std_logic; - ui_cmd_in : in std_logic; - ui_cmd_en : in std_logic; - ui_dqcount : in std_logic_vector(3 DOWNTO 0); - ui_dq_lower_dec : in std_logic; - ui_dq_lower_inc : in std_logic; - ui_dq_upper_dec : in std_logic; - ui_dq_upper_inc : in std_logic; - ui_udqs_inc : in std_logic; - ui_udqs_dec : in std_logic; - ui_ldqs_inc : in std_logic; - ui_ldqs_dec : in std_logic; - uo_data : out std_logic_vector(7 DOWNTO 0); - uo_data_valid : out std_logic; - uo_done_cal : out std_logic; - uo_cmd_ready_in : out std_logic; - uo_refrsh_flag : out std_logic; - uo_cal_start : out std_logic; - uo_sdo : out std_logic; - status : out std_logic_vector(31 DOWNTO 0); - selfrefresh_enter : in std_logic; - selfrefresh_mode : out std_logic - ); -end component; - -signal uo_data : std_logic_vector(7 downto 0); - - constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "111111"; - -constant C_PORT_CONFIG : string := "B32_B32_W32_R32_W32_R32"; - - -constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_0(2 downto 0) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(14 downto 12) & C_ARB_TIME_SLOT_0(17 downto 15)); -constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_1(2 downto 0) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(14 downto 12) & C_ARB_TIME_SLOT_1(17 downto 15)); -constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_2(2 downto 0) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(14 downto 12) & C_ARB_TIME_SLOT_2(17 downto 15)); -constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_3(2 downto 0) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(14 downto 12) & C_ARB_TIME_SLOT_3(17 downto 15)); -constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_4(2 downto 0) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(14 downto 12) & C_ARB_TIME_SLOT_4(17 downto 15)); -constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_5(2 downto 0) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(14 downto 12) & C_ARB_TIME_SLOT_5(17 downto 15)); -constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_6(2 downto 0) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(14 downto 12) & C_ARB_TIME_SLOT_6(17 downto 15)); -constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_7(2 downto 0) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(14 downto 12) & C_ARB_TIME_SLOT_7(17 downto 15)); -constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_8(2 downto 0) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(14 downto 12) & C_ARB_TIME_SLOT_8(17 downto 15)); -constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_9(2 downto 0) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(14 downto 12) & C_ARB_TIME_SLOT_9(17 downto 15)); -constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_10(2 downto 0) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(14 downto 12) & C_ARB_TIME_SLOT_10(17 downto 15)); -constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_11(2 downto 0) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(14 downto 12) & C_ARB_TIME_SLOT_11(17 downto 15)); - - -constant C_MC_CALIBRATION_CLK_DIV : integer := 1; -constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -constant C_SKIP_DYN_IN_TERM : integer := 1; - -constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000"; -constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0"; -constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000"; - -signal status : std_logic_vector(31 downto 0); -signal uo_data_valid : std_logic; -signal uo_cmd_ready_in : std_logic; -signal uo_refrsh_flag : std_logic; -signal uo_cal_start : std_logic; -signal uo_sdo : std_logic; -signal mcb3_zio : std_logic; - - -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of acch : architecture IS - "mig_v3_5_ddr_s6, Coregen 12.2"; - -attribute CORE_GENERATION_INFO : string; -attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr_s6,mig_v3_5,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR_SDRAM,CLK_PERIOD=5000, MEMORY_PART=mt46v32m16xx-5b-it, OUTPUT_DRV=FULL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1_Port2_Port3_Port4_Port5, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=UNCALIB_TERM, DATA_TERMINATION=50 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}"; - -begin - - -memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper -generic map - ( - C_MEMCLK_PERIOD => C_MEMCLK_PERIOD, - C_P0_MASK_SIZE => C_P0_MASK_SIZE, - C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE, - C_P1_MASK_SIZE => C_P1_MASK_SIZE, - C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE, - - C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS, - C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0, - C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1, - C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2, - C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3, - C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4, - C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5, - C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6, - C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7, - C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8, - C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9, - C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10, - C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11, - - C_PORT_CONFIG => C_PORT_CONFIG, - C_PORT_ENABLE => C_PORT_ENABLE, - - C_MEM_TRAS => C_MEM_TRAS, - C_MEM_TRCD => C_MEM_TRCD, - C_MEM_TREFI => C_MEM_TREFI, - C_MEM_TRFC => C_MEM_TRFC, - C_MEM_TRP => C_MEM_TRP, - C_MEM_TWR => C_MEM_TWR, - C_MEM_TRTP => C_MEM_TRTP, - C_MEM_TWTR => C_MEM_TWTR, - - C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER, - C_NUM_DQ_PINS => C_NUM_DQ_PINS, - C_MEM_TYPE => C_MEM_TYPE, - C_MEM_DENSITY => C_MEM_DENSITY, - C_MEM_BURST_LEN => C_MEM_BURST_LEN, - C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY, - C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH, - C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH, - C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS, - - C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS, - C_MEM_DDR2_RTT => C_MEM_DDR2_RTT, - C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN, - C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR, - C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR, - - C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY, - C_MEM_DDR3_ODS => C_MEM_DDR3_ODS, - C_MEM_DDR3_RTT => C_MEM_DDR3_RTT, - C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY, - C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR, - C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT, - C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR, - C_MEM_MDDR_ODS => C_MEM_MDDR_ODS, - C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV, - C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, - C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY, - - C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS, - C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA, - C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA, - C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA, - C_CALIB_SOFT_IP => C_CALIB_SOFT_IP, - - C_SIMULATION => C_SIMULATION, - C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL, - C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL, - C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM, - C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT, - - LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL, - UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL, - LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL, - UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL, - DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL, - DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL, - DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL, - DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL, - DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL, - DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL, - DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL, - DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL, - DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL, - DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL, - DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL, - DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL, - DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL, - DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL, - DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL, - DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL - ) - -port map -( - sys_rst => async_rst, - sysclk_2x => sysclk_2x, - sysclk_2x_180 => sysclk_2x_180, - pll_ce_0 => pll_ce_0, - pll_ce_90 => pll_ce_90, - pll_lock => pll_lock, - mcbx_dram_addr => mcb3_dram_a, - mcbx_dram_ba => mcb3_dram_ba, - mcbx_dram_ras_n => mcb3_dram_ras_n, - mcbx_dram_cas_n => mcb3_dram_cas_n, - mcbx_dram_we_n => mcb3_dram_we_n, - mcbx_dram_cke => mcb3_dram_cke, - mcbx_dram_clk => mcb3_dram_ck, - mcbx_dram_clk_n => mcb3_dram_ck_n, - mcbx_dram_dq => mcb3_dram_dq, - mcbx_dram_odt => open, - mcbx_dram_ldm => mcb3_dram_dm, - mcbx_dram_udm => mcb3_dram_udm, - mcbx_dram_dqs => mcb3_dram_dqs, - mcbx_dram_dqs_n => open, - mcbx_dram_udqs => mcb3_dram_udqs, - mcbx_dram_udqs_n => open, - mcbx_dram_ddr3_rst => open, - calib_recal => '0', - rzq => mcb3_rzq, - zio => mcb3_zio, - ui_read => '0', - ui_add => '0', - ui_cs => '0', - ui_clk => mcb_drp_clk, - ui_sdi => '0', - ui_addr => (others => '0'), - ui_broadcast => '0', - ui_drp_update => '0', - ui_done_cal => '1', - ui_cmd => '0', - ui_cmd_in => '0', - ui_cmd_en => '0', - ui_dqcount => (others => '0'), - ui_dq_lower_dec => '0', - ui_dq_lower_inc => '0', - ui_dq_upper_dec => '0', - ui_dq_upper_inc => '0', - ui_udqs_inc => '0', - ui_udqs_dec => '0', - ui_ldqs_inc => '0', - ui_ldqs_dec => '0', - uo_data => uo_data, - uo_data_valid => uo_data_valid, - uo_done_cal => calib_done, - uo_cmd_ready_in => uo_cmd_ready_in, - uo_refrsh_flag => uo_refrsh_flag, - uo_cal_start => uo_cal_start, - uo_sdo => uo_sdo, - status => status, - selfrefresh_enter => '0', - selfrefresh_mode => selfrefresh_mode, - - - p0_arb_en => '1', - p0_cmd_clk => p0_cmd_clk, - p0_cmd_en => p0_cmd_en, - p0_cmd_instr => p0_cmd_instr, - p0_cmd_bl => p0_cmd_bl, - p0_cmd_byte_addr => p0_cmd_byte_addr, - p0_cmd_empty => p0_cmd_empty, - p0_cmd_full => p0_cmd_full, - p0_wr_clk => p0_wr_clk, - p0_wr_en => p0_wr_en, - p0_wr_mask => p0_wr_mask, - p0_wr_data => p0_wr_data, - p0_wr_full => p0_wr_full, - p0_wr_empty => p0_wr_empty, - p0_wr_count => p0_wr_count, - p0_wr_underrun => p0_wr_underrun, - p0_wr_error => p0_wr_error, - p0_rd_clk => p0_rd_clk, - p0_rd_en => p0_rd_en, - p0_rd_data => p0_rd_data, - p0_rd_full => p0_rd_full, - p0_rd_empty => p0_rd_empty, - p0_rd_count => p0_rd_count, - p0_rd_overflow => p0_rd_overflow, - p0_rd_error => p0_rd_error, - p1_arb_en => '1', - p1_cmd_clk => p1_cmd_clk, - p1_cmd_en => p1_cmd_en, - p1_cmd_instr => p1_cmd_instr, - p1_cmd_bl => p1_cmd_bl, - p1_cmd_byte_addr => p1_cmd_byte_addr, - p1_cmd_empty => p1_cmd_empty, - p1_cmd_full => p1_cmd_full, - p1_wr_clk => p1_wr_clk, - p1_wr_en => p1_wr_en, - p1_wr_mask => p1_wr_mask, - p1_wr_data => p1_wr_data, - p1_wr_full => p1_wr_full, - p1_wr_empty => p1_wr_empty, - p1_wr_count => p1_wr_count, - p1_wr_underrun => p1_wr_underrun, - p1_wr_error => p1_wr_error, - p1_rd_clk => p1_rd_clk, - p1_rd_en => p1_rd_en, - p1_rd_data => p1_rd_data, - p1_rd_full => p1_rd_full, - p1_rd_empty => p1_rd_empty, - p1_rd_count => p1_rd_count, - p1_rd_overflow => p1_rd_overflow, - p1_rd_error => p1_rd_error, - p2_arb_en => '1', - p2_cmd_clk => p2_cmd_clk, - p2_cmd_en => p2_cmd_en, - p2_cmd_instr => p2_cmd_instr, - p2_cmd_bl => p2_cmd_bl, - p2_cmd_byte_addr => p2_cmd_byte_addr, - p2_cmd_empty => p2_cmd_empty, - p2_cmd_full => p2_cmd_full, - p2_rd_clk => '0', - p2_rd_en => '0', - p2_rd_data => open, - p2_rd_full => open, - p2_rd_empty => open, - p2_rd_count => open, - p2_rd_overflow => open, - p2_rd_error => open, - p2_wr_clk => p2_wr_clk, - p2_wr_en => p2_wr_en, - p2_wr_mask => p2_wr_mask, - p2_wr_data => p2_wr_data, - p2_wr_full => p2_wr_full, - p2_wr_empty => p2_wr_empty, - p2_wr_count => p2_wr_count, - p2_wr_underrun => p2_wr_underrun, - p2_wr_error => p2_wr_error, - p3_arb_en => '1', - p3_cmd_clk => p3_cmd_clk, - p3_cmd_en => p3_cmd_en, - p3_cmd_instr => p3_cmd_instr, - p3_cmd_bl => p3_cmd_bl, - p3_cmd_byte_addr => p3_cmd_byte_addr, - p3_cmd_empty => p3_cmd_empty, - p3_cmd_full => p3_cmd_full, - p3_rd_clk => p3_rd_clk, - p3_rd_en => p3_rd_en, - p3_rd_data => p3_rd_data, - p3_rd_full => p3_rd_full, - p3_rd_empty => p3_rd_empty, - p3_rd_count => p3_rd_count, - p3_rd_overflow => p3_rd_overflow, - p3_rd_error => p3_rd_error, - p3_wr_clk => '0', - p3_wr_en => '0', - p3_wr_mask => (others => '0'), - p3_wr_data => (others => '0'), - p3_wr_full => open, - p3_wr_empty => open, - p3_wr_count => open, - p3_wr_underrun => open, - p3_wr_error => open, - p4_arb_en => '1', - p4_cmd_clk => p4_cmd_clk, - p4_cmd_en => p4_cmd_en, - p4_cmd_instr => p4_cmd_instr, - p4_cmd_bl => p4_cmd_bl, - p4_cmd_byte_addr => p4_cmd_byte_addr, - p4_cmd_empty => p4_cmd_empty, - p4_cmd_full => p4_cmd_full, - p4_rd_clk => '0', - p4_rd_en => '0', - p4_rd_data => open, - p4_rd_full => open, - p4_rd_empty => open, - p4_rd_count => open, - p4_rd_overflow => open, - p4_rd_error => open, - p4_wr_clk => p4_wr_clk, - p4_wr_en => p4_wr_en, - p4_wr_mask => p4_wr_mask, - p4_wr_data => p4_wr_data, - p4_wr_full => p4_wr_full, - p4_wr_empty => p4_wr_empty, - p4_wr_count => p4_wr_count, - p4_wr_underrun => p4_wr_underrun, - p4_wr_error => p4_wr_error, - p5_arb_en => '1', - p5_cmd_clk => p5_cmd_clk, - p5_cmd_en => p5_cmd_en, - p5_cmd_instr => p5_cmd_instr, - p5_cmd_bl => p5_cmd_bl, - p5_cmd_byte_addr => p5_cmd_byte_addr, - p5_cmd_empty => p5_cmd_empty, - p5_cmd_full => p5_cmd_full, - p5_rd_clk => p5_rd_clk, - p5_rd_en => p5_rd_en, - p5_rd_data => p5_rd_data, - p5_rd_full => p5_rd_full, - p5_rd_empty => p5_rd_empty, - p5_rd_count => p5_rd_count, - p5_rd_overflow => p5_rd_overflow, - p5_rd_error => p5_rd_error, - p5_wr_clk => '0', - p5_wr_en => '0', - p5_wr_mask => (others => '0'), - p5_wr_data => (others => '0'), - p5_wr_full => open, - p5_wr_empty => open, - p5_wr_count => open, - p5_wr_underrun => open, - p5_wr_error => open -); - - - -end architecture; - Index: ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd (nonexistent) @@ -1,6943 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version: %version --- \ \ Application: MIG --- / / Filename: mcb_raw_wrapper.v --- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:37 $ --- \ \ / \ Date Created: Thu June 24 2008 --- \___\/\___\ --- ---Device: Spartan6 ---Design Name: DDR/DDR2/DDR3/LPDDR ---Purpose: ---Reference: --- This module is the intialization control logic of the memory interface. --- All commands are issued from here acoording to the burst, CAS Latency and --- the user commands. --- --- Revised History: --- Rev 1.1 - added port_enable assignment for all configurations and rearrange --- assignment siganls according to port number --- - added timescale directive -SN 7-28-08 --- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through --- 15 -SN 7-28-08 --- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08 --- - removed ghighb, gpwrdnb, gsr, gwe in port declaration. --- For now tb need to force the signals inside the MCB and Wrapper --- until a glbl.v is ready. Not sure how to do this in NCVerilog --- flow. -SN 7-28-08 --- --- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08 --- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08 --- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09 --- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08 --- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90 --- delay_we_90 ,delay_address,delay_ba_90 = --- --removed :assign #50 delay_dqnum = dqnum; --- --removed :assign #50 delay_dqpum = dqpum; --- --removed :assign #50 delay_dqnlm = dqnlm; --- --removed :assign #50 delay_dqplm = dqplm; --- --removed : delay_dqsIO_w_en_90_n --- --removed : delay_dqsIO_w_en_90_p --- --removed : delay_dqsIO_w_en_0 --- -- corrected spelling error: C_MEM_RTRAS --- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09 --- -- rename the memc_wrapper.v to mcb_raw_wrapper.v --- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09 --- -- connection has been updated --- Rev 1.8 -- update memory parameter equations. 1-30_2009 --- -- added portion of Soft IP --- -- CAL_CLK_DIV is not used but MCB still has it --- Rev 1.9 -- added Error checking for Invalid command to unidirectional port --- Rev 1.10 -- changed the backend connection so that Simulation will work while --- sw tools try to fix the model issues. 2-3-2009 --- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions. --- It is acutally 180 degree difference. --- Rev 1.11 -- Added MCB_Soft_Calibration_top. --- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009 --- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines. --- Rev 1.14 -- Added minium condition for tRTP valud/ --- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009 --- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009 --- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009 --- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010 --- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009. --- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable --- Dynamic DQS calibration in Soft Calibration module. --- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if --- RTT value is set to "disabled" --- -- Corrected the UIUDQSDEC connection between soft_calib and MCB. --- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010 --- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . --- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32). ---************************************************************************************************************************* -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; -library unisim; -use unisim.vcomponents.all; - -entity mcb_raw_wrapper is -generic( - C_MEMCLK_PERIOD : integer := 2500; - C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1'); - - C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN"; - - C_ARB_NUM_TIME_SLOTS : integer := 12; - C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101"; - C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000"; - C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011"; - C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010"; - C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011"; - C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100"; - C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101"; - C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000"; - C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011"; - C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010"; - C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011"; - C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100"; - C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32"; - - - C_MEM_TRAS : integer := 45000; - C_MEM_TRCD : integer := 12500; - C_MEM_TREFI : integer := 7800; - C_MEM_TRFC : integer := 127500; - C_MEM_TRP : integer := 12500; - C_MEM_TWR : integer := 15000; - C_MEM_TRTP : integer := 7500; - C_MEM_TWTR : integer := 7500; - - C_NUM_DQ_PINS : integer := 8; - C_MEM_TYPE : string := "DDR3"; - C_MEM_DENSITY : string := "512M"; - C_MEM_BURST_LEN : integer := 8; - - C_MEM_CAS_LATENCY : integer := 4; - C_MEM_ADDR_WIDTH : integer := 13; - C_MEM_BANKADDR_WIDTH : integer := 3; - C_MEM_NUM_COL_BITS : integer := 11; - - C_MEM_DDR3_CAS_LATENCY : integer := 7; - C_MEM_MOBILE_PA_SR : string := "FULL"; - C_MEM_DDR1_2_ODS : string := "FULL"; - C_MEM_DDR3_ODS : string := "DIV6"; - C_MEM_DDR2_RTT : string := "50OHMS"; - C_MEM_DDR3_RTT : string := "DIV2"; - C_MEM_MDDR_ODS : string := "FULL"; - - C_MEM_DDR2_DIFF_DQS_EN : string := "YES"; - C_MEM_DDR2_3_PA_SR : string := "OFF"; - C_MEM_DDR3_CAS_WR_LATENCY : integer := 5; - - C_MEM_DDR3_AUTO_SR : string := "ENABLED"; - C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; - C_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; - C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets - - C_MC_CALIB_BYPASS : string := "NO"; - C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000"; - C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000"; - - C_CALIB_SOFT_IP : string := "TRUE"; - C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration - C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration - C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration - C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented - - ---- ADDED for 1.0 silicon support to bypass Calibration ////// --- 07-10-09 chipl ---//////////////////////////////////////////////////////////// - LDQSP_TAP_DELAY_VAL : integer := 0; - UDQSP_TAP_DELAY_VAL : integer := 0; - LDQSN_TAP_DELAY_VAL : integer := 0; - UDQSN_TAP_DELAY_VAL : integer := 0; - DQ0_TAP_DELAY_VAL : integer := 0; - DQ1_TAP_DELAY_VAL : integer := 0; - DQ2_TAP_DELAY_VAL : integer := 0; - DQ3_TAP_DELAY_VAL : integer := 0; - DQ4_TAP_DELAY_VAL : integer := 0; - DQ5_TAP_DELAY_VAL : integer := 0; - DQ6_TAP_DELAY_VAL : integer := 0; - DQ7_TAP_DELAY_VAL : integer := 0; - DQ8_TAP_DELAY_VAL : integer := 0; - DQ9_TAP_DELAY_VAL : integer := 0; - DQ10_TAP_DELAY_VAL : integer := 0; - DQ11_TAP_DELAY_VAL : integer := 0; - DQ12_TAP_DELAY_VAL : integer := 0; - DQ13_TAP_DELAY_VAL : integer := 0; - DQ14_TAP_DELAY_VAL : integer := 0; - DQ15_TAP_DELAY_VAL : integer := 0; - - C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000"; - C_MC_CALIBRATION_CLK_DIV : integer := 1; - C_MC_CALIBRATION_MODE : string := "CALIBRATION"; - C_MC_CALIBRATION_DELAY : string := "HALF"; - - C_P0_MASK_SIZE : integer := 4; - C_P0_DATA_PORT_SIZE : integer := 32; - C_P1_MASK_SIZE : integer := 4; - C_P1_DATA_PORT_SIZE : integer := 32 - ); - PORT ( - - sysclk_2x : in std_logic; - sysclk_2x_180 : in std_logic; - pll_ce_0 : in std_logic; - pll_ce_90 : in std_logic; - pll_lock : in std_logic; - sys_rst : in std_logic; - - p0_arb_en : in std_logic; - p0_cmd_clk : in std_logic; - p0_cmd_en : in std_logic; - p0_cmd_instr : in std_logic_vector(2 downto 0); - p0_cmd_bl : in std_logic_vector(5 downto 0); - p0_cmd_byte_addr : in std_logic_vector(29 downto 0); - p0_cmd_empty : out std_logic; - p0_cmd_full : out std_logic; - - p0_wr_clk : in std_logic; - p0_wr_en : in std_logic; - p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); - p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); - p0_wr_full : out std_logic; - p0_wr_empty : out std_logic; - p0_wr_count : out std_logic_vector(6 downto 0); - p0_wr_underrun : out std_logic; - p0_wr_error : out std_logic; - - p0_rd_clk : in std_logic; - p0_rd_en : in std_logic; - p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); - p0_rd_full : out std_logic; - p0_rd_empty : out std_logic; - p0_rd_count : out std_logic_vector(6 downto 0); - p0_rd_overflow : out std_logic; - p0_rd_error : out std_logic; - - p1_arb_en : in std_logic; - p1_cmd_clk : in std_logic; - p1_cmd_en : in std_logic; - p1_cmd_instr : in std_logic_vector(2 downto 0); - p1_cmd_bl : in std_logic_vector(5 downto 0); - p1_cmd_byte_addr : in std_logic_vector(29 downto 0); - p1_cmd_empty : out std_logic; - p1_cmd_full : out std_logic; - p1_wr_clk : in std_logic; - p1_wr_en : in std_logic; - p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); - p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); - p1_wr_full : out std_logic; - p1_wr_empty : out std_logic; - p1_wr_count : out std_logic_vector(6 downto 0); - p1_wr_underrun : out std_logic; - p1_wr_error : out std_logic; - p1_rd_clk : in std_logic; - p1_rd_en : in std_logic; - p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); - p1_rd_full : out std_logic; - p1_rd_empty : out std_logic; - p1_rd_count : out std_logic_vector(6 downto 0); - p1_rd_overflow : out std_logic; - p1_rd_error : out std_logic; - - p2_arb_en : in std_logic; - p2_cmd_clk : in std_logic; - p2_cmd_en : in std_logic; - p2_cmd_instr : in std_logic_vector(2 downto 0); - p2_cmd_bl : in std_logic_vector(5 downto 0); - p2_cmd_byte_addr : in std_logic_vector(29 downto 0); - p2_cmd_empty : out std_logic; - p2_cmd_full : out std_logic; - p2_wr_clk : in std_logic; - p2_wr_en : in std_logic; - p2_wr_mask : in std_logic_vector(3 downto 0); - p2_wr_data : in std_logic_vector(31 downto 0); - p2_wr_full : out std_logic; - p2_wr_empty : out std_logic; - p2_wr_count : out std_logic_vector(6 downto 0); - p2_wr_underrun : out std_logic; - p2_wr_error : out std_logic; - p2_rd_clk : in std_logic; - p2_rd_en : in std_logic; - p2_rd_data : out std_logic_vector(31 downto 0); - p2_rd_full : out std_logic; - p2_rd_empty : out std_logic; - p2_rd_count : out std_logic_vector(6 downto 0); - p2_rd_overflow : out std_logic; - p2_rd_error : out std_logic; - - p3_arb_en : in std_logic; - p3_cmd_clk : in std_logic; - p3_cmd_en : in std_logic; - p3_cmd_instr : in std_logic_vector(2 downto 0); - p3_cmd_bl : in std_logic_vector(5 downto 0); - p3_cmd_byte_addr : in std_logic_vector(29 downto 0); - p3_cmd_empty : out std_logic; - p3_cmd_full : out std_logic; - p3_wr_clk : in std_logic; - p3_wr_en : in std_logic; - p3_wr_mask : in std_logic_vector(3 downto 0); - p3_wr_data : in std_logic_vector(31 downto 0); - p3_wr_full : out std_logic; - p3_wr_empty : out std_logic; - p3_wr_count : out std_logic_vector(6 downto 0); - p3_wr_underrun : out std_logic; - p3_wr_error : out std_logic; - p3_rd_clk : in std_logic; - p3_rd_en : in std_logic; - p3_rd_data : out std_logic_vector(31 downto 0); - p3_rd_full : out std_logic; - p3_rd_empty : out std_logic; - p3_rd_count : out std_logic_vector(6 downto 0); - p3_rd_overflow : out std_logic; - p3_rd_error : out std_logic; - - p4_arb_en : in std_logic; - p4_cmd_clk : in std_logic; - p4_cmd_en : in std_logic; - p4_cmd_instr : in std_logic_vector(2 downto 0); - p4_cmd_bl : in std_logic_vector(5 downto 0); - p4_cmd_byte_addr : in std_logic_vector(29 downto 0); - p4_cmd_empty : out std_logic; - p4_cmd_full : out std_logic; - p4_wr_clk : in std_logic; - p4_wr_en : in std_logic; - p4_wr_mask : in std_logic_vector(3 downto 0); - p4_wr_data : in std_logic_vector(31 downto 0); - p4_wr_full : out std_logic; - p4_wr_empty : out std_logic; - p4_wr_count : out std_logic_vector(6 downto 0); - p4_wr_underrun : out std_logic; - p4_wr_error : out std_logic; - p4_rd_clk : in std_logic; - p4_rd_en : in std_logic; - p4_rd_data : out std_logic_vector(31 downto 0); - p4_rd_full : out std_logic; - p4_rd_empty : out std_logic; - p4_rd_count : out std_logic_vector(6 downto 0); - p4_rd_overflow : out std_logic; - p4_rd_error : out std_logic; - - p5_arb_en : in std_logic; - p5_cmd_clk : in std_logic; - p5_cmd_en : in std_logic; - p5_cmd_instr : in std_logic_vector(2 downto 0); - p5_cmd_bl : in std_logic_vector(5 downto 0); - p5_cmd_byte_addr : in std_logic_vector(29 downto 0); - p5_cmd_empty : out std_logic; - p5_cmd_full : out std_logic; - p5_wr_clk : in std_logic; - p5_wr_en : in std_logic; - p5_wr_mask : in std_logic_vector(3 downto 0); - p5_wr_data : in std_logic_vector(31 downto 0); - p5_wr_full : out std_logic; - p5_wr_empty : out std_logic; - p5_wr_count : out std_logic_vector(6 downto 0); - p5_wr_underrun : out std_logic; - p5_wr_error : out std_logic; - p5_rd_clk : in std_logic; - p5_rd_en : in std_logic; - p5_rd_data : out std_logic_vector(31 downto 0); - p5_rd_full : out std_logic; - p5_rd_empty : out std_logic; - p5_rd_count : out std_logic_vector(6 downto 0); - p5_rd_overflow : out std_logic; - p5_rd_error : out std_logic; - - mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0); - mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0); - mcbx_dram_ras_n : out std_logic; - mcbx_dram_cas_n : out std_logic; - mcbx_dram_we_n : out std_logic; - mcbx_dram_cke : out std_logic; - mcbx_dram_clk : out std_logic; - mcbx_dram_clk_n : out std_logic; - mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0); - mcbx_dram_dqs : INOUT std_logic; - mcbx_dram_dqs_n : INOUT std_logic; - mcbx_dram_udqs : INOUT std_logic; - mcbx_dram_udqs_n : INOUT std_logic; - mcbx_dram_udm : out std_logic; - mcbx_dram_ldm : out std_logic; - mcbx_dram_odt : out std_logic; - mcbx_dram_ddr3_rst : out std_logic; - - calib_recal : in std_logic; - rzq : INOUT std_logic; - zio : INOUT std_logic; - ui_read : in std_logic; - ui_add : in std_logic; - ui_cs : in std_logic; - ui_clk : in std_logic; - ui_sdi : in std_logic; - ui_addr : in std_logic_vector(4 downto 0); - ui_broadcast : in std_logic; - ui_drp_update : in std_logic; - ui_done_cal : in std_logic; - ui_cmd : in std_logic; - ui_cmd_in : in std_logic; - ui_cmd_en : in std_logic; - ui_dqcount : in std_logic_vector(3 downto 0); - ui_dq_lower_dec : in std_logic; - ui_dq_lower_inc : in std_logic; - ui_dq_upper_dec : in std_logic; - ui_dq_upper_inc : in std_logic; - ui_udqs_inc : in std_logic; - ui_udqs_dec : in std_logic; - ui_ldqs_inc : in std_logic; - ui_ldqs_dec : in std_logic; - uo_data : out std_logic_vector(7 downto 0); - uo_data_valid : out std_logic; - uo_done_cal : out std_logic; - uo_cmd_ready_in : out std_logic; - uo_refrsh_flag : out std_logic; - uo_cal_start : out std_logic; - uo_sdo : out std_logic; - status : out std_logic_vector(31 downto 0); - selfrefresh_enter : in std_logic; - selfrefresh_mode : out std_logic - ); -end mcb_raw_wrapper; - - architecture aarch of mcb_raw_wrapper is - -component mcb_soft_calibration_top is - generic ( - C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets - C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, - -- and does dynamic recal, - -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* - -- no dynamic recal will be done - SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration - SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration - SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration - C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented - C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design - - ); - port ( - UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock - RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for - -- IODRP (sub)controller - IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's - DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high - -- (MCB hard calib complete) - PLL_LOCK : in std_logic; -- Lock signal from PLL - SELFREFRESH_REQ : in std_logic; - SELFREFRESH_MCB_MODE : in std_logic; - SELFREFRESH_MCB_REQ : out std_logic; - SELFREFRESH_MODE : out std_logic; - MCB_UIADD : out std_logic; -- to MCB's UIADD port - MCB_UISDI : out std_logic; -- to MCB's UISDI port - MCB_UOSDO : in std_logic; - MCB_UODONECAL : in std_logic; - MCB_UOREFRSHFLAG : in std_logic; - MCB_UICS : out std_logic; - MCB_UIDRPUPDATE : out std_logic; - MCB_UIBROADCAST : out std_logic; - MCB_UIADDR : out std_logic_vector(4 downto 0); - MCB_UICMDEN : out std_logic; - MCB_UIDONECAL : out std_logic; - MCB_UIDQLOWERDEC : out std_logic; - MCB_UIDQLOWERINC : out std_logic; - MCB_UIDQUPPERDEC : out std_logic; - MCB_UIDQUPPERINC : out std_logic; - MCB_UILDQSDEC : out std_logic; - MCB_UILDQSINC : out std_logic; - MCB_UIREAD : out std_logic; - MCB_UIUDQSDEC : out std_logic; - MCB_UIUDQSINC : out std_logic; - MCB_RECAL : out std_logic; - MCB_SYSRST : out std_logic; - MCB_UICMD : out std_logic; - MCB_UICMDIN : out std_logic; - MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); - MCB_UODATA : in std_logic_vector(7 downto 0); - MCB_UODATAVALID : in std_logic; - MCB_UOCMDREADY : in std_logic; - MCB_UO_CAL_START : in std_logic; - RZQ_PIN : inout std_logic; - ZIO_PIN : inout std_logic; - CKE_Train : out std_logic - ); -end component; - -constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR"; -constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR"; -constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER"; -constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE"; -constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED"; -constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL"; - -constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0"; - -constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR"; -constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER"; -constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE"; - -constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR"; -constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER"; -constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE"; - --- MIG always set the below ADD_LATENCY to zero -constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF"; -constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0; -constant C_MEM_MOBILE_TC_SR : INTEGER := 0; - --- convert the memory timing to memory clock units. I -constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); -constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); -constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); -constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); -constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); -constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); - - function cdiv return integer is - begin - if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then - return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1; - else - return (C_MEM_TRTP/C_MEMCLK_PERIOD); - end if; - end function cdiv; - -constant MEM_RTP_VAL1 : INTEGER := cdiv; - - -function MEM_RTP_CYC1 return integer is - begin - if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then - return 4; - else if(MEM_RTP_VAL1 < 2) then - return 2; - else - return MEM_RTP_VAL1; - end if; - end if; - end function MEM_RTP_CYC1; - -constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1; - -function MEM_WTR_CYC return integer is - begin - if (C_MEM_TYPE = "DDR") then - return 2; - elsif (C_MEM_TYPE = "DDR3") then - return 4; - elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then - return C_MEM_TWTR; - elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then - return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); - elsif (C_MEM_TYPE = "DDR2")then - return 2; - else - return 3; - end if; - end function MEM_WTR_CYC; - -constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC; - -function DDR2_WRT_RECOVERY_CYC return integer is - begin - if (not(C_MEM_TYPE = "DDR2")) then - return 5; - else - return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); - end if; - end function DDR2_WRT_RECOVERY_CYC; - - -constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC; - -function DDR3_WRT_RECOVERY_CYC return integer is - begin - if (not(C_MEM_TYPE = "DDR3")) then - return 5; - else - return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD); - end if; - end function DDR3_WRT_RECOVERY_CYC; - -constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC; ----------------------------------------------------------------------------- --- signla Declarations ----------------------------------------------------------------------------- -signal addr_in0 : std_logic_vector(31 downto 0); -signal allzero : std_logic_vector(127 downto 0) := (others => '0'); -signal dqs_out_p : std_logic; -signal dqs_out_n : std_logic; -signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network -signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network -signal udqs_sys_p: std_logic; -signal udqs_sys_n: std_logic; -signal dqs_p : std_logic; -- open net now ? -signal dqs_n : std_logic; -- open net now ? - --- IOI and IOB enable/tristate interface -signal dqIO_w_en_0 : std_logic; --enable DQ pads -signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS -signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS - ---memory chip control interface -signal address_90 : std_logic_vector(14 downto 0); -signal ba_90 : std_logic_vector(2 downto 0); -signal ras_90 : std_logic; -signal cas_90 : std_logic; -signal we_90 : std_logic; -signal cke_90 : std_logic; -signal odt_90 : std_logic; -signal rst_90 : std_logic; - --- calibration IDELAY control signals -signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output -signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection -signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands -signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands -signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal -signal ioi_drp_add : std_logic; --DRP interface - serial address signal -signal ioi_drp_broadcast : std_logic; -signal ioi_drp_train : std_logic; - --- Calibration datacapture siganls -signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux -signal dq_in_p : std_logic; --positive signal sent to calibration logic -signal dq_in_n : std_logic; --negative signal sent to calibration logic -signal cal_done: std_logic; - ---DQS calibration interface -signal udqs_n : std_logic; -signal udqs_p : std_logic; -signal udqs_dqocal_p : std_logic; -signal udqs_dqocal_n : std_logic; - --- MUI enable interface -signal df_en_n90 : std_logic; - ---INTERNAL signal FOR DRP chain --- IOI <-> MUI -signal ioi_int_tmp : std_logic; - -signal dqo_n : std_logic_vector(15 downto 0); -signal dqo_p : std_logic_vector(15 downto 0); -signal dqnlm : std_logic; -signal dqplm : std_logic; -signal dqnum : std_logic; -signal dqpum : std_logic; - --- IOI <-> IOB routes -signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0); -signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0); -signal ioi_cas : std_logic; -signal ioi_ck : std_logic; -signal ioi_ckn : std_logic; -signal ioi_cke : std_logic; -signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); -signal ioi_dqs : std_logic; -signal ioi_dqsn : std_logic; -signal ioi_udqs : std_logic; -signal ioi_udqsn : std_logic; -signal ioi_odt : std_logic; -signal ioi_ras : std_logic; -signal ioi_rst : std_logic; -signal ioi_we : std_logic; -signal ioi_udm : std_logic; -signal ioi_ldm : std_logic; - -signal in_dq : std_logic_vector(15 downto 0); -signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); -signal in_dqs : std_logic; -signal in_pre_dqsp : std_logic; -signal in_pre_dqsn : std_logic; -signal in_pre_udqsp : std_logic; -signal in_pre_udqsn : std_logic; -signal in_udqs : std_logic; - --- Memory tri-state control signals -signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0); -signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0); -signal t_cas : std_logic; -signal t_ck : std_logic; -signal t_ckn : std_logic; -signal t_cke : std_logic; -signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); -signal t_dqs : std_logic; -signal t_dqsn : std_logic; -signal t_udqs : std_logic; -signal t_udqsn : std_logic; -signal t_odt : std_logic; -signal t_ras : std_logic; -signal t_rst : std_logic; -signal t_we : std_logic; - -signal t_udm : std_logic; -signal t_ldm : std_logic; - -signal idelay_dqs_ioi_s : std_logic; -signal idelay_dqs_ioi_m : std_logic; -signal idelay_udqs_ioi_s : std_logic; -signal idelay_udqs_ioi_m : std_logic; - -signal dqs_pin : std_logic; -signal udqs_pin : std_logic; - --- USER Interface signals --- translated memory addresses -signal p0_cmd_ra : std_logic_vector(14 downto 0); -signal p0_cmd_ba : std_logic_vector(2 downto 0); -signal p0_cmd_ca : std_logic_vector(11 downto 0); -signal p1_cmd_ra : std_logic_vector(14 downto 0); -signal p1_cmd_ba : std_logic_vector(2 downto 0); -signal p1_cmd_ca : std_logic_vector(11 downto 0); -signal p2_cmd_ra : std_logic_vector(14 downto 0); -signal p2_cmd_ba : std_logic_vector(2 downto 0); -signal p2_cmd_ca : std_logic_vector(11 downto 0); -signal p3_cmd_ra : std_logic_vector(14 downto 0); -signal p3_cmd_ba : std_logic_vector(2 downto 0); -signal p3_cmd_ca : std_logic_vector(11 downto 0); -signal p4_cmd_ra : std_logic_vector(14 downto 0); -signal p4_cmd_ba : std_logic_vector(2 downto 0); -signal p4_cmd_ca : std_logic_vector(11 downto 0); -signal p5_cmd_ra : std_logic_vector(14 downto 0); -signal p5_cmd_ba : std_logic_vector(2 downto 0); -signal p5_cmd_ca : std_logic_vector(11 downto 0); - - -- user command wires mapped from logical ports to physical ports -signal mig_p0_arb_en : std_logic; -signal mig_p0_cmd_clk : std_logic; -signal mig_p0_cmd_en : std_logic; -signal mig_p0_cmd_ra : std_logic_vector(14 downto 0); -signal mig_p0_cmd_ba : std_logic_vector(2 downto 0); -signal mig_p0_cmd_ca : std_logic_vector(11 downto 0); - -signal mig_p0_cmd_instr : std_logic_vector(2 downto 0); -signal mig_p0_cmd_bl : std_logic_vector(5 downto 0); -signal mig_p0_cmd_empty : std_logic; -signal mig_p0_cmd_full : std_logic; - -signal mig_p1_arb_en : std_logic; -signal mig_p1_cmd_clk : std_logic; -signal mig_p1_cmd_en : std_logic; -signal mig_p1_cmd_ra : std_logic_vector(14 downto 0); -signal mig_p1_cmd_ba : std_logic_vector(2 downto 0); -signal mig_p1_cmd_ca : std_logic_vector(11 downto 0); - -signal mig_p1_cmd_instr : std_logic_vector(2 downto 0); -signal mig_p1_cmd_bl : std_logic_vector(5 downto 0); -signal mig_p1_cmd_empty : std_logic; -signal mig_p1_cmd_full : std_logic; - -signal mig_p2_arb_en : std_logic; -signal mig_p2_cmd_clk : std_logic; -signal mig_p2_cmd_en : std_logic; -signal mig_p2_cmd_ra : std_logic_vector(14 downto 0); -signal mig_p2_cmd_ba : std_logic_vector(2 downto 0); -signal mig_p2_cmd_ca : std_logic_vector(11 downto 0); - -signal mig_p2_cmd_instr : std_logic_vector(2 downto 0); -signal mig_p2_cmd_bl : std_logic_vector(5 downto 0); -signal mig_p2_cmd_empty : std_logic; -signal mig_p2_cmd_full : std_logic; - -signal mig_p3_arb_en : std_logic; -signal mig_p3_cmd_clk : std_logic; -signal mig_p3_cmd_en : std_logic; -signal mig_p3_cmd_ra : std_logic_vector(14 downto 0); -signal mig_p3_cmd_ba : std_logic_vector(2 downto 0); -signal mig_p3_cmd_ca : std_logic_vector(11 downto 0); - -signal mig_p3_cmd_instr : std_logic_vector(2 downto 0); -signal mig_p3_cmd_bl : std_logic_vector(5 downto 0); -signal mig_p3_cmd_empty : std_logic; -signal mig_p3_cmd_full : std_logic; - -signal mig_p4_arb_en : std_logic; -signal mig_p4_cmd_clk : std_logic; -signal mig_p4_cmd_en : std_logic; -signal mig_p4_cmd_ra : std_logic_vector(14 downto 0); -signal mig_p4_cmd_ba : std_logic_vector(2 downto 0); -signal mig_p4_cmd_ca : std_logic_vector(11 downto 0); - -signal mig_p4_cmd_instr : std_logic_vector(2 downto 0); -signal mig_p4_cmd_bl : std_logic_vector(5 downto 0); -signal mig_p4_cmd_empty : std_logic; -signal mig_p4_cmd_full : std_logic; - -signal mig_p5_arb_en : std_logic; -signal mig_p5_cmd_clk : std_logic; -signal mig_p5_cmd_en : std_logic; -signal mig_p5_cmd_ra : std_logic_vector(14 downto 0); -signal mig_p5_cmd_ba : std_logic_vector(2 downto 0); -signal mig_p5_cmd_ca : std_logic_vector(11 downto 0); - -signal mig_p5_cmd_instr : std_logic_vector(2 downto 0); -signal mig_p5_cmd_bl : std_logic_vector(5 downto 0); -signal mig_p5_cmd_empty : std_logic; -signal mig_p5_cmd_full : std_logic; - -signal mig_p0_wr_clk : std_logic; -signal mig_p0_rd_clk : std_logic; -signal mig_p1_wr_clk : std_logic; -signal mig_p1_rd_clk : std_logic; -signal mig_p2_clk : std_logic; -signal mig_p3_clk : std_logic; -signal mig_p4_clk : std_logic; -signal mig_p5_clk : std_logic; - -signal mig_p0_wr_en : std_logic; -signal mig_p0_rd_en : std_logic; -signal mig_p1_wr_en : std_logic; -signal mig_p1_rd_en : std_logic; -signal mig_p2_en : std_logic; -signal mig_p3_en : std_logic; -signal mig_p4_en : std_logic; -signal mig_p5_en : std_logic; - -signal mig_p0_wr_data : std_logic_vector(31 downto 0); -signal mig_p1_wr_data : std_logic_vector(31 downto 0); -signal mig_p2_wr_data : std_logic_vector(31 downto 0); -signal mig_p3_wr_data : std_logic_vector(31 downto 0); -signal mig_p4_wr_data : std_logic_vector(31 downto 0); -signal mig_p5_wr_data : std_logic_vector(31 downto 0); - -signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); -signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); -signal mig_p2_wr_mask : std_logic_vector(3 downto 0); -signal mig_p3_wr_mask : std_logic_vector(3 downto 0); -signal mig_p4_wr_mask : std_logic_vector(3 downto 0); -signal mig_p5_wr_mask : std_logic_vector(3 downto 0); - -signal mig_p0_rd_data : std_logic_vector(31 downto 0); -signal mig_p1_rd_data : std_logic_vector(31 downto 0); -signal mig_p2_rd_data : std_logic_vector(31 downto 0); -signal mig_p3_rd_data : std_logic_vector(31 downto 0); -signal mig_p4_rd_data : std_logic_vector(31 downto 0); -signal mig_p5_rd_data : std_logic_vector(31 downto 0); - -signal mig_p0_rd_overflow : std_logic; -signal mig_p1_rd_overflow : std_logic; -signal mig_p2_overflow : std_logic; -signal mig_p3_overflow : std_logic; - -signal mig_p4_overflow : std_logic; -signal mig_p5_overflow : std_logic; - -signal mig_p0_wr_underrun : std_logic; -signal mig_p1_wr_underrun : std_logic; -signal mig_p2_underrun : std_logic; -signal mig_p3_underrun : std_logic; -signal mig_p4_underrun : std_logic; -signal mig_p5_underrun : std_logic; - -signal mig_p0_rd_error : std_logic; -signal mig_p0_wr_error : std_logic; -signal mig_p1_rd_error : std_logic; -signal mig_p1_wr_error : std_logic; -signal mig_p2_error : std_logic; -signal mig_p3_error : std_logic; -signal mig_p4_error : std_logic; -signal mig_p5_error : std_logic; - -signal mig_p0_wr_count : std_logic_vector(6 downto 0); -signal mig_p1_wr_count : std_logic_vector(6 downto 0); -signal mig_p0_rd_count : std_logic_vector(6 downto 0); -signal mig_p1_rd_count : std_logic_vector(6 downto 0); - -signal mig_p2_count : std_logic_vector(6 downto 0); -signal mig_p3_count : std_logic_vector(6 downto 0); -signal mig_p4_count : std_logic_vector(6 downto 0); -signal mig_p5_count : std_logic_vector(6 downto 0); - -signal mig_p0_wr_full : std_logic; -signal mig_p1_wr_full : std_logic; - -signal mig_p0_rd_empty : std_logic; -signal mig_p1_rd_empty : std_logic; -signal mig_p0_wr_empty : std_logic; -signal mig_p1_wr_empty : std_logic; -signal mig_p0_rd_full : std_logic; -signal mig_p1_rd_full : std_logic; -signal mig_p2_full : std_logic; -signal mig_p3_full : std_logic; -signal mig_p4_full : std_logic; -signal mig_p5_full : std_logic; -signal mig_p2_empty : std_logic; -signal mig_p3_empty : std_logic; -signal mig_p4_empty : std_logic; -signal mig_p5_empty : std_logic; - --- SELFREESH control signal for suspend feature -signal selfrefresh_mcb_enter : std_logic; -signal selfrefresh_mcb_mode : std_logic; - -signal MCB_SYSRST : std_logic; -signal ioclk0 : std_logic; -signal ioclk90 : std_logic; -signal hard_done_cal : std_logic; -signal uo_data_int : std_logic_vector(7 downto 0); -signal uo_data_valid_int : std_logic; -signal uo_cmd_ready_in_int : std_logic; -signal syn_uiclk_pll_lock : std_logic; -signal int_sys_rst : std_logic; - ---testing -signal ioi_drp_update : std_logic; -signal aux_sdi_sdo : std_logic_vector(7 downto 0); - - - signal mcb_recal : std_logic; - signal mcb_ui_read : std_logic; - signal mcb_ui_add : std_logic; - signal mcb_ui_cs : std_logic; - signal mcb_ui_clk : std_logic; - signal mcb_ui_sdi : std_logic; - signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0); - signal mcb_ui_broadcast : std_logic; - signal mcb_ui_drp_update : std_logic; - signal mcb_ui_done_cal : std_logic; - signal mcb_ui_cmd : std_logic; - signal mcb_ui_cmd_in : std_logic; - signal mcb_ui_cmd_en : std_logic; - signal mcb_ui_dqcount : std_logic_vector(3 downto 0); - signal mcb_ui_dq_lower_dec : std_logic; - signal mcb_ui_dq_lower_inc : std_logic; - signal mcb_ui_dq_upper_dec : std_logic; - signal mcb_ui_dq_upper_inc : std_logic; - signal mcb_ui_udqs_inc : std_logic; - signal mcb_ui_udqs_dec : std_logic; - signal mcb_ui_ldqs_inc : std_logic; - signal mcb_ui_ldqs_dec : std_logic; - - signal DONE_SOFTANDHARD_CAL : std_logic; - - - signal ck_shiftout0_1 : std_logic; - signal ck_shiftout0_2 : std_logic; - signal ck_shiftout1_3 : std_logic; - signal ck_shiftout1_4 : std_logic; - - signal udm_oq : std_logic; - signal udm_t : std_logic; - signal ldm_oq : std_logic; - signal ldm_t : std_logic; - signal dqsp_oq : std_logic; - signal dqsp_tq : std_logic; - signal dqs_shiftout0_1 : std_logic; - signal dqs_shiftout0_2 : std_logic; - signal dqs_shiftout1_3 : std_logic; - signal dqs_shiftout1_4 : std_logic; - - signal dqsn_oq : std_logic; - signal dqsn_tq : std_logic; - - signal udqsp_oq : std_logic; - signal udqsp_tq : std_logic; - signal udqs_shiftout0_1 : std_logic; - signal udqs_shiftout0_2 : std_logic; - signal udqs_shiftout1_3 : std_logic; - signal udqs_shiftout1_4 : std_logic; - - signal udqsn_oq : std_logic; - signal udqsn_tq : std_logic; - - signal aux_sdi_out_dqsp : std_logic; - signal aux_sdi_out_udqsp : std_logic; - signal aux_sdi_out_udqsn : std_logic; - signal aux_sdi_out_0 : std_logic; - signal aux_sdi_out_1 : std_logic; - signal aux_sdi_out_2 : std_logic; - signal aux_sdi_out_3 : std_logic; - signal aux_sdi_out_5 : std_logic; - signal aux_sdi_out_6 : std_logic; - signal aux_sdi_out_7 : std_logic; - signal aux_sdi_out_9 : std_logic; - signal aux_sdi_out_10 : std_logic; - signal aux_sdi_out_11 : std_logic; - signal aux_sdi_out_12 : std_logic; - signal aux_sdi_out_13 : std_logic; - signal aux_sdi_out_14 : std_logic; - signal aux_sdi_out_15 : std_logic; - signal aux_sdi_out_8 : std_logic; - signal aux_sdi_out_dqsn : std_logic; - signal aux_sdi_out_4 : std_logic; - signal aux_sdi_out_udm : std_logic; - signal aux_sdi_out_ldm : std_logic; - signal uo_cal_start_int : std_logic; - - signal cke_train : std_logic; - signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); - signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); - - signal p0_wr_full_i : std_logic; - signal p0_rd_empty_i : std_logic; - signal p1_wr_full_i : std_logic; - signal p1_rd_empty_i : std_logic; - signal pllclk1 : std_logic_vector(1 downto 0); - signal pllce1 : std_logic_vector(1 downto 0); - signal uo_refrsh_flag_xhdl23 : std_logic; - SIGNAL uo_sdo_xhdl24 : STD_LOGIC; - signal Max_Value_Cal_Error : std_logic; - - attribute max_fanout : string; - attribute syn_maxfan : integer; - attribute max_fanout of int_sys_rst : signal is "1"; - attribute syn_maxfan of int_sys_rst : signal is 1; - -begin - uo_cmd_ready_in <= uo_cmd_ready_in_int; - uo_data_valid <= uo_data_valid_int; - uo_data <= uo_data_int; - uo_refrsh_flag <= uo_refrsh_flag_xhdl23; - uo_sdo <= uo_sdo_xhdl24; - - p0_wr_full <= p0_wr_full_i; - p0_rd_empty <= p0_rd_empty_i; - p1_wr_full <= p1_wr_full_i; - p1_rd_empty <= p1_rd_empty_i; - ioclk0 <= sysclk_2x; - ioclk90 <= sysclk_2x_180; - pllclk1 <= (ioclk90 & ioclk0); - pllce1 <= (pll_ce_90 & pll_ce_0); - - -- Added 2/22 - Add flop to pll_lock status signal to improve timing - process (ui_clk) - begin - if (ui_clk'event and ui_clk = '1') then - syn_uiclk_pll_lock <= pll_lock; - end if; - end process; - - int_sys_rst <= sys_rst or not(syn_uiclk_pll_lock); - ---Address Remapping --- Byte Address remapping --- --- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0] --- column address remap for port 0 - -x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12 -x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column - --- port 0 address remapping - - x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate - p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate - p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - end generate; - - x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - end generate; - --- port 1 address remapping - - x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row - p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1)); - - end generate; - - - x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - - x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - - end generate; - - -- port 2 address remapping - x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row - p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - - x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - - end generate; - - --- port 3 address remapping - x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row - p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - - end generate; - - x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - - end generate; - - x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1)); - - end generate; - - - x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - - x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - end generate; - - - - - -- port 4 address remapping - - x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row - p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - - end generate; - - x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - - x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - end generate; - - - --- port 5 address remapping - x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row - p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - - x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1)); - end generate; - - - x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - end generate; - - x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - end generate; -end generate; --x16_addr_rbc - -x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate - - - -- port 0 address remapping - -x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - -x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - -x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row - p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - -x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row - p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - end generate; - -x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column - p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - -x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column - p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - end generate; - - - - - --- port 1 address remapping - x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - -x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - end generate; - -x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row - p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - -x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row - p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - end generate; - -x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column - p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - end generate; - -x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column - p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - end generate; - - - - -- port 2 address remapping -x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - end generate; - -x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - - end generate; - -x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row - p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - - end generate; - -x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row - p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - end generate; - -x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column - p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - -x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column - p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - - end generate; - - - -- port 3 address remapping -x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - - end generate; - -x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - - end generate; - -x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row - p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - - end generate; - -x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row - p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - - end generate; - -x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column - p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - -x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column - p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - - end generate; - - - -- port 4 address remapping -x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - - end generate; - -x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - - end generate; - -x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row - p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - - end generate; - -x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row - p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - end generate; - -x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column - p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - -x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column - p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - - end generate; - - -- port 5 address remapping -x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1); - - end generate; - -x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1)); - - end generate; - -x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row - p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1); - end generate; - -x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row - p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1)); - - end generate; - -x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column - p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1); - - end generate; - -x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column - p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1)); - - end generate; - end generate;--x16_addr_rbc_n -end generate; --x16_addr - - - - - - -x8_addr : if(C_NUM_DQ_PINS = 8) generate -x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate --- port 0 address remapping - -x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10 - - end generate; - - x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10 - - end generate; - - - x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - - --- port 1 address remapping - x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10 - - end generate; - - x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10 - - end generate; - - - x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - - -- port 2 address remapping - x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10 - - end generate; - - x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 *** - - end generate; - - - x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - - --- port 3 address remapping - x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10 - - end generate; - - x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10 - - end generate; - - - x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - --- port 4 address remapping - x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10 - - end generate; - - x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10 - - end generate; - - - x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - - -- port 5 address remapping - x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10 - - end generate; - - x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10 - - end generate; - - - x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - end generate; --x8_addr_rbc - - - -x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate - -- port 0 address remapping - x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - -- port 1 address remapping - x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - ---port 2 address remapping - x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - -- port 3 address remapping - x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - - --- port 4 address remapping - x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & - p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS )); - end generate; - - x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - - --- port 5 address remapping - x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)& - p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS )); - - end generate; - - x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); - - end generate; - - x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); - - end generate; - - - x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0); - - end generate; - - x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0)); - - end generate; - end generate; --x8_addr_rbc_n - end generate; --x8_addr - - - - - - - - - -x4_addr : if(C_NUM_DQ_PINS = 4) generate -x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate - --- port 0 address remapping -x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11 - - end generate; - - x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - end generate; - - --- port 1 address remapping -x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11 - - end generate; - - x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - end generate; - - --- port 2 address remapping -x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - end generate; - - - x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11 - - end generate; - - x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - end generate; - - --- port 3 address remapping -x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - end generate; - - x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - end generate; - - - x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11 - - end generate; - - x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - end generate; - - - - - - - x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32" - ) generate --- port 4 address remapping - -x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - end generate; - -x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - -x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - end generate; - -x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - end generate; - - -x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11 - - end generate; - -x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - end generate; --- port 5 address remapping - - -x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - end generate; - -x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - -x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - end generate; - -x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - end generate; - - -x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11 - - end generate; - -x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - end generate; - end generate; --x4_p4_p5 - end generate; --x4_addr_rbc - - - - -x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate - --- port 0 address remapping - x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - end generate; - - x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - end generate; - - x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - end generate; - - x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - end generate; - - - x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - end generate; - - x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - end generate; - - --- port 1 address remapping - x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - - end generate; - - - x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - - x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - --- port 2 address remapping - x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - - end generate; - - - x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - - x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - --- port 3 address remapping - x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - - end generate; - - - x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - - x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - - - x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32" - ) generate --- port 4 address remapping - - x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - - end generate; - - - x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - - x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - end generate; - - --- port 5 address remapping - - x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank - p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank - p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1)); - - end generate; - - x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row - p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1); - - - end generate; - - x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row - p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1)); - - - end generate; - - - x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column - p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - - x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column - p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); - - - end generate; - -end generate; --x4_p4_p5_n - -end generate; --x4_addr_rbc_n -end generate; --x4_addr - - - - - -- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0 -u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32" - ) generate - - --synthesis translate_off - -- PORT2 - process (p2_cmd_en,p2_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and - p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then - report "ERROR - Invalid Command for write only port 2"; - end if; - end process; - - process (p2_cmd_en,p2_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and - p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then - report "ERROR - Invalid Command for read only port 2"; - end if; - end process; - - -- PORT3 - process (p3_cmd_en,p3_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and - p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then - report "ERROR - Invalid Command for write only port 3"; - end if; - end process; - - process (p3_cmd_en,p3_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and - p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then - report "ERROR - Invalid Command for read only port 3"; - end if; - end process; - - -- PORT4 - process (p4_cmd_en,p4_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and - p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then - report "ERROR - Invalid Command for write only port 4"; - end if; - end process; - - process (p4_cmd_en,p4_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and - p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then - report "ERROR - Invalid Command for read only port 4"; - end if; - end process; - - -- PORT5 - process (p5_cmd_en,p5_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and - p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then - report "ERROR - Invalid Command for write only port 5"; - end if; - end process; - - process (p5_cmd_en,p5_cmd_instr) - begin - if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and - p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then - report "ERROR - Invalid Command for read only port 5"; - end if; - end process; - - - - - --synthesis translate_on - - - -- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up - -- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx. - -- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration.. - -- - - -- Inputs from Application CMD Port - - p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate - - mig_p0_arb_en <= p0_arb_en ; - mig_p0_cmd_clk <= p0_cmd_clk ; - mig_p0_cmd_en <= p0_cmd_en ; - mig_p0_cmd_ra <= p0_cmd_ra ; - mig_p0_cmd_ba <= p0_cmd_ba ; - mig_p0_cmd_ca <= p0_cmd_ca ; - mig_p0_cmd_instr <= p0_cmd_instr; - mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ; - p0_cmd_empty <= mig_p0_cmd_empty; - p0_cmd_full <= mig_p0_cmd_full ; - end generate; - - p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate - mig_p0_arb_en <= '0'; - mig_p0_cmd_clk <= '0'; - mig_p0_cmd_en <= '0'; - mig_p0_cmd_ra <= (others => '0'); - mig_p0_cmd_ba <= (others => '0'); - mig_p0_cmd_ca <= (others => '0'); - mig_p0_cmd_instr <= (others => '0'); - mig_p0_cmd_bl <= (others => '0'); - p0_cmd_empty <= '0'; - p0_cmd_full <= '0'; - - end generate; - - p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate - mig_p1_arb_en <= p1_arb_en ; - mig_p1_cmd_clk <= p1_cmd_clk ; - mig_p1_cmd_en <= p1_cmd_en ; - mig_p1_cmd_ra <= p1_cmd_ra ; - mig_p1_cmd_ba <= p1_cmd_ba ; - mig_p1_cmd_ca <= p1_cmd_ca ; - mig_p1_cmd_instr <= p1_cmd_instr; - mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ; - p1_cmd_empty <= mig_p1_cmd_empty; - p1_cmd_full <= mig_p1_cmd_full ; - end generate; - - p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate - - mig_p1_arb_en <= '0'; - mig_p1_cmd_clk <= '0'; - mig_p1_cmd_en <= '0'; - mig_p1_cmd_ra <= (others => '0'); - mig_p1_cmd_ba <= (others => '0'); - mig_p1_cmd_ca <= (others => '0'); - mig_p1_cmd_instr <= (others => '0'); - mig_p1_cmd_bl <= (others => '0'); - p1_cmd_empty <= '0'; - p1_cmd_full <= '0'; - end generate; - - - p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate - mig_p2_arb_en <= p2_arb_en ; - mig_p2_cmd_clk <= p2_cmd_clk ; - mig_p2_cmd_en <= p2_cmd_en ; - mig_p2_cmd_ra <= p2_cmd_ra ; - mig_p2_cmd_ba <= p2_cmd_ba ; - mig_p2_cmd_ca <= p2_cmd_ca ; - mig_p2_cmd_instr <= p2_cmd_instr; - mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ; - - p2_cmd_empty <= mig_p2_cmd_empty; - p2_cmd_full <= mig_p2_cmd_full ; - end generate; - - p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate - mig_p2_arb_en <= '0'; - mig_p2_cmd_clk <= '0'; - mig_p2_cmd_en <= '0'; - mig_p2_cmd_ra <= (others => '0'); - mig_p2_cmd_ba <= (others => '0'); - mig_p2_cmd_ca <= (others => '0'); - mig_p2_cmd_instr <= (others => '0'); - mig_p2_cmd_bl <= (others => '0'); - p2_cmd_empty <= '0'; - p2_cmd_full <= '0'; - end generate; - - p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate - - mig_p3_arb_en <= p3_arb_en ; - mig_p3_cmd_clk <= p3_cmd_clk ; - mig_p3_cmd_en <= p3_cmd_en ; - mig_p3_cmd_ra <= p3_cmd_ra ; - mig_p3_cmd_ba <= p3_cmd_ba ; - mig_p3_cmd_ca <= p3_cmd_ca ; - mig_p3_cmd_instr <= p3_cmd_instr; - mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ; - p3_cmd_empty <= mig_p3_cmd_empty; - p3_cmd_full <= mig_p3_cmd_full ; - end generate; - - p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate - mig_p3_arb_en <= '0'; - mig_p3_cmd_clk <= '0'; - mig_p3_cmd_en <= '0'; - mig_p3_cmd_ra <= (others => '0'); - mig_p3_cmd_ba <= (others => '0'); - mig_p3_cmd_ca <= (others => '0'); - mig_p3_cmd_instr <= (others => '0'); - mig_p3_cmd_bl <= (others => '0'); - p3_cmd_empty <= '0'; - p3_cmd_full <= '0'; - end generate; - - - p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate - - mig_p4_arb_en <= p4_arb_en ; - mig_p4_cmd_clk <= p4_cmd_clk ; - mig_p4_cmd_en <= p4_cmd_en ; - mig_p4_cmd_ra <= p4_cmd_ra ; - mig_p4_cmd_ba <= p4_cmd_ba ; - mig_p4_cmd_ca <= p4_cmd_ca ; - mig_p4_cmd_instr <= p4_cmd_instr; - mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ; - - p4_cmd_empty <= mig_p4_cmd_empty; - p4_cmd_full <= mig_p4_cmd_full ; -end generate; - - p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate - - mig_p4_arb_en <= '0'; - mig_p4_cmd_clk <= '0'; - mig_p4_cmd_en <= '0'; - mig_p4_cmd_ra <= (others => '0'); - mig_p4_cmd_ba <= (others => '0'); - mig_p4_cmd_ca <= (others => '0'); - mig_p4_cmd_instr <= (others => '0'); - mig_p4_cmd_bl <= (others => '0'); - p4_cmd_empty <= '0'; - p4_cmd_full <= '0'; -end generate; - - p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate - mig_p5_arb_en <= p5_arb_en ; - mig_p5_cmd_clk <= p5_cmd_clk ; - mig_p5_cmd_en <= p5_cmd_en ; - mig_p5_cmd_ra <= p5_cmd_ra ; - mig_p5_cmd_ba <= p5_cmd_ba ; - mig_p5_cmd_ca <= p5_cmd_ca ; - mig_p5_cmd_instr <= p5_cmd_instr; - mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ; - - p5_cmd_empty <= mig_p5_cmd_empty; - p5_cmd_full <= mig_p5_cmd_full ; - -end generate; - - p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate - - mig_p5_arb_en <= '0'; - mig_p5_cmd_clk <= '0'; - mig_p5_cmd_en <= '0'; - mig_p5_cmd_ra <= (others => '0'); - mig_p5_cmd_ba <= (others => '0'); - mig_p5_cmd_ca <= (others => '0'); - mig_p5_cmd_instr <= (others => '0'); - mig_p5_cmd_bl <= (others => '0'); - p5_cmd_empty <= '0'; - p5_cmd_full <= '0'; -end generate; - - - -p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate - mig_p0_wr_clk <= p0_wr_clk; - mig_p0_rd_clk <= p0_rd_clk; - mig_p0_wr_en <= p0_wr_en; - mig_p0_rd_en <= p0_rd_en; - mig_p0_wr_mask <= p0_wr_mask(3 downto 0); - mig_p0_wr_data <= p0_wr_data(31 downto 0); - p0_rd_data <= mig_p0_rd_data; - p0_rd_full <= mig_p0_rd_full; - p0_rd_empty_i <= mig_p0_rd_empty; - p0_rd_error <= mig_p0_rd_error; - p0_wr_error <= mig_p0_wr_error; - p0_rd_overflow <= mig_p0_rd_overflow; - p0_wr_underrun <= mig_p0_wr_underrun; - p0_wr_empty <= mig_p0_wr_empty; - p0_wr_full_i <= mig_p0_wr_full; - p0_wr_count <= mig_p0_wr_count; - p0_rd_count <= mig_p0_rd_count ; -end generate; -p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate - mig_p0_wr_clk <= '0'; - mig_p0_rd_clk <= '0'; - mig_p0_wr_en <= '0'; - mig_p0_rd_en <= '0'; - mig_p0_wr_mask <= (others => '0'); - mig_p0_wr_data <= (others => '0'); - p0_rd_data <= (others => '0'); - p0_rd_full <= '0'; - p0_rd_empty_i <= '0'; - p0_rd_error <= '0'; - p0_wr_error <= '0'; - p0_rd_overflow <= '0'; - p0_wr_underrun <= '0'; - p0_wr_empty <= '0'; - p0_wr_full_i <= '0'; - p0_wr_count <= (others => '0'); - p0_rd_count <= (others => '0'); -end generate; - -p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate - - mig_p1_wr_clk <= p1_wr_clk; - mig_p1_rd_clk <= p1_rd_clk; - mig_p1_wr_en <= p1_wr_en; - mig_p1_wr_mask <= p1_wr_mask(3 downto 0); - mig_p1_wr_data <= p1_wr_data(31 downto 0); - mig_p1_rd_en <= p1_rd_en; - p1_rd_data <= mig_p1_rd_data; - p1_rd_empty_i <= mig_p1_rd_empty; - p1_rd_full <= mig_p1_rd_full; - p1_rd_error <= mig_p1_rd_error; - p1_wr_error <= mig_p1_wr_error; - p1_rd_overflow <= mig_p1_rd_overflow; - p1_wr_underrun <= mig_p1_wr_underrun; - p1_wr_empty <= mig_p1_wr_empty; - p1_wr_full_i <= mig_p1_wr_full; - p1_wr_count <= mig_p1_wr_count; - p1_rd_count <= mig_p1_rd_count ; - -end generate; -p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate - - mig_p1_wr_clk <= '0'; - mig_p1_rd_clk <= '0'; - mig_p1_wr_en <= '0'; - mig_p1_wr_mask <= (others => '0'); - mig_p1_wr_data <= (others => '0'); - mig_p1_rd_en <= '0'; - p1_rd_data <= (others => '0'); - p1_rd_empty_i <= '0'; - p1_rd_full <= '0'; - p1_rd_error <= '0'; - p1_wr_error <= '0'; - p1_rd_overflow <= '0'; - p1_wr_underrun <= '0'; - p1_wr_empty <= '0'; - p1_wr_full_i <= '0'; - p1_wr_count <= (others => '0'); - p1_rd_count <= (others => '0'); -end generate; -end generate; - - - - ---whenever PORT 2 is in Write mode --- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE ---u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate - -u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32" - ) generate - -p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate - mig_p2_clk <= p2_wr_clk; - mig_p2_wr_data <= p2_wr_data(31 downto 0); - mig_p2_wr_mask <= p2_wr_mask(3 downto 0); - mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir - p2_wr_error <= mig_p2_error; - p2_wr_full <= mig_p2_full; - p2_wr_empty <= mig_p2_empty; - p2_wr_underrun <= mig_p2_underrun; - p2_wr_count <= mig_p2_count ;-- wr port - end generate; -p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate - mig_p2_clk <= '0'; - mig_p2_wr_data <= (others => '0'); - mig_p2_wr_mask <= (others => '0'); - mig_p2_en <= '0'; - p2_wr_error <= '0'; - p2_wr_full <= '0'; - p2_wr_empty <= '0'; - p2_wr_underrun <= '0'; - p2_wr_count <= (others => '0'); -end generate; - p2_rd_data <= (others => '0'); - p2_rd_overflow <= '0'; - p2_rd_error <= '0'; - p2_rd_full <= '0'; - p2_rd_empty <= '0'; - p2_rd_count <= (others => '0'); --- p2_rd_error <= '0'; - end generate; ---u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate - -u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate - - p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate - mig_p2_clk <= p2_rd_clk; - p2_rd_data <= mig_p2_rd_data; - mig_p2_en <= p2_rd_en; - p2_rd_overflow <= mig_p2_overflow; - p2_rd_error <= mig_p2_error; - p2_rd_full <= mig_p2_full; - p2_rd_empty <= mig_p2_empty; - p2_rd_count <= mig_p2_count ;-- wr port - end generate; - p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate - mig_p2_clk <= '0'; - p2_rd_data <= (others => '0'); - mig_p2_en <= '0'; - - p2_rd_overflow <= '0'; - p2_rd_error <= '0'; - p2_rd_full <= '0'; - p2_rd_empty <= '0'; - p2_rd_count <= (others => '0'); - end generate; - mig_p2_wr_data <= (others => '0'); - mig_p2_wr_mask <= (others => '0'); - p2_wr_error <= '0'; - p2_wr_full <= '0'; - p2_wr_empty <= '0'; - p2_wr_underrun <= '0'; - p2_wr_count <= (others => '0'); - - end generate; ---u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode - -u_config1_3W: if( - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode - -p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate - - mig_p3_clk <= p3_wr_clk; - mig_p3_wr_data <= p3_wr_data(31 downto 0); - mig_p3_wr_mask <= p3_wr_mask(3 downto 0); - mig_p3_en <= p3_wr_en; - p3_wr_full <= mig_p3_full; - p3_wr_empty <= mig_p3_empty; - p3_wr_underrun <= mig_p3_underrun; - p3_wr_count <= mig_p3_count ;-- wr port - p3_wr_error <= mig_p3_error; - end generate; - -p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate - mig_p3_clk <= '0'; - mig_p3_wr_data <= (others => '0'); - mig_p3_wr_mask <= (others => '0'); - mig_p3_en <= '0'; - p3_wr_full <= '0'; - p3_wr_empty <= '0'; - p3_wr_underrun <= '0'; - p3_wr_count <= (others => '0'); - p3_wr_error <= '0'; - - end generate; - p3_rd_overflow <= '0'; - p3_rd_error <= '0'; - p3_rd_full <= '0'; - p3_rd_empty <= '0'; - p3_rd_count <= (others => '0'); - p3_rd_data <= (others => '0'); - end generate; - -u_config1_3R : if( - C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate - -p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate - - mig_p3_clk <= p3_rd_clk; - p3_rd_data <= mig_p3_rd_data; - mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir - p3_rd_overflow <= mig_p3_overflow; - p3_rd_error <= mig_p3_error; - p3_rd_full <= mig_p3_full; - p3_rd_empty <= mig_p3_empty; - p3_rd_count <= mig_p3_count ;-- wr port - end generate; -p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate - mig_p3_clk <= '0'; - mig_p3_en <= '0'; - p3_rd_overflow <= '0'; - p3_rd_full <= '0'; - p3_rd_empty <= '0'; - p3_rd_count <= (others => '0'); - p3_rd_error <= '0'; - p3_rd_data <= (others => '0'); - end generate; - p3_wr_full <= '0'; - p3_wr_empty <= '0'; - p3_wr_underrun <= '0'; - p3_wr_count <= (others => '0'); - p3_wr_error <= '0'; - mig_p3_wr_data <= (others => '0'); - mig_p3_wr_mask <= (others => '0'); - end generate; - - -u_config1_4W: if( - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate - -- whenever PORT 4 is in Write mode - -p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate - mig_p4_clk <= p4_wr_clk; - mig_p4_wr_data <= p4_wr_data(31 downto 0); - mig_p4_wr_mask <= p4_wr_mask(3 downto 0); - mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir - p4_wr_full <= mig_p4_full; - p4_wr_empty <= mig_p4_empty; - p4_wr_underrun <= mig_p4_underrun; - p4_wr_count <= mig_p4_count ;-- wr port - p4_wr_error <= mig_p4_error; - end generate; - -p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate - mig_p4_clk <= '0'; - mig_p4_wr_data <= (others => '0'); - mig_p4_wr_mask <= (others => '0'); - mig_p4_en <= '0'; - p4_wr_full <= '0'; - p4_wr_empty <= '0'; - p4_wr_underrun <= '0'; - p4_wr_count <= (others => '0'); - p4_wr_error <= '0'; - end generate; - - p4_rd_overflow <= '0'; - p4_rd_error <= '0'; - p4_rd_full <= '0'; - p4_rd_empty <= '0'; - p4_rd_count <= (others => '0'); - p4_rd_data <= (others => '0'); - end generate; - -u_config1_4R : if( - C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate - -p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate - mig_p4_clk <= p4_rd_clk; - p4_rd_data <= mig_p4_rd_data; - mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir - p4_rd_overflow <= mig_p4_overflow; - p4_rd_error <= mig_p4_error; - p4_rd_full <= mig_p4_full; - p4_rd_empty <= mig_p4_empty; - p4_rd_count <= mig_p4_count ;-- wr port - end generate; -p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate - mig_p4_clk <= '0'; - p4_rd_data <= (others => '0'); - mig_p4_en <= '0'; - p4_rd_overflow <= '0'; - p4_rd_error <= '0'; - p4_rd_full <= '0'; - p4_rd_empty <= '0'; - p4_rd_count <= (others => '0'); - end generate; - p4_wr_full <= '0'; - p4_wr_empty <= '0'; - p4_wr_underrun <= '0'; - p4_wr_count <= (others => '0'); - p4_wr_error <= '0'; - mig_p4_wr_data <= (others => '0'); - mig_p4_wr_mask <= (others => '0'); - end generate; - -u_config1_5W: if( - C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate - -- whenever PORT 5 is in Write mode - - -p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate - mig_p5_clk <= p5_wr_clk; - mig_p5_wr_data <= p5_wr_data(31 downto 0); - mig_p5_wr_mask <= p5_wr_mask(3 downto 0); - mig_p5_en <= p5_wr_en; - p5_wr_full <= mig_p5_full; - p5_wr_empty <= mig_p5_empty; - p5_wr_underrun <= mig_p5_underrun; - p5_wr_count <= mig_p5_count ; - p5_wr_error <= mig_p5_error; - -end generate; -p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate - mig_p5_clk <= '0'; - mig_p5_wr_data <= (others => '0'); - mig_p5_wr_mask <= (others => '0'); - mig_p5_en <= '0'; - p5_wr_full <= '0'; - p5_wr_empty <= '0'; - p5_wr_underrun <= '0'; - p5_wr_count <= (others => '0'); - p5_wr_error <= '0'; -end generate; - p5_rd_data <= (others => '0'); - p5_rd_overflow <= '0'; - p5_rd_error <= '0'; - p5_rd_full <= '0'; - p5_rd_empty <= '0'; - p5_rd_count <= (others => '0'); -end generate; - - - -u_config1_5R :if( - C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or - C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate - -p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate - mig_p5_clk <= p5_rd_clk; - p5_rd_data <= mig_p5_rd_data; - mig_p5_en <= p5_rd_en; - p5_rd_overflow <= mig_p5_overflow; - p5_rd_error <= mig_p5_error; - p5_rd_full <= mig_p5_full; - p5_rd_empty <= mig_p5_empty; - p5_rd_count <= mig_p5_count ; - -end generate; - -p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate - - mig_p5_clk <= '0'; - p5_rd_data <= (others => '0'); - mig_p5_en <= '0'; - p5_rd_overflow <= '0'; - p5_rd_error <= '0'; - p5_rd_full <= '0'; - p5_rd_empty <= '0'; - p5_rd_count <= (others => '0'); - -end generate; - p5_wr_full <= '0'; - p5_wr_empty <= '0'; - p5_wr_underrun <= '0'; - p5_wr_count <= (others => '0'); - p5_wr_error <= '0'; - mig_p5_wr_data <= (others => '0'); - mig_p5_wr_mask <= (others => '0'); - -end generate; - - --////////////////////////////////////////////////////////////////////////// - --/////////////////////////////////////////////////////////////////////////// - ---- - ---- B32_B32_B32_B32 - ---- - --/////////////////////////////////////////////////////////////////////////// - --////////////////////////////////////////////////////////////////////////// - -u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate - - - -- Inputs from Application CMD Port - -- ************* need to hook up rd /wr error outputs - -p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate - -- command port signals - mig_p0_arb_en <= p0_arb_en ; - mig_p0_cmd_clk <= p0_cmd_clk ; - mig_p0_cmd_en <= p0_cmd_en ; - mig_p0_cmd_ra <= p0_cmd_ra ; - mig_p0_cmd_ba <= p0_cmd_ba ; - mig_p0_cmd_ca <= p0_cmd_ca ; - mig_p0_cmd_instr <= p0_cmd_instr; - mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ; - -- Data port signals - mig_p0_rd_en <= p0_rd_en; - mig_p0_wr_clk <= p0_wr_clk; - mig_p0_rd_clk <= p0_rd_clk; - mig_p0_wr_en <= p0_wr_en; - mig_p0_wr_data <= p0_wr_data(31 downto 0); - mig_p0_wr_mask <= p0_wr_mask(3 downto 0); - p0_wr_count <= mig_p0_wr_count; - p0_rd_count <= mig_p0_rd_count ; -end generate; - -p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate - - mig_p0_arb_en <= '0'; - mig_p0_cmd_clk <= '0'; - mig_p0_cmd_en <= '0'; - mig_p0_cmd_ra <= (others => '0'); - mig_p0_cmd_ba <= (others => '0'); - mig_p0_cmd_ca <= (others => '0'); - mig_p0_cmd_instr <= (others => '0'); - mig_p0_cmd_bl <= (others => '0'); - - mig_p0_rd_en <= '0'; - mig_p0_wr_clk <= '0'; - mig_p0_rd_clk <= '0'; - mig_p0_wr_en <= '0'; - mig_p0_wr_data <= (others => '0'); - mig_p0_wr_mask <= (others => '0'); - p0_wr_count <= (others => '0'); - p0_rd_count <= (others => '0'); - - -end generate; - - - -p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate - -- command port signals - - mig_p1_arb_en <= p1_arb_en ; - mig_p1_cmd_clk <= p1_cmd_clk ; - mig_p1_cmd_en <= p1_cmd_en ; - mig_p1_cmd_ra <= p1_cmd_ra ; - mig_p1_cmd_ba <= p1_cmd_ba ; - mig_p1_cmd_ca <= p1_cmd_ca ; - mig_p1_cmd_instr <= p1_cmd_instr; - mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ; - - -- Data port signals - - mig_p1_wr_en <= p1_wr_en; - mig_p1_wr_clk <= p1_wr_clk; - mig_p1_rd_en <= p1_rd_en; - mig_p1_wr_data <= p1_wr_data(31 downto 0); - mig_p1_wr_mask <= p1_wr_mask(3 downto 0); - mig_p1_rd_clk <= p1_rd_clk; - p1_wr_count <= mig_p1_wr_count; - p1_rd_count <= mig_p1_rd_count; - -end generate; -p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate - - mig_p1_arb_en <= '0'; - mig_p1_cmd_clk <= '0'; - mig_p1_cmd_en <= '0'; - mig_p1_cmd_ra <= (others => '0'); - mig_p1_cmd_ba <= (others => '0'); - mig_p1_cmd_ca <= (others => '0'); - mig_p1_cmd_instr <= (others => '0'); - mig_p1_cmd_bl <= (others => '0'); - -- Data port signals - mig_p1_wr_en <= '0'; - mig_p1_wr_clk <= '0'; - mig_p1_rd_en <= '0'; - mig_p1_wr_data <= (others => '0'); - mig_p1_wr_mask <= (others => '0'); - mig_p1_rd_clk <= '0'; - p1_wr_count <= (others => '0'); - p1_rd_count <= (others => '0'); - -end generate; - - - -p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate - --MCB Physical port Logical Port - mig_p2_arb_en <= p2_arb_en ; - mig_p2_cmd_clk <= p2_cmd_clk ; - mig_p2_cmd_en <= p2_cmd_en ; - mig_p2_cmd_ra <= p2_cmd_ra ; - mig_p2_cmd_ba <= p2_cmd_ba ; - mig_p2_cmd_ca <= p2_cmd_ca ; - mig_p2_cmd_instr <= p2_cmd_instr; - mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ; - - mig_p2_en <= p2_rd_en; - mig_p2_clk <= p2_rd_clk; - mig_p3_en <= p2_wr_en; - mig_p3_clk <= p2_wr_clk; - mig_p3_wr_data <= p2_wr_data(31 downto 0); - mig_p3_wr_mask <= p2_wr_mask(3 downto 0); - p2_wr_count <= mig_p3_count; - p2_rd_count <= mig_p2_count; -end generate; -p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate - - mig_p2_arb_en <= '0'; - mig_p2_cmd_clk <= '0'; - mig_p2_cmd_en <= '0'; - mig_p2_cmd_ra <= (others => '0'); - mig_p2_cmd_ba <= (others => '0'); - mig_p2_cmd_ca <= (others => '0'); - mig_p2_cmd_instr <= (others => '0'); - mig_p2_cmd_bl <= (others => '0'); - - mig_p2_en <= '0'; - mig_p2_clk <= '0'; - mig_p3_en <= '0'; - mig_p3_clk <= '0'; - mig_p3_wr_data <= (others => '0'); - mig_p3_wr_mask <= (others => '0'); - p2_rd_count <= (others => '0'); - p2_wr_count <= (others => '0'); - -end generate; - - -p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate - --MCB Physical port Logical Port - mig_p4_arb_en <= p3_arb_en ; - mig_p4_cmd_clk <= p3_cmd_clk ; - mig_p4_cmd_en <= p3_cmd_en ; - mig_p4_cmd_ra <= p3_cmd_ra ; - mig_p4_cmd_ba <= p3_cmd_ba ; - mig_p4_cmd_ca <= p3_cmd_ca ; - mig_p4_cmd_instr <= p3_cmd_instr; - mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ; - - mig_p4_clk <= p3_rd_clk; - mig_p4_en <= p3_rd_en; - mig_p5_clk <= p3_wr_clk; - mig_p5_en <= p3_wr_en; - mig_p5_wr_data <= p3_wr_data(31 downto 0); - mig_p5_wr_mask <= p3_wr_mask(3 downto 0); - p3_rd_count <= mig_p4_count; - p3_wr_count <= mig_p5_count; -end generate; - -p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate - mig_p4_arb_en <= '0'; - mig_p4_cmd_clk <= '0'; - mig_p4_cmd_en <= '0'; - mig_p4_cmd_ra <= (others => '0'); - mig_p4_cmd_ba <= (others => '0'); - mig_p4_cmd_ca <= (others => '0'); - mig_p4_cmd_instr <= (others => '0'); - mig_p4_cmd_bl <= (others => '0'); - - mig_p4_clk <= '0'; - mig_p4_en <= '0'; - mig_p5_clk <= '0'; - mig_p5_en <= '0'; - mig_p5_wr_data <= (others => '0'); - mig_p5_wr_mask <= (others => '0'); - p3_rd_count <= (others => '0'); - p3_wr_count <= (others => '0'); -end generate; - - p0_cmd_empty <= mig_p0_cmd_empty ; - p0_cmd_full <= mig_p0_cmd_full ; - p1_cmd_empty <= mig_p1_cmd_empty ; - p1_cmd_full <= mig_p1_cmd_full ; - p2_cmd_empty <= mig_p2_cmd_empty ; - p2_cmd_full <= mig_p2_cmd_full ; - p3_cmd_empty <= mig_p4_cmd_empty ; - p3_cmd_full <= mig_p4_cmd_full ; - - - -- outputs to Applications User Port - p0_rd_data <= mig_p0_rd_data; - p1_rd_data <= mig_p1_rd_data; - p2_rd_data <= mig_p2_rd_data; - p3_rd_data <= mig_p4_rd_data; - - p0_rd_empty_i <= mig_p0_rd_empty; - p1_rd_empty_i <= mig_p1_rd_empty; - p2_rd_empty <= mig_p2_empty; - p3_rd_empty <= mig_p4_empty; - - p0_rd_full <= mig_p0_rd_full; - p1_rd_full <= mig_p1_rd_full; - p2_rd_full <= mig_p2_full; - p3_rd_full <= mig_p4_full; - - p0_rd_error <= mig_p0_rd_error; - p1_rd_error <= mig_p1_rd_error; - p2_rd_error <= mig_p2_error; - p3_rd_error <= mig_p4_error; - - p0_rd_overflow <= mig_p0_rd_overflow; - p1_rd_overflow <= mig_p1_rd_overflow; - p2_rd_overflow <= mig_p2_overflow; - p3_rd_overflow <= mig_p4_overflow; - - p0_wr_underrun <= mig_p0_wr_underrun; - p1_wr_underrun <= mig_p1_wr_underrun; - p2_wr_underrun <= mig_p3_underrun; - p3_wr_underrun <= mig_p5_underrun; - - p0_wr_empty <= mig_p0_wr_empty; - p1_wr_empty <= mig_p1_wr_empty; - p2_wr_empty <= mig_p3_empty; - p3_wr_empty <= mig_p5_empty; - - p0_wr_full_i <= mig_p0_wr_full; - p1_wr_full_i <= mig_p1_wr_full; - p2_wr_full <= mig_p3_full; - p3_wr_full <= mig_p5_full; - - p0_wr_error <= mig_p0_wr_error; - p1_wr_error <= mig_p1_wr_error; - p2_wr_error <= mig_p3_error; - p3_wr_error <= mig_p5_error; - - -- unused ports signals - p4_cmd_empty <= '0'; - p4_cmd_full <= '0'; - mig_p2_wr_mask <= (others => '0'); - mig_p4_wr_mask <= (others => '0'); - - mig_p2_wr_data <= (others => '0'); - mig_p4_wr_data <= (others => '0'); - - - p5_cmd_empty <= '0'; - p5_cmd_full <= '0'; - - - mig_p3_cmd_clk <= '0'; - mig_p3_cmd_en <= '0'; - mig_p3_cmd_ra <= (others => '0'); - mig_p3_cmd_ba <= (others => '0'); - mig_p3_cmd_ca <= (others => '0'); - mig_p3_cmd_instr <= (others => '0'); - mig_p3_cmd_bl <= (others => '0'); - mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config - - - - - mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config - mig_p5_cmd_clk <= '0'; - mig_p5_cmd_en <= '0'; - mig_p5_cmd_ra <= (others => '0'); - mig_p5_cmd_ba <= (others => '0'); - mig_p5_cmd_ca <= (others => '0'); - mig_p5_cmd_instr <= (others => '0'); - mig_p5_cmd_bl <= (others => '0'); - -end generate; --- --- --- --////////////////////////////////////////////////////////////////////////// --- --/////////////////////////////////////////////////////////////////////////// --- ---- --- ---- B64_B32_B32 --- ---- --- --/////////////////////////////////////////////////////////////////////////// --- --////////////////////////////////////////////////////////////////////////// --- --- --- -u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate - - -- Inputs from Application CMD Port - - -p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate - mig_p0_arb_en <= p0_arb_en ; - mig_p0_cmd_clk <= p0_cmd_clk ; - mig_p0_cmd_en <= p0_cmd_en ; - mig_p0_cmd_ra <= p0_cmd_ra ; - mig_p0_cmd_ba <= p0_cmd_ba ; - mig_p0_cmd_ca <= p0_cmd_ca ; - mig_p0_cmd_instr <= p0_cmd_instr; - mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ; - p0_cmd_empty <= mig_p0_cmd_empty ; - p0_cmd_full <= mig_p0_cmd_full ; - - mig_p0_wr_clk <= p0_wr_clk; - mig_p0_rd_clk <= p0_rd_clk; - mig_p1_wr_clk <= p0_wr_clk; - mig_p1_rd_clk <= p0_rd_clk; - - mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i; - mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i; - mig_p0_wr_data <= p0_wr_data(31 downto 0); - mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0); - mig_p1_wr_data <= p0_wr_data(63 downto 32); - mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4); - - p0_rd_empty_i <= mig_p1_rd_empty; - p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data); - mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i; - mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i; - - - p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output - p0_rd_count <= mig_p1_rd_count; - p0_wr_empty <= mig_p1_wr_empty; - p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error; - p0_wr_full_i <= mig_p1_wr_full; - p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun; - p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow; - p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error; - p0_rd_full <= mig_p1_rd_full; - -end generate; -p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate - - mig_p0_arb_en <= '0'; - mig_p0_cmd_clk <= '0'; - mig_p0_cmd_en <= '0'; - mig_p0_cmd_ra <= (others => '0'); - mig_p0_cmd_ba <= (others => '0'); - mig_p0_cmd_ca <= (others => '0'); - mig_p0_cmd_instr <= (others => '0'); - mig_p0_cmd_bl <= (others => '0'); - p0_cmd_empty <= '0'; - p0_cmd_full <= '0'; - - - mig_p0_wr_clk <= '0'; - mig_p0_rd_clk <= '0'; - mig_p1_wr_clk <= '0'; - mig_p1_rd_clk <= '0'; - - mig_p0_wr_en <= '0'; - mig_p1_wr_en <= '0'; - mig_p0_wr_data <= (others => '0'); - mig_p0_wr_mask <= (others => '0'); - mig_p1_wr_data <= (others => '0'); - mig_p1_wr_mask <= (others => '0'); - - p0_rd_empty_i <= '0'; - p0_rd_data <= (others => '0'); - mig_p0_rd_en <= '0'; - mig_p1_rd_en <= '0'; - - - p0_wr_count <= (others => '0'); - p0_rd_count <= (others => '0'); - p0_wr_empty <= '0'; - p0_wr_error <= '0'; - p0_wr_full_i <= '0'; - p0_wr_underrun <= '0'; - p0_rd_overflow <= '0'; - p0_rd_error <= '0'; - p0_rd_full <= '0'; -end generate; - - - - -p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate - - mig_p2_arb_en <= p1_arb_en ; - mig_p2_cmd_clk <= p1_cmd_clk ; - mig_p2_cmd_en <= p1_cmd_en ; - mig_p2_cmd_ra <= p1_cmd_ra ; - mig_p2_cmd_ba <= p1_cmd_ba ; - mig_p2_cmd_ca <= p1_cmd_ca ; - mig_p2_cmd_instr <= p1_cmd_instr; - mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ; - - p1_cmd_empty <= mig_p2_cmd_empty; - p1_cmd_full <= mig_p2_cmd_full; - - mig_p2_clk <= p1_rd_clk; - mig_p3_clk <= p1_wr_clk; - - mig_p3_en <= p1_wr_en; - mig_p3_wr_data <= p1_wr_data(31 downto 0); - mig_p3_wr_mask <= p1_wr_mask(3 downto 0); - mig_p2_en <= p1_rd_en; - - p1_rd_data <= mig_p2_rd_data; - p1_wr_count <= mig_p3_count; - p1_rd_count <= mig_p2_count; - p1_wr_empty <= mig_p3_empty; - p1_wr_error <= mig_p3_error; - p1_wr_full_i <= mig_p3_full; - p1_wr_underrun <= mig_p3_underrun; - p1_rd_overflow <= mig_p2_overflow; - p1_rd_error <= mig_p2_error; - p1_rd_full <= mig_p2_full; - p1_rd_empty_i <= mig_p2_empty; - end generate; - -p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate - - mig_p2_arb_en <= '0'; - mig_p2_cmd_clk <= '0'; - mig_p2_cmd_en <= '0'; - mig_p2_cmd_ra <= (others => '0'); - mig_p2_cmd_ba <= (others => '0'); - mig_p2_cmd_ca <= (others => '0'); - mig_p2_cmd_instr <= (others => '0'); - mig_p2_cmd_bl <= (others => '0'); - p1_cmd_empty <= '0'; - p1_cmd_full <= '0'; - mig_p3_en <= '0'; - mig_p3_wr_data <= (others => '0'); - mig_p3_wr_mask <= (others => '0'); - mig_p2_en <= '0'; - - mig_p2_clk <= '0'; - mig_p3_clk <= '0'; - - p1_rd_data <= (others => '0'); - p1_wr_count <= (others => '0'); - p1_rd_count <= (others => '0'); - p1_wr_empty <= '0'; - p1_wr_error <= '0'; - p1_wr_full_i <= '0'; - p1_wr_underrun <= '0'; - p1_rd_overflow <= '0'; - p1_rd_error <= '0'; - p1_rd_full <= '0'; - p1_rd_empty_i <= '0'; - -end generate; - -p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate - mig_p4_arb_en <= p2_arb_en ; - mig_p4_cmd_clk <= p2_cmd_clk ; - mig_p4_cmd_en <= p2_cmd_en ; - mig_p4_cmd_ra <= p2_cmd_ra ; - mig_p4_cmd_ba <= p2_cmd_ba ; - mig_p4_cmd_ca <= p2_cmd_ca ; - mig_p4_cmd_instr <= p2_cmd_instr; - mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ; - - p2_cmd_empty <= mig_p4_cmd_empty ; - p2_cmd_full <= mig_p4_cmd_full ; - mig_p5_en <= p2_wr_en; - mig_p5_wr_data <= p2_wr_data(31 downto 0); - mig_p5_wr_mask <= p2_wr_mask(3 downto 0); - mig_p4_en <= p2_rd_en; - - mig_p4_clk <= p2_rd_clk; - mig_p5_clk <= p2_wr_clk; - - p2_rd_data <= mig_p4_rd_data; - p2_wr_count <= mig_p5_count; - p2_rd_count <= mig_p4_count; - p2_wr_empty <= mig_p5_empty; - p2_wr_full <= mig_p5_full; - p2_wr_error <= mig_p5_error; - p2_wr_underrun <= mig_p5_underrun; - p2_rd_overflow <= mig_p4_overflow; - p2_rd_error <= mig_p4_error; - p2_rd_full <= mig_p4_full; - p2_rd_empty <= mig_p4_empty; - -end generate; - -p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate - - mig_p4_arb_en <= '0'; - mig_p4_cmd_clk <= '0'; - mig_p4_cmd_en <= '0'; - mig_p4_cmd_ra <= (others => '0'); - mig_p4_cmd_ba <= (others => '0'); - mig_p4_cmd_ca <= (others => '0'); - mig_p4_cmd_instr <= (others => '0'); - mig_p4_cmd_bl <= (others => '0'); - p2_cmd_empty <= '0'; - p2_cmd_full <= '0'; - mig_p5_en <= '0'; - mig_p5_wr_data <= (others => '0'); - mig_p5_wr_mask <= (others => '0'); - mig_p4_en <= '0'; - - mig_p4_clk <= '0'; - mig_p5_clk <= '0'; - - p2_rd_data <= (others => '0'); - p2_wr_count <= (others => '0'); - p2_rd_count <= (others => '0'); - p2_wr_empty <= '0'; - p2_wr_full <= '0'; - p2_wr_error <= '0'; - p2_wr_underrun <= '0'; - p2_rd_overflow <= '0'; - p2_rd_error <= '0'; - p2_rd_full <= '0'; - p2_rd_empty <= '0'; - -end generate; - - -- MCB's port 1,3,5 is not used in this Config mode - mig_p1_arb_en <= '0'; - mig_p1_cmd_clk <= '0'; - mig_p1_cmd_en <= '0'; - mig_p1_cmd_ra <= (others => '0'); - mig_p1_cmd_ba <= (others => '0'); - mig_p1_cmd_ca <= (others => '0'); - - mig_p1_cmd_instr <= (others => '0'); - mig_p1_cmd_bl <= (others => '0'); - - mig_p3_arb_en <= '0'; - mig_p3_cmd_clk <= '0'; - mig_p3_cmd_en <= '0'; - mig_p3_cmd_ra <= (others => '0'); - mig_p3_cmd_ba <= (others => '0'); - mig_p3_cmd_ca <= (others => '0'); - - mig_p3_cmd_instr <= (others => '0'); - mig_p3_cmd_bl <= (others => '0'); - - mig_p5_arb_en <= '0'; - mig_p5_cmd_clk <= '0'; - mig_p5_cmd_en <= '0'; - mig_p5_cmd_ra <= (others => '0'); - mig_p5_cmd_ba <= (others => '0'); - mig_p5_cmd_ca <= (others => '0'); - - mig_p5_cmd_instr <= (others => '0'); - mig_p5_cmd_bl <= (others => '0'); - -end generate; - -u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate - - -- Inputs from Application CMD Port - -p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate - - mig_p0_arb_en <= p0_arb_en ; - mig_p1_arb_en <= p0_arb_en ; - - mig_p0_cmd_clk <= p0_cmd_clk ; - mig_p0_cmd_en <= p0_cmd_en ; - mig_p0_cmd_ra <= p0_cmd_ra ; - mig_p0_cmd_ba <= p0_cmd_ba ; - mig_p0_cmd_ca <= p0_cmd_ca ; - mig_p0_cmd_instr <= p0_cmd_instr; - mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ; - - mig_p0_wr_clk <= p0_wr_clk; - mig_p0_rd_clk <= p0_rd_clk; - mig_p1_wr_clk <= p0_wr_clk; - mig_p1_rd_clk <= p0_rd_clk; - mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i; - mig_p0_wr_data <= p0_wr_data(31 downto 0); - mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0); - mig_p1_wr_data <= p0_wr_data(63 downto 32); - mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4); - mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i; - mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i; - mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i; - p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data); - - p0_cmd_empty <= mig_p0_cmd_empty ; - p0_cmd_full <= mig_p0_cmd_full ; - p0_wr_empty <= mig_p1_wr_empty; - p0_wr_full_i <= mig_p1_wr_full; - p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error; - p0_wr_count <= mig_p1_wr_count; - p0_rd_count <= mig_p1_rd_count; - p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun; - p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow; - p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error; - p0_rd_full <= mig_p1_rd_full; - p0_rd_empty_i <= mig_p1_rd_empty; -end generate; - -p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate - mig_p0_arb_en <= '0'; - mig_p0_cmd_clk <= '0'; - mig_p0_cmd_en <= '0'; - mig_p0_cmd_ra <= (others => '0'); - mig_p0_cmd_ba <= (others => '0'); - mig_p0_cmd_ca <= (others => '0'); - mig_p0_cmd_instr <= (others => '0'); - mig_p0_cmd_bl <= (others => '0'); - - mig_p0_wr_clk <= '0'; - mig_p0_rd_clk <= '0'; - mig_p1_wr_clk <= '0'; - mig_p1_rd_clk <= '0'; - mig_p0_wr_en <= '0'; - mig_p1_wr_en <= '0'; - mig_p0_wr_data <= (others => '0'); - mig_p0_wr_mask <= (others => '0'); - mig_p1_wr_data <= (others => '0'); - mig_p1_wr_mask <= (others => '0'); - -- mig_p1_wr_en <= (others => '0'); - mig_p0_rd_en <= '0'; - mig_p1_rd_en <= '0'; - p0_rd_data <= (others => '0'); - - - p0_cmd_empty <= '0'; - p0_cmd_full <= '0'; - p0_wr_empty <= '0'; - p0_wr_full_i <= '0'; - p0_wr_error <= '0'; - p0_wr_count <= (others => '0'); - p0_rd_count <= (others => '0'); - p0_wr_underrun <= '0'; - p0_rd_overflow <= '0'; - p0_rd_error <= '0'; - p0_rd_full <= '0'; - p0_rd_empty_i <= '0'; - - -end generate; - - -p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate - - mig_p2_arb_en <= p1_arb_en ; - - mig_p2_cmd_clk <= p1_cmd_clk ; - mig_p2_cmd_en <= p1_cmd_en ; - mig_p2_cmd_ra <= p1_cmd_ra ; - mig_p2_cmd_ba <= p1_cmd_ba ; - mig_p2_cmd_ca <= p1_cmd_ca ; - mig_p2_cmd_instr <= p1_cmd_instr; - mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ; - - - mig_p2_clk <= p1_rd_clk; - mig_p3_clk <= p1_wr_clk; - mig_p4_clk <= p1_rd_clk; - mig_p5_clk <= p1_wr_clk; - mig_p3_en <= p1_wr_en and not p1_wr_full_i; - mig_p5_en <= p1_wr_en and not p1_wr_full_i; - mig_p3_wr_data <= p1_wr_data(31 downto 0); - mig_p3_wr_mask <= p1_wr_mask(3 downto 0); - mig_p5_wr_data <= p1_wr_data(63 downto 32); - mig_p5_wr_mask <= p1_wr_mask(3 downto 0); - mig_p2_en <= p1_rd_en and not p1_rd_empty_i; - mig_p4_en <= p1_rd_en and not p1_rd_empty_i; - - p1_cmd_empty <= mig_p2_cmd_empty ; - p1_cmd_full <= mig_p2_cmd_full ; - - p1_wr_count <= mig_p5_count; - p1_rd_count <= mig_p4_count; - p1_wr_full_i <= mig_p5_full; - p1_wr_error <= mig_p5_error or mig_p5_error; - p1_wr_empty <= mig_p5_empty; - p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun; - p1_rd_overflow <= mig_p4_overflow; - p1_rd_error <= mig_p4_error; - p1_rd_full <= mig_p4_full; - p1_rd_empty_i <= mig_p4_empty; - - p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data); - -end generate; -p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate - - mig_p2_arb_en <= '0'; - -- mig_p3_arb_en <= (others => '0'); - -- mig_p4_arb_en <= (others => '0'); - -- mig_p5_arb_en <= (others => '0'); - - mig_p2_cmd_clk <= '0'; - mig_p2_cmd_en <= '0'; - mig_p2_cmd_ra <= (others => '0'); - mig_p2_cmd_ba <= (others => '0'); - mig_p2_cmd_ca <= (others => '0'); - mig_p2_cmd_instr <= (others => '0'); - mig_p2_cmd_bl <= (others => '0'); - mig_p2_clk <= '0'; - mig_p3_clk <= '0'; - mig_p4_clk <= '0'; - mig_p5_clk <= '0'; - mig_p3_en <= '0'; - mig_p5_en <= '0'; - mig_p3_wr_data <= (others => '0'); - mig_p3_wr_mask <= (others => '0'); - mig_p5_wr_data <= (others => '0'); - mig_p5_wr_mask <= (others => '0'); - mig_p2_en <= '0'; - mig_p4_en <= '0'; - p1_cmd_empty <= '0'; - p1_cmd_full <= '0'; - - p1_wr_count <= (others => '0'); - p1_rd_count <= (others => '0'); - p1_wr_full_i <= '0'; - p1_wr_error <= '0'; - p1_wr_empty <= '0'; - p1_wr_underrun <= '0'; - p1_rd_overflow <= '0'; - p1_rd_error <= '0'; - p1_rd_full <= '0'; - p1_rd_empty_i <= '0'; - p1_rd_data <= (others => '0'); - -end generate; - - -- unused MCB's signals in this configuration - mig_p3_arb_en <= '0'; - mig_p4_arb_en <= '0'; - mig_p5_arb_en <= '0'; - - mig_p3_cmd_clk <= '0'; - mig_p3_cmd_en <= '0'; - mig_p3_cmd_ra <= (others => '0'); - mig_p3_cmd_ba <= (others => '0'); - mig_p3_cmd_ca <= (others => '0'); - mig_p3_cmd_instr <= (others => '0'); - - mig_p4_cmd_clk <= '0'; - mig_p4_cmd_en <= '0'; - mig_p4_cmd_ra <= (others => '0'); - mig_p4_cmd_ba <= (others => '0'); - mig_p4_cmd_ca <= (others => '0'); - mig_p4_cmd_instr <= (others => '0'); - mig_p4_cmd_bl <= (others => '0'); - - mig_p5_cmd_clk <= '0'; - mig_p5_cmd_en <= '0'; - mig_p5_cmd_ra <= (others => '0'); - mig_p5_cmd_ba <= (others => '0'); - mig_p5_cmd_ca <= (others => '0'); - mig_p5_cmd_instr <= (others => '0'); - mig_p5_cmd_bl <= (others => '0'); - - end generate; - - ---*******************************BEGIN OF CONFIG 5 SIGNALS ******************************** - -u_config_5: if(C_PORT_CONFIG = "B128" ) generate - - - -- Inputs from Application CMD Port - - mig_p0_arb_en <= p0_arb_en ; - mig_p0_cmd_clk <= p0_cmd_clk ; - mig_p0_cmd_en <= p0_cmd_en ; - mig_p0_cmd_ra <= p0_cmd_ra ; - mig_p0_cmd_ba <= p0_cmd_ba ; - mig_p0_cmd_ca <= p0_cmd_ca ; - mig_p0_cmd_instr <= p0_cmd_instr; - mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ; - p0_cmd_empty <= mig_p0_cmd_empty ; - p0_cmd_full <= mig_p0_cmd_full ; - - - - -- Inputs from Application User Port - - mig_p0_wr_clk <= p0_wr_clk; - mig_p0_rd_clk <= p0_rd_clk; - mig_p1_wr_clk <= p0_wr_clk; - mig_p1_rd_clk <= p0_rd_clk; - - mig_p2_clk <= p0_rd_clk; - mig_p3_clk <= p0_wr_clk; - mig_p4_clk <= p0_rd_clk; - mig_p5_clk <= p0_wr_clk; - - - - mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i; - mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i; - mig_p3_en <= p0_wr_en and not p0_wr_full_i; - mig_p5_en <= p0_wr_en and not p0_wr_full_i; - - - - mig_p0_wr_data <= p0_wr_data(31 downto 0); - mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0); - mig_p1_wr_data <= p0_wr_data(63 downto 32); - mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4); - mig_p3_wr_data <= p0_wr_data(95 downto 64); - mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8); - mig_p5_wr_data <= p0_wr_data(127 downto 96); - mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12); - - mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i; - mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i; - mig_p2_en <= p0_rd_en and not p0_rd_empty_i; - mig_p4_en <= p0_rd_en and not p0_rd_empty_i; - - -- outputs to Applications User Port - p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data); - p0_rd_empty_i <= mig_p4_empty; - p0_rd_full <= mig_p4_full; - p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error; - p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow; - - p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun; - p0_wr_empty <= mig_p5_empty; - p0_wr_full_i <= mig_p5_full; - p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error; - - p0_wr_count <= mig_p5_count; - p0_rd_count <= mig_p4_count; - - - -- unused MCB's siganls in this configuration - - mig_p1_arb_en <= '0'; - mig_p1_cmd_clk <= '0'; - mig_p1_cmd_en <= '0'; - mig_p1_cmd_ra <= (others => '0'); - mig_p1_cmd_ba <= (others => '0'); - mig_p1_cmd_ca <= (others => '0'); - - mig_p1_cmd_instr <= (others => '0'); - mig_p1_cmd_bl <= (others => '0'); - - mig_p2_arb_en <= '0'; - mig_p2_cmd_clk <= '0'; - mig_p2_cmd_en <= '0'; - mig_p2_cmd_ra <= (others => '0'); - mig_p2_cmd_ba <= (others => '0'); - mig_p2_cmd_ca <= (others => '0'); - - mig_p2_cmd_instr <= (others => '0'); - mig_p2_cmd_bl <= (others => '0'); - - mig_p3_arb_en <= '0'; - mig_p3_cmd_clk <= '0'; - mig_p3_cmd_en <= '0'; - mig_p3_cmd_ra <= (others => '0'); - mig_p3_cmd_ba <= (others => '0'); - mig_p3_cmd_ca <= (others => '0'); - - mig_p3_cmd_instr <= (others => '0'); - mig_p3_cmd_bl <= (others => '0'); - - mig_p4_arb_en <= '0'; - mig_p4_cmd_clk <= '0'; - mig_p4_cmd_en <= '0'; - mig_p4_cmd_ra <= (others => '0'); - mig_p4_cmd_ba <= (others => '0'); - mig_p4_cmd_ca <= (others => '0'); - - mig_p4_cmd_instr <= (others => '0'); - mig_p4_cmd_bl <= (others => '0'); - - mig_p5_arb_en <= '0'; - mig_p5_cmd_clk <= '0'; - mig_p5_cmd_en <= '0'; - mig_p5_cmd_ra <= (others => '0'); - mig_p5_cmd_ba <= (others => '0'); - mig_p5_cmd_ca <= (others => '0'); - - mig_p5_cmd_instr <= (others => '0'); - mig_p5_cmd_bl <= (others => '0'); - ---*******************************END OF CONFIG 5 SIGNALS ******************************** - -end generate; - -uo_cal_start <= uo_cal_start_int; - - - -samc_0: MCB - GENERIC MAP - ( PORT_CONFIG => C_PORT_CONFIG, - MEM_WIDTH => C_NUM_DQ_PINS , - MEM_TYPE => C_MEM_TYPE , - MEM_BURST_LEN => C_MEM_BURST_LEN , - MEM_ADDR_ORDER => C_MEM_ADDR_ORDER, - MEM_CAS_LATENCY => C_MEM_CAS_LATENCY, - MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY , - MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY , - MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY , - MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR , - MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS , - MEM_DDR3_ODS => C_MEM_DDR3_ODS , - MEM_DDR2_RTT => C_MEM_DDR2_RTT , - MEM_DDR3_RTT => C_MEM_DDR3_RTT , - MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY , - MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY , - MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR , - MEM_MDDR_ODS => C_MEM_MDDR_ODS , - MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN , - MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR , - MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY, - MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR , - MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR, - MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT , - MEM_RA_SIZE => C_MEM_ADDR_WIDTH , - MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH , - MEM_CA_SIZE => C_MEM_NUM_COL_BITS , - MEM_RAS_VAL => MEM_RAS_VAL , - MEM_RCD_VAL => MEM_RCD_VAL , - MEM_REFI_VAL => MEM_REFI_VAL , - MEM_RFC_VAL => MEM_RFC_VAL , - MEM_RP_VAL => MEM_RP_VAL , - MEM_WR_VAL => MEM_WR_VAL , - MEM_RTP_VAL => MEM_RTP_VAL , - MEM_WTR_VAL => MEM_WTR_VAL , - CAL_BYPASS => C_MC_CALIB_BYPASS, - CAL_RA => C_MC_CALIBRATION_RA, - CAL_BA => C_MC_CALIBRATION_BA , - CAL_CA => C_MC_CALIBRATION_CA, - CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV, - CAL_DELAY => C_MC_CALIBRATION_DELAY, --- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE, - ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS, - ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0, - ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1, - ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2, - ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3, - ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4, - ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5, - ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6, - ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7, - ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8, - ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9, - ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10, - ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11 - ) PORT MAP - ( - - -- HIGH-SPEED PLL clock interface - - PLLCLK => pllclk1, - PLLCE => pllce1, - - PLLLOCK => '1', - - -- DQS CLOCK NETWork interface - - DQSIOIN => idelay_dqs_ioi_s, - DQSIOIP => idelay_dqs_ioi_m, - UDQSIOIN => idelay_udqs_ioi_s, - UDQSIOIP => idelay_udqs_ioi_m, - - - --DQSPIN => in_pre_dqsp, - DQI => in_dq, - -- RESETS - GLOBAl and local - SYSRST => MCB_SYSRST , - - -- command port 0 - P0ARBEN => mig_p0_arb_en, - P0CMDCLK => mig_p0_cmd_clk, - P0CMDEN => mig_p0_cmd_en, - P0CMDRA => mig_p0_cmd_ra, - P0CMDBA => mig_p0_cmd_ba, - P0CMDCA => mig_p0_cmd_ca, - - P0CMDINSTR => mig_p0_cmd_instr, - P0CMDBL => mig_p0_cmd_bl, - P0CMDEMPTY => mig_p0_cmd_empty, - P0CMDFULL => mig_p0_cmd_full, - - -- command port 1 - - P1ARBEN => mig_p1_arb_en, - P1CMDCLK => mig_p1_cmd_clk, - P1CMDEN => mig_p1_cmd_en, - P1CMDRA => mig_p1_cmd_ra, - P1CMDBA => mig_p1_cmd_ba, - P1CMDCA => mig_p1_cmd_ca, - - P1CMDINSTR => mig_p1_cmd_instr, - P1CMDBL => mig_p1_cmd_bl, - P1CMDEMPTY => mig_p1_cmd_empty, - P1CMDFULL => mig_p1_cmd_full, - - -- command port 2 - - P2ARBEN => mig_p2_arb_en, - P2CMDCLK => mig_p2_cmd_clk, - P2CMDEN => mig_p2_cmd_en, - P2CMDRA => mig_p2_cmd_ra, - P2CMDBA => mig_p2_cmd_ba, - P2CMDCA => mig_p2_cmd_ca, - - P2CMDINSTR => mig_p2_cmd_instr, - P2CMDBL => mig_p2_cmd_bl, - P2CMDEMPTY => mig_p2_cmd_empty, - P2CMDFULL => mig_p2_cmd_full, - - -- command port 3 - - P3ARBEN => mig_p3_arb_en, - P3CMDCLK => mig_p3_cmd_clk, - P3CMDEN => mig_p3_cmd_en, - P3CMDRA => mig_p3_cmd_ra, - P3CMDBA => mig_p3_cmd_ba, - P3CMDCA => mig_p3_cmd_ca, - - P3CMDINSTR => mig_p3_cmd_instr, - P3CMDBL => mig_p3_cmd_bl, - P3CMDEMPTY => mig_p3_cmd_empty, - P3CMDFULL => mig_p3_cmd_full, - - -- command port 4 -- don't care in config 2 - - P4ARBEN => mig_p4_arb_en, - P4CMDCLK => mig_p4_cmd_clk, - P4CMDEN => mig_p4_cmd_en, - P4CMDRA => mig_p4_cmd_ra, - P4CMDBA => mig_p4_cmd_ba, - P4CMDCA => mig_p4_cmd_ca, - - P4CMDINSTR => mig_p4_cmd_instr, - P4CMDBL => mig_p4_cmd_bl, - P4CMDEMPTY => mig_p4_cmd_empty, - P4CMDFULL => mig_p4_cmd_full, - - -- command port 5-- don't care in config 2 - - P5ARBEN => mig_p5_arb_en, - P5CMDCLK => mig_p5_cmd_clk, - P5CMDEN => mig_p5_cmd_en, - P5CMDRA => mig_p5_cmd_ra, - P5CMDBA => mig_p5_cmd_ba, - P5CMDCA => mig_p5_cmd_ca, - - P5CMDINSTR => mig_p5_cmd_instr, - P5CMDBL => mig_p5_cmd_bl, - P5CMDEMPTY => mig_p5_cmd_empty, - P5CMDFULL => mig_p5_cmd_full, - - - -- IOI & IOB SIGNals/tristate interface - - DQIOWEN0 => dqIO_w_en_0, - DQSIOWEN90P => dqsIO_w_en_90_p, - DQSIOWEN90N => dqsIO_w_en_90_n, - - - -- IOB MEMORY INTerface signals - ADDR => address_90, - BA => ba_90 , - RAS => ras_90 , - CAS => cas_90 , - WE => we_90 , - CKE => cke_90 , - ODT => odt_90 , - RST => rst_90 , - - -- CALIBRATION DRP interface - IOIDRPCLK => ioi_drp_clk , - IOIDRPADDR => ioi_drp_addr , - IOIDRPSDO => ioi_drp_sdo , - IOIDRPSDI => ioi_drp_sdi , - IOIDRPCS => ioi_drp_cs , - IOIDRPADD => ioi_drp_add , - IOIDRPBROADCAST => ioi_drp_broadcast , - IOIDRPTRAIN => ioi_drp_train , - IOIDRPUPDATE => ioi_drp_update , - - -- CALIBRATION DAtacapture interface - --SPECIAL COMMANDs - RECAL => mcb_recal , - UIREAD => mcb_ui_read, - UIADD => mcb_ui_add , - UICS => mcb_ui_cs , - UICLK => mcb_ui_clk , - UISDI => mcb_ui_sdi , - UIADDR => mcb_ui_addr , - UIBROADCAST => mcb_ui_broadcast, - UIDRPUPDATE => mcb_ui_drp_update, - UIDONECAL => mcb_ui_done_cal, - UICMD => mcb_ui_cmd, - UICMDIN => mcb_ui_cmd_in, - UICMDEN => mcb_ui_cmd_en, - UIDQCOUNT => mcb_ui_dqcount, - UIDQLOWERDEC => mcb_ui_dq_lower_dec, - UIDQLOWERINC => mcb_ui_dq_lower_inc, - UIDQUPPERDEC => mcb_ui_dq_upper_dec, - UIDQUPPERINC => mcb_ui_dq_upper_inc, - UIUDQSDEC => mcb_ui_udqs_dec, - UIUDQSINC => mcb_ui_udqs_inc, - UILDQSDEC => mcb_ui_ldqs_dec, - UILDQSINC => mcb_ui_ldqs_inc, - UODATA => uo_data_int, - UODATAVALID => uo_data_valid_int, - UODONECAL => hard_done_cal , - UOCMDREADYIN => uo_cmd_ready_in_int, - UOREFRSHFLAG => uo_refrsh_flag_xhdl23, - UOCALSTART => uo_cal_start_int, - UOSDO => uo_sdo_xhdl24, - - --CONTROL SIGNALS - STATUS => status, - SELFREFRESHENTER => selfrefresh_mcb_enter, - SELFREFRESHMODE => selfrefresh_mcb_mode, ------------------------------------------------- ---MUIs ------------------------------------------------- - - P0RDDATA => mig_p0_rd_data ( 31 downto 0), - P1RDDATA => mig_p1_rd_data ( 31 downto 0), - P2RDDATA => mig_p2_rd_data ( 31 downto 0), - P3RDDATA => mig_p3_rd_data ( 31 downto 0), - P4RDDATA => mig_p4_rd_data ( 31 downto 0), - P5RDDATA => mig_p5_rd_data ( 31 downto 0), - LDMN => dqnlm , - UDMN => dqnum , - DQON => dqo_n , - DQOP => dqo_p , - LDMP => dqplm , - UDMP => dqpum , - - P0RDCOUNT => mig_p0_rd_count , - P0WRCOUNT => mig_p0_wr_count , - P1RDCOUNT => mig_p1_rd_count , - P1WRCOUNT => mig_p1_wr_count , - P2COUNT => mig_p2_count , - P3COUNT => mig_p3_count , - P4COUNT => mig_p4_count , - P5COUNT => mig_p5_count , - - -- NEW ADDED FIFo status siganls - -- MIG USER PORT 0 - P0RDEMPTY => mig_p0_rd_empty, - P0RDFULL => mig_p0_rd_full, - P0RDOVERFLOW => mig_p0_rd_overflow, - P0WREMPTY => mig_p0_wr_empty, - P0WRFULL => mig_p0_wr_full, - P0WRUNDERRUN => mig_p0_wr_underrun, - -- MIG USER PORT 1 - P1RDEMPTY => mig_p1_rd_empty, - P1RDFULL => mig_p1_rd_full, - P1RDOVERFLOW => mig_p1_rd_overflow, - P1WREMPTY => mig_p1_wr_empty, - P1WRFULL => mig_p1_wr_full, - P1WRUNDERRUN => mig_p1_wr_underrun, - - -- MIG USER PORT 2 - P2EMPTY => mig_p2_empty, - P2FULL => mig_p2_full, - P2RDOVERFLOW => mig_p2_overflow, - P2WRUNDERRUN => mig_p2_underrun, - - P3EMPTY => mig_p3_empty , - P3FULL => mig_p3_full , - P3RDOVERFLOW => mig_p3_overflow, - P3WRUNDERRUN => mig_p3_underrun , - -- MIG USER PORT 3 - P4EMPTY => mig_p4_empty, - P4FULL => mig_p4_full, - P4RDOVERFLOW => mig_p4_overflow, - P4WRUNDERRUN => mig_p4_underrun, - - P5EMPTY => mig_p5_empty , - P5FULL => mig_p5_full , - P5RDOVERFLOW => mig_p5_overflow, - P5WRUNDERRUN => mig_p5_underrun, - - --------------------------------------------------------- - P0WREN => mig_p0_wr_en, - P0RDEN => mig_p0_rd_en, - P1WREN => mig_p1_wr_en, - P1RDEN => mig_p1_rd_en, - P2EN => mig_p2_en, - P3EN => mig_p3_en, - P4EN => mig_p4_en, - P5EN => mig_p5_en, - -- WRITE MASK BIts connection - P0RWRMASK => mig_p0_wr_mask(3 downto 0), - P1RWRMASK => mig_p1_wr_mask(3 downto 0), - P2WRMASK => mig_p2_wr_mask(3 downto 0), - P3WRMASK => mig_p3_wr_mask(3 downto 0), - P4WRMASK => mig_p4_wr_mask(3 downto 0), - P5WRMASK => mig_p5_wr_mask(3 downto 0), - -- DATA WRITE COnnection - P0WRDATA => mig_p0_wr_data(31 downto 0), - P1WRDATA => mig_p1_wr_data(31 downto 0), - P2WRDATA => mig_p2_wr_data(31 downto 0), - P3WRDATA => mig_p3_wr_data(31 downto 0), - P4WRDATA => mig_p4_wr_data(31 downto 0), - P5WRDATA => mig_p5_wr_data(31 downto 0), - - P0WRERROR => mig_p0_wr_error, - P1WRERROR => mig_p1_wr_error, - P0RDERROR => mig_p0_rd_error, - P1RDERROR => mig_p1_rd_error, - - P2ERROR => mig_p2_error, - P3ERROR => mig_p3_error, - P4ERROR => mig_p4_error, - P5ERROR => mig_p5_error, - - -- USER SIDE DAta ports clock - -- 128 BITS CONnections - P0WRCLK => mig_p0_wr_clk , - P1WRCLK => mig_p1_wr_clk , - P0RDCLK => mig_p0_rd_clk , - P1RDCLK => mig_p1_rd_clk , - P2CLK => mig_p2_clk , - P3CLK => mig_p3_clk , - P4CLK => mig_p4_clk , - P5CLK => mig_p5_clk - ); - ---////////////////////////////////////////////////////// ---// Input Termination Calibration ---////////////////////////////////////////////////////// - - uo_done_cal <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE - hard_done_cal; - - - gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE - mcb_soft_calibration_top_inst : mcb_soft_calibration_top - generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT, - C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, - SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL, - SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL, - SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM, - C_SIMULATION => C_SIMULATION, - C_MEM_TYPE => C_MEM_TYPE - ) - - PORT MAP ( - UI_CLK => ui_clk, - RST => int_sys_rst, - IOCLK => ioclk0, - DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL, - PLL_LOCK => pll_lock, - - SELFREFRESH_REQ => selfrefresh_enter, -- from user app - SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB - SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb - SELFREFRESH_MODE => selfrefresh_mode, -- to user app - - MCB_UIADD => mcb_ui_add, - MCB_UISDI => mcb_ui_sdi, - MCB_UOSDO => uo_sdo_xhdl24, - MCB_UODONECAL => hard_done_cal, - MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23, - MCB_UICS => mcb_ui_cs, - MCB_UIDRPUPDATE => mcb_ui_drp_update, - MCB_UIBROADCAST => mcb_ui_broadcast, - MCB_UIADDR => mcb_ui_addr, - MCB_UICMDEN => mcb_ui_cmd_en, - MCB_UIDONECAL => mcb_ui_done_cal, - MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec, - MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc, - MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec, - MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc, - MCB_UILDQSDEC => mcb_ui_ldqs_dec, - MCB_UILDQSINC => mcb_ui_ldqs_inc, - MCB_UIREAD => mcb_ui_read, - MCB_UIUDQSDEC => mcb_ui_udqs_dec, - MCB_UIUDQSINC => mcb_ui_udqs_inc, - MCB_RECAL => mcb_recal, - MCB_SYSRST => MCB_SYSRST, - MCB_UICMD => mcb_ui_cmd, - MCB_UICMDIN => mcb_ui_cmd_in, - MCB_UIDQCOUNT => mcb_ui_dqcount, - MCB_UODATA => uo_data_int, - MCB_UODATAVALID => uo_data_valid_int, - MCB_UOCMDREADY => uo_cmd_ready_in_int, - MCB_UO_CAL_START => uo_cal_start_int, - RZQ_PIN => rzq, - ZIO_PIN => zio, - CKE_Train => cke_train - ); - mcb_ui_clk <= ui_clk; - END GENERATE; - - - gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate - DONE_SOFTANDHARD_CAL <= '0'; - MCB_SYSRST <= int_sys_rst; - mcb_recal <= calib_recal; - mcb_ui_read <= ui_read; - mcb_ui_add <= ui_add; - mcb_ui_cs <= ui_cs; - mcb_ui_clk <= ui_clk; - mcb_ui_sdi <= ui_sdi; - mcb_ui_addr <= ui_addr; - mcb_ui_broadcast <= ui_broadcast; - mcb_ui_drp_update <= ui_drp_update; - mcb_ui_done_cal <= ui_done_cal; - mcb_ui_cmd <= ui_cmd; - mcb_ui_cmd_in <= ui_cmd_in; - mcb_ui_cmd_en <= ui_cmd_en; - mcb_ui_dqcount <= ui_dqcount; - mcb_ui_dq_lower_dec <= ui_dq_lower_dec; - mcb_ui_dq_lower_inc <= ui_dq_lower_inc; - mcb_ui_dq_upper_dec <= ui_dq_upper_dec; - mcb_ui_dq_upper_inc <= ui_dq_upper_inc; - mcb_ui_udqs_inc <= ui_udqs_inc; - mcb_ui_udqs_dec <= ui_udqs_dec; - mcb_ui_ldqs_inc <= ui_ldqs_inc; - mcb_ui_ldqs_dec <= ui_ldqs_dec; - end generate; - - - ---////////////////////////////////////////////////////// ---//ODDRDES2 instantiations ---////////////////////////////////////////////////////// - --------- ---ADDR --------- - - gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE - - - ioi_addr_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_addr(addr_ioi), - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_addr(addr_ioi), - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => address_90(addr_ioi), - D2 => address_90(addr_ioi), - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - END GENERATE; - --------- ---BA --------- - - gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE - - - ioi_ba_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_ba(ba_ioi), - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_ba(ba_ioi), - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => ba_90(ba_ioi), - D2 => ba_90(ba_ioi), - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - END GENERATE; - --------- ---CAS --------- - ioi_cas_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_cas, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_cas, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => cas_90, - D2 => cas_90, - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - --------- ---CKE --------- - ioi_cke_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2, - TRAIN_PATTERN => 15 - ) - PORT MAP ( - OQ => ioi_cke, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_cke, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => cke_90, - D2 => cke_90, - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => '0', --int_sys_rst - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => cke_train - ); --------- ---ODT --------- - xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE - - ioi_odt_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 --- TRAIN_PATTERN => 0 - ) - PORT MAP ( - OQ => ioi_odt, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_odt, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => odt_90, - D2 => odt_90, - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - END GENERATE; - --------- ---RAS --------- - ioi_ras_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_ras, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_ras, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => ras_90, - D2 => ras_90, - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); --------- ---RST --------- - xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE - ioi_rst_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_rst, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_rst, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => rst_90, - D2 => rst_90, - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - END GENERATE; --------- ---WE --------- - ioi_we_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_we, - TQ => t_we, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => we_90, - D2 => we_90, - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - --------- ---CK --------- - ioi_ck_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ioi_ck, - SHIFTOUT1 => open,--ck_shiftout0_1, - SHIFTOUT2 => open,--ck_shiftout0_2, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => t_ck, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => '0', - D2 => '1', - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => '0', --int_sys_rst - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - ----------- -----CKN ----------- --- ioi_ckn_0 : OSERDES2 --- GENERIC MAP ( --- BYPASS_GCLK_FF => TRUE, --- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, --- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, --- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, --- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE, --- DATA_WIDTH => 2 --- ) --- PORT MAP ( --- OQ => ioi_ckn, --- SHIFTOUT1 => open, --- SHIFTOUT2 => open, --- SHIFTOUT3 => open,--ck_shiftout1_3, --- SHIFTOUT4 => open,--ck_shiftout1_4, --- TQ => t_ckn, --- CLK0 => ioclk0, --- CLK1 => '0', --- CLKDIV => '0', --- D1 => '1', --- D2 => '0', --- D3 => '0', --- D4 => '0', --- IOCE => pll_ce_0, --- OCE => '1', --- RST => '0', --- SHIFTIN1 => '0', --- SHIFTIN2 => '0', --- SHIFTIN3 => '0', --- SHIFTIN4 => '0', --- T1 => '0', --- T2 => '0', --- T3 => '0', --- T4 => '0', --- TCE => '1', --- TRAIN => '0' --- ); --- --------- ---UDM --------- - - ioi_udm_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => udm_oq, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => udm_t, - CLK0 => ioclk90, - CLK1 => '0', - CLKDIV => '0', - D1 => dqpum, - D2 => dqnum, - D3 => '0', - D4 => '0', - IOCE => pll_ce_90, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => dqIO_w_en_0, - T2 => dqIO_w_en_0, - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - --------- ---LDM --------- - ioi_ldm_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - ) - PORT MAP ( - OQ => ldm_oq, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => ldm_t, - CLK0 => ioclk90, - CLK1 => '0', - CLKDIV => '0', - D1 => dqplm, - D2 => dqnlm, - D3 => '0', - D4 => '0', - IOCE => pll_ce_90, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => dqIO_w_en_0, - T2 => dqIO_w_en_0, - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); --------- ---DQ --------- - gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE - oserdes2_dq_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2, - TRAIN_PATTERN => 5 - ) - PORT MAP ( - OQ => dq_oq(dq), - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => dq_tq(dq), - CLK0 => ioclk90, - CLK1 => '0', - CLKDIV => '0', - D1 => dqo_p(dq), - D2 => dqo_n(dq), - D3 => '0', - D4 => '0', - IOCE => pll_ce_90, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => dqIO_w_en_0, - T2 => dqIO_w_en_0, - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => ioi_drp_train - ); - END GENERATE; - --------- ---DQSP --------- - - - oserdes2_dqsp_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 - -- TRAIN_PATTERN => 0 - ) - PORT MAP ( - OQ => dqsp_oq, - SHIFTOUT1 => open,--dqs_shiftout0_1, - SHIFTOUT2 => open,--dqs_shiftout0_2, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => dqsp_tq, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => '0', - D2 => '1', - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0',--dqs_shiftout1_3, - SHIFTIN4 => '0',--dqs_shiftout1_4, - T1 => dqsIO_w_en_90_n, - T2 => dqsIO_w_en_90_p, - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - --------- ---DQSN --------- - - oserdes2_dqsn_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE, - DATA_WIDTH => 2 - -- TRAIN_PATTERN => 0 - ) - PORT MAP ( - OQ => dqsn_oq, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open,--dqs_shiftout1_3, - SHIFTOUT4 => open,--dqs_shiftout1_4, - TQ => dqsn_tq, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => '1', - D2 => '0', - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0',--dqs_shiftout0_1, - SHIFTIN2 => '0',--dqs_shiftout0_2, - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => dqsIO_w_en_90_n, - T2 => dqsIO_w_en_90_p, - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - --------- ---UDQSP --------- - - oserdeS2_UDQSP_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER, - DATA_WIDTH => 2 --- TRAIN_PATTERN => 0 - ) - PORT MAP ( - OQ => udqsp_oq, - SHIFTOUT1 => open,--udqs_shiftout0_1, - SHIFTOUT2 => open,--udqs_shiftout0_2, - SHIFTOUT3 => open, - SHIFTOUT4 => open, - TQ => udqsp_tq, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => '0', - D2 => '1', - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0', - SHIFTIN2 => '0', - SHIFTIN3 => '0',--udqs_shiftout1_3, - SHIFTIN4 => '0',--udqs_shiftout1_4, - T1 => dqsIO_w_en_90_n, - t2 => dqsIO_w_en_90_p, - T3 => '0', - T4 => '0', - tce => '1', - train => '0' - ); - --------- ---UDQSN --------- - - oserdes2_udqsn_0 : OSERDES2 - GENERIC MAP ( - BYPASS_GCLK_FF => TRUE, - DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ, - DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT, - OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE, - SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE, - DATA_WIDTH => 2 --- TRAIN_PATTERN => 0 - ) - PORT MAP ( - OQ => udqsn_oq, - SHIFTOUT1 => open, - SHIFTOUT2 => open, - SHIFTOUT3 => open,--udqs_shiftout1_3, - SHIFTOUT4 => open,--udqs_shiftout1_4, - TQ => udqsn_tq, - CLK0 => ioclk0, - CLK1 => '0', - CLKDIV => '0', - D1 => '1', - D2 => '0', - D3 => '0', - D4 => '0', - IOCE => pll_ce_0, - OCE => '1', - RST => int_sys_rst, - SHIFTIN1 => '0',--udqs_shiftout0_1, - SHIFTIN2 => '0',--udqs_shiftout0_2, - SHIFTIN3 => '0', - SHIFTIN4 => '0', - T1 => dqsIO_w_en_90_n, - T2 => dqsIO_w_en_90_p, - T3 => '0', - T4 => '0', - TCE => '1', - TRAIN => '0' - ); - ------------------------------------------------------- ---*********************************** OSERDES2 instantiations end ******************************************* ------------------------------------------------------- - ------------------------------------------------- ---&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& ------------------------------------------------- ----#####################################--X16 MEMORY WIDTH-############################################# - - dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE - ---//////////////////////////////////////////////// ---DQ14 ---//////////////////////////////////////////////// - - iodrp2_DQ_14 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ14_TAP_DELAY_VAL, - MCB_ADDRESS => 7, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_14, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(14), - DQSOUTN => open, - DQSOUTP => in_dq(14), - SDO => open, - TOUT => t_dq(14), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_15, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(14), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(14), - SDI => ioi_drp_sdo, - T => dq_tq(14) - ); - ---//////////////////////////////////////////////// ---DQ15 ---//////////////////////////////////////////////// - - - iodrp2_dq_15 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ15_TAP_DELAY_VAL, - MCB_ADDRESS => 7, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_15, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(15), - DQSOUTN => open, - DQSOUTP => in_dq(15), - SDO => open, - TOUT => t_dq(15), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => '0', - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(15), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(15), - SDI => ioi_drp_sdo, - T => dq_tq(15) - ); - ---//////////////////////////////////////////////// ---DQ12 ---//////////////////////////////////////////////// - - iodrp2_DQ_12 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ12_TAP_DELAY_VAL, - MCB_ADDRESS => 6, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_12, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(12), - DQSOUTN => open, - DQSOUTP => in_dq(12), - SDO => open, - TOUT => t_dq(12), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_13, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(12), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(12), - SDI => ioi_drp_sdo, - T => dq_tq(12) - ); - ---//////////////////////////////////////////////// ---DQ13 ---//////////////////////////////////////////////// - - iodrp2_dq_13 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ13_TAP_DELAY_VAL, - MCB_ADDRESS => 6, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_13, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(13), - DQSOUTN => open, - DQSOUTP => in_dq(13), - SDO => open, - TOUT => t_dq(13), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_14, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(13), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(13), - SDI => ioi_drp_sdo, - T => dq_tq(13) - ); - ---///////// ---UDQSP ---///////// - - iodrp2_UDQSP_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => UDQSP_TAP_DELAY_VAL, - MCB_ADDRESS => 14, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_udqsp, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_udqs, - DQSOUTN => open, - DQSOUTP => idelay_udqs_ioi_m, - SDO => open, - TOUT => t_udqs, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_udqsn, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_udqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => udqsp_oq, - SDI => ioi_drp_sdo, - T => udqsp_tq - ); - ---///////// ---UDQSN ---///////// - - iodrp2_udqsn_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => UDQSN_TAP_DELAY_VAL, - MCB_ADDRESS => 14, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_udqsn, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_udqsn, - DQSOUTN => open, - DQSOUTP => idelay_udqs_ioi_s, - SDO => open, - TOUT => t_udqsn, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_12, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_udqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => udqsn_oq, - SDI => ioi_drp_sdo, - T => udqsn_tq - ); - ---///////////////////////////////////////////////// ---//DQ10 ---//////////////////////////////////////////////// - iodrp2_DQ_10 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ10_TAP_DELAY_VAL, - MCB_ADDRESS => 5, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_10, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(10), - DQSOUTN => open, - DQSOUTP => in_dq(10), - SDO => open, - TOUT => t_dq(10), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_11, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(10), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(10), - SDI => ioi_drp_sdo, - T => dq_tq(10) - ); - ---///////////////////////////////////////////////// ---//DQ11 ---//////////////////////////////////////////////// - - iodrp2_dq_11 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ11_TAP_DELAY_VAL, - MCB_ADDRESS => 5, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_11, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(11), - DQSOUTN => open, - DQSOUTP => in_dq(11), - SDO => open, - TOUT => t_dq(11), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_udqsp, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(11), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(11), - SDI => ioi_drp_sdo, - T => dq_tq(11) - ); - ---///////////////////////////////////////////////// ---//DQ8 ---//////////////////////////////////////////////// - - iodrp2_DQ_8 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ8_TAP_DELAY_VAL, - MCB_ADDRESS => 4, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_8, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(8), - DQSOUTN => open, - DQSOUTP => in_dq(8), - SDO => open, - TOUT => t_dq(8), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_9, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(8), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(8), - SDI => ioi_drp_sdo, - T => dq_tq(8) - ); - ---///////////////////////////////////////////////// ---//DQ9 ---//////////////////////////////////////////////// - - iodrp2_dq_9 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ9_TAP_DELAY_VAL, - MCB_ADDRESS => 4, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_9, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(9), - DQSOUTN => open, - DQSOUTP => in_dq(9), - SDO => open, - TOUT => t_dq(9), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_10, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(9), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(9), - SDI => ioi_drp_sdo, - T => dq_tq(9) - ); - ---///////////////////////////////////////////////// ---//DQ0 ---//////////////////////////////////////////////// - - iodrp2_DQ_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ0_TAP_DELAY_VAL, - MCB_ADDRESS => 0, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_0, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(0), - DQSOUTN => open, - DQSOUTP => in_dq(0), - SDO => open, - TOUT => t_dq(0), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_1, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(0), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(0), - SDI => ioi_drp_sdo, - T => dq_tq(0) - ); - ---///////////////////////////////////////////////// ---//DQ1 ---//////////////////////////////////////////////// - - iodrp2_dq_1 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ1_TAP_DELAY_VAL, - MCB_ADDRESS => 0, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_1, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(1), - DQSOUTN => open, - DQSOUTP => in_dq(1), - SDO => open, - TOUT => t_dq(1), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_8, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(1), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(1), - SDI => ioi_drp_sdo, - T => dq_tq(1) - ); - ---///////////////////////////////////////////////// ---//DQ2 ---//////////////////////////////////////////////// - - iodrp2_DQ_2 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ2_TAP_DELAY_VAL, - MCB_ADDRESS => 1, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_2, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(2), - DQSOUTN => open, - DQSOUTP => in_dq(2), - SDO => open, - TOUT => t_dq(2), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_3, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(2), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(2), - SDI => ioi_drp_sdo, - T => dq_tq(2) - ); - ---///////////////////////////////////////////////// ---//DQ3 ---//////////////////////////////////////////////// - - iodrp2_dq_3 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ3_TAP_DELAY_VAL, - MCB_ADDRESS => 1, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_3, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(3), - DQSOUTN => open, - DQSOUTP => in_dq(3), - SDO => open, - TOUT => t_dq(3), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_0, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(3), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(3), - SDI => ioi_drp_sdo, - T => dq_tq(3) - ); - ---///////// ---//DQSP ---///////// - - iodrp2_DQSP_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => LDQSP_TAP_DELAY_VAL, - MCB_ADDRESS => 15, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_dqsp, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dqs, - DQSOUTN => open, - DQSOUTP => idelay_dqs_ioi_m, - SDO => open, - TOUT => t_dqs, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_dqsn, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dqsp_oq, - SDI => ioi_drp_sdo, - T => dqsp_tq - ); - ---///////// ---//DQSN ---///////// - - iodrp2_dqsn_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => LDQSN_TAP_DELAY_VAL, - MCB_ADDRESS => 15, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_dqsn, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dqsn, - DQSOUTN => open, - DQSOUTP => idelay_dqs_ioi_s, - SDO => open, - TOUT => t_dqsn, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_2, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dqsn_oq, - SDI => ioi_drp_sdo, - T => dqsn_tq - ); - ---///////////////////////////////////////////////// ---//DQ6 ---//////////////////////////////////////////////// - - iodrp2_DQ_6 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ6_TAP_DELAY_VAL, - MCB_ADDRESS => 3, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_6, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(6), - DQSOUTN => open, - DQSOUTP => in_dq(6), - SDO => open, - TOUT => t_dq(6), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_7, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(6), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(6), - SDI => ioi_drp_sdo, - T => dq_tq(6) - ); - ---///////////////////////////////////////////////// ---//DQ7 ---//////////////////////////////////////////////// - - iodrp2_dq_7 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ7_TAP_DELAY_VAL, - MCB_ADDRESS => 3, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_7, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(7), - DQSOUTN => open, - DQSOUTP => in_dq(7), - SDO => open, - TOUT => t_dq(7), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_dqsp, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(7), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(7), - SDI => ioi_drp_sdo, - T => dq_tq(7) - ); - ---///////////////////////////////////////////////// ---//DQ4 ---//////////////////////////////////////////////// - - iodrp2_DQ_4 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ4_TAP_DELAY_VAL, - MCB_ADDRESS => 2, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_4, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(4), - DQSOUTN => open, - DQSOUTP => in_dq(4), - SDO => open, - TOUT => t_dq(4), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_5, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(4), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(4), - SDI => ioi_drp_sdo, - T => dq_tq(4) - ); - ---///////////////////////////////////////////////// ---//DQ5 ---//////////////////////////////////////////////// - - iodrp2_dq_5 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ5_TAP_DELAY_VAL, - MCB_ADDRESS => 2, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_5, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(5), - DQSOUTN => open, - DQSOUTP => in_dq(5), - SDO => open, - TOUT => t_dq(5), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_6, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(5), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(5), - SDI => ioi_drp_sdo, - T => dq_tq(5) - ); - - - - ---///////////////////////////////////////////////// ---//UDM ---//////////////////////////////////////////////// - - iodrp2_dq_udm : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => 0, - MCB_ADDRESS => 8, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => ioi_drp_sdi, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_udm, - DQSOUTN => open, - DQSOUTP => open, - SDO => open, - TOUT => t_udm, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_ldm, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => '0', - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => udm_oq, - SDI => ioi_drp_sdo, - T => udm_t - ); - ---///////////////////////////////////////////////// ---//LDM ---//////////////////////////////////////////////// - - iodrp2_dq_ldm : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => 0, - MCB_ADDRESS => 8, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_ldm, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_ldm, - DQSOUTN => open, - DQSOUTP => open, - SDO => open, - TOUT => t_ldm, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_4, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => '0', - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => ldm_oq, - SDI => ioi_drp_sdo, - T => ldm_t - ); - -end generate; - ----#####################################--X8 MEMORY WIDTH-############################################# - - dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE ---///////////////////////////////////////////////// ---//DQ0 ---//////////////////////////////////////////////// - iodrp2_DQ_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ0_TAP_DELAY_VAL, - MCB_ADDRESS => 0, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_0, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(0), - DQSOUTN => open, - DQSOUTP => in_dq(0), - SDO => open, - TOUT => t_dq(0), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_1, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(0), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(0), - SDI => ioi_drp_sdo, - T => dq_tq(0) - ); - ---///////////////////////////////////////////////// ---//DQ1 ---//////////////////////////////////////////////// - - iodrp2_dq_1 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ1_TAP_DELAY_VAL, - MCB_ADDRESS => 0, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_1, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(1), - DQSOUTN => open, - DQSOUTP => in_dq(1), - SDO => open, - TOUT => t_dq(1), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => '0', - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(1), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(1), - SDI => ioi_drp_sdo, - T => dq_tq(1) - ); - ---///////////////////////////////////////////////// ---//DQ2 ---//////////////////////////////////////////////// - - iodrp2_DQ_2 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ2_TAP_DELAY_VAL, - MCB_ADDRESS => 1, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_2, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(2), - DQSOUTN => open, - DQSOUTP => in_dq(2), - SDO => open, - TOUT => t_dq(2), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_3, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(2), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(2), - SDI => ioi_drp_sdo, - T => dq_tq(2) - ); - ---///////////////////////////////////////////////// ---//DQ3 ---//////////////////////////////////////////////// - - iodrp2_dq_3 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ3_TAP_DELAY_VAL, - MCB_ADDRESS => 1, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_3, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(3), - DQSOUTN => open, - DQSOUTP => in_dq(3), - SDO => open, - TOUT => t_dq(3), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_0, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(3), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(3), - SDI => ioi_drp_sdo, - T => dq_tq(3) - ); - ---///////// ---//DQSP ---///////// - - iodrp2_DQSP_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => LDQSP_TAP_DELAY_VAL, - MCB_ADDRESS => 15, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_dqsp, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dqs, - DQSOUTN => open, - DQSOUTP => idelay_dqs_ioi_m, - SDO => open, - TOUT => t_dqs, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_dqsn, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dqsp_oq, - SDI => ioi_drp_sdo, - T => dqsp_tq - ); - ---///////// ---//DQSN ---///////// - iodrp2_dqsn_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => LDQSN_TAP_DELAY_VAL, - MCB_ADDRESS => 15, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_dqsn, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dqsn, - DQSOUTN => open, - DQSOUTP => idelay_dqs_ioi_s, - SDO => open, - TOUT => t_dqsn, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_2, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dqsn_oq, - SDI => ioi_drp_sdo, - T => dqsn_tq - ); - ---///////////////////////////////////////////////// ---//DQ6 ---//////////////////////////////////////////////// - - iodrp2_DQ_6 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ6_TAP_DELAY_VAL, - MCB_ADDRESS => 3, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_6, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(6), - DQSOUTN => open, - DQSOUTP => in_dq(6), - SDO => open, - TOUT => t_dq(6), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_7, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(6), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(6), - SDI => ioi_drp_sdo, - T => dq_tq(6) - ); - ---///////////////////////////////////////////////// ---//DQ7 ---//////////////////////////////////////////////// - - iodrp2_dq_7 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ7_TAP_DELAY_VAL, - MCB_ADDRESS => 3, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_7, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(7), - DQSOUTN => open, - DQSOUTP => in_dq(7), - SDO => open, - TOUT => t_dq(7), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_dqsp, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(7), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(7), - SDI => ioi_drp_sdo, - T => dq_tq(7) - ); - ---///////////////////////////////////////////////// ---//DQ4 ---//////////////////////////////////////////////// - - iodrp2_DQ_4 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ4_TAP_DELAY_VAL, - MCB_ADDRESS => 2, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_4, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(4), - DQSOUTN => open, - DQSOUTP => in_dq(4), - SDO => open, - TOUT => t_dq(4), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_5, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(4), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(4), - SDI => ioi_drp_sdo, - T => dq_tq(4) - ); ---///////////////////////////////////////////////// ---//DQ5 ---//////////////////////////////////////////////// - - - iodrp2_dq_5 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ5_TAP_DELAY_VAL, - MCB_ADDRESS => 2, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_5, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(5), - DQSOUTN => open, - DQSOUTP => in_dq(5), - SDO => open, - TOUT => t_dq(5), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_6, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(5), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(5), - SDI => ioi_drp_sdo, - T => dq_tq(5) - ); - - - ---NEED TO GENERATE UDM so that user won't instantiate in this location - ---///////////////////////////////////////////////// ---//UDM ---//////////////////////////////////////////////// - - iodrp2_dq_udm : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => 0, - MCB_ADDRESS => 8, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => ioi_drp_sdi, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_udm, - DQSOUTN => open, - DQSOUTP => open, - SDO => open, - TOUT => t_udm, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_ldm, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => '0', - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => udm_oq, - SDI => ioi_drp_sdo, - T => udm_t - ); - ---///////////////////////////////////////////////// ---//LDM ---//////////////////////////////////////////////// - - iodrp2_dq_ldm : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => 0, - MCB_ADDRESS => 8, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_ldm, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_ldm, - DQSOUTN => open, - DQSOUTP => open, - SDO => open, - TOUT => t_ldm, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_4, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => '0', - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => ldm_oq, - SDI => ioi_drp_sdo, - T => ldm_t - ); - -end generate; - ----#####################################--X4 MEMORY WIDTH-############################################# - - dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE ---///////////////////////////////////////////////// ---//DQ0 ---//////////////////////////////////////////////// - - iodrp2_DQ_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ0_TAP_DELAY_VAL, - MCB_ADDRESS => 0, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_0, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(0), - DQSOUTN => open, - DQSOUTP => in_dq(0), - SDO => open, - TOUT => t_dq(0), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_1, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(0), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(0), - SDI => ioi_drp_sdo, - T => dq_tq(0) - ); - - --///////////////////////////////////////////////// ---//DQ1 ---//////////////////////////////////////////////// - - iodrp2_dq_1 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ1_TAP_DELAY_VAL, - MCB_ADDRESS => 0, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_1, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(1), - DQSOUTN => open, - DQSOUTP => in_dq(1), - SDO => open, - TOUT => t_dq(1), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => '0', - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(1), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(1), - SDI => ioi_drp_sdo, - T => dq_tq(1) - ); - - --///////////////////////////////////////////////// ---//DQ2 ---//////////////////////////////////////////////// - - iodrp2_DQ_2 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ2_TAP_DELAY_VAL, - MCB_ADDRESS => 1, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_2, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(2), - DQSOUTN => open, - DQSOUTP => in_dq(2), - SDO => open, - TOUT => t_dq(2), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_3, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(2), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(2), - SDI => ioi_drp_sdo, - T => dq_tq(2) - ); - ---///////////////////////////////////////////////// ---//DQ3 ---//////////////////////////////////////////////// - - iodrp2_dq_3 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => DQ3_TAP_DELAY_VAL, - MCB_ADDRESS => 1, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_3, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dq(3), - DQSOUTN => open, - DQSOUTP => in_dq(3), - SDO => open, - TOUT => t_dq(3), - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_0, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dq(3), - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dq_oq(3), - SDI => ioi_drp_sdo, - T => dq_tq(3) - ); - ---/////////////////////////////////////////////// ---DQSP ---/////////////////////////////////////////////// - iodrp2_DQSP_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => LDQSP_TAP_DELAY_VAL, - MCB_ADDRESS => 15, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_dqsp, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dqs, - DQSOUTN => open, - DQSOUTP => idelay_dqs_ioi_m, - SDO => open, - TOUT => t_dqs, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_dqsn, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dqsp_oq, - SDI => ioi_drp_sdo, - T => dqsp_tq - ); - ---/////////////////////////////////////////////// ---DQSN ---/////////////////////////////////////////////// - - iodrp2_dqsn_0 : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQS_IODRP2_DATA_RATE, - IDELAY_VALUE => LDQSN_TAP_DELAY_VAL, - MCB_ADDRESS => 15, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_dqsn, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_dqsn, - DQSOUTN => open, - DQSOUTP => idelay_dqs_ioi_s, - SDO => open, - TOUT => t_dqsn, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_2, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => in_pre_dqsp, - IOCLK0 => ioclk0, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => dqsn_oq, - SDI => ioi_drp_sdo, - T => dqsn_tq - ); ---/////////////////////////////////////////////// ---UDM ---////////////////////////////////////////////// - --NEED TO GENERATE UDM so that user won't instantiate in this location - - - iodrp2_dq_udm : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => 0, - MCB_ADDRESS => 8, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => ioi_drp_sdi, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_udm, - DQSOUTN => open, - DQSOUTP => open, - SDO => open, - TOUT => t_udm, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_ldm, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => '0', - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => udm_oq, - SDI => ioi_drp_sdo, - T => udm_t - ); - ---/////////////////////////////////////////////// ---LDM ---////////////////////////////////////////////// - - - iodrp2_dq_ldm : IODRP2_MCB - GENERIC MAP ( - DATA_RATE => C_DQ_IODRP2_DATA_RATE, - IDELAY_VALUE => 0, - MCB_ADDRESS => 8, - ODELAY_VALUE => 0, - SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE, - SIM_TAPDELAY_VALUE => 10 - ) - PORT MAP ( - AUXSDO => aux_sdi_out_ldm, - DATAOUT => open, - DATAOUT2 => open, - DOUT => ioi_ldm, - DQSOUTN => open, - DQSOUTP => open, - SDO => open, - TOUT => t_ldm, - ADD => ioi_drp_add, - AUXADDR => ioi_drp_addr, - AUXSDOIN => aux_sdi_out_4, - BKST => ioi_drp_broadcast, - CLK => ioi_drp_clk, - CS => ioi_drp_cs, - IDATAIN => '0', - IOCLK0 => ioclk90, - IOCLK1 => '0', - MEMUPDATE => ioi_drp_update, - ODATAIN => ldm_oq, - SDI => ioi_drp_sdo, - T => ldm_t - ); - -end generate; - ------------------------------------------------- ---&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& ------------------------------------------------- - - -------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - --IOBs instantiations - -- this part need more inputs from design team - -- for now just use as listed in fpga.v - -----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - --- DRAM Address - gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE - iob_addr_inst : OBUFT - PORT MAP ( - I => ioi_addr(addr_i), - T => t_addr(addr_i), - O => mcbx_dram_addr(addr_i) - ); - END GENERATE; - - gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE - iob_ba_inst : OBUFT - PORT MAP ( - I => ioi_ba(ba_i), - T => t_ba(ba_i), - O => mcbx_dram_ba(ba_i) - ); - END GENERATE; - --- DRAM control ---RAS - iob_ras : OBUFT - PORT MAP ( - O => mcbx_dram_ras_n, - I => ioi_ras, - T => t_ras - ); - ---CAS - iob_cas : OBUFT - PORT MAP ( - O => mcbx_dram_cas_n, - I => ioi_cas, - T => t_cas - ); - ---WE - iob_we : OBUFT - PORT MAP ( - O => mcbx_dram_we_n, - I => ioi_we, - T => t_we - ); - ---CKE - iob_cke : OBUFT - PORT MAP ( - O => mcbx_dram_cke, - I => ioi_cke, - T => t_cke - ); - ---DDR3 RST - gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE - iob_rst : OBUFT - PORT MAP ( - O => mcbx_dram_ddr3_rst, - I => ioi_rst, - T => t_rst - ); - END GENERATE; - ---ODT - gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF"))) - OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE - iob_odt : OBUFT - PORT MAP ( - O => mcbx_dram_odt, - I => ioi_odt, - t => t_odt - ); - END GENERATE; - ---MEMORY CLOCK - iob_clk : OBUFTDS - PORT MAP ( - I => ioi_ck, - T => t_ck, - O => mcbx_dram_clk, - OB => mcbx_dram_clk_n - ); - ---DQ - gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE - gen_iob_dq_inst : IOBUF - PORT MAP ( - IO => mcbx_dram_dq(dq_i), - I => ioi_dq(dq_i), - T => t_dq(dq_i), - O => in_pre_dq(dq_i) - ); - END GENERATE; - --- x4 and x8 ---DQS -gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and -(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate - iob_dqs : IOBUF - PORT MAP ( - IO => mcbx_dram_dqs, - I => ioi_dqs, - T => t_dqs, - O => in_pre_dqsp - ); -end generate; - ---DQSP/DQSN -gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and -(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate - iob_dqs : IOBUFDS - PORT MAP ( - IO => mcbx_dram_dqs, - IOB => mcbx_dram_dqs_n, - I => ioi_dqs, - T => t_dqs, - O => in_pre_dqsp - ); -end generate; - --- x16 ---UDQS -gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and -(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate - iob_udqs : IOBUF - PORT MAP ( - IO => mcbx_dram_udqs, - I => ioi_udqs, - T => t_udqs, - O => in_pre_udqsp - ); -end generate; - -----UDQSP/UDQSN -gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and -(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate - iob_udqs : IOBUFDS - PORT MAP ( - IO => mcbx_dram_udqs, - IOB => mcbx_dram_udqs_n, - I => ioi_udqs, - T => t_udqs, - O => in_pre_udqsp - ); -end generate; - --- DQS PULLDWON -gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate -dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs); -end generate; - -gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and -(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate -dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs); -dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n); -end generate; - --- DQSN PULLUP -gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and -(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate -udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs); -end generate; - -gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and - (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate -udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs); -udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n); -end generate; - ---UDM -gen_udm : if(C_NUM_DQ_PINS = 16) generate - iob_udm : OBUFT - PORT MAP ( - I => ioi_udm, - T => t_udm, - O => mcbx_dram_udm - ); -end generate; ---LDM - iob_ldm : OBUFT - PORT MAP ( - I => ioi_ldm, - T => t_ldm, - O => mcbx_dram_ldm - ); - - end aarch; -

ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd =================================================================== --- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd (revision 5) +++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd (nonexistent) @@ -1,281 +0,0 @@ ---***************************************************************************** --- (c) Copyright 2009 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.5 --- \ \ Application : MIG --- / / Filename : memc3_infrastructure.vhd --- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $ --- \ \ / \ Date Created : Jul 03 2009 --- \___\/\___\ --- ---Device : Spartan-6 ---Design Name : DDR/DDR2/DDR3/LPDDR ---Purpose : Clock generation/distribution and reset synchronization ---Reference : ---Revision History : ---***************************************************************************** -library ieee; -use ieee.std_logic_1164.all; -library unisim; -use unisim.vcomponents.all; - -entity memc3_infrastructure is -generic - ( - C_MEMCLK_PERIOD : integer := 2500; - C_RST_ACT_LOW : integer := 1; - C_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; - C_CLKOUT0_DIVIDE : integer := 2; - C_CLKOUT1_DIVIDE : integer := 2; - C_CLKOUT2_DIVIDE : integer := 16; - C_CLKOUT3_DIVIDE : integer := 8; - C_CLKFBOUT_MULT : integer := 4; - C_DIVCLK_DIVIDE : integer := 1 - - ); -port -( - sys_clk_p : in std_logic; - sys_clk_n : in std_logic; - sys_clk : in std_logic; - sys_rst_n : in std_logic; - clk0 : out std_logic; - rst0 : out std_logic; - async_rst : out std_logic; - sysclk_2x : out std_logic; - sysclk_2x_180 : out std_logic; - mcb_drp_clk : out std_logic; - pll_ce_0 : out std_logic; - pll_ce_90 : out std_logic; - pll_lock : out std_logic - -); -end entity; -architecture syn of memc3_infrastructure is - - -- # of clock cycles to delay deassertion of reset. Needs to be a fairly - -- high number not so much for metastability protection, but to give time - -- for reset (i.e. stable clock cycles) to propagate through all state - -- machines and to all control signals (i.e. not all control signals have - -- resets, instead they rely on base state logic being reset, and the effect - -- of that reset propagating through the logic). Need this because we may not - -- be getting stable clock cycles while reset asserted (i.e. since reset - -- depends on PLL/DCM lock status) - - constant RST_SYNC_NUM : integer := 25; - constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0; - constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000; - - - signal clk_2x_0 : std_logic; - signal clk_2x_180 : std_logic; - signal clk0_bufg : std_logic; - signal clk0_bufg_in : std_logic; - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; - signal locked : std_logic; - signal bufpll_mcb_locked : std_logic; - signal mcb_drp_clk_sig : std_logic; - - attribute max_fanout : string; - attribute syn_maxfan : integer; - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; - -begin - - sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n; - clk0 <= clk0_bufg; - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** - - u_pll_adv : PLL_ADV - generic map - ( - BANDWIDTH => "OPTIMIZED", - CLKIN1_PERIOD => CLK_PERIOD_NS, - CLKIN2_PERIOD => CLK_PERIOD_NS, - CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE, - CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE, - CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE, - CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE, - CLKOUT4_DIVIDE => 1, - CLKOUT5_DIVIDE => 1, - CLKOUT0_PHASE => 0.000, - CLKOUT1_PHASE => 180.000, - CLKOUT2_PHASE => 0.000, - CLKOUT3_PHASE => 0.000, - CLKOUT4_PHASE => 0.000, - CLKOUT5_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT2_DUTY_CYCLE => 0.500, - CLKOUT3_DUTY_CYCLE => 0.500, - CLKOUT4_DUTY_CYCLE => 0.500, - CLKOUT5_DUTY_CYCLE => 0.500, - COMPENSATION => "INTERNAL", - DIVCLK_DIVIDE => C_DIVCLK_DIVIDE, - CLKFBOUT_MULT => C_CLKFBOUT_MULT, - CLKFBOUT_PHASE => 0.0, - REF_JITTER => 0.005000 - ) - port map - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', - CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DWE => '0', - REL => '0', - RST => sys_rst, - CLKFBDCM => open, - CLKFBOUT => clkfbout_clkfbin, - CLKOUTDCM0 => open, - CLKOUTDCM1 => open, - CLKOUTDCM2 => open, - CLKOUTDCM3 => open, - CLKOUTDCM4 => open, - CLKOUTDCM5 => open, - CLKOUT0 => clk_2x_0, - CLKOUT1 => clk_2x_180, - CLKOUT2 => clk0_bufg_in, - CLKOUT3 => mcb_drp_clk_bufg_in, - CLKOUT4 => open, - CLKOUT5 => open, - DO => open, - DRDY => open, - LOCKED => locked - ); - - U_BUFG_CLK0 : BUFG - port map - ( - O => clk0_bufg, - I => clk0_bufg_in - ); - - U_BUFG_CLK1 : BUFG - port map ( - O => mcb_drp_clk_sig, - I => mcb_drp_clk_bufg_in - ); - - process (clk0_bufg, sys_rst) - begin - if (clk0_bufg'event and clk0_bufg = '1') then - if(sys_rst = '1') then - powerup_pll_locked <= '0'; - elsif (bufpll_mcb_locked = '1') then - powerup_pll_locked <= '1'; - end if; - end if; - end process; - - --*************************************************************************** - -- Reset synchronization - -- NOTES: - -- 1. shut down the whole operation if the PLL hasn't yet locked (and - -- by inference, this means that external sys_rst has been asserted - - -- PLL deasserts LOCKED as soon as sys_rst asserted) - -- 2. asynchronously assert reset. This was we can assert reset even if - -- there is no clock (needed for things like 3-stating output buffers). - -- reset deassertion is synchronous. - -- 3. asynchronous reset only look at pll_lock from PLL during power up. After - -- power up and pll_lock is asserted, the powerup_pll_locked will be asserted - -- forever until sys_rst is asserted again. PLL will lose lock when FPGA - -- enters suspend mode. We don't want reset to MCB get - -- asserted in the application that needs suspend feature. - --*************************************************************************** - - rst_tmp <= sys_rst or not(powerup_pll_locked); - - async_rst <= rst_tmp; - -process (clk0_bufg, rst_tmp) - begin - if (rst_tmp = '1') then - rst0_sync_r <= (others => '1'); - elsif (rising_edge(clk0_bufg)) then - rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0) - end if; - end process; - - rst0 <= rst0_sync_r(RST_SYNC_NUM-1); - - -BUFPLL_MCB_INST : BUFPLL_MCB -port map -( IOCLK0 => sysclk_2x, - IOCLK1 => sysclk_2x_180, - LOCKED => locked, - GCLK => mcb_drp_clk_sig, - SERDESSTROBE0 => pll_ce_0, - SERDESSTROBE1 => pll_ce_90, - PLLIN0 => clk_2x_0, - PLLIN1 => clk_2x_180, - LOCK => bufpll_mcb_locked - ); - -end architecture syn; - Index: ipcore_dir/mem0/user_design/par/mem_interface_top.ut =================================================================== --- ipcore_dir/mem0/user_design/par/mem_interface_top.ut (revision 5) +++ ipcore_dir/mem0/user_design/par/mem_interface_top.ut (nonexistent) @@ -1,22 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g CRC:Enable --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullNone --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No --g ConfigRate:6 Index: ipcore_dir/mem0/user_design/par/mem0.ucf =================================================================== --- ipcore_dir/mem0/user_design/par/mem0.ucf (revision 5) +++ ipcore_dir/mem0/user_design/par/mem0.ucf (nonexistent) @@ -1,140 +0,0 @@ -############################################################################ -## -## Xilinx, Inc. 2006 www.xilinx.com -## Fri Aug 20 11:42:53 2010 -## Generated by MIG Version 3.5 -## -############################################################################ -## File name : mem0.ucf -## -## Details : Constraints file -## FPGA family: spartan6 -## FPGA: xc6slx16-ftg256 -## Speedgrade: -2 -## Design Entry: VHDL -## Design: without Test bench -## DCM Used: Enable -## Compatible FPGA's: xc6slx9-ftg256,xc6slx25-ftg256 -## No.Of Memory Controllers: 1 -## -############################################################################ -############################################################################ -# VCC AUX VOLTAGE -############################################################################ -CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3 - -############################################################################ -# Extended MCB performance mode requires a different Vccint specification to -# achieve higher maximum frequencies for DDR2 and DDR3.Consult the Spartan-6 -#datasheet (DS162) table 2 and 24 for more information -############################################################################ -CONFIG MCB_PERFORMANCE= STANDARD; - - -################################################################################## -# Timing Ignore constraints for paths crossing the clock domain -################################################################################## -NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG; -NET "c?_pll_lock" TIG; - - -############################################################################ -## Memory Controller 3 -## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT -## Frequency: 200 MHz -## Time Period: 5000 ps -## Supported Part Numbers: MT46V32M16BN-5B-IT -############################################################################ - -############################################################################ -## Clock constraints -############################################################################ -NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3"; -TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 5 ns HIGH 50 %; -############################################################################ - -############################################################################ -## I/O TERMINATION -############################################################################ -NET "mcb3_dram_dq[*]" IN_TERM = UNTUNED_SPLIT_50; -NET "mcb3_dram_dqs" IN_TERM = UNTUNED_SPLIT_50; -NET "mcb3_dram_udqs" IN_TERM = UNTUNED_SPLIT_50; - -############################################################################ -# I/O STANDARDS -############################################################################ - -NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_a[*]" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_dqs" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_udqs" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL2_II; -NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL2_II; -NET "mcb3_dram_cke" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_ras_n" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_cas_n" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_we_n" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_dm" IOSTANDARD = SSTL2_II; -NET "mcb3_dram_udm" IOSTANDARD = SSTL2_II; -NET "mcb3_rzq" IOSTANDARD = SSTL2_II; -NET "c3_sys_clk" IOSTANDARD = LVCMOS25; -NET "c3_sys_rst_n" IOSTANDARD = LVCMOS25; -############################################################################ -# MCB 3 -# Pin Location Constraints for Clock, Masks, Address, and Controls -############################################################################ - -NET "mcb3_dram_a[0]" LOC = "K5" ; -NET "mcb3_dram_a[10]" LOC = "G6" ; -NET "mcb3_dram_a[11]" LOC = "E3" ; -NET "mcb3_dram_a[12]" LOC = "F3" ; -NET "mcb3_dram_a[1]" LOC = "K6" ; -NET "mcb3_dram_a[2]" LOC = "D1" ; -NET "mcb3_dram_a[3]" LOC = "L4" ; -NET "mcb3_dram_a[4]" LOC = "G5" ; -NET "mcb3_dram_a[5]" LOC = "H4" ; -NET "mcb3_dram_a[6]" LOC = "H3" ; -NET "mcb3_dram_a[7]" LOC = "D3" ; -NET "mcb3_dram_a[8]" LOC = "B2" ; -NET "mcb3_dram_a[9]" LOC = "A2" ; -NET "mcb3_dram_ba[0]" LOC = "C3" ; -NET "mcb3_dram_ba[1]" LOC = "C2" ; -NET "mcb3_dram_cas_n" LOC = "H5" ; -NET "mcb3_dram_ck" LOC = "E2" ; -NET "mcb3_dram_ck_n" LOC = "E1" ; -NET "mcb3_dram_cke" LOC = "F4" ; -NET "mcb3_dram_dm" LOC = "J4" ; -NET "mcb3_dram_dq[0]" LOC = "K2" ; -NET "mcb3_dram_dq[10]" LOC = "M2" ; -NET "mcb3_dram_dq[11]" LOC = "M1" ; -NET "mcb3_dram_dq[12]" LOC = "P2" ; -NET "mcb3_dram_dq[13]" LOC = "P1" ; -NET "mcb3_dram_dq[14]" LOC = "R2" ; -NET "mcb3_dram_dq[15]" LOC = "R1" ; -NET "mcb3_dram_dq[1]" LOC = "K1" ; -NET "mcb3_dram_dq[2]" LOC = "J3" ; -NET "mcb3_dram_dq[3]" LOC = "J1" ; -NET "mcb3_dram_dq[4]" LOC = "F2" ; -NET "mcb3_dram_dq[5]" LOC = "F1" ; -NET "mcb3_dram_dq[6]" LOC = "G3" ; -NET "mcb3_dram_dq[7]" LOC = "G1" ; -NET "mcb3_dram_dq[8]" LOC = "L3" ; -NET "mcb3_dram_dq[9]" LOC = "L1" ; -NET "mcb3_dram_dqs" LOC = "H2" ; -NET "mcb3_dram_ras_n" LOC = "J6" ; -NET "c3_sys_clk" LOC = "M9" ; -NET "c3_sys_rst_n" LOC = "P6" ; -NET "mcb3_dram_udm" LOC = "K3" ; -NET "mcb3_dram_udqs" LOC = "N3" ; -NET "mcb3_dram_we_n" LOC = "C1" ; - -################################################################################## -#RZQ is required for all MCB designs. Do not move the location # -#of this pin for ES devices.For production devices, RZQ can be moved to any # -#valid package pin within the MCB bank.For designs using Calibrated Input Termination, # -#a 2R resistor should be connected between RZQand ground, where R is the desired# -#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.# -################################################################################## -NET "mcb3_rzq" LOC = "M4" ; - Index: ipcore_dir/mem0/user_design/par/readme.txt =================================================================== --- ipcore_dir/mem0/user_design/par/readme.txt (revision 5) +++ ipcore_dir/mem0/user_design/par/readme.txt (nonexistent) @@ -1,146 +0,0 @@ -::**************************************************************************** -:: (c) Copyright 2009 Xilinx, Inc. All rights reserved. -:: -:: This file contains confidential and proprietary information -:: of Xilinx, Inc. and is protected under U.S. and -:: international copyright and other intellectual property -:: laws. -:: -:: DISCLAIMER -:: This disclaimer is not a license and does not grant any -:: rights to the materials distributed herewith. Except as -:: otherwise provided in a valid license issued to you by -:: Xilinx, and to the maximum extent permitted by applicable -:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -:: (2) Xilinx shall not be liable (whether in contract or tort, -:: including negligence, or under any other theory of -:: liability) for any loss or damage of any kind or nature -:: related to, arising under or in connection with these -:: materials, including for any direct, or any indirect, -:: special, incidental, or consequential loss or damage -:: (including loss of data, profits, goodwill, or any type of -:: loss or damage suffered as a result of any action brought -:: by a third party) even if such damage or loss was -:: reasonably foreseeable or Xilinx had been advised of the -:: possibility of the same. -:: -:: CRITICAL APPLICATIONS -:: Xilinx products are not designed or intended to be fail- -:: safe, or for use in any application requiring fail-safe -:: performance, such as life-support or safety devices or -:: systems, Class III medical devices, nuclear facilities, -:: applications related to the deployment of airbags, or any -:: other applications that could lead to death, personal -:: injury, or severe property or environmental damage -:: (individually and collectively, "Critical -:: Applications"). Customer assumes the sole risk and -:: liability of any use of Xilinx products in Critical -:: Applications, subject only to applicable laws and -:: regulations governing limitations on product liability. -:: -:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -:: PART OF THIS FILE AT ALL TIMES. -:: -::**************************************************************************** -:: ____ ____ -:: / /\/ / -:: /___/ \ / Vendor : Xilinx -:: \ \ \/ Version : 3.5 -:: \ \ Application : MIG -:: / / Filename : readme.txt -:: /___/ /\ Date Last Modified : $Date: 2010/05/21 09:18:32 $ -:: \ \ / \ Date Created : Fri Feb 06 2009 -:: \___\/\___\ -:: -:: Device : Spartan-6 -:: Design Name : DDR/DDR2/DDR3/LPDDR -:: Purpose : Information about par folder -:: Reference : -:: Revision History : -::**************************************************************************** - -This folder has the batch files to synthesize using XST or Synplify Pro and -implement the design either in "Command Line Mode" or in "GUI Mode". - -Steps to run the design using the ise_flow (batch mode): - -1. Executing the "ise_flow.bat" file synthesizes the design using XST or - Synplify Pro and does implement the design. - a. First it removes the XST/Synplify Pro report files, implementation - files, supporting scripts, the generated chipscope designs (if - enabled) and the ISE project files (if exist any on previous runs) - b. Synthesizes the design either with XST or Synplicity - c. Implements the design with ISE. - -2. After the design is run, it creates ise_flow_results.txt file that will have - the ISE log information. - -Steps to run the design using the create_ise (GUI mode - for XST cases only): - -1. This file will appear for XST cases only. - -2. On executing the "create_ise.bat" file creates "test.xise" project file - and set all the properties of the design selected. - -3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file. - -4. In Linux operating systems, test.xise project can be invoked by executing the command - 'ise test.xise' from the terminal. - -Other files in PAR folder : - -* "mem0.ucf" file is the constraint file for the design. - It has clock constraints, location constraints and IO standards. - -* "mem_interface_top.ut" file has the options for the Configuration file - generation i.e. the "mem0.bit" file to run in batch mode. - -* "rem_files.bat" file has all the ISE/Synplify Pro generated report files, - implementation files, supporting scripts, the generated chipscope designs - (if enabled) and the ISE project files. - -* "set_ise_prop.tcl" file has all the properties that are to be - set in GUI mode. - -* "ise_run.txt" file has synthesis options for the XST tool. - This file is used for batch mode. - -* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to - generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the - EDIF/NGC files, you must execute the following commands before starting - synthesis and PAR. - - coregen -b ila_coregen.xco - coregen -b icon_coregen.xco - coregen -b vio_coregen.xco - -Note : When you generate the design using "Debug Signals for Memory Controller" - option Enable, the above mentioned ChipScope coregen commands are printed - into ise_flow.bat and create_ise.bat files. The mem0 rtl file - will have the design debug signals portmapped to vio and icon - ChipScope modules. - -* At the start of a Chip Scope Analyzer project, all of the signals in - every core have generic names. "mem0.cdc" is a file that contains - all the signal names of all cores. Upon importing this file, signal names are - renamed to the specified names in "mem0.cdc" file. This file will work - for the generated designs from MIG. If any of the design parameter values - are changed after generating the design, this file will not work. - For Multiple Controller designs, signal names provided in CDC file are of - the controller that is enabled for Debug in the GUI. - -synth folder: - -1. mem_interface_top_synp.sdc -2. script_synp.tcl -3. mem0.prj -4. mem0.lso - - mem_interface_top_synp.sdc and script_synp.tcl files are being used by - Synplify Pro and mem0.prj and mem0.lso are being used by XST. - - Index: ipcore_dir/mem0/user_design/par/ise_run.txt =================================================================== --- ipcore_dir/mem0/user_design/par/ise_run.txt (revision 5) +++ ipcore_dir/mem0/user_design/par/ise_run.txt (nonexistent) @@ -1,57 +0,0 @@ -set -tmpdir ../synth/__projnav -set -xsthdpdir ../synth/xst -run -#Source Parameters --ifn ../synth/mem0.prj --ifmt mixed --iuc No -#Target Parameters --ofn mem0 --ofmt NGC --p xc6slx16-2ftg256 -#Source Options --top mem0 --fsm_extract Yes --fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --shreg_extract Yes --resource_sharing Yes --async_to_sync no --mult_style auto --register_balancing No -#Target Options --iobuf Yes -#Max fanout value shouldn't be set below 64 for MCB design --max_fanout 500 --bufg 16 --register_duplication yes --optimize_primitives No --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal yes -#General Options --opt_mode Speed --opt_level 1 --lso ../synth/mem0.lso --keep_hierarchy NO --netlist_hierarchy as_optimized --rtlview Yes --glob_opt allclocknets --read_cores Yes --write_timing_constraints No --cross_clock_analysis No --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --auto_bram_packing No --slice_utilization_ratio_maxmargin 5 -quit Index: ipcore_dir/mem0/user_design/par/set_ise_prop.tcl =================================================================== --- ipcore_dir/mem0/user_design/par/set_ise_prop.tcl (revision 5) +++ ipcore_dir/mem0/user_design/par/set_ise_prop.tcl (nonexistent) @@ -1,89 +0,0 @@ -project new test.xise - -project set "Device Family" "spartan6" - -project set "Device" "xc6slx16" - -project set "Package" "ftg256" - -project set "Speed Grade" "-2" - -project set "Synthesis Tool" "XST (VHDL/Verilog)" - -project set "Simulator" "ISim (VHDL/Verilog)" - -xfile add "../rtl/iodrp_controller.vhd" -xfile add "../rtl/iodrp_mcb_controller.vhd" -xfile add "../rtl/mcb_raw_wrapper.vhd" -xfile add "../rtl/mcb_soft_calibration.vhd" -xfile add "../rtl/mcb_soft_calibration_top.vhd" -xfile add "../rtl/mem0.vhd" -xfile add "../rtl/memc3_infrastructure.vhd" -xfile add "../rtl/memc3_wrapper.vhd" - -xfile add "mem0.ucf" - -project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" -project set "Safe Implementation" "No" -process "Synthesize - XST" -project set "FSM Style" "LUT" -process "Synthesize - XST" -project set "RAM Extraction" "True" -process "Synthesize - XST" -project set "RAM Style" "Auto" -process "Synthesize - XST" -project set "ROM Extraction" "True" -process "Synthesize - XST" -project set "ROM Style" "Auto" -process "Synthesize - XST" -project set "Resource Sharing" "True" -process "Synthesize - XST" -project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST" -project set "Register Balancing" "No" -process "Synthesize - XST" -project set "Add I/O Buffers" "True" -process "Synthesize - XST" -project set "Max Fanout" "500" -process "Synthesize - XST" -project set "Number of Clock Buffers" "8" -process "Synthesize - XST" -project set "Register Duplication" "True" -process "Synthesize - XST" -project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST" -project set "Use Clock Enable" "Yes" -process "Synthesize - XST" -project set "Use Synchronous Set" "Yes" -process "Synthesize - XST" -project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST" -project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" -project set "Equivalent Register Removal" "True" -process "Synthesize - XST" -project set "Optimization Goal" "Speed" -process "Synthesize - XST" -project set "Optimization Effort" "Normal" -process "Synthesize - XST" -project set "Library Search Order" "../synth/mem0.lso" -process "Synthesize - XST" -project set "Keep Hierarchy" "Soft" -process "Synthesize - XST" -project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" -project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" -project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" -project set "Read Cores" "True" -process "Synthesize - XST" -project set "Write Timing Constraints" "False" -process "Synthesize - XST" -project set "Cross Clock Analysis" "False" -process "Synthesize - XST" -project set "Hierarchy Separator" "/" -process "Synthesize - XST" -project set "Bus Delimiter" "<>" -process "Synthesize - XST" -project set "Case" "Maintain" -process "Synthesize - XST" -project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" -project set "Automatic BRAM Packing" "False" -process "Synthesize - XST" -project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map - -project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route" - -project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing" - -project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File" -project set "Create Binary Configuration File" "False" -process "Generate Programming File" -project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File" -project set "Configuration Rate" "6" -process "Generate Programming File" -project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" -project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" -project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" -project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" -project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" -project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" -project set "Unused IOB Pins" "Float" -process "Generate Programming File" -project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" -project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File" -project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" -project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" -project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" -project set "Enable Internal Done Pipe" "False" -process "Generate Programming File" -project set "Drive Done Pin High" "False" -process "Generate Programming File" -project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" - -project close - - Index: ipcore_dir/mem0/user_design/synth/mem0.lso =================================================================== --- ipcore_dir/mem0/user_design/synth/mem0.lso (revision 5) +++ ipcore_dir/mem0/user_design/synth/mem0.lso (nonexistent) @@ -1 +0,0 @@ -work Index: ipcore_dir/mem0/user_design/synth/mem_interface_top_synp.sdc =================================================================== --- ipcore_dir/mem0/user_design/synth/mem_interface_top_synp.sdc (revision 5) +++ ipcore_dir/mem0/user_design/synth/mem_interface_top_synp.sdc (nonexistent) @@ -1,20 +0,0 @@ -# Synplicity, Inc. constraint file -# Written on Mon Jun 27 15:50:39 2005 - -define_attribute {v:work.iodrp_controller} syn_hier {hard} -define_attribute {v:work.iodrp_mcb_controller} syn_hier {hard} -define_attribute {v:work.mcb_raw_wrapper} syn_hier {hard} -define_attribute {v:work.mcb_soft_calibration} syn_hier {hard} -define_attribute {v:work.mcb_soft_calibration_top} syn_hier {hard} -define_attribute {v:work.mem0} syn_hier {hard} -define_attribute {v:work.memc3_infrastructure} syn_hier {hard} -define_attribute {v:work.memc3_wrapper} syn_hier {hard} - -# clock Constraints -define_clock -disable -name {memc3_infrastructure_inst} -period 5000 -clockgroup default_clkgroup_1 -define_clock -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 5000 -clockgroup default_clkgroup_2 -define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 5000 -clockgroup default_clkgroup_3 - - - - Index: ipcore_dir/mem0/user_design/synth/script_synp.tcl =================================================================== --- ipcore_dir/mem0/user_design/synth/script_synp.tcl (revision 5) +++ ipcore_dir/mem0/user_design/synth/script_synp.tcl (nonexistent) @@ -1,39 +0,0 @@ -project -new -add_file -vhdl "../rtl/iodrp_controller.vhd" -add_file -vhdl "../rtl/iodrp_mcb_controller.vhd" -add_file -vhdl "../rtl/mcb_raw_wrapper.vhd" -add_file -vhdl "../rtl/mcb_soft_calibration.vhd" -add_file -vhdl "../rtl/mcb_soft_calibration_top.vhd" -add_file -vhdl "../rtl/mem0.vhd" -add_file -vhdl "../rtl/memc3_infrastructure.vhd" -add_file -vhdl "../rtl/memc3_wrapper.vhd" -add_file -constraint "../synth/mem_interface_top_synp.sdc" -impl -add rev_1 -set_option -technology spartan6 -set_option -part xc6slx16 -set_option -package ftg256 -set_option -speed_grade -2 -set_option -default_enum_encoding default -set_option -symbolic_fsm_compiler 1 -set_option -resource_sharing 0 -set_option -use_fsm_explorer 0 -set_option -top_module "mem0" -set_option -frequency 200 -set_option -fanout_limit 1000 -set_option -disable_io_insertion 0 -set_option -pipe 1 -set_option -fixgatedclocks 0 -set_option -retiming 0 -set_option -modular 0 -set_option -update_models_cp 0 -set_option -verification_mode 0 -set_option -write_verilog 0 -set_option -write_vhdl 0 -set_option -write_apr_constraint 0 -project -result_file "../synth/rev_1/mem0.edf" -set_option -vlog_std v2001 -set_option -auto_constrain_io 0 -impl -active "../synth/rev_1" -project -run -project -save -

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