URL
https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk
Subversion Repositories usb_fpga_1_11
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb_fpga_1_11/trunk/examples/usb-fpga-1.11/1.11b/memtest/fpga
- from Rev 7 to Rev 9
- ↔ Reverse comparison
Rev 7 → Rev 9
/ipcore_dir/mem0.xise
File deleted
/ipcore_dir/mem0.xco
File deleted
/ipcore_dir/dcm0.xise
File deleted
/ipcore_dir/dcm0.xco
File deleted
/ipcore_dir/clean.sh
File deleted
ipcore_dir/clean.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/synth/mem0.prj
===================================================================
--- ipcore_dir/mem0/user_design/synth/mem0.prj (revision 7)
+++ ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent)
@@ -1,8 +0,0 @@
-vhdl work ../rtl/iodrp_controller.vhd
-vhdl work ../rtl/iodrp_mcb_controller.vhd
-vhdl work ../rtl/mcb_raw_wrapper.vhd
-vhdl work ../rtl/mcb_soft_calibration.vhd
-vhdl work ../rtl/mcb_soft_calibration_top.vhd
-vhdl work ../rtl/mem0.vhd
-vhdl work ../rtl/memc3_infrastructure.vhd
-vhdl work ../rtl/memc3_wrapper.vhd
Index: ipcore_dir/mem0/user_design/mig.prj
===================================================================
--- ipcore_dir/mem0/user_design/mig.prj (revision 7)
+++ ipcore_dir/mem0/user_design/mig.prj (nonexistent)
@@ -1,53 +0,0 @@
-
-
- mem0
- xc6slx16-ftg256/-2
- 3.5
-
- DDR_SDRAM/Components/MT46V32M16XX-5B-IT
- 5000
- 0
- 1
- FALSE
-
- 13
- 10
- 2
-
-
-
- 4(010)
- 3
- Enable-Normal
- Normal
- Class II
- Class II
- UNCALIB_TERM
- 50 Ohms
-
-
-
- 1
- Disable
- Single-Ended
- Two 32-bit bi-directional and four 32-bit unidirectional ports
- M4
- M5
- Port0,Port1,Port2,Port3,Port4,Port5
- Bi-directional,Bi-directional,Write,Read,Write,Read
- ROW_BANK_COLUMN
- Round Robin
- 012345
- 123450
- 234501
- 345012
- 450123
- 501234
- 012345
- 123450
- 234501
- 345012
- 450123
- 501234
-
-
Index: ipcore_dir/mem0/user_design/clean.sh
===================================================================
--- ipcore_dir/mem0/user_design/clean.sh (revision 7)
+++ ipcore_dir/mem0/user_design/clean.sh (nonexistent)
@@ -1,85 +0,0 @@
-#!/bin/bash
-
-# This files / directories from this directory will not be removed
-# Filenames with spaces or other spuid characters will be ignored
-sourcefiles="*.sh *.prj"
-subdirs="par rtl synth"
-
-# This sould not be edited.
-list_files() {
- if [ "$2" != "" ]; then
- echo "$1"
- for i in $2; do
- echo " $i"
- done
- fi
-}
-
-rmfiles=""
-rmdirs=""
-keepfiles=""
-keepdirs=""
-allfiles=`ls -A`
-for f in $allfiles; do
- keep=false
- for i in $sourcefiles; do
- if [ "$i" == "$f" ]; then
- keep=true
- fi
- done
- for i in $subdirs; do
- if [ "$i" == "$f" ]; then
- keep=true
- fi
- done
- for i in $binfiles; do # binfiles is set by distclean.sh
- if [ "$i" == "$f" ]; then
- keep=false
- fi
- done
- if [ -d "$f" ]; then
- if $keep; then
- keepdirs+=" $f"
- else
- rmdirs+=" $f"
- fi
- fi
- if [ -f "$f" ]; then
- if $keep; then
- keepfiles+=" $f"
- else
- rmfiles+=" $f"
- fi
- fi
-done
-
-
-echo
-echo "Directory $PWD:"
-list_files "This directories will NOT be removed:" "$keepdirs"
-list_files "This files will NOT be removed:" "$keepfiles"
-list_files "This directories will be removed:" "$rmdirs"
-list_files "This files will be removed:" "$rmfiles"
-
-if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
- c="yes"
-else
- echo -n 'Confirm this by entering "yes": '
- read c
-fi
-
-if [ "$c" == "yes" ]; then
- [ "$rmfiles" != "" ] && rm $rmfiles
- [ "$rmdirs" != "" ] && rm -r $rmdirs
-
- for d in $subdirs; do
- if [ -x "$d/clean.sh" ]; then
- cd $d
- ./clean.sh || exit 1
- cd ..
- fi
- done
-
- exit 0
-fi
-exit 1
ipcore_dir/mem0/user_design/clean.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff
===================================================================
--- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 7)
+++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent)
@@ -1,61 +0,0 @@
---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200
-+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200
-@@ -122,7 +122,6 @@
- signal mcb_drp_clk_bufg_in : std_logic;
- signal clkfbout_clkfbin : std_logic;
- signal rst_tmp : std_logic;
-- signal sys_clk_ibufg : std_logic;
- signal sys_rst : std_logic;
- signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
- signal powerup_pll_locked : std_logic;
-@@ -135,7 +134,6 @@
- attribute KEEP : string;
- attribute max_fanout of rst0_sync_r : signal is "10";
- attribute syn_maxfan of rst0_sync_r : signal is 10;
-- attribute KEEP of sys_clk_ibufg : signal is "TRUE";
-
- begin
-
-@@ -144,33 +142,6 @@
- pll_lock <= bufpll_mcb_locked;
- mcb_drp_clk <= mcb_drp_clk_sig;
-
-- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
-- --***********************************************************************
-- -- Differential input clock input buffers
-- --***********************************************************************
-- u_ibufg_sys_clk : IBUFGDS
-- generic map (
-- DIFF_TERM => TRUE
-- )
-- port map (
-- I => sys_clk_p,
-- IB => sys_clk_n,
-- O => sys_clk_ibufg
-- );
-- end generate;
--
--
-- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
-- --***********************************************************************
-- -- SINGLE_ENDED input clock input buffers
-- --***********************************************************************
-- u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
-- end generate;
--
- --***************************************************************************
- -- Global clock generation and distribution
- --***************************************************************************
-@@ -209,7 +180,7 @@
- (
- CLKFBIN => clkfbout_clkfbin,
- CLKINSEL => '1',
-- CLKIN1 => sys_clk_ibufg,
-+ CLKIN1 => sys_clk,
- CLKIN2 => '0',
- DADDR => (others => '0'),
- DCLK => '0',
Index: ipcore_dir/mem0/user_design/par/ise_flow.sh
===================================================================
--- ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 7)
+++ ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent)
@@ -1,86 +0,0 @@
-#!/bin/csh -f
-#*****************************************************************************
-# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# ****************************************************************************
-# ____ ____
-# / /\/ /
-# /___/ \ / Vendor : Xilinx
-# \ \ \/ Version : 3.5
-# \ \ Application : MIG
-# / / Filename : ise_flow.bat
-# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $
-# \ \ / \ Date Created : Fri Feb 06 2009
-# \___\/\___\
-#
-# Device : Spartan-6
-# Design Name : DDR/DDR2/DDR3/LPDDR
-# Purpose : Batch file to run PAR through ISE batch mode
-# Reference :
-# Revision History :
-# ****************************************************************************
-
-./rem_files.sh
-
-
-
-
-echo Synthesis Tool: XST
-
-mkdir "../synth/__projnav" > ise_flow_results.txt
-mkdir "../synth/xst" >> ise_flow_results.txt
-mkdir "../synth/xst/work" >> ise_flow_results.txt
-
-xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
-ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx16ftg256-2 mem0.ngc mem0.ngd >> ise_flow_results.txt
-
-map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt
-par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt
-trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt
-bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt
-
-echo done!
ipcore_dir/mem0/user_design/par/ise_flow.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/par/makeproj.sh
===================================================================
--- ipcore_dir/mem0/user_design/par/makeproj.sh (revision 7)
+++ ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent)
@@ -1,2 +0,0 @@
-NEWPROJECT .
-SETPROJECT .
ipcore_dir/mem0/user_design/par/makeproj.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/par/icon_coregen.xco
===================================================================
--- ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 7)
+++ ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent)
@@ -1,48 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 11.1
-# Date: Wed Mar 11 07:09:11 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = True
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = vhdl
-SET device = xc6slx16
-SET devicefamily = spartan6
-SET flowvendor = ISE
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = ftg256
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -2
-SET verilogsim = False
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
-# END Select
-# BEGIN Parameters
-CSET component_name=icon
-CSET enable_jtag_bufg=true
-CSET number_control_ports=2
-CSET use_ext_bscan=false
-CSET use_softbscan=false
-CSET use_unused_bscan=false
-CSET user_scan_chain=USER1
-# END Parameters
-GENERATE
-# CRC: 7da1f376
-
Index: ipcore_dir/mem0/user_design/par/vio_coregen.xco
===================================================================
--- ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 7)
+++ ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent)
@@ -1,51 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 11.2
-# Date: Fri Jun 12 05:42:56 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = vhdl
-SET device = xc6slx16
-SET devicefamily = spartan6
-SET flowvendor = ISE
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = ftg256
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -2
-SET verilogsim = False
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
-# END Select
-# BEGIN Parameters
-CSET asynchronous_input_port_width=8
-CSET asynchronous_output_port_width=7
-CSET component_name=vio
-CSET enable_asynchronous_input_port=false
-CSET enable_asynchronous_output_port=true
-CSET enable_synchronous_input_port=false
-CSET enable_synchronous_output_port=false
-CSET invert_clock_input=false
-CSET synchronous_input_port_width=8
-CSET synchronous_output_port_width=8
-# END Parameters
-GENERATE
-# CRC: 66fe39ed
-
Index: ipcore_dir/mem0/user_design/par/create_ise.sh
===================================================================
--- ipcore_dir/mem0/user_design/par/create_ise.sh (revision 7)
+++ ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent)
@@ -1,72 +0,0 @@
-#!/bin/csh -f
-#*****************************************************************************
-# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# ****************************************************************************
-# ____ ____
-# / /\/ /
-# /___/ \ / Vendor : Xilinx
-# \ \ \/ Version : 3.5
-# \ \ Application : MIG
-# / / Filename : create_ise.bat
-# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:15 $
-# \ \ / \ Date Created : Fri Feb 06 2009
-# \___\/\___\
-#
-# Device : Spartan-6
-# Design Name : DDR/DDR2/DDR3/LPDDR
-# Purpose : Batch file to run PAR through ISE
-# Reference :
-# Revision History :
-# ****************************************************************************
-
-./rem_files.sh
-
-
-
-
-xtclsh set_ise_prop.tcl
ipcore_dir/mem0/user_design/par/create_ise.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/par/rem_files.sh
===================================================================
--- ipcore_dir/mem0/user_design/par/rem_files.sh (revision 7)
+++ ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent)
@@ -1,169 +0,0 @@
-##!/bin/csh -f
-##****************************************************************************
-## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##****************************************************************************
-## ____ ____
-## / /\/ /
-## /___/ \ / Vendor : Xilinx
-## \ \ \/ Version : 3.5
-## \ \ Application : MIG
-## / / Filename : rem_files.bat
-## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $
-## \ \ / \ Date Created : Fri Feb 06 2009
-## \___\/\___\
-##
-## Device : Spartan-6
-## Design Name : DDR/DDR2/DDR3/LPDDR
-## Purpose : Batch file to remove files generated from ISE
-## Reference :
-## Revision History :
-##****************************************************************************
-
-rm -rf "../synth/__projnav"
-rm -rf "../synth/xst"
-rm -rf "../synth/_ngo"
-
-rm -rf tmp
-rm -rf _xmsgs
-rm -rf ila_xdb
-rm -rf icon_xdb
-rm -rf vio_xdb
-
-rm -rf xlnx_auto_0_xdb
-
-rm -rf vio_xmdf.tcl
-rm -rf vio_readme.txt
-rm -rf vio_flist.txt
-rm -rf vio.xise del
-rm -rf vio.xco del
-rm -rf vio.ngc del
-rm -rf vio.ise del
-rm -rf vio.gise del
-rm -rf vio.cdc del
-
-rm -rf coregen.cgp
-rm -rf coregen.cgc
-rm -rf coregen.log
-rm -rf ila.cdc
-rm -rf ila.gise
-rm -rf ila.ise
-rm -rf ila.ngc
-rm -rf ila.xco
-rm -rf ila.xise
-rm -rf ila_flist.txt
-rm -rf ila_readme.txt
-rm -rf ila_xmdf.tcl
-
-rm -rf icon.asy
-rm -rf icon.gise
-rm -rf icon.ise
-rm -rf icon.ncf
-rm -rf icon.ngc
-rm -rf icon.xco
-rm -rf icon.xise
-rm -rf icon_flist.txt
-rm -rf icon_readme.txt
-rm -rf icon_xmdf.tcl
-
-rm -rf ise_flow_results.txt
-rm -rf mem0_vhdl.prj
-rm -rf mem_interface_top.syr
-rm -rf mem0.ngc
-rm -rf mem0.ngr
-rm -rf mem0_xst.xrpt
-rm -rf mem0.bld
-rm -rf mem0.ngd
-rm -rf mem0_ngdbuild.xrpt
-rm -rf mem0_map.map
-rm -rf mem0_map.mrp
-rm -rf mem0_map.ngm
-rm -rf mem0.pcf
-rm -rf mem0_map.ncd
-rm -rf mem0_map.xrpt
-rm -rf mem0_summary.xml
-rm -rf mem0_usage.xml
-rm -rf mem0.ncd
-rm -rf mem0.par
-rm -rf mem0.xpi
-rm -rf mem0.ptwx
-rm -rf mem0.pad
-rm -rf mem0.unroutes
-rm -rf mem0_pad.csv
-rm -rf mem0_pad.txt
-rm -rf mem0_par.xrpt
-rm -rf mem0.twx
-rm -rf mem0.bgn
-rm -rf mem0.twr
-rm -rf mem0.drc
-rm -rf mem0_bitgen.xwbt
-rm -rf mem0.bit
-
-# Files and folders generated by create ise
-rm -rf test_xdb
-rm -rf _xmsgs
-rm -rf test.gise
-rm -rf test.xise
-rm -rf test.xise
-
-# Files and folders generated by ISE through GUI mode
-rm -rf _ngo
-rm -rf xst
-rm -rf mem0.lso
-rm -rf mem0.prj
-rm -rf mem0.xst
-rm -rf mem0.stx
-rm -rf mem0_prev_built.ngd
-rm -rf test.ntrc_log
-rm -rf mem0_guide.ncd
-rm -rf mem0.cmd_log
-rm -rf mem0_summary.html
-rm -rf mem0.ut
-rm -rf par_usage_statistics.html
-rm -rf usage_statistics_webtalk.html
-rm -rf webtalk.log
-rm -rf device_usage_statistics.html
ipcore_dir/mem0/user_design/par/rem_files.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/par/ila_coregen.xco
===================================================================
--- ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 7)
+++ ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent)
@@ -1,131 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 11.1
-# Date: Wed Mar 11 06:55:40 2009
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = vhdl
-SET device = xc6slx16
-SET devicefamily = spartan6
-SET flowvendor = ISE
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = ftg256
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -2
-SET verilogsim = False
-SET vhdlsim = False
-# END Project Options
-# BEGIN Select
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
-# END Select
-# BEGIN Parameters
-CSET component_name=ila
-CSET counter_width_1=Disabled
-CSET counter_width_10=Disabled
-CSET counter_width_11=Disabled
-CSET counter_width_12=Disabled
-CSET counter_width_13=Disabled
-CSET counter_width_14=Disabled
-CSET counter_width_15=Disabled
-CSET counter_width_16=Disabled
-CSET counter_width_2=Disabled
-CSET counter_width_3=Disabled
-CSET counter_width_4=Disabled
-CSET counter_width_5=Disabled
-CSET counter_width_6=Disabled
-CSET counter_width_7=Disabled
-CSET counter_width_8=Disabled
-CSET counter_width_9=Disabled
-CSET data_port_width=256
-CSET data_same_as_trigger=false
-CSET enable_storage_qualification=true
-CSET enable_trigger_output_port=false
-CSET exclude_from_data_storage_1=true
-CSET exclude_from_data_storage_10=true
-CSET exclude_from_data_storage_11=true
-CSET exclude_from_data_storage_12=true
-CSET exclude_from_data_storage_13=true
-CSET exclude_from_data_storage_14=true
-CSET exclude_from_data_storage_15=true
-CSET exclude_from_data_storage_16=true
-CSET exclude_from_data_storage_2=true
-CSET exclude_from_data_storage_3=true
-CSET exclude_from_data_storage_4=true
-CSET exclude_from_data_storage_5=true
-CSET exclude_from_data_storage_6=true
-CSET exclude_from_data_storage_7=true
-CSET exclude_from_data_storage_8=true
-CSET exclude_from_data_storage_9=true
-CSET match_type_1=basic_with_edges
-CSET match_type_10=basic
-CSET match_type_11=basic
-CSET match_type_12=basic
-CSET match_type_13=basic
-CSET match_type_14=basic
-CSET match_type_15=basic
-CSET match_type_16=basic
-CSET match_type_2=basic
-CSET match_type_3=basic
-CSET match_type_4=basic
-CSET match_type_5=basic
-CSET match_type_6=basic
-CSET match_type_7=basic
-CSET match_type_8=basic
-CSET match_type_9=basic
-CSET match_units_1=1
-CSET match_units_10=1
-CSET match_units_11=1
-CSET match_units_12=1
-CSET match_units_13=1
-CSET match_units_14=1
-CSET match_units_15=1
-CSET match_units_16=1
-CSET match_units_2=1
-CSET match_units_3=1
-CSET match_units_4=1
-CSET match_units_5=1
-CSET match_units_6=1
-CSET match_units_7=1
-CSET match_units_8=1
-CSET match_units_9=1
-CSET max_sequence_levels=1
-CSET number_of_trigger_ports=1
-CSET sample_data_depth=1024
-CSET sample_on=Rising
-CSET trigger_port_width_1=2
-CSET trigger_port_width_10=8
-CSET trigger_port_width_11=8
-CSET trigger_port_width_12=8
-CSET trigger_port_width_13=8
-CSET trigger_port_width_14=8
-CSET trigger_port_width_15=8
-CSET trigger_port_width_16=8
-CSET trigger_port_width_2=8
-CSET trigger_port_width_3=8
-CSET trigger_port_width_4=8
-CSET trigger_port_width_5=8
-CSET trigger_port_width_6=8
-CSET trigger_port_width_7=8
-CSET trigger_port_width_8=8
-CSET trigger_port_width_9=8
-CSET use_rpms=true
-# END Parameters
-GENERATE
-# CRC: eff89f81
-
Index: ipcore_dir/mem0/clean.sh
===================================================================
--- ipcore_dir/mem0/clean.sh (revision 7)
+++ ipcore_dir/mem0/clean.sh (nonexistent)
@@ -1,86 +0,0 @@
-#!/bin/bash
-
-# This files / directories from this directory will not be removed
-# Filenames with spaces or other spuid characters will be ignored
-sourcefiles="*.sh"
-subdirs="user_design"
-
-
-# This sould not be edited.
-list_files() {
- if [ "$2" != "" ]; then
- echo "$1"
- for i in $2; do
- echo " $i"
- done
- fi
-}
-
-rmfiles=""
-rmdirs=""
-keepfiles=""
-keepdirs=""
-allfiles=`ls -A`
-for f in $allfiles; do
- keep=false
- for i in $sourcefiles; do
- if [ "$i" == "$f" ]; then
- keep=true
- fi
- done
- for i in $subdirs; do
- if [ "$i" == "$f" ]; then
- keep=true
- fi
- done
- for i in $binfiles; do # binfiles is set by distclean.sh
- if [ "$i" == "$f" ]; then
- keep=false
- fi
- done
- if [ -d "$f" ]; then
- if $keep; then
- keepdirs+=" $f"
- else
- rmdirs+=" $f"
- fi
- fi
- if [ -f "$f" ]; then
- if $keep; then
- keepfiles+=" $f"
- else
- rmfiles+=" $f"
- fi
- fi
-done
-
-
-echo
-echo "Directory $PWD:"
-list_files "This directories will NOT be removed:" "$keepdirs"
-list_files "This files will NOT be removed:" "$keepfiles"
-list_files "This directories will be removed:" "$rmdirs"
-list_files "This files will be removed:" "$rmfiles"
-
-if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
- c="yes"
-else
- echo -n 'Confirm this by entering "yes": '
- read c
-fi
-
-if [ "$c" == "yes" ]; then
- [ "$rmfiles" != "" ] && rm $rmfiles
- [ "$rmdirs" != "" ] && rm -r $rmdirs
-
- for d in $subdirs; do
- if [ -x "$d/clean.sh" ]; then
- cd $d
- ./clean.sh || exit 1
- cd ..
- fi
- done
-
- exit 0
-fi
-exit 1
ipcore_dir/mem0/clean.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/dcm0.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ipcore_dir/dcm0.ise
===================================================================
--- ipcore_dir/dcm0.ise (revision 7)
+++ ipcore_dir/dcm0.ise (nonexistent)
ipcore_dir/dcm0.ise
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property