URL
https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk
Subversion Repositories usb_fpga_1_11
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- This comparison shows the changes necessary to convert path
/usb_fpga_1_11/trunk/examples/usb-fpga-1.11/1.11c/memtest/fpga
- from Rev 5 to Rev 7
- ↔ Reverse comparison
Rev 5 → Rev 7
/memtest.bit
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memtest.bit
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
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Index: ipcore_dir/mem0_xmdf.tcl
===================================================================
--- ipcore_dir/mem0_xmdf.tcl (revision 5)
+++ ipcore_dir/mem0_xmdf.tcl (nonexistent)
@@ -1,78 +0,0 @@
-# The package naming convention is _xmdf
-package provide mem0_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is _xmdf
-namespace eval ::mem0_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::mem0_xmdf::xmdfInit { instance } {
- # Variable containing name of library into which module is compiled
- # Recommendation:
- # Required
- utilities_xmdf::xmdfSetData $instance Module Attributes Name mem0
-}
-# ::mem0_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::mem0_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
- # Array containing libraries that are assumed to exist
- # Examples include unisim and xilinxcorelib
- # Optional
- # In this example, we assume that the unisim library will
- # be magically
- # available to the simulation and synthesis tool
- utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
- utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
- incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/iodrp_controller.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/iodrp_mcb_controller.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mcb_raw_wrapper.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mcb_soft_calibration.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mcb_soft_calibration_top.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/mem0.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/memc3_infrastructure.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/rtl/memc3_wrapper.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem0/user_design/par/mem0.ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module mem0
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
Index: ipcore_dir/dcm0_xmdf.tcl
===================================================================
--- ipcore_dir/dcm0_xmdf.tcl (revision 5)
+++ ipcore_dir/dcm0_xmdf.tcl (nonexistent)
@@ -1,160 +0,0 @@
-# The package naming convention is _xmdf
-package provide dcm0_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is _xmdf
-namespace eval ::dcm0_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::dcm0_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation:
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name dcm0
-}
-# ::dcm0_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::dcm0_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/clk_wiz_readme.txt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/dcm0.ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/doc/clk_wiz_ds709.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/doc/clk_wiz_gsg521.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/example_design/dcm0_exdes.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/example_design/dcm0_exdes.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/implement.bat
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/implement.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/xst.prj
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/implement/xst.scr
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/dcm0_tb.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/dcm0_tb.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simcmds.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_isim.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_mti.do
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_ncsim.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/simulate_vcs.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/ucli_commands.key
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/vcs_session.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/wave.do
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0/simulation/functional/wave.sv
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.ejp
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.vho
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dcm0_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module dcm0
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
Index: ipcore_dir/dcm0.vhd
===================================================================
--- ipcore_dir/dcm0.vhd (revision 5)
+++ ipcore_dir/dcm0.vhd (nonexistent)
@@ -1,160 +0,0 @@
--- file: dcm0.vhd
---
--- DISCLAIMER OF LIABILITY
---
--- This file contains proprietary and confidential information of
--- Xilinx, Inc. ("Xilinx"), that is distributed under a license
--- from Xilinx, and may be used, copied and/or disclosed only
--- pursuant to the terms of a valid license agreement with Xilinx.
---
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
--- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
--- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
--- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
--- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
--- does not warrant that functions included in the Materials will
--- meet the requirements of Licensee, or that the operation of the
--- Materials will be uninterrupted or error-free, or that defects
--- in the Materials will be corrected. Furthermore, Xilinx does
--- not warrant or make any representations regarding use, or the
--- results of the use, of the Materials in terms of correctness,
--- accuracy, reliability or otherwise.
---
--- Xilinx products are not designed or intended to be fail-safe,
--- or for use in any application requiring fail-safe performance,
--- such as life-support or safety devices or systems, Class III
--- medical devices, nuclear facilities, applications related to
--- the deployment of airbags, or any other applications that could
--- lead to death, personal injury or severe property or
--- environmental damage (individually and collectively, "critical
--- applications"). Customer assumes the sole risk and liability
--- of any use of Xilinx products in critical applications,
--- subject only to applicable laws and regulations governing
--- limitations on product liability.
---
--- Copyright 2008, 2009 Xilinx, Inc.
--- All rights reserved.
---
--- This disclaimer and copyright notice must be retained as part
--- of this file at all times.
---
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- Output Output Phase Duty Cycle Pk-to-Pk Phase
--- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
--- CLK_OUT1 200.000 0.000 N/A 217.125 N/A
--- CLK_OUT2 50.000 0.000 N/A 207.125 N/A
---
-------------------------------------------------------------------------------
--- Input Clock Input Freq (MHz) Input Jitter (UI)
-------------------------------------------------------------------------------
--- primary 48.000 0.010
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity dcm0 is
-port
- (-- Clock in ports
- CLK_IN1 : in std_logic;
- -- Clock out ports
- CLK_OUT1 : out std_logic;
- CLK_OUT2 : out std_logic;
- -- Status and control signals
- RESET : in std_logic;
- LOCKED : out std_logic;
- CLK_VALID : out std_logic
- );
-end dcm0;
-
-architecture xilinx of dcm0 is
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm0,clk_wiz_v1_4,{component_name=dcm0,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,diff_ext_feedback=false,primtype_sel=DCM_CLKGEN,num_out_clk=2,clkin1_period=20.83333,clkin2_period=20.83333,use_power_down=false}";
- -- Input clock buffering / unused connectors
- signal clkin1 : std_logic;
- -- Output clock buffering / unused connectors
- signal clkfx : std_logic;
- signal clkfx180_unused : std_logic;
- signal clkfxdv : std_logic;
- signal clkfbout : std_logic;
- -- Dynamic programming unused signals
- signal progdone_unused : std_logic;
- signal locked_internal : std_logic;
- signal status_internal : std_logic_vector(2 downto 1);
-
-begin
-
-
- -- Input buffering
- --------------------------------------
- clkin1_buf : IBUFG
- port map
- (O => clkin1,
- I => CLK_IN1);
-
-
- -- Clocking primitive
- --------------------------------------
- -- Instantiation of the DCM primitive
- -- * Unused inputs are tied off
- -- * Unused outputs are labeled unused
- dcm_clkgen_inst: DCM_CLKGEN
- generic map
- (CLKFXDV_DIVIDE => 4,
- CLKFX_DIVIDE => 6,
- CLKFX_MULTIPLY => 25,
- SPREAD_SPECTRUM => "NONE",
- STARTUP_WAIT => FALSE,
- CLKIN_PERIOD => 20.83333,
- CLKFX_MD_MAX => 0.000)
- port map
- -- Input clock
- (CLKIN => clkin1,
- -- Output clocks
- CLKFX => clkfx,
- CLKFX180 => clkfx180_unused,
- CLKFXDV => clkfxdv,
- -- Ports for dynamic phase shift
- PROGCLK => '0',
- PROGEN => '0',
- PROGDATA => '0',
- PROGDONE => progdone_unused,
- -- Other control and status signals
- FREEZEDCM => '0',
- LOCKED => locked_internal,
- STATUS => status_internal,
- RST => RESET);
-
- LOCKED <= locked_internal;
- CLK_VALID <= ( locked_internal and ( not status_internal(2) ) );
-
- -- Output buffering
- -------------------------------------
-
-
- clkout1_buf : AUTOBUF
- generic map
- (BUFFER_TYPE => "BUFG")
- port map
- (O => CLK_OUT1,
- I => clkfx);
-
-
- clkout2_buf : AUTOBUF
- generic map
- (BUFFER_TYPE => "BUFG")
- port map
- (O => CLK_OUT2,
- I => clkfxdv);
-end xilinx;
ipcore_dir/dcm0.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/datasheet.txt
===================================================================
--- ipcore_dir/mem0/user_design/datasheet.txt (revision 5)
+++ ipcore_dir/mem0/user_design/datasheet.txt (nonexistent)
@@ -1,64 +0,0 @@
-
-
-CORE Generator Options:
- Target Device : xc6slx25-ftg256
- Speed Grade : -3
- HDL : vhdl
- Synthesis Tool : ISE
-
-MIG Output Options:
- Component Name : mem0
- No of Controllers : 1
- Hardware Test Bench : disabled
-
-
-/*******************************************************/
-/* Controller 3 */
-/*******************************************************/
-Controller Options :
- Memory : DDR_SDRAM
- Design Clock Frequency : 5000 ps (200.00 MHz)
- Memory Type : Components
- Memory Part : MT46V32M16XX-5B-IT
- Equivalent Part(s) : MT46V32M16BN-5B-IT
- Row Address : 13
- Bank Address : 2
- Data Mask : enabled
-
-Memory Options :
- Mode Register :
- Burst Length : 4(010)
- CAS Latency : 3
- DLL Enable : Enable-Normal
- Output Drive Strength : Normal
-
-User Interface Parameters :
- Configuration Type : Two 32-bit bi-directional and four 32-bit unidirectional ports
- Ports Selected : Port0, Port1, Port2, Port3, Port4, Port5
- Memory Address Mapping : ROW_BANK_COLUMN
-
- Arbitration Algorithm : Round Robin
-
- Arbitration :
- Time Slot0 : 012345
- Time Slot1 : 123450
- Time Slot2 : 234501
- Time Slot3 : 345012
- Time Slot4 : 450123
- Time Slot5 : 501234
- Time Slot6 : 012345
- Time Slot7 : 123450
- Time Slot8 : 234501
- Time Slot9 : 345012
- Time Slot10: 450123
- Time Slot11: 501234
-
-FPGA Options :
- Class for Address and Control : II
- Class for Data : II
- Memory Interface Pin Termination : UNCALIB_TERM
- DQ/DQS : 50 Ohms
- Bypass Calibration : enabled
- Debug Signals for Memory Controller : Disable
- Input Clock Type : Single-Ended
-
\ No newline at end of file
Index: ipcore_dir/mem0/user_design/sim/cmd_prbs_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/cmd_prbs_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/cmd_prbs_gen.vhd (nonexistent)
@@ -1,247 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: cmd_prbs_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:07 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This moduel use LFSR to generate random address, isntructions
--- or burst_length.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-
-ENTITY cmd_prbs_gen IS
- GENERIC (
- TCQ : time := 100 ps;
- FAMILY : STRING := "SPARTAN6";
- ADDR_WIDTH : INTEGER := 29;
- DWIDTH : INTEGER := 32;
- PRBS_CMD : STRING := "ADDRESS";
- PRBS_WIDTH : INTEGER := 64;
- SEED_WIDTH : INTEGER := 32;
-
- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
- PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- prbs_seed_init : IN STD_LOGIC;
- clk_en : IN STD_LOGIC;
- prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
-
- prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
- );
-END cmd_prbs_gen;
-
-ARCHITECTURE trans OF cmd_prbs_gen IS
- SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
- SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
-
- function logb2 (val : integer) return integer is
- variable vec_con : integer;
- variable rtn : integer := 1;
- begin
- vec_con := val;
- for index in 0 to 31 loop
- if(vec_con = 1) then
- rtn := rtn + 1;
- return(rtn);
- end if;
- vec_con := vec_con/2;
- rtn := rtn + 1;
- end loop;
- end function logb2;
-
-
-BEGIN
-
- ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
-
- xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (prbs_seed_init = '1') THEN
- lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
- ELSIF (clk_en = '1') THEN
- lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
- lfsr_q(63) <= lfsr_q(62) ;
- lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
-
- lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
-
- lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
- lfsr_q(1) <= lfsr_q(64) ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (lfsr_q(32 DOWNTO 1))
- BEGIN
- prbs <= lfsr_q(32 DOWNTO 1);
- END PROCESS;
-
- END GENERATE;
-
-
- xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (prbs_seed_init = '1') THEN
- lfsr_q <= prbs_seed_i ;
- ELSIF (clk_en = '1') THEN
-
- lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
- lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
- lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
-
- lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
- lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
- lfsr_q(2) <= lfsr_q(1) ;
-
- lfsr_q(1) <= lfsr_q(32) ;
- END IF;
- END IF;
- END PROCESS;
-
-
-
- PROCESS (lfsr_q(32 DOWNTO 1))
- BEGIN
-
- IF (FAMILY = "SPARTAN6") THEN
- FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
- IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
- prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
- ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
- prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
- ELSE
- prbs(i) <= lfsr_q(i + 1);
- END IF;
- END LOOP;
- prbs(logb2(DWIDTH) downto 0) <= (others => '0');
- ELSE
- FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
- IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
- prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
- ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
- prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
- ELSE
- prbs(i) <= lfsr_q(i + 1);
- END IF;
- END LOOP;
- prbs(logb2(DWIDTH) downto 0) <= (others => '0');
- END IF;
-
- END PROCESS;
-
-
- END GENERATE;
-
-
- xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (prbs_seed_init = '1') THEN
- lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
- ELSIF (clk_en = '1') THEN
-
- lfsr_q(20) <= lfsr_q(19) ;
-
- lfsr_q(19) <= lfsr_q(18) ;
-
- lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
- lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
-
- lfsr_q(1) <= lfsr_q(20) ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
- BEGIN
- prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
- END PROCESS;
-
-
- END GENERATE;
-
- prbs_o <= prbs;
-
-END trans;
-
-
-
ipcore_dir/mem0/user_design/sim/cmd_prbs_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/afifo.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/afifo.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/afifo.vhd (nonexistent)
@@ -1,280 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: afifo.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:07 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: A generic synchronous fifo.
--- Reference:
--- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- use ieee.numeric_std.all;
-
-
-
-ENTITY afifo IS
- GENERIC (
- TCQ : TIME := 100 ps;
- DSIZE : INTEGER := 32;
- FIFO_DEPTH : INTEGER := 16;
- ASIZE : INTEGER := 4;
- SYNC : INTEGER := 1
- );
- PORT (
- wr_clk : IN STD_LOGIC;
- rst : IN STD_LOGIC;
- wr_en : IN STD_LOGIC;
- wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
- rd_en : IN STD_LOGIC;
- rd_clk : IN STD_LOGIC;
- rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
- full : OUT STD_LOGIC;
- empty : OUT STD_LOGIC;
- almost_full : OUT STD_LOGIC
- );
-END afifo;
-
-ARCHITECTURE trans OF afifo IS
- TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
-
-
-
- SIGNAL mem : mem_array;
-
- SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-
- SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
- SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
-
- SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL i : INTEGER;
- SIGNAL j : INTEGER;
- SIGNAL k : INTEGER;
-
- SIGNAL rd_strobe : STD_LOGIC;
-
- SIGNAL n : INTEGER;
- SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-
- SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
- SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-
- -- Declare intermediate signals for referenced outputs
- SIGNAL full_xhdl1 : STD_LOGIC;
- SIGNAL almost_full_int : STD_LOGIC;
- SIGNAL empty_xhdl0 : STD_LOGIC;
-BEGIN
- -- Drive referenced outputs
- ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
- ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
-
- full <= full_xhdl1;
- empty <= empty_xhdl0;
- xhdl3 : IF (SYNC = 1) GENERATE
- PROCESS (rd_ptr)
- BEGIN
- rd_capture_ptr <= rd_ptr;
- END PROCESS;
- END GENERATE;
-
-
-
-
- xhdl4 : IF (SYNC = 1) GENERATE
- PROCESS (wr_ptr)
- BEGIN
- wr_capture_ptr <= wr_ptr;
- END PROCESS;
- END GENERATE;
-
- wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
- rd_data <= mem(conv_integer(rd_addr));
-
-
-
- PROCESS (wr_clk)
- BEGIN
- IF (wr_clk'EVENT AND wr_clk = '1') THEN
- IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
- mem(to_integer(unsigned(wr_addr))) <= wr_data;
- END IF;
- END IF;
- END PROCESS;
-
- rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
- rd_strobe <= rd_en AND NOT(empty_xhdl0);
- PROCESS (rd_ptr)
- BEGIN
- rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
- FOR n IN 0 TO ASIZE - 1 LOOP
- rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
- END LOOP;
- END PROCESS;
-
- PROCESS (rd_clk)
- BEGIN
- IF (rd_clk'EVENT AND rd_clk = '1') THEN
- IF (rst = '1') THEN
- rd_ptr <= (others=> '0');
- rd_gray <= (others=> '0');
- ELSE
- IF (rd_strobe = '1') THEN
- rd_ptr <= rd_ptr + 1;
- END IF;
- rd_ptr_tmp <= rd_ptr;
- rd_gray <= rd_gray_nxt;
- END IF;
- END IF;
- END PROCESS;
-
- buf_filled <= wr_capture_ptr - rd_ptr;
- PROCESS (rd_clk)
- BEGIN
- IF (rd_clk'EVENT AND rd_clk = '1') THEN
- IF (rst = '1') THEN
- empty_xhdl0 <= '1';
- ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
- empty_xhdl0 <= '1';
- ELSE
- empty_xhdl0 <= '0';
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (rd_clk)
- BEGIN
- IF (rd_clk'EVENT AND rd_clk = '1') THEN
- IF (rst = '1') THEN
- wr_ptr <= (others => '0');
- wr_gray <= (others => '0');
- ELSE
- IF (wr_en = '1') THEN
-
- wr_ptr <= wr_ptr + 1;
- END IF;
- wr_gray <= wr_gray_nxt;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (wr_ptr)
- BEGIN
- wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
- FOR n IN 0 TO ASIZE - 1 LOOP
- wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
- END LOOP;
- END PROCESS;
-
- buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
-
-
- PROCESS (wr_clk)
- BEGIN
- IF (wr_clk'EVENT AND wr_clk = '1') THEN
- IF (rst = '1') THEN
- full_xhdl1 <= '0';
- ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
- full_xhdl1 <= '1';
- ELSE
- full_xhdl1 <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- almost_full <= almost_full_int;
- PROCESS (wr_clk)
- BEGIN
- IF (wr_clk'EVENT AND wr_clk = '1') THEN
- IF (rst = '1') THEN
- almost_full_int <= '0';
-
- ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
-
- almost_full_int <= '1';
- ELSE
- almost_full_int <= '0';
- END IF;
- END IF;
- END PROCESS;
-
-
-
-END trans;
-
-
ipcore_dir/mem0/user_design/sim/afifo.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/rd_data_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/rd_data_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/rd_data_gen.vhd (nonexistent)
@@ -1,434 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: rd_data_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This module has all the timing control for generating "compare data"
--- to compare the read data from memory.
--- Reference:
--- Revision History: 2010/01/09 parameter MEM_BURST_LEN is missing in v6_data_gen instance module.
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
-
-entity rd_data_gen is
- generic (
-
- FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
- MEM_BURST_LEN : integer := 8;
- ADDR_WIDTH : integer := 32;
- BL_WIDTH : integer := 6;
- DWIDTH : integer := 32;
- DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : integer := 8;
- SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
-
- COLUMN_WIDTH : integer := 10
- );
- port (
-
- clk_i : in std_logic; --
- rst_i : in std_logic_vector(4 downto 0);
- prbs_fseed_i : in std_logic_vector(31 downto 0);
- data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
- rd_mdata_en : in std_logic;
-
- cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
- -- And then it should reasserted when
- -- it is generating the last_word.
- cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
- last_word_o : out std_logic;
-
- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
-
- addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
- bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
- user_bl_cnt_is_1_o : out std_logic;
- data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen in sp6
- -- connect from mcb_rd_empty when used as rd_data_gen in sp6
- -- connect from rd_data_valid in v6
- -- When both data_rdy and data_valid is asserted, the ouput data is valid.
- data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
- -- pattern is available.
- data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
- );
-end entity rd_data_gen;
-
-ARCHITECTURE trans OF rd_data_gen IS
-
-COMPONENT sp6_data_gen IS
- GENERIC (
-
- ADDR_WIDTH : INTEGER := 32;
- BL_WIDTH : INTEGER := 6;
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_PRBS";
- NUM_DQ_PINS : INTEGER := 8;
- COLUMN_WIDTH : INTEGER := 10
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- data_rdy_i : IN STD_LOGIC;
- cmd_startA : IN STD_LOGIC;
- cmd_startB : IN STD_LOGIC;
- cmd_startC : IN STD_LOGIC;
- cmd_startD : IN STD_LOGIC;
- cmd_startE : IN STD_LOGIC;
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
-
- fifo_rdy_i : IN STD_LOGIC;
- data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
- );
-END COMPONENT;
-
-COMPONENT v6_data_gen IS
- GENERIC (
-
- ADDR_WIDTH : INTEGER := 32;
- MEM_BURST_LEN : integer := 8;
-
- BL_WIDTH : INTEGER := 6;
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_ALL";
- NUM_DQ_PINS : INTEGER := 8;
- SEL_VICTIM_LINE : INTEGER := 3;
- COLUMN_WIDTH : INTEGER := 10
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- data_rdy_i : IN STD_LOGIC;
- cmd_startA : IN STD_LOGIC;
- cmd_startB : IN STD_LOGIC;
- cmd_startC : IN STD_LOGIC;
- cmd_startD : IN STD_LOGIC;
- cmd_startE : IN STD_LOGIC;
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
-
- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
-
- fifo_rdy_i : IN STD_LOGIC;
- data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
- );
-END COMPONENT;
-
-
- SIGNAL prbs_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL cmd_start : STD_LOGIC;
- SIGNAL adata : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL hdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL ndata : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL w1data : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL v6_w1data : STD_LOGIC_VECTOR(NUM_DQ_PINS * 4 - 1 DOWNTO 0);
-
- signal w0data : std_logic_vector(31 downto 0);
- signal data : std_logic_vector(DWIDTH - 1 downto 0);
- signal cmd_rdy : std_logic;
- signal data_valid : std_logic;
- signal user_burst_cnt : std_logic_vector(6 downto 0);
- signal data_rdy_r1 : std_logic;
- signal data_rdy_r2 : std_logic;
- signal next_count_is_one : std_logic;
- signal cmd_valid_r1 : std_logic;
- signal w3data : std_logic_vector(31 downto 0);
-
- signal data_port_fifo_rdy : std_logic;
-
- --assign cmd_start = cmd_valid_i & cmd_rdy ;
-
- signal user_bl_cnt_is_1 : std_logic;
-
- signal cmd_start_b : std_logic;
-
- -- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
- -- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
-
- -- counter to count user burst length
-
- signal u_bcount_2 : std_logic;
-
- -- Declare intermediate signals for referenced outputs
- signal last_word_o_xhdl1 : std_logic;
- signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
-begin
- -- Drive referenced outputs
- last_word_o <= last_word_o_xhdl1;
- data_port_fifo_rdy <= data_rdy_i;
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- data_rdy_r1 <= data_rdy_i;
- data_rdy_r2 <= data_rdy_r1;
- cmd_valid_r1 <= cmd_valid_i;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (user_burst_cnt = "0000010" and data_rdy_i = '1') then
- next_count_is_one <= '1';
- else
- next_count_is_one <= '0';
- end if;
- end if;
- end process;
-
- user_bl_cnt_is_1_o <= user_bl_cnt_is_1;
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "SPARTAN6") or
- (user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "VIRTEX6") ) then
- user_bl_cnt_is_1 <= '1';
- else
- user_bl_cnt_is_1 <= '0';
- end if;
- end if;
- end process;
-
- process (cmd_valid_i, cmd_valid_r1, cmd_rdy, user_bl_cnt_is_1, rd_mdata_en)
- begin
- if (FAMILY = "SPARTAN6") then
- cmd_start <= cmd_valid_i and cmd_rdy;
- cmd_start_b <= cmd_valid_i and cmd_rdy;
- else
- if (MEM_BURST_LEN = 4) then
- cmd_start <= rd_mdata_en;
- else
- cmd_start <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
- cmd_start_b <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
- end if;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- user_burst_cnt <= "0000000";
- elsif (cmd_start = '1') then
- if (bl_i = "000000") then
- user_burst_cnt <= "1000000" ;
- else
- user_burst_cnt <= ('0' & bl_i) ;
- end if;
- elsif (data_port_fifo_rdy = '1') then
- if (user_burst_cnt /= "0000000") then
- user_burst_cnt <= user_burst_cnt - "0000001";
- else
- user_burst_cnt <= "0000000";
- end if;
- end if;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((user_burst_cnt = "0000010" and data_rdy_i = '1') or (cmd_start = '1' and bl_i = "000001")) then
- u_bcount_2 <= '1';
- elsif (last_word_o_xhdl1 = '1') then
- u_bcount_2 <= '0';
- end if;
- end if;
- end process;
-
-
- last_word_o_xhdl1 <= u_bcount_2 and data_rdy_i;
-
- -- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
- -- is assert and reassert during the last data
-
- --data_valid_o logic
-
- cmd_rdy_o <= cmd_rdy;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdy <= '1';
- elsif (cmd_start = '1') then
- cmd_rdy <= '0';
- elsif (data_port_fifo_rdy = '1' and user_burst_cnt = "0000001") then
-
- cmd_rdy <= '1';
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- data_valid <= '0';
- elsif (user_burst_cnt = "0000001" and data_port_fifo_rdy = '1') then
- data_valid <= '0';
- elsif ((user_burst_cnt >= "0000001") or cmd_start = '1') then
- data_valid <= '1';
- end if;
- end if;
- end process;
-
-
- process (data_valid, data_port_fifo_rdy)
- begin
- if (FAMILY = "SPARTAN6") then
- data_valid_o <= data_valid;
- else
-
- data_valid_o <= data_port_fifo_rdy;
- end if;
- end process;
-
- xhdl2 : if (FAMILY = "SPARTAN6") generate
-
-
-
- sp6_data_gen_inst : sp6_data_gen
- generic map (
- ADDR_WIDTH => 32,
- BL_WIDTH => BL_WIDTH,
- DWIDTH => DWIDTH,
- DATA_PATTERN => DATA_PATTERN,
- NUM_DQ_PINS => NUM_DQ_PINS,
- COLUMN_WIDTH => COLUMN_WIDTH
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(1),
- data_rdy_i => data_rdy_i,
- prbs_fseed_i => prbs_fseed_i,
-
- data_mode_i => data_mode_i,
- cmd_startA => cmd_start,
- cmd_startB => cmd_start,
- cmd_startC => cmd_start,
- cmd_startD => cmd_start,
- cmd_startE => cmd_start,
- fixed_data_i => fixed_data_i,
-
- addr_i => addr_i,
- user_burst_cnt => user_burst_cnt,
- fifo_rdy_i => data_port_fifo_rdy,
- data_o => data_o
- );
-
- end generate;
- xhdl3 : if (FAMILY = "VIRTEX6") generate
-
-
-
- v6_data_gen_inst : v6_data_gen
- generic map (
- ADDR_WIDTH => 32,
- BL_WIDTH => BL_WIDTH,
- MEM_BURST_LEN => MEM_BURST_LEN,
-
- DWIDTH => DWIDTH,
- DATA_PATTERN => DATA_PATTERN,
- NUM_DQ_PINS => NUM_DQ_PINS,
- SEL_VICTIM_LINE => SEL_VICTIM_LINE,
- COLUMN_WIDTH => COLUMN_WIDTH
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(1),
- data_rdy_i => data_rdy_i,
- prbs_fseed_i => prbs_fseed_i,
-
- data_mode_i => data_mode_i,
- cmd_startA => cmd_start,
- cmd_startB => cmd_start,
- cmd_startC => cmd_start,
- cmd_startD => cmd_start,
- cmd_startE => cmd_start,
- fixed_data_i => fixed_data_i,
-
- m_addr_i => addr_i, --(m_addr_i ),
- addr_i => addr_i,
- user_burst_cnt => user_burst_cnt,
- fifo_rdy_i => data_port_fifo_rdy,
- data_o => data_o
- );
-
- end generate;
-
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/sim/rd_data_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/data_prbs_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/data_prbs_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/data_prbs_gen.vhd (nonexistent)
@@ -1,135 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: data_prbs_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:07 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This module is used LFSR to generate random data for memory
--- data write or memory data read comparison.The first data is
--- seeded by the input prbs_seed_i which is connected to memory address.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
-
-
-ENTITY data_prbs_gen IS
- GENERIC (
- EYE_TEST : STRING := "FALSE";
- PRBS_WIDTH : INTEGER := 32;
- SEED_WIDTH : INTEGER := 32
--- TAPS : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- clk_en : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- prbs_seed_init : IN STD_LOGIC;
- prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
-
- prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
- );
-END data_prbs_gen;
-
-ARCHITECTURE trans OF data_prbs_gen IS
-
- SIGNAL prbs : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
- SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
- SIGNAL i : INTEGER;
-BEGIN
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
-
-
- lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
- ELSIF (clk_en = '1') THEN
-
- lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
- lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
- lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
-
- lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
- lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
- lfsr_q(2) <= lfsr_q(1);
-
- lfsr_q(1) <= lfsr_q(32);
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
- BEGIN
- prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
- END PROCESS;
-
-
- prbs_o <= prbs;
-
-END trans;
-
-
ipcore_dir/mem0/user_design/sim/data_prbs_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/mcb_traffic_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/mcb_traffic_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/mcb_traffic_gen.vhd (nonexistent)
@@ -1,1002 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: mcb_traffic_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/05/20 22:23:35 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This is top level module of memory traffic generator which can
--- generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
--- hard memory controller core.
--- Reference:
--- Revision History: 2009 Brought out internal signals cmp_data and cmp_error as outputs.
--- 2010/01/09 Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
--- 2010/05/03 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG.
--- 2010/05/20 If MEM_BURST_LEN value is passed with value of zero, it is treated as
--- "OTF" Burst Mode and TG will only generate BL 8 traffic.
-
---*****************************************************************************
-
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-ENTITY mcb_traffic_gen IS
- GENERIC (
- TCQ : TIME := 100 ps;
- FAMILY : STRING := "SPARTAN6";
- SIMULATION : STRING := "FALSE";
- MEM_BURST_LEN : INTEGER := 8;
- PORT_MODE : STRING := "BI_MODE";
- DATA_PATTERN : STRING := "DGEN_ADDR";
- CMD_PATTERN : STRING := "CGEN_ALL";
-
- ADDR_WIDTH : INTEGER := 30;
-
- CMP_DATA_PIPE_STAGES : INTEGER := 0;
-
- MEM_COL_WIDTH : INTEGER := 10;
- NUM_DQ_PINS : INTEGER := 16;
- DQ_ERROR_WIDTH : integer := 1;
-
- SEL_VICTIM_LINE : INTEGER := 3;
- DWIDTH : INTEGER := 32;
-
- EYE_TEST : STRING := "FALSE";
-
-
- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
- PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- run_traffic_i : IN STD_LOGIC;
- manual_clear_error : IN STD_LOGIC;
- start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- load_seed_i : IN STD_LOGIC;
-
- addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-
- instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-
- bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-
- mode_load_i : IN STD_LOGIC;
-
- fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-
- fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
- bram_cmd_i : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
- bram_valid_i : IN STD_LOGIC;
- bram_rdy_o : OUT STD_LOGIC;
-
- mcb_cmd_en_o : OUT STD_LOGIC;
- mcb_cmd_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- mcb_cmd_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- mcb_cmd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-
- mcb_cmd_full_i : IN STD_LOGIC;
-
- mcb_wr_en_o : OUT STD_LOGIC;
- mcb_wr_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- mcb_wr_data_end_o : OUT STD_LOGIC;
- mcb_wr_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
-
- mcb_wr_full_i : IN STD_LOGIC;
- mcb_wr_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
-
- mcb_rd_en_o : OUT STD_LOGIC;
- mcb_rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- mcb_rd_empty_i : IN STD_LOGIC;
- mcb_rd_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
- counts_rst : IN STD_LOGIC;
- wr_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
- rd_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
-
- error : OUT STD_LOGIC;
- cmp_data_valid : OUT STD_LOGIC;
-
- error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
- cmp_error : out std_logic;
- cmp_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
- mem_rd_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
- dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
- cumlative_dq_lane_error :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
-
-
- );
-END mcb_traffic_gen;
-
-ARCHITECTURE trans OF mcb_traffic_gen IS
- COMPONENT mcb_flow_control IS
- GENERIC (
- TCQ : TIME := 100 ps;
- FAMILY : string := "SPARTAN6"
- );
- PORT (
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
- cmd_rdy_o : OUT STD_LOGIC;
- cmd_valid_i : IN STD_LOGIC;
- cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- mcb_cmd_full : IN STD_LOGIC;
- cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- cmd_en_o : OUT STD_LOGIC;
- last_word_wr_i : IN STD_LOGIC;
- wdp_rdy_i : IN STD_LOGIC;
- wdp_valid_o : OUT STD_LOGIC;
- wdp_validB_o : OUT STD_LOGIC;
- wdp_validC_o : OUT STD_LOGIC;
- wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- last_word_rd_i : IN STD_LOGIC;
- rdp_rdy_i : IN STD_LOGIC;
- rdp_valid_o : OUT STD_LOGIC;
- rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT cmd_gen IS
- GENERIC (
- TCQ : TIME := 100 ps;
-
- FAMILY : STRING := "SPARTAN6";
- MEM_BURST_LEN : INTEGER := 8;
- NUM_DQ_PINS : INTEGER := 8;
- DATA_PATTERN : STRING := "DGEN_PRBS";
- CMD_PATTERN : STRING := "CGEN_ALL";
- ADDR_WIDTH : INTEGER := 30;
- DWIDTH : INTEGER := 32;
- PIPE_STAGES : INTEGER := 0;
- MEM_COL_WIDTH : INTEGER := 10;
- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
- PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
- );
- PORT (
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
- run_traffic_i : IN STD_LOGIC;
- rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
- force_wrcmd_gen_i : IN STD_LOGIC;
- start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- load_seed_i : IN STD_LOGIC;
- addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- mode_load_i : IN STD_LOGIC;
- fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- bram_valid_i : IN STD_LOGIC;
- bram_rdy_o : OUT STD_LOGIC;
- reading_rd_data_i : IN STD_LOGIC;
- rdy_i : IN STD_LOGIC;
- addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- cmd_o_vld : OUT STD_LOGIC
- );
- END COMPONENT;
-
-
- component afifo IS
- GENERIC (
- TCQ : TIME := 100 ps;
- DSIZE : INTEGER := 32;
- FIFO_DEPTH : INTEGER := 16;
- ASIZE : INTEGER := 4;
- SYNC : INTEGER := 1
- );
- PORT (
- wr_clk : IN STD_LOGIC;
- rst : IN STD_LOGIC;
- wr_en : IN STD_LOGIC;
- wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
- rd_en : IN STD_LOGIC;
- rd_clk : IN STD_LOGIC;
- rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
- full : OUT STD_LOGIC;
- almost_full : OUT STD_LOGIC;
- empty : OUT STD_LOGIC
- );
-END component;
-
-component read_data_path IS
- GENERIC (
- TCQ : TIME := 100 ps;
-
- FAMILY : STRING := "SPARTAN6";
- MEM_BURST_LEN : INTEGER := 8;
- ADDR_WIDTH : INTEGER := 32;
- CMP_DATA_PIPE_STAGES : INTEGER := 3;
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : INTEGER := 8;
- DQ_ERROR_WIDTH : INTEGER := 1;
- SEL_VICTIM_LINE : integer := 3;
- MEM_COL_WIDTH : INTEGER := 10
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : in std_logic_vector(9 downto 0);
- manual_clear_error : IN STD_LOGIC;
- cmd_rdy_o : OUT STD_LOGIC;
- cmd_valid_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- cmd_en_i : IN STD_LOGIC;
- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
-
- addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
-
- data_rdy_o : OUT STD_LOGIC;
- data_valid_i : IN STD_LOGIC;
- data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- last_word_rd_o : OUT STD_LOGIC;
- data_error_o : OUT STD_LOGIC;
- cmp_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- rd_mdata_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- cmp_data_valid : OUT STD_LOGIC;
- cmp_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- cmp_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- force_wrcmd_gen_o : out std_logic;
- rd_buff_avail_o : out std_logic_vector(6 downto 0);
- dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
- cumlative_dq_lane_error_r :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
-
-
- );
-END component;
-
-component write_data_path IS
- GENERIC (
- TCQ : TIME := 100 ps;
- FAMILY : STRING := "SPARTAN6";
- MEM_BURST_LEN : INTEGER := 8;
- ADDR_WIDTH : INTEGER := 32;
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_ALL";
- NUM_DQ_PINS : INTEGER := 8;
- SEL_VICTIM_LINE : INTEGER := 3;
- MEM_COL_WIDTH : INTEGER := 10;
- EYE_TEST : string := "FALSE"
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : in std_logic_vector(9 downto 0);
- cmd_rdy_o : OUT STD_LOGIC;
- cmd_valid_i : IN STD_LOGIC;
- cmd_validB_i : IN STD_LOGIC;
- cmd_validC_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
-
- addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- data_rdy_i : IN STD_LOGIC;
- data_valid_o : OUT STD_LOGIC;
- last_word_wr_o : OUT STD_LOGIC;
- data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- data_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
- data_wr_end_o : out std_logic
- );
-END component;
-
-component tg_status IS
- GENERIC (
- TCQ : TIME := 100 ps;
- DWIDTH : INTEGER := 32
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- manual_clear_error : IN STD_LOGIC;
- data_error_i : IN STD_LOGIC;
- cmp_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- cmp_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- cmp_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- mcb_cmd_full_i : IN STD_LOGIC;
- mcb_wr_full_i : IN STD_LOGIC;
- mcb_rd_empty_i : IN STD_LOGIC;
- error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
- error : OUT STD_LOGIC
- );
-
-
-END component;
-
- attribute KEEP : STRING;
- attribute MAX_FANOUT : STRING;
-
-
-function MEM_BLENGTH return integer is
- begin
- if (MEM_BURST_LEN = 4) then
- return 4;
- elsif (MEM_BURST_LEN = 8) then
- return 8;
- else
- return 8;
- end if;
- end function MEM_BLENGTH;
-
-
- constant MEM_BLEN : INTEGER := MEM_BLENGTH;
-
- SIGNAL mcb_wr_en : STD_LOGIC;
- SIGNAL cmd2flow_valid : STD_LOGIC;
- SIGNAL cmd2flow_cmd : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL cmd2flow_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL cmd2flow_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL last_word_rd : STD_LOGIC;
- SIGNAL last_word_wr : STD_LOGIC;
- SIGNAL flow2cmd_rdy : STD_LOGIC;
- SIGNAL wr_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL rd_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL wr_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL rd_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL run_traffic_reg : STD_LOGIC;
- SIGNAL wr_validB : STD_LOGIC;
- SIGNAL wr_valid : STD_LOGIC;
- SIGNAL wr_validC : STD_LOGIC;
- SIGNAL bram_addr_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL bram_instr_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL bram_bl_i : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL AC2_G_E2 : STD_LOGIC;
- SIGNAL AC1_G_E1 : STD_LOGIC;
- SIGNAL AC3_G_E3 : STD_LOGIC;
- SIGNAL upper_end_matched : STD_LOGIC;
- SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
- SIGNAL lower_end_matched : STD_LOGIC;
- SIGNAL addr_o : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL m_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL dcount_rst : STD_LOGIC;
- SIGNAL rd_addr_error : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL rd_rdy : STD_LOGIC;
- SIGNAL cmp_error_int : STD_LOGIC;
- SIGNAL cmd_full : STD_LOGIC;
-
- SIGNAL cmp_data_int : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- SIGNAL mem_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- SIGNAL cmp_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL cmp_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
-
- SIGNAL rst_ra : STD_LOGIC_VECTOR(9 DOWNTO 0);
- SIGNAL rst_rb : STD_LOGIC_VECTOR(9 DOWNTO 0);
-
- SIGNAL mcb_wr_full_r1 : STD_LOGIC;
- SIGNAL mcb_wr_full_r2 : STD_LOGIC;
- SIGNAL mcb_rd_empty_r : STD_LOGIC;
- SIGNAL force_wrcmd_gen : STD_LOGIC;
- SIGNAL rd_buff_avail : STD_LOGIC_VECTOR(6 DOWNTO 0);
-
- SIGNAL data_mode_r_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
- SIGNAL data_mode_r_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
- SIGNAL data_mode_r_c : STD_LOGIC_VECTOR(3 DOWNTO 0);
- SIGNAL tmp_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL error_access_range : STD_LOGIC ;
-
- SIGNAL mcb_rd_empty : STD_LOGIC;
-
- SIGNAL mcb_wr_full : STD_LOGIC;
-
- SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- SIGNAL wr_rdy : STD_LOGIC;
-
- SIGNAL rd_valid : STD_LOGIC;
-
- SIGNAL cmd_rd_en : STD_LOGIC;
- -- X-HDL generated signals
-
- SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
- SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
- SIGNAL xhdl17 : STD_LOGIC;
- SIGNAL xhdl19 : STD_LOGIC;
- SIGNAL ZEROS : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- -- Declare intermediate signals for referenced outputs
- SIGNAL bram_rdy_o_xhdl0 : STD_LOGIC;
- SIGNAL mcb_cmd_en_o_xhdl5 : STD_LOGIC;
- SIGNAL mcb_cmd_instr_o_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL mcb_cmd_addr_o_xhdl3 : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- SIGNAL mcb_cmd_bl_o_xhdl4 : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL mcb_wr_data_o_xhdl9 : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
- SIGNAL mcb_wr_mask_o_xhdl10 : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
- SIGNAL mcb_rd_en : STD_LOGIC;
- SIGNAL wr_data_counts_xhdl12 : STD_LOGIC_VECTOR(47 DOWNTO 0);
- SIGNAL rd_data_counts_xhdl11 : STD_LOGIC_VECTOR(47 DOWNTO 0);
- SIGNAL error_xhdl1 : STD_LOGIC;
- SIGNAL error_status_xhdl2 : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
-
- SIGNAL cmd_fifo_wr : STD_LOGIC;
- SIGNAL xfer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL fifo_error : STD_LOGIC;
- SIGNAL cmd_fifo_rd : STD_LOGIC;
- SIGNAL cmd_fifo_empty : STD_LOGIC;
- SIGNAL xfer_cmd_bl : STD_LOGIC;
- SIGNAL cmd_fifo_full : STD_LOGIC;
- SIGNAL rd_mdata_afull_set : STD_LOGIC;
- SIGNAL rd_mdata_fifo_afull : STD_LOGIC;
- SIGNAL rdpath_data_valid_i : STD_LOGIC;
- SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
- SIGNAL rd_v6_mdata : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- SIGNAL mdata_wren : STD_LOGIC;
- attribute KEEP of rst_ra : signal is "TRUE";
- attribute KEEP of rst_rb : signal is "TRUE";
- attribute KEEP of mcb_wr_full_r1 : signal is "TRUE";
- attribute KEEP of mcb_wr_full_r2 : signal is "TRUE";
- attribute MAX_FANOUT of rst_ra : signal is "20";
- attribute MAX_FANOUT of rst_rb : signal is "20";
-
-
-BEGIN
-
-
- mem_rd_data <= mem_rd_data_i;
- ZEROS <= (others => '0');
-
- cmp_data <= cmp_data_int;
- cmp_error <= cmp_error_int;
- -- Drive referenced outputs
- bram_rdy_o <= bram_rdy_o_xhdl0;
- mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
- mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
- mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
- mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
- mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
- mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
- mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
- mcb_rd_en_o <= mcb_rd_en;
- wr_data_counts <= wr_data_counts_xhdl12;
- rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
- error <= error_xhdl1;
- error_status <= error_status_xhdl2;
- tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
--- tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
-
---synthesis translate_off
- PROCESS
- BEGIN
- IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
- report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
- report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
-
- END IF;
- WAIT;
- END PROCESS;
-
- PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
- BEGIN
- IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
- report "Error ! Data access beyond address range"; -- severity ERROR;
- error_access_range <= '1';
- -- $stop();
- END IF;
- END PROCESS;
---synthesis translate_on
-
- mcb_rd_empty <= mcb_rd_empty_i;
-
- mcb_wr_full <= mcb_wr_full_i;
-
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- data_mode_r_a <= data_mode_i;
- data_mode_r_b <= data_mode_i;
- data_mode_r_c <= data_mode_i;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_ra(0)) = '1') THEN
- mcb_wr_full_r1 <= '0';
- ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
- mcb_wr_full_r1 <= '1';
- mcb_wr_full_r2 <= '1';
- ELSE
- mcb_wr_full_r1 <= '0';
- mcb_wr_full_r2 <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_ra(0)) = '1') THEN
- mcb_rd_empty_r <= '1';
- ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
- mcb_rd_empty_r <= '1';
- ELSE
- mcb_rd_empty_r <= '0';
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
- rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- run_traffic_reg <= run_traffic_i;
- END IF;
- END PROCESS;
-
- bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
- bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
- bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
- dcount_rst <= counts_rst OR rst_ra(0);
-
-
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') then
- IF (dcount_rst = '1') THEN
- wr_data_counts_xhdl12 <= (OTHERS => '0');
- ELSIF (mcb_wr_en = '1') THEN
- wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
- END IF;
- end if;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') then
- IF (dcount_rst = '1') THEN
- rd_data_counts_xhdl11 <= (others => '0');
- ELSIF (mcb_rd_en = '1') THEN
- rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
- END IF;
- end if;
- END PROCESS;
-
- xhdl13 : IF (SIMULATION = "TRUE") GENERATE
- cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (mcb_cmd_en_o_xhdl5 = '1') THEN
- if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
- fifo_error <= '1';
- ELSE
- fifo_error <= '0';
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
-
-
- xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
- xfer_cmd_bl <= xhdl15(32);
- xfer_addr <= xhdl15(31 downto 0);
- cmd_fifo : afifo
- GENERIC MAP (
- TCQ => TCQ,
- DSIZE => 38,
- FIFO_DEPTH => 16,
- ASIZE => 4,
- SYNC => 1
- )
- PORT MAP (
- wr_clk => clk_i,
- rst => rst_ra(0),
- wr_en => cmd_fifo_wr,
- wr_data => xhdl14,
- rd_en => cmd_fifo_rd,
- rd_clk => clk_i,
- rd_data => xhdl15,
- full => cmd_fifo_full,
- almost_full => open,
- empty => cmd_fifo_empty
- );
- END GENERATE;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- end_addr_r <= end_addr_i;
- END IF;
- END PROCESS;
-
-
-
- u_c_gen : cmd_gen
- GENERIC MAP (
- TCQ => TCQ,
- FAMILY => FAMILY,
- MEM_BURST_LEN => MEM_BLEN,
- NUM_DQ_PINS => NUM_DQ_PINS,
- DATA_PATTERN => DATA_PATTERN,
- CMD_PATTERN => CMD_PATTERN,
- ADDR_WIDTH => ADDR_WIDTH,
- DWIDTH => DWIDTH,
- MEM_COL_WIDTH => MEM_COL_WIDTH,
- PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
- PRBS_SADDR_MASK_POS => PRBS_SADDR_MASK_POS,
- PRBS_EADDR => PRBS_EADDR,
- PRBS_SADDR => PRBS_SADDR
- )
- PORT MAP (
- clk_i => clk_i,
- rst_i => rst_ra,
- rd_buff_avail_i => rd_buff_avail,
- reading_rd_data_i => mcb_rd_en,
- force_wrcmd_gen_i => force_wrcmd_gen,
- run_traffic_i => run_traffic_reg,
- start_addr_i => start_addr_i,
- end_addr_i => end_addr_r,
- cmd_seed_i => cmd_seed_i,
- data_seed_i => data_seed_i,
- load_seed_i => load_seed_i,
- addr_mode_i => addr_mode_i,
- data_mode_i => data_mode_r_a,
- instr_mode_i => instr_mode_i,
- bl_mode_i => bl_mode_i,
- mode_load_i => mode_load_i,
- fixed_bl_i => fixed_bl_i,
- fixed_addr_i => fixed_addr_i,
- fixed_instr_i => fixed_instr_i,
- bram_addr_i => bram_addr_i,
- bram_instr_i => bram_instr_i,
- bram_bl_i => bram_bl_i,
- bram_valid_i => bram_valid_i,
- bram_rdy_o => bram_rdy_o_xhdl0,
- rdy_i => flow2cmd_rdy,
- instr_o => cmd2flow_cmd,
- addr_o => cmd2flow_addr,
- bl_o => cmd2flow_bl,
- m_addr_o => m_addr,
- cmd_o_vld => cmd2flow_valid
- );
- mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
- cmd_full <= mcb_cmd_full_i;
-
-
- mcb_control : mcb_flow_control
- GENERIC MAP (
- TCQ => TCQ,
- FAMILY => FAMILY
- )
- PORT MAP (
- clk_i => clk_i,
- rst_i => rst_ra,
- cmd_rdy_o => flow2cmd_rdy,
- cmd_valid_i => cmd2flow_valid,
- cmd_i => cmd2flow_cmd,
- addr_i => cmd2flow_addr,
- bl_i => cmd2flow_bl,
- mcb_cmd_full => cmd_full,
- cmd_o => mcb_cmd_instr_o_xhdl6,
- addr_o => addr_o,
- bl_o => mcb_cmd_bl_o_xhdl4,
- cmd_en_o => mcb_cmd_en_o_xhdl5,
- last_word_wr_i => last_word_wr,
- wdp_rdy_i => wr_rdy,
- wdp_valid_o => wr_valid,
- wdp_validB_o => wr_validB,
- wdp_validC_o => wr_validC,
- wr_addr_o => wr_addr,
- wr_bl_o => wr_bl,
- last_word_rd_i => last_word_rd,
- rdp_rdy_i => rd_rdy,
- rdp_valid_o => rd_valid,
- rd_addr_o => rd_addr,
- rd_bl_o => rd_bl
- );
-
- mdata_wren <= not mcb_rd_empty;
-
- rd_mdata_fifo : afifo
- GENERIC MAP (
- TCQ => TCQ,
- DSIZE => DWIDTH,
- FIFO_DEPTH => 32,
- ASIZE => 5,
- SYNC => 1
- )
- PORT MAP (
- wr_clk => clk_i,
- rst => rst_rb(0),
- wr_en => mdata_wren,
- wr_data => mcb_rd_data_i,
- rd_en => mcb_rd_en,
- rd_clk => clk_i,
- rd_data => rd_v6_mdata,
- full => open,
- almost_full => open,
- empty => rd_mdata_fifo_empty
- );
-
-
-
- cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_rb(0) = '1') THEN
- rd_mdata_afull_set <= '0';
- ELSIF (rd_mdata_fifo_afull = '1') THEN
- rd_mdata_afull_set <= '1';
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
- BEGIN
-
- IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
- rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
- ELSE
- rdpath_data_valid_i <= not(mcb_rd_empty);
-
- END IF;
- END PROCESS;
-
- PROCESS(rd_v6_mdata,mcb_rd_data_i)
- BEGIN
-
- IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
- rdpath_rd_data_i <= rd_v6_mdata;
- ELSE
- rdpath_rd_data_i <= mcb_rd_data_i;
-
- END IF;
- END PROCESS;
-
- RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
-
-
-
-
- xhdl17 <= NOT(mcb_rd_empty);
- read_data_path_inst : read_data_path
- GENERIC MAP (
- TCQ => TCQ,
- family => FAMILY,
- MEM_BURST_LEN => MEM_BLEN,
- cmp_data_pipe_stages => CMP_DATA_PIPE_STAGES,
- addr_width => ADDR_WIDTH,
- sel_victim_line => SEL_VICTIM_LINE,
- data_pattern => DATA_PATTERN,
- dwidth => DWIDTH,
- num_dq_pins => NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
- mem_col_width => MEM_COL_WIDTH
- )
- PORT MAP (
- clk_i => clk_i,
- rst_i => rst_rb,
- manual_clear_error => manual_clear_error,
- cmd_rdy_o => rd_rdy,
- cmd_valid_i => rd_valid,
- prbs_fseed_i => data_seed_i,
- cmd_sent => mcb_cmd_instr_o_xhdl6,
- bl_sent => mcb_cmd_bl_o_xhdl4,
- cmd_en_i => cmd_rd_en,
- data_mode_i => data_mode_r_b,
- last_word_rd_o => last_word_rd,
- m_addr_i => m_addr,
- fixed_data_i => fixed_data_i,
-
- addr_i => rd_addr,
- bl_i => rd_bl,
- data_rdy_o => mcb_rd_en,
- data_valid_i => rdpath_data_valid_i,
- data_i => rdpath_rd_data_i,
- data_error_o => cmp_error_int,
- cmp_data_o => cmp_data_int,
- rd_mdata_o => mem_rd_data_i,
- cmp_data_valid => cmp_data_valid,
- cmp_addr_o => cmp_addr,
- cmp_bl_o => cmp_bl,
- force_wrcmd_gen_o => force_wrcmd_gen,
- rd_buff_avail_o => rd_buff_avail,
- dq_error_bytelane_cmp => dq_error_bytelane_cmp,
- cumlative_dq_lane_error_r => cumlative_dq_lane_error
-
-
-
- );
-
- END GENERATE;
-
- xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
-
- xhdl19 <= NOT(mcb_wr_full);
- write_data_path_inst : write_data_path
- GENERIC MAP (
- TCQ => TCQ,
- family => FAMILY,
- MEM_BURST_LEN => MEM_BLEN,
-
- addr_width => ADDR_WIDTH,
- data_pattern => DATA_PATTERN,
- dwidth => DWIDTH,
- num_dq_pins => NUM_DQ_PINS,
- sel_victim_line => SEL_VICTIM_LINE,
- mem_col_width => MEM_COL_WIDTH,
- eye_test => EYE_TEST
- )
- PORT MAP (
- clk_i => clk_i,
- rst_i => rst_rb,
- cmd_rdy_o => wr_rdy,
- cmd_valid_i => wr_valid,
- cmd_validb_i => wr_validB,
- cmd_validc_i => wr_validC,
- prbs_fseed_i => data_seed_i,
- data_mode_i => data_mode_r_c,
- last_word_wr_o => last_word_wr,
- m_addr_i => m_addr,
- fixed_data_i => fixed_data_i,
-
- addr_i => wr_addr,
- bl_i => wr_bl,
- data_rdy_i => xhdl19,
- data_valid_o => mcb_wr_en,
- data_o => mcb_wr_data_o_xhdl9,
- data_mask_o => mcb_wr_mask_o_xhdl10,
- data_wr_end_o => mcb_wr_data_end_o_xhdl8
--- tpt_hdata =>
- );
-
- END GENERATE;
-
- mcb_wr_en_o <= mcb_wr_en;
-
-
-
- tg_status_inst : tg_status
- GENERIC MAP (
- dwidth => DWIDTH
- )
- PORT MAP (
- clk_i => clk_i,
- rst_i => rst_ra(2),
- manual_clear_error => manual_clear_error,
- data_error_i => cmp_error_int,
- cmp_data_i => cmp_data_int,
- rd_data_i => mem_rd_data_i,
- cmp_addr_i => cmp_addr,
- cmp_bl_i => cmp_bl,
- mcb_cmd_full_i => mcb_cmd_full_i,
- mcb_wr_full_i => mcb_wr_full,
- mcb_rd_empty_i => mcb_rd_empty,
- error_status => error_status_xhdl2,
- error => error_xhdl1
- );
-
-END trans;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ipcore_dir/mem0/user_design/sim/mcb_traffic_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/mcb_flow_control.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/mcb_flow_control.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/mcb_flow_control.vhd (nonexistent)
@@ -1,539 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: mcb_flow_control.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This module is the main flow control between cmd_gen.v,
--- write_data_path and read_data_path modules.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-
-ENTITY mcb_flow_control IS
- GENERIC (
- TCQ : TIME := 100 ps;
- FAMILY : STRING := "SPARTAN6"
- );
- PORT (
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
- cmd_rdy_o : OUT STD_LOGIC;
- cmd_valid_i : IN STD_LOGIC;
- cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- mcb_cmd_full : IN STD_LOGIC;
- cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- cmd_en_o : OUT STD_LOGIC;
- last_word_wr_i : IN STD_LOGIC;
- wdp_rdy_i : IN STD_LOGIC;
- wdp_valid_o : OUT STD_LOGIC;
- wdp_validB_o : OUT STD_LOGIC;
- wdp_validC_o : OUT STD_LOGIC;
- wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- last_word_rd_i : IN STD_LOGIC;
- rdp_rdy_i : IN STD_LOGIC;
- rdp_valid_o : OUT STD_LOGIC;
- rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
- );
-END mcb_flow_control;
-
-ARCHITECTURE trans OF mcb_flow_control IS
-
- constant READY : std_logic_vector(4 downto 0) := "00001";
- constant READ : std_logic_vector(4 downto 0) := "00010";
- constant WRITE : std_logic_vector(4 downto 0) := "00100";
- constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
- constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
-
- constant RD : std_logic_vector(2 downto 0) := "001";
- constant RDP : std_logic_vector(2 downto 0) := "011";
- constant WR : std_logic_vector(2 downto 0) := "000";
- constant WRP : std_logic_vector(2 downto 0) := "010";
- constant REFRESH : std_logic_vector(2 downto 0) := "100";
- constant NOP : std_logic_vector(2 downto 0) := "101";
-
- SIGNAL cmd_fifo_rdy : STD_LOGIC;
- SIGNAL cmd_rd : STD_LOGIC;
- SIGNAL cmd_wr : STD_LOGIC;
- SIGNAL cmd_others : STD_LOGIC;
- SIGNAL push_cmd : STD_LOGIC;
- SIGNAL xfer_cmd : STD_LOGIC;
- SIGNAL rd_vld : STD_LOGIC;
- SIGNAL wr_vld : STD_LOGIC;
- SIGNAL cmd_rdy : STD_LOGIC;
- SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
-
- SIGNAL rdp_valid : STD_LOGIC;
- SIGNAL wdp_valid : STD_LOGIC;
- SIGNAL wdp_validB : STD_LOGIC;
- SIGNAL wdp_validC : STD_LOGIC;
-
- SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
- SIGNAL push_cmd_r : STD_LOGIC;
- SIGNAL wait_done : STD_LOGIC;
- SIGNAL cmd_en_r1 : STD_LOGIC;
- SIGNAL wr_in_progress : STD_LOGIC;
- SIGNAL tst_cmd_rdy_o : STD_LOGIC;
-
- SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
- SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-
- -- Declare intermediate signals for referenced outputs
- SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
-BEGIN
- -- Drive referenced outputs
- cmd_rdy_o <= cmd_rdy_o_xhdl0;
- cmd_en_o <= cmd_en_r1;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- cmd_rdy_o_xhdl0 <= cmd_rdy;
- tst_cmd_rdy_o <= cmd_rdy;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(8)) = '1') THEN
- cmd_en_r1 <= '0' ;
- ELSIF (xfer_cmd = '1') THEN
- cmd_en_r1 <= '1' ;
- ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
- cmd_en_r1 <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(9)) = '1') THEN
- cmd_fifo_rdy <= '1';
- ELSIF (xfer_cmd = '1') THEN
- cmd_fifo_rdy <= '0';
- ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
- cmd_fifo_rdy <= '1';
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(9)) = '1') THEN
- addr_o <= (others => '0');
- cmd_o <= (others => '0');
- bl_o <= (others => '0');
- ELSIF (xfer_cmd = '1') THEN
- addr_o <= addr_reg;
- IF (FAMILY = "SPARTAN6") THEN
- cmd_o <= cmd_reg;
- ELSE
- cmd_o <= ("00" & cmd_reg(0));
- END IF;
- bl_o <= bl_reg;
- END IF;
- END IF;
- END PROCESS;
-
- wr_addr_o <= addr_i;
- rd_addr_o <= addr_i;
- rd_bl_o <= bl_i;
- wr_bl_o <= bl_i;
- wdp_valid_o <= wdp_valid;
- wdp_validB_o <= wdp_validB;
- wdp_validC_o <= wdp_validC;
- rdp_valid_o <= rdp_valid;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(8)) = '1') THEN
- wait_done <= '1' ;
- ELSIF (push_cmd_r = '1') THEN
- wait_done <= '1' ;
- ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
- wait_done <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- push_cmd_r <= push_cmd ;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (push_cmd = '1') THEN
- cmd_reg <= cmd_i ;
- addr_reg <= addr_i ;
- bl_reg <= bl_i - "000001" ;
- END IF;
- END IF;
- END PROCESS;
-
- cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
- '0';
- cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
- '0';
- cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
- '0';
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0)= '1') THEN
-
- cmd_wr_pending_r1 <= '0' ;
- ELSIF (last_word_wr_i = '1') THEN
-
- cmd_wr_pending_r1 <= '1' ;
- ELSIF (push_cmd = '1') THEN
- cmd_wr_pending_r1 <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((cmd_rd AND push_cmd) = '1') THEN
- cmd_rd_pending_r1 <= '1' ;
- ELSIF (xfer_cmd = '1') THEN
-
- cmd_rd_pending_r1 <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0)= '1') THEN
- wr_in_progress <= '0';
- ELSIF (last_word_wr_i = '1') THEN
- wr_in_progress <= '0';
- ELSIF (current_state = WRITE) THEN
-
- wr_in_progress <= '1';
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0)= '1') THEN
- current_state <= "00001" ;
- ELSE
- current_state <= next_state ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
- BEGIN
- push_cmd <= '0';
-
- xfer_cmd <= '0';
- wdp_valid <= '0';
- wdp_validB <= '0';
-
- wdp_validC <= '0';
- rdp_valid <= '0';
- cmd_rdy <= '0';
- next_state <= current_state;
- CASE current_state IS
-
- WHEN READY =>
- IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
- next_state <= READ;
- push_cmd <= '1';
- xfer_cmd <= '0';
- rdp_valid <= '1';
-
- ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
- next_state <= WRITE;
- push_cmd <= '1';
- wdp_valid <= '1';
- wdp_validB <= '1';
- wdp_validC <= '1';
-
- ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
- next_state <= REFRESH_ST;
- push_cmd <= '1';
- xfer_cmd <= '0';
-
- ELSE
- next_state <= READY;
- push_cmd <= '0';
- END IF;
-
- IF (cmd_fifo_rdy = '1') THEN
- cmd_rdy <= '1';
- ELSE
- cmd_rdy <= '0';
- END IF;
-
- WHEN REFRESH_ST =>
- IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
- next_state <= READ;
- push_cmd <= '1';
- rdp_valid <= '1';
- wdp_valid <= '0';
- xfer_cmd <= '1';
-
- ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
- next_state <= WRITE;
- push_cmd <= '1';
- xfer_cmd <= '1';
-
- wdp_valid <= '1';
- wdp_validB <= '1';
- wdp_validC <= '1';
-
- ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
- push_cmd <= '1';
- xfer_cmd <= '1';
-
- ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
- next_state <= CMD_WAIT;
- tstpointA <= "1001";
-
- ELSE
- next_state <= READ;
-
- END IF;
-
- IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
- cmd_rdy <= '1';
- ELSE
- cmd_rdy <= '0';
- END IF;
-
- WHEN READ =>
- IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
- next_state <= READ;
- push_cmd <= '1';
- rdp_valid <= '1';
- wdp_valid <= '0';
- xfer_cmd <= '1';
- tstpointA <= "0101";
- ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
- next_state <= WRITE;
- push_cmd <= '1';
- xfer_cmd <= '1';
- wdp_valid <= '1';
- wdp_validB <= '1';
- wdp_validC <= '1';
- tstpointA <= "0110";
- ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
- next_state <= READ;
- push_cmd <= '0';
- xfer_cmd <= '0';
- tstpointA <= "0111";
- wdp_valid <= '0';
- wdp_validB <= '0';
- wdp_validC <= '0';
- rdp_valid <= '0';
- ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
- next_state <= REFRESH_ST;
- push_cmd <= '1';
- xfer_cmd <= '1';
- wdp_valid <= '0';
- wdp_validB <= '0';
- wdp_validC <= '0';
- rdp_valid <= '0';
- tstpointA <= "1000";
- ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
- next_state <= CMD_WAIT;
- tstpointA <= "1001";
- ELSE
- next_state <= READ;
- END IF;
-
- IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
- cmd_rdy <= wait_done; --'1';
- ELSE
- cmd_rdy <= '0';
- END IF;
-
- WHEN WRITE =>
- IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
- next_state <= READ;
- push_cmd <= '1';
- xfer_cmd <= '1';
- rdp_valid <= '1';
- tstpointA <= "0000";
- ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
- next_state <= WRITE;
- tstpointA <= "0001";
- IF ((cmd_wr AND last_word_wr_i) = '1') THEN
- wdp_valid <= '1';
- wdp_validB <= '1';
- wdp_validC <= '1';
- ELSE
- wdp_valid <= '0';
- wdp_validB <= '0';
- wdp_validC <= '0';
- END IF;
- IF (last_word_wr_i = '1') THEN
- push_cmd <= '1';
- xfer_cmd <= '1';
- ELSE
- push_cmd <= '0';
- xfer_cmd <= '0';
- END IF;
- ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
- next_state <= REFRESH_ST;
- push_cmd <= '1';
- xfer_cmd <= '1';
- tstpointA <= "0010";
- wdp_valid <= '0';
- wdp_validB <= '0';
- wdp_validC <= '0';
- rdp_valid <= '0';
- ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
- next_state <= CMD_WAIT;
- push_cmd <= '0';
- xfer_cmd <= '0';
- tstpointA <= "0011";
- ELSE
- next_state <= WRITE;
- tstpointA <= "0100";
- END IF;
- IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
- cmd_rdy <= wait_done;
- ELSE
- cmd_rdy <= '0';
- END IF;
-
- WHEN CMD_WAIT =>
- IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
- next_state <= CMD_WAIT;
- cmd_rdy <= '0';
- tstpointA <= "1010";
- ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
- next_state <= READ;
- push_cmd <= '1';
- xfer_cmd <= '1';
- cmd_rdy <= '1';
- rdp_valid <= '1';
- tstpointA <= "1011";
- ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
- next_state <= WRITE;
- push_cmd <= '1';
- xfer_cmd <= '1';
- wdp_valid <= '1';
- wdp_validB <= '1';
- wdp_validC <= '1';
- cmd_rdy <= '1';
- tstpointA <= "1100";
- ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
- next_state <= REFRESH_ST;
- push_cmd <= '1';
- xfer_cmd <= '1';
- tstpointA <= "1101";
- cmd_rdy <= '1';
- ELSE
- next_state <= CMD_WAIT;
- tstpointA <= "1110";
- IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
- cmd_rdy <= '1';
- ELSE
- cmd_rdy <= '0';
- END IF;
- END IF;
-
- WHEN OTHERS =>
- push_cmd <= '0';
- xfer_cmd <= '0';
- wdp_valid <= '0';
- wdp_validB <= '0';
- wdp_validC <= '0';
- next_state <= READY;
- END CASE;
- END PROCESS;
-
-
-END trans;
-
-
ipcore_dir/mem0/user_design/sim/mcb_flow_control.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/isim.sh
===================================================================
--- ipcore_dir/mem0/user_design/sim/isim.sh (revision 5)
+++ ipcore_dir/mem0/user_design/sim/isim.sh (nonexistent)
@@ -1,70 +0,0 @@
-#!/bin/csh -f
-#*****************************************************************************
-# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# ****************************************************************************
-# ____ ____
-# / /\/ /
-# /___/ \ / Vendor : Xilinx
-# \ \ \/ Version : 3.5
-# \ \ Application : MIG
-# / / Filename : isim.bat
-# /___/ /\ Date Last Modified : $Date: 2010/05/13 09:59:45 $
-# \ \ / \ Date Created : Fri Feb 06 2009
-# \___\/\___\
-#
-# Device : Spartan-6
-# Design Name : DDR/DDR2/DDR3/LPDDR
-# Purpose : Batch file to run Simulation through ISIM
-# Reference :
-# Revision History :
-# ****************************************************************************
-
-echo Simulation Tool: ISIM
-fuse work.sim_tb_top work.glbl -prj mem0.prj -L unisim -L secureip -o mem0
-./mem0 -gui -tclbatch isim.tcl -wdb mem0.wdb
-echo done
ipcore_dir/mem0/user_design/sim/isim.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/sp6_data_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/sp6_data_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/sp6_data_gen.vhd (nonexistent)
@@ -1,793 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: sp6_data_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This module generates different data pattern as described in
--- parameter DATA_PATTERN and is set up for Spartan 6 family.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-entity sp6_data_gen is
- generic (
-
- ADDR_WIDTH : integer := 32;
- BL_WIDTH : integer := 6;
- DWIDTH : integer := 32;
- DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : integer := 8;
- COLUMN_WIDTH : integer := 10
- );
- port (
-
- clk_i : in std_logic; --
- rst_i : in std_logic;
- prbs_fseed_i : in std_logic_vector(31 downto 0);
-
- data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
- data_rdy_i : in std_logic;
- cmd_startA : in std_logic;
- cmd_startB : in std_logic;
- cmd_startC : in std_logic;
- cmd_startD : in std_logic;
- cmd_startE : in std_logic;
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
- user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
-
- fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
- -- connect from mcb_rd_empty when used as rd_data_gen
- -- When both data_rdy and data_valid is asserted, the ouput data is valid.
- data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
- );
-end entity sp6_data_gen;
-
-architecture trans of sp6_data_gen is
-
-COMPONENT data_prbs_gen IS
- GENERIC (
- EYE_TEST : STRING := "FALSE";
- PRBS_WIDTH : INTEGER := 32;
- SEED_WIDTH : INTEGER := 32
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- clk_en : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- prbs_seed_init : IN STD_LOGIC;
- prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
-
- prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
- );
-END COMPONENT;
-
- --
- signal prbs_data : std_logic_vector(31 downto 0);
-
- signal adata : std_logic_vector(31 downto 0);
- signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
- signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
- signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
- signal data : std_logic_vector(DWIDTH - 1 downto 0);
- signal burst_count_reached2 : std_logic;
-
- signal data_valid : std_logic;
- signal walk_cnt : std_logic_vector(2 downto 0);
- signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
-
- signal i : integer;
- signal j : integer;
- signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
- signal BLANK : std_logic_vector(7 downto 0);
-
- signal SHIFT_0 : std_logic_vector(7 downto 0);
- signal SHIFT_1 : std_logic_vector(7 downto 0);
- signal SHIFT_2 : std_logic_vector(7 downto 0);
- signal SHIFT_3 : std_logic_vector(7 downto 0);
- signal SHIFT_4 : std_logic_vector(7 downto 0);
- signal SHIFT_5 : std_logic_vector(7 downto 0);
- signal SHIFT_6 : std_logic_vector(7 downto 0);
- signal SHIFT_7 : std_logic_vector(7 downto 0);
- signal SHIFTB_0 : std_logic_vector(31 downto 0);
- signal SHIFTB_1 : std_logic_vector(31 downto 0);
- signal SHIFTB_2 : std_logic_vector(31 downto 0);
- signal SHIFTB_3 : std_logic_vector(31 downto 0);
- signal SHIFTB_4 : std_logic_vector(31 downto 0);
- signal SHIFTB_5 : std_logic_vector(31 downto 0);
- signal SHIFTB_6 : std_logic_vector(31 downto 0);
- signal SHIFTB_7 : std_logic_vector(31 downto 0);
- signal TSTB : std_logic_vector(3 downto 0);
- --*********************************************************************************************
-
- -- 4'b0000: data = 32'b0; //bram
- -- 4'b0001: data = 32'b0; // fixed
- -- address as data
- -- DGEN_HAMMER
- -- DGEN_NEIGHBOUR
- -- DGEN_WALKING1
- -- DGEN_WALKING0
-
- --bram
- -- fixed
- -- address as data
- -- DGEN_HAMMER
- -- DGEN_NEIGHBOUR
- -- DGEN_WALKING1
- -- DGEN_WALKING0
-
- --bram
- -- fixed
- -- address as data
- -- DGEN_HAMMER
- -- DGEN_NEIGHBOUR
- -- DGEN_WALKING1
- -- DGEN_WALKING0
-
- -- WALKING ONES:
-
- -- WALKING ONE
-
- -- NEIGHBOR ONE
-
- -- WALKING ZERO
-
- -- WALKING ONE
-
- -- NEIGHBOR ONE
-
- -- WALKING ZERO
-
- signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
- signal ndata_rising : std_logic;
- signal shift_en : std_logic;
- signal data_clk_en : std_logic;
- SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
-
-begin
- ZEROS <= (others => '0');
- data_o <= data;
- xhdl0 : if (DWIDTH = 32) generate
- process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
- begin
- case data_mode_i is
- when "0001" =>
- data <= fixed_data_i;
- when "0010" =>
- data <= adata;
- when "0011" =>
- data <= hdata;
- when "0100" =>
- data <= ndata;
- when "0101" =>
- data <= w1data;
- when "0110" =>
- data <= w1data;
- when "0111" =>
- data <= prbs_data;
- WHEN OTHERS =>
- data <= (others => '0');
- END CASE;
- END PROCESS;
-
- end generate;
- xhdl1 : if (DWIDTH = 64) generate
- process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
- begin
- case data_mode_i is
- when "0000" =>
- data <= (others => '0');
- when "0001" =>
- data <= fixed_data_i;
- when "0010" =>
--- data <= (adata & adata)(31 downto 0);
- data <= (adata & adata);
- when "0011" =>
- data <= hdata;
- when "0100" =>
- data <= ndata;
- when "0101" =>
- data <= w1data;
- when "0110" =>
- data <= w1data;
- when "0111" =>
--- data <= (prbs_data & prbs_data)(31 downto 0);
- data <= (prbs_data & prbs_data);
- when others =>
- data <= (others => '0');
- end case;
- end process;
-
- end generate;
- xhdl2 : if (DWIDTH = 128) generate
- process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
- begin
- case data_mode_i is
- when "0000" =>
- data <= (others => '0');
- when "0001" =>
- data <= fixed_data_i;
- when "0010" =>
--- data <= (adata & adata & adata & adata)(31 downto 0);
- data <= (adata & adata & adata & adata);
- when "0011" =>
- data <= hdata;
- when "0100" =>
- data <= ndata;
- when "0101" =>
- data <= w1data;
- when "0110" =>
- data <= w1data;
- when "0111" =>
--- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
- data <= (prbs_data & prbs_data & prbs_data & prbs_data);
- when others =>
- data <= (others => '0');--"00000000000000000000000000000000";
- end case;
- end process;
-
- end generate;
- xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
- process (data_mode_i)
- begin
- if (data_mode_i = "0101" or data_mode_i = "0100") then
- BLANK <= "00000000";
- SHIFT_0 <= "00000001";
- SHIFT_1 <= "00000010";
- SHIFT_2 <= "00000100";
- SHIFT_3 <= "00001000";
- SHIFT_4 <= "00010000";
- SHIFT_5 <= "00100000";
- SHIFT_6 <= "01000000";
- SHIFT_7 <= "10000000";
- elsif (data_mode_i = "0100") then
- BLANK <= "00000000";
- SHIFT_0 <= "00000001";
- SHIFT_1 <= "00000010";
- SHIFT_2 <= "00000100";
- SHIFT_3 <= "00001000";
- SHIFT_4 <= "00010000";
- SHIFT_5 <= "00100000";
- SHIFT_6 <= "01000000";
- SHIFT_7 <= "10000000";
- elsif (data_mode_i = "0110") then
- BLANK <= "11111111";
- SHIFT_0 <= "11111110";
- SHIFT_1 <= "11111101";
- SHIFT_2 <= "11111011";
- SHIFT_3 <= "11110111";
- SHIFT_4 <= "11101111";
- SHIFT_5 <= "11011111";
- SHIFT_6 <= "10111111";
- SHIFT_7 <= "01111111";
- else
- BLANK <= "11111111";
- SHIFT_0 <= "11111110";
- SHIFT_1 <= "11111101";
- SHIFT_2 <= "11111011";
- SHIFT_3 <= "11110111";
- SHIFT_4 <= "11101111";
- SHIFT_5 <= "11011111";
- SHIFT_6 <= "10111111";
- SHIFT_7 <= "01111111";
- end if;
- end process;
-
- end generate;
- process (data_mode_i)
- begin
- if (data_mode_i = "0101") then
- SHIFTB_0 <= "00000000000000100000000000000001";
- SHIFTB_1 <= "00000000000010000000000000000100";
- SHIFTB_2 <= "00000000001000000000000000010000";
- SHIFTB_3 <= "00000000100000000000000001000000";
- SHIFTB_4 <= "00000010000000000000000100000000";
- SHIFTB_5 <= "00001000000000000000010000000000";
- SHIFTB_6 <= "00100000000000000001000000000000";
- SHIFTB_7 <= "10000000000000000100000000000000";
- elsif (data_mode_i = "0100") then
- SHIFTB_0 <= "00000000000000000000000000000001";
- SHIFTB_1 <= "00000000000000000000000000000010";
- SHIFTB_2 <= "00000000000000000000000000000100";
- SHIFTB_3 <= "00000000000000000000000000001000";
- SHIFTB_4 <= "00000000000000000000000000010000";
- SHIFTB_5 <= "00000000000000000000000000100000";
- SHIFTB_6 <= "00000000000000000000000001000000";
- SHIFTB_7 <= "00000000000000000000000010000000";
- else
- SHIFTB_0 <= "11111111111111011111111111111110";
- SHIFTB_1 <= "11111111111101111111111111111011";
- SHIFTB_2 <= "11111111110111111111111111101111";
- SHIFTB_3 <= "11111111011111111111111110111111";
- SHIFTB_4 <= "11111101111111111111111011111111";
- SHIFTB_5 <= "11110111111111111111101111111111";
- SHIFTB_6 <= "11011111111111111110111111111111";
- SHIFTB_7 <= "01111111111111111011111111111111";
- end if;
- end process;
-
- xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i = '1') then
- w1data <= (others => '0');
- ndata_rising <= '1';
- shift_en <= '0';
- elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
- if (NUM_DQ_PINS = 16) then
- if (cmd_startC = '1') then
- case addr_i(4 downto 2) is
- when "000" =>
- w1data <= SHIFTB_0;
- when "001" =>
- w1data <= SHIFTB_1;
- when "010" =>
- w1data <= SHIFTB_2;
- when "011" =>
- w1data <= SHIFTB_3;
- when "100" =>
- w1data <= SHIFTB_4;
- when "101" =>
- w1data <= SHIFTB_5;
- when "110" =>
- w1data <= SHIFTB_6;
-
- when "111" =>
- w1data <= SHIFTB_7;
- when others =>
- w1data <= SHIFTB_0;
- end case;
-
- ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
- --shifting
- elsif (data_mode_i = "0100") then
- w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
- else
-
- w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
- end if;
- elsif (NUM_DQ_PINS = 8) then
- if (cmd_startC = '1') then -- loading data pattern according the incoming address
- case addr_i(2) is
- when '0' =>
- w1data <= SHIFTB_0;
- when '1' =>
- w1data <= SHIFTB_1;
- when others =>
- w1data <= SHIFTB_0;
- end case;
- else
- -- (cmd_startC)
- -- Shifting
- -- need neigbour pattern ********************
-
- w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
- end if;
- elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
- -- need neigbour pattern ********************
- if (data_mode_i = "0100") then
- w1data <= "00001000000001000000001000000001";
- else
- w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
- end if;
- end if;
- end if;
- end if;
- end process;
-
-
--- -- DWIDTH == 32
- end generate;
-
- xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i = '1') then
-
- w1data <= (others => '0');
- elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
-
- if (NUM_DQ_PINS = 16) then
- if (cmd_startC = '1') then
-
-
- case addr_i(4 downto 3) is
- -- 7:0
-
- when "00" =>
- w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
- w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
-
- when "01" =>
- w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
- w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
- when "10" =>
- w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
- w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
-
- when "11" =>
- w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
- w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
- --15:8
-
- when others =>
- w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
- end case;
- else
-
- --(NUM_DQ_PINS == 16) (cmd_startC)
- --shifting
- if (data_mode_i = "0100") then
- w1data(63 downto 48) <= "0000000000000000";
- w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
- w1data(31 downto 16) <= "0000000000000000";
-
- w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
- else
-
--- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
- w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
- w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
- w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
- w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
- w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
- w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
- w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
- end if;
- end if;
-
- --(DQ_PINS == 16
- elsif (NUM_DQ_PINS = 8) then
- if (cmd_startC = '1') then -- loading data pattern according the incoming address
-
- if (data_mode_i = "0100") then
-
- case addr_i(3) is
-
- when '0' =>
- w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
-
- when '1' =>
- w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
- --15:8
-
- when others =>
- w1data <= (others => '0');--"00000000000000000000000000000000";
- end case;
- else
-
- w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
- w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
- w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
- end if;
- -- Shifting
- elsif (data_mode_i = "0100") then
-
- w1data(63 downto 56) <= "00000000";
-
- w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
- w1data(47 downto 40) <= "00000000";
-
- w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
- w1data(31 downto 24) <= "00000000";
-
- w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
- w1data(15 downto 8) <= "00000000";
-
- w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
- else
- w1data <= w1data; --(NUM_DQ_PINS == 8)
- end if;
- elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
- if (data_mode_i = "0100") then
- w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
- else
-
- w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
- end if;
- end if;
- end if;
- end if;
- end process;
-
- end generate;
-
-
- xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i = '1') then
-
- w1data <= (others => '0');
- elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
-
- if (NUM_DQ_PINS = 16) then
- if (cmd_startC = '1') then
-
- case addr_i(4) is
-
- -- 32
-
- when '0' =>
- w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
- w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
- w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
- w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-
- -- 32
-
- when '1' =>
- w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
- w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
- w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
- w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
- --15:8
-
- when others =>
- w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
- end case;
- else
-
- --(NUM_DQ_PINS == 16) (cmd_startC)
- --shifting
- if (data_mode_i = "0100") then
- w1data(127 downto 112) <= "0000000000000000";
- w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
- w1data(95 downto 80) <= "0000000000000000";
-
- w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
- w1data(63 downto 48) <= "0000000000000000";
- w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
- w1data(31 downto 16) <= "0000000000000000";
-
- w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
- else
-
- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
- end if;
- end if;
-
- --(DQ_PINS == 16
- elsif (NUM_DQ_PINS = 8) then
- if (cmd_startC = '1') then -- loading data pattern according the incoming address
- if (data_mode_i = "0100") then
- w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
- else
-
- w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
- end if;
- else
- -- Shifting
-
- --{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
- w1data <= w1data; -- else
- end if;
- --(NUM_DQ_PINS == 8)
- elsif (data_mode_i = "0100") then
- w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
- else
-
- w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
- end if;
- end if;
- end if;
- end process;
-
- end generate;
-
- -- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
- -- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
- -- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
- xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i = '1') then
- hdata <= (others => '0');
--- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
- elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
-
- if (NUM_DQ_PINS = 16) then
- hdata <= "00000000000000001111111111111111";
- elsif (NUM_DQ_PINS = 8) then
- hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
- elsif (NUM_DQ_PINS = 4) then
- hdata <= "00001111000011110000111100001111";
- end if;
- end if;
- end if;
- end process;
-
- end generate;
-
- xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i = '1') then
- hdata <= (others => '0');
- elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
- if (NUM_DQ_PINS = 16) then
- hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
- elsif (NUM_DQ_PINS = 8) then
- hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
- elsif (NUM_DQ_PINS = 4) then
-
- hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
- end if;
- end if;
- end if;
- end process;
-
- end generate;
-
- xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i = '1') then
- hdata <= (others => '0');
- elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
- if (NUM_DQ_PINS = 16) then
- hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
- elsif (NUM_DQ_PINS = 8) then
- hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
- elsif (NUM_DQ_PINS = 4) then
-
- hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
- end if;
- end if;
- end if;
- end process;
-
- end generate;
-
- process (w1data, hdata)
- begin
- for i in 0 to DWIDTH - 1 loop
-
- ndata(i) <= hdata(i) xor w1data(i);
- end loop;
- end process;
-
-
- -- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
- -- the position of the pin driving oppsite polarity
- -- addr_i[6:2] = 5'h0f ; 32 bit data port
- -- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
- -- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-
- -- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
- -- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
- -- => the 1st data pattern : 32'h12345678
- -- => the 2nd data pattern : 32'h12345679
- -- => the 3rd data pattern : 32'h1234567a
- -- => the 4th data pattern : 32'h1234567b
-
- --data_rdy_i
-
- xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
- --data_o logic
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (cmd_startD = '1') then
- adata <= addr_i;
- elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
- if (DWIDTH = 128) then
- adata <= adata + "00000000000000000000000000010000";
- elsif (DWIDTH = 64) then
- adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
- else
- adata <= adata + "00000000000000000000000000000100";
- end if;
- end if;
- end if;
- end process;
-
- end generate;
-
- -- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
- -- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
- --
-
- xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-
- -- PRBS DATA GENERATION
- -- xor all the tap positions before feedback to 1st stage.
-
--- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
- data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
-
-
- data_prbs_gen_inst : data_prbs_gen
- generic map (
- prbs_width => 32,
- seed_width => 32
- )
- port map (
- clk_i => clk_i,
- clk_en => data_clk_en,
- rst_i => rst_i,
- prbs_fseed_i => prbs_fseed_i,
- prbs_seed_init => cmd_startE,
- prbs_seed_i => addr_i(31 downto 0),
- prbs_o => prbs_data
- );
-
- end generate;
-
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/sim/sp6_data_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/readme.txt
===================================================================
--- ipcore_dir/mem0/user_design/sim/readme.txt (revision 5)
+++ ipcore_dir/mem0/user_design/sim/readme.txt (nonexistent)
@@ -1,171 +0,0 @@
-###############################################################################
-## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-###############################################################################
-## ____ ____
-## / /\/ /
-## /___/ \ / Vendor : Xilinx
-## \ \ \/ Version : 3.5
-## \ \ Application : MIG
-## / / Filename : readme.txt
-## /___/ /\ Date Last Modified : $Date: 2010/04/06 08:26:18 $
-## \ \ / \ Date Created : Mon Oct 19 2009
-## \___\/\___\
-##
-## Device : Spartan-6
-## Design Name : DDR/DDR2/DDR3/LPDDR
-## Purpose : Steps to run simulation using ISIM/Modelsim simualtor in this folder
-## Assumptions:
-## - Simulation takes place in \sim\ folder of MIG output directory
-## Reference :
-## Revision History:
-###############################################################################
-
-
-**************************************************************************************
-*** FUNCTIONAL SIMULATION ***
-**************************************************************************************
-
-Th sim/functional folder has files to perform functional simulation of the design.
-
-1. Simulation using Modelsim simulator
-
-A) sim.do File :
-
- 1) The 'sim.do' file has commands to compile and simulate memory interface
- design and run the simulation for specified period of time.
-
- 2) It has the syntax to Map the required libraries.
- Also, $XILINX environment variable must be set in order to compile glbl.v file
- 3) Displays the waveforms that are listed with "add wave" command.
-
-B) Steps to run the Modelsim simulation:
-
- 1) The user should invoke the Modelsim simulator GUI.
- 2) Change the present working directory path to the sim/functional folder.
- In Transcript window, at Modelsim prompt, type the following command to
- change directory path.
- cd
-
- 2) Run the simulation using sim.do file.
- At Modelsim prompt, type the following command:
- do sim.do
-
- 3) To exit simulation, type the following command at Modelsim prompt:
- quit -f
-
- 4) Verify the transcript file for the memory transactions.
-
-
-2. Simulation using ISIM simulator
-
-A) Following files are provided :
-
- 1) The '.prj' file contains the list of all the files associated with the design.
- It also contains the hdl, library and the source file name.
-
- 2) The '.tcl' file contains the Tcl commands for simulation and
- resume on error.
-
- 3) The 'isim.bat' has commands which use '.prj' and '.tcl' files.
-
-
-B) Steps to run the ISIM simulation:
-
- The user should execute the file isim.bat, which does the following steps:
- 1) Compiles, elaborates the design and generates the simulation executable using
- the fuse command in 'isim.bat' file.
-
- 2) Invokes the ISIM GUI.
-
- 3) User can add required signals from objects window to the waveform viewer and run
- simulation for specified time using the command "run
ipcore_dir/mem0/user_design/sim/read_posted_fifo.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/cmd_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/cmd_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/cmd_gen.vhd (nonexistent)
@@ -1,1076 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: cmd_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:07 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This module genreates different type of commands, address,
--- burst_length to mcb_flow_control module.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-
-ENTITY cmd_gen IS
- GENERIC (
- FAMILY : STRING := "SPARTAN6";
- MEM_BURST_LEN : INTEGER := 8;
- TCQ : TIME := 100 ps;
- PORT_MODE : STRING := "BI_MODE";
- NUM_DQ_PINS : INTEGER := 8;
- DATA_PATTERN : STRING := "DGEN_ALL";
- CMD_PATTERN : STRING := "CGEN_ALL";
- ADDR_WIDTH : INTEGER := 30;
- DWIDTH : INTEGER := 32;
- PIPE_STAGES : INTEGER := 0;
- MEM_COL_WIDTH : INTEGER := 10;
- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
- PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
- );
- PORT (
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
- run_traffic_i : IN STD_LOGIC;
- rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
- force_wrcmd_gen_i : IN STD_LOGIC;
- start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- load_seed_i : IN STD_LOGIC;
- addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- mode_load_i : IN STD_LOGIC;
- fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- bram_valid_i : IN STD_LOGIC;
- bram_rdy_o : OUT STD_LOGIC;
- reading_rd_data_i : IN STD_LOGIC;
- rdy_i : IN STD_LOGIC;
- addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- cmd_o_vld : OUT STD_LOGIC
- );
-END cmd_gen;
-
-ARCHITECTURE trans OF cmd_gen IS
- constant PRBS_ADDR_WIDTH : INTEGER := 32;
- constant INSTR_PRBS_WIDTH : INTEGER := 16;
- constant BL_PRBS_WIDTH : INTEGER := 16;
-
- constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
- constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
- constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
- constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
- constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
- constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
- constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
-COMPONENT pipeline_inserter IS
- GENERIC (
- DATA_WIDTH : INTEGER := 32;
- PIPE_STAGES : INTEGER := 1
- );
- PORT (
- data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
- clk_i : IN STD_LOGIC;
- en_i : IN STD_LOGIC;
-
- data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
- );
-END COMPONENT;
-
-COMPONENT cmd_prbs_gen IS
- GENERIC (
- TCQ : time := 100 ps;
- FAMILY : STRING := "SPARTAN6";
- ADDR_WIDTH : INTEGER := 29;
- DWIDTH : INTEGER := 32;
- PRBS_CMD : STRING := "ADDRESS";
- PRBS_WIDTH : INTEGER := 64;
- SEED_WIDTH : INTEGER := 32;
- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
- PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
- PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- prbs_seed_init : IN STD_LOGIC;
- clk_en : IN STD_LOGIC;
- prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
-
- prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
- );
-END COMPONENT;
-
-function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
-begin
- if A = true then
- return '1';
- else
- return '0';
- end if;
-end function BOOLEAN_TO_STD_LOGIC;
-
- SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
- SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
- SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
- SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
- SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL mode_load_d1 : STD_LOGIC;
- SIGNAL mode_load_d2 : STD_LOGIC;
- SIGNAL mode_load_pulse : STD_LOGIC;
- SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
- SIGNAL cmd_clk_en : STD_LOGIC;
- SIGNAL pipe_out_vld : STD_LOGIC;
- SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
- SIGNAL force_bl1 : STD_LOGIC;
- SIGNAL A0_G_E0 : STD_LOGIC;
- SIGNAL A1_G_E1 : STD_LOGIC;
- SIGNAL A2_G_E2 : STD_LOGIC;
- SIGNAL A3_G_E3 : STD_LOGIC;
- SIGNAL AC3_G_E3 : STD_LOGIC;
- SIGNAL AC2_G_E2 : STD_LOGIC;
- SIGNAL AC1_G_E1 : STD_LOGIC;
- SIGNAL bl_out_clk_en : STD_LOGIC;
- SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
- SIGNAL instr_vld : STD_LOGIC;
- SIGNAL bl_out_vld : STD_LOGIC;
- SIGNAL cmd_vld : STD_LOGIC;
- SIGNAL run_traffic_r : STD_LOGIC;
- SIGNAL run_traffic_pulse : STD_LOGIC;
-
- SIGNAL pipe_data_in_vld : STD_LOGIC;
- SIGNAL gen_addr_larger : STD_LOGIC;
- SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
- SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
- SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
- SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
- SIGNAL instr_vld_dly1 : STD_LOGIC;
- SIGNAL first_load_pulse : STD_LOGIC;
- SIGNAL mem_init_done : STD_LOGIC;
- SIGNAL i : INTEGER;
- SIGNAL force_wrcmd_gen : STD_LOGIC;
- SIGNAL force_smallvalue : STD_LOGIC;
-
- SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
- SIGNAL force_rd : STD_LOGIC;
- SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL refresh_cmd_en : STD_LOGIC;
- SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
- SIGNAL refresh_prbs : STD_LOGIC;
- SIGNAL cmd_clk_en_r : STD_LOGIC;
-
- signal instr_mode_reg : std_logic_vector(3 downto 0);
-
-
- -- X-HDL generated signals
-
- SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-
- -- Declare intermediate signals for referenced outputs
- SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
- SIGNAL mode_load_pulse_r1 : STD_LOGIC;
-
-BEGIN
- -- Drive referenced outputs
- bl_o <= bl_o_xhdl0;
- addr_o <= pipe_data_o(31 DOWNTO 0);
- instr_o <= pipe_data_o(34 DOWNTO 32);
- bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
- cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
- pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
- pipe_data_o <= pipe_data_in;
-
-
- cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- cmd_vld <= cmd_clk_en;
- END IF;
- END PROCESS;
- END GENERATE;
-
- cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
- END IF;
- END PROCESS;
- END GENERATE;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- run_traffic_r <= run_traffic_i ;
- IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
- run_traffic_pulse <= '1' ;
- ELSE
- run_traffic_pulse <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
- bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
- bl_out_vld <= bl_out_clk_en ;
- pipe_data_in_vld <= instr_vld ;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0) = '1') THEN
- first_load_pulse <= '1' ;
- ELSIF (mode_load_pulse = '1') THEN
- first_load_pulse <= '0' ;
- ELSE
- first_load_pulse <= first_load_pulse ;
- END IF;
- END IF;
- END PROCESS;
-
-
- cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
-
- pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(0)) = '1') THEN
- pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
- ELSIF (instr_vld = '1') THEN
- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-
- IF (DWIDTH = 32) THEN
- pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
- ELSIF (DWIDTH = 64) THEN
- pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
- ELSE
- pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
- END IF;
-
- ELSE
- IF (DWIDTH = 32) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
- ELSIF (DWIDTH = 64) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
- ELSIF (DWIDTH = 128) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
- END IF;
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(1)) = '1') THEN
- pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
- ELSIF (instr_vld = '1') THEN
- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
- pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
-
- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
- IF (MEM_BURST_LEN = 8) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
- ELSE
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
- END IF;
-
- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-
- IF (MEM_BURST_LEN = 8) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
- ELSE
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
- END IF;
-
- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
- IF (MEM_BURST_LEN = 8) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
- ELSE
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
- END IF;
-
- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
- IF (MEM_BURST_LEN = 8) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
- ELSE
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
- END IF;
- ELSIF (NUM_DQ_PINS = 8) THEN
- IF (MEM_BURST_LEN = 8) THEN
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
- ELSE
- pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
- END IF;
-
-
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(1)) = '1') THEN
- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
- ELSIF (instr_vld = '1') THEN
- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
-
- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
-
- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0) = '1') THEN
- force_wrcmd_gen <= '0' ;
- ELSIF (buf_avail_r = "0111111") THEN
- force_wrcmd_gen <= '0' ;
- ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
- force_wrcmd_gen <= '1' ;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- instr_mode_reg <= instr_mode_i ;
-
- END IF;
- END PROCESS;
- -- **********************************************
-
- PROCESS (clk_i) BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(2)) = '1') THEN
- pipe_data_in(40 DOWNTO 32) <= "000000000";
- force_smallvalue <= '0';
- ELSIF (instr_vld = '1') THEN
-
- IF (instr_mode_reg = 0) THEN
- pipe_data_in(34 DOWNTO 32) <= instr_out ;
-
- ELSIF (instr_out(2) = '1') THEN
-
- pipe_data_in(34 DOWNTO 32) <= "100" ;
-
-
- ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
-
- pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
-
- ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
- pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
- ELSE
- pipe_data_in(34 DOWNTO 32) <= instr_out;
-
- END IF;
- ----********* condition the generated bl value except if TG is programmed for BRAM interface'
- ---- if the generated address is close to end address range, the bl_out will be altered to 1.
- --
- IF (bl_mode_i = 0) THEN
- pipe_data_in(40 DOWNTO 35) <= bl_out ;
- ELSIF ( FAMILY = "VIRTEX6") THEN
- pipe_data_in(40 DOWNTO 35) <= bl_out ;
- ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
-
- pipe_data_in(40 DOWNTO 35) <= "000001" ;
-
-
- -- **********************************************
-
- ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
- IF (bl_mode_reg = "10") THEN
- force_smallvalue <= NOT(force_smallvalue) ;
- END IF;
- IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
- pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
- ELSE
- pipe_data_in(40 DOWNTO 35) <= bl_out ;
- END IF;
- ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
- IF (FAMILY = "SPARTAN6") THEN
- pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
- ELSE
- pipe_data_in(40 DOWNTO 35) <= bl_out ;
- END IF;
- END IF; --IF (bl_mode_i = 0) THEN
- END IF; --IF ((rst_i(2)) = '1') THEN
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(2)) = '1') THEN
- pipe_data_in(41) <= '0' ;
- ELSIF (cmd_vld = '1') THEN
- pipe_data_in(41) <= instr_vld ;
- ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
- pipe_data_in(41) <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- instr_vld_dly1 <= instr_vld;
- END IF;
- END PROCESS;
-
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0) = '1') THEN
- rd_data_counts_asked <= (others => '0') ;
- ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
- IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
- rd_data_counts_asked <= rd_data_counts_asked + 64 ;
-
- ELSE
- rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
-
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i(0) = '1') THEN
- rd_data_received_counts <= (others => '0');
- rd_data_received_counts_total <= (others => '0');
- ELSIF (reading_rd_data_i = '1') THEN
- rd_data_received_counts <= rd_data_received_counts + '1';
- rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(3)) = '1') THEN
- IF (CMD_PATTERN = "CGEN_BRAM") THEN
- addr_mode_reg <= "000";
- ELSE
- addr_mode_reg <= "011";
- END IF;
- ELSIF (mode_load_pulse = '1') THEN
- addr_mode_reg <= addr_mode_i;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (mode_load_pulse = '1') THEN
- bl_mode_reg <= bl_mode_i;
- END IF;
- mode_load_d1 <= mode_load_i;
- mode_load_d2 <= mode_load_d1;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
- END IF;
- END PROCESS;
-
- xhdl4 <= addr_mode_reg;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(3)) = '1') THEN
- addr_out <= start_addr_i;
- ELSE
- CASE xhdl4 IS
- WHEN "000" =>
- addr_out <= bram_addr_i;
- WHEN "001" =>
- addr_out <= fixed_addr;
- WHEN "010" =>
- addr_out <= prbs_addr;
- WHEN "011" =>
- addr_out <= ("00" & seq_addr(29 DOWNTO 0));
- WHEN "100" =>
--- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
- addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
- WHEN "101" =>
- addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
- -- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
- WHEN OTHERS =>
- addr_out <= (others => '0');--"00000000000000000000000000000000";
- END CASE;
- END IF;
- END IF;
- END PROCESS;
-
- xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
-
-
- addr_prbs_gen : cmd_prbs_gen
- GENERIC MAP (
- family => FAMILY,
- addr_width => 32,
- dwidth => DWIDTH,
- prbs_width => 32,
- seed_width => 32,
- prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
- prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
- prbs_eaddr => PRBS_EADDR,
- prbs_saddr => PRBS_SADDR
- )
- PORT MAP (
- clk_i => clk_i,
- clk_en => cmd_clk_en,
- prbs_seed_init => mode_load_pulse,
- prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
- prbs_o => prbs_addr
- );
- END GENERATE;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
- gen_addr_larger <= '1';
- ELSE
- gen_addr_larger <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (mem_init_done = '1') THEN
- INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
- ELSE
- IF (fixed_bl_i = "000000") THEN
- INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
- ELSE
- INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
- INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
-
- ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
- INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
- ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
- INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
- ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
- INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
- ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
- INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
- AC3_G_E3 <= '1';
- ELSE
- AC3_G_E3 <= '0';
- END IF;
- IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
- AC2_G_E2 <= '1';
- ELSE
- AC2_G_E2 <= '0';
- END IF;
- IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
- AC1_G_E1 <= '1';
- ELSE
- AC1_G_E1 <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
- seq_addr <= addr_counts;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- mode_load_pulse_r1 <= mode_load_pulse;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- addr_counts_next_r <= addr_counts + (INC_COUNTS);
-
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- cmd_clk_en_r <= cmd_clk_en;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(4)) = '1') THEN
- addr_counts <= start_addr_i;
- mem_init_done <= '0';
- ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
--- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
- IF (addr_counts_next_r >= end_addr_i) THEN
- addr_counts <= start_addr_i;
- mem_init_done <= '1';
- ELSIF (addr_counts < end_addr_r) THEN
- addr_counts <= addr_counts + INC_COUNTS;
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
- fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
- (fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
- (fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
- (fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
- (fixed_addr_i(31 DOWNTO 6) & "000000");
- END GENERATE;
- xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
- bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
- END GENERATE;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(4)) = '1') THEN
- force_rd_counts <= (others => '0');--"0000000000";
- ELSIF (instr_vld = '1') THEN
- force_rd_counts <= force_rd_counts + "0000000001";
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(4)) = '1') THEN
- force_rd <= '0';
- ELSIF ((force_rd_counts(3)) = '1') THEN
- force_rd <= '1';
- ELSE
- force_rd <= '0';
- END IF;
- END IF;
- END PROCESS;
-
-
-
--- adding refresh timer to limit the amount of issuing refresh command.
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(4)) = '1') THEN
- refresh_timer <= (others => '0');
- ELSE
- refresh_timer <= refresh_timer + 1;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(4)) = '1') THEN
- refresh_cmd_en <= '0';
- ELSIF (refresh_timer = "1111111111") THEN
- refresh_cmd_en <= '1';
- ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
- refresh_cmd_en <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (FAMILY = "SPARTAN6") THEN
- refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
- ELSE
- refresh_prbs <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- --synthesis translate_off
- PROCESS (instr_mode_i)
- BEGIN
- IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
- report "Error ! Not valid instruction mode";
- END IF;
- END PROCESS;
- --synthesis translate_on
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- CASE instr_mode_i IS
- WHEN "0000" =>
- instr_out <= bram_instr_i;
- WHEN "0001" =>
- instr_out <= fixed_instr_i;
- WHEN "0010" =>
- instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
- WHEN "0011" =>
- instr_out <= ("00" & prbs_instr_a(0));
- WHEN "0100" =>
- instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
-
- WHEN "0101" =>
- instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
- WHEN OTHERS =>
- instr_out <= ("00" & prbs_instr_a(0));
- END CASE;
- END IF;
- END PROCESS;
-
-
- xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
-
-
-
-
- instr_prbs_gen_a : cmd_prbs_gen
- GENERIC MAP (
- prbs_cmd => "INSTR",
- family => FAMILY,
- addr_width => 32,
- seed_width => 15,
- prbs_width => 20
- )
- PORT MAP (
- clk_i => clk_i,
- clk_en => cmd_clk_en,
- prbs_seed_init => load_seed_i,
- prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
- prbs_o => prbs_instr_a
- );
-
-
-
- instr_prbs_gen_b : cmd_prbs_gen
- GENERIC MAP (
- prbs_cmd => "INSTR",
- family => FAMILY,
- seed_width => 15,
- prbs_width => 20
- )
- PORT MAP (
- clk_i => clk_i,
- clk_en => cmd_clk_en,
- prbs_seed_init => load_seed_i,
- prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
- prbs_o => prbs_instr_b
- );
-
- END GENERATE;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
- A3_G_E3 <= '1' ;
- ELSE
-
- A3_G_E3 <= '0' ;
- END IF;
- IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
- A2_G_E2 <= '1' ;
- ELSE
-
- A2_G_E2 <= '0' ;
- END IF;
- IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
- A1_G_E1 <= '1' ;
- ELSE
-
- A1_G_E1 <= '0' ;
- END IF;
- IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
-
-
-
-
-
- A0_G_E0 <= '1' ;
- ELSE
-
- A0_G_E0 <= '0' ;
- END IF;
- END IF;
- END PROCESS;
-
---testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
-
- PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
- BEGIN
- IF ((rst_i(5)) = '1') THEN
- force_bl1 <= '0';
-
-
- ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
- (buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
- force_bl1 <= '1' ;
- ELSE
- force_bl1 <= '0' ;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i(6)) = '1') THEN
- bl_out_reg <= fixed_bl_i;
- ELSIF (bl_out_vld = '1') THEN
-
- bl_out_reg <= bl_out;
- END IF;
- END IF;
- END PROCESS;
-
- xhdl12 <= bl_mode_reg;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (mode_load_pulse = '1') THEN
- bl_out <= fixed_bl_i;
- ELSIF (cmd_clk_en = '1') THEN
- CASE xhdl12 IS
- WHEN "00" =>
- bl_out <= bram_bl_i;
- WHEN "01" =>
- bl_out <= fixed_bl_i;
- WHEN "10" =>
- bl_out <= prbs_brlen;
- WHEN OTHERS =>
- bl_out <= "000001";
- END CASE;
- END IF;
- END IF;
- END PROCESS;
-
- --synthesis translate_off
- PROCESS (bl_out)
- BEGIN
- IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
- report "Error ! Not valid burst length"; --severity ERROR;
- END IF;
- END PROCESS;
- --synthesis translate_on
-
- xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
-
-
-
-
- bl_prbs_gen : cmd_prbs_gen
- GENERIC MAP (
- TCQ => TCQ,
- family => FAMILY,
- prbs_cmd => "BLEN",
- addr_width => 32,
- seed_width => 15,
- prbs_width => 20
- )
- PORT MAP (
- clk_i => clk_i,
- clk_en => cmd_clk_en,
-
- prbs_seed_init => load_seed_i,
- prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
- prbs_o => prbs_bl
- );
-
- END GENERATE;
--- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
- PROCESS (prbs_bl) BEGIN
- IF (FAMILY = "SPARTAN6") THEN
- if (prbs_bl(5 DOWNTO 0) = "000000") then
--- prbs_brlen <= xhdl14;
- prbs_brlen <= "000001";
- else
- prbs_brlen <= prbs_bl(5 DOWNTO 0);
- end if;
- ELSE
- prbs_brlen <= "000010";
- END IF;
- END PROCESS;
-
-
-
-END trans;
-
-
ipcore_dir/mem0/user_design/sim/cmd_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/ddr_model_parameters_c3.vh
===================================================================
--- ipcore_dir/mem0/user_design/sim/ddr_model_parameters_c3.vh (revision 5)
+++ ipcore_dir/mem0/user_design/sim/ddr_model_parameters_c3.vh (nonexistent)
@@ -1,381 +0,0 @@
-/****************************************************************************************
-*
-* Disclaimer This software code and all associated documentation, comments or other
-* of Warranty: information (collectively "Software") is provided "AS IS" without
-* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
-* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
-* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
-* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
-* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
-* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
-* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
-* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
-* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
-* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
-* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
-* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
-* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
-* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
-* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
-* DAMAGES. Because some jurisdictions prohibit the exclusion or
-* limitation of liability for consequential or incidental damages, the
-* above limitation may not apply to you.
-*
-* Copyright 2003 Micron Technology, Inc. All rights reserved.
-*
-****************************************************************************************/
-
- // Timing parameters based on Speed Grade
-
-`ifdef x128Mb
-
-`ifdef sg5B // Timing Parameters for -5B (CL = 3)
- parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
- parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg75E // Timing Parameters for -75E (CL = 2)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg75Z // Timing Parameters for -75Z (CL = 2)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `define sg75 // Timing Parameters for -75 (CL = 2.5)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`endif `endif `endif `endif
-
- // Size Parameters based on Part Width
-
-`ifdef x4
- parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
-`else `ifdef x8
- parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
-`else `define x16
- parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
-`endif `endif
-
-
-`else `ifdef x256Mb
-
-`ifdef sg5B // Timing Parameters for -5B (CL = 3)
- parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
- parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg6 // Timing Parameters for -6 (CL = 2.5)
- parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg75E // Timing Parameters for -75E (CL = 2)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg75Z // Timing Parameters for -75Z (CL = 2)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `define sg75 // Timing Parameters for -75 (CL = 2.5)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`endif `endif `endif `endif `endif
- // Size Parameters based on Part Width
-
-`ifdef x4
- parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
-`else `ifdef x8
- parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
-`else `define x16
- parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
-`endif `endif
-
-
-`else `ifdef x512Mb
-
-`ifdef sg5B // Timing Parameters for -5B (CL = 3)
- parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
- parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg6 // Timing Parameters for -6 (CL = 2.5)
- parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg75E // Timing Parameters for -75E (CL = 2)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg75Z // Timing Parameters for -75Z (CL = 2)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `define sg75 // Timing Parameters for -75 (CL = 2.5)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 75.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`endif `endif `endif `endif `endif
-
- // Size Parameters based on Part Width
-
-`ifdef x4
- parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 12; // Set this parameter to control how many Column bits are used
-`else `ifdef x8
- parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
-`else `define x16
- parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
-`endif `endif
-
-`else `define x1Gb
-
-`ifdef sg5B // Timing Parameters for -5B (CL = 3)
- parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 10.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
- parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
- parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 15.0; // tRP ns Precharge command period
- parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`else `define sg75 // Timing Parameters for -75 (CL = 2.5)
- parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
- parameter tDQSQ = 0.5; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter tMRD = 15.0; // tMRD ns Load Mode Register command cycle time
- parameter tRAP = 20.0; // tRAP ns ACTIVE to READ with Auto precharge command
- parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
- parameter tRC = 65.0; // tRC ns Active to Active/Auto Refresh command time
- parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
- parameter tRCD = 20.0; // tRCD ns Active to Read/Write command time
- parameter tRP = 20.0; // tRP ns Precharge command period
- parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
- parameter tWR = 15.0; // tWR ns Write recovery time
-`endif `endif
- // Size Parameters based on Part Width
-
-`ifdef x4
- parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 12; // Set this parameter to control how many Column bits are used
-`else `ifdef x8
- parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 1; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 1; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
-`else `define x16
- parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
- parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
- parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
- parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
- parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
-`endif `endif
-
-`endif `endif `endif
-
- parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used
- parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; //10; // BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
- parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
-
- parameter no_halt = 1; // If set to 1, the model won't halt on command sequence/major errors
- parameter DEBUG = 1; // Turn on DEBUG message
Index: ipcore_dir/mem0/user_design/sim/write_data_path.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/write_data_path.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/write_data_path.vhd (nonexistent)
@@ -1,210 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: write_data_path.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This is top level of write path.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
-
-entity write_data_path is
- generic (
- TCQ : TIME := 100 ps;
- MEM_BURST_LEN : integer := 8;
- FAMILY : string := "SPARTAN6";
- ADDR_WIDTH : integer := 32;
- DWIDTH : integer := 32;
- DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : integer := 8;
- SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
-
- MEM_COL_WIDTH : integer := 10;
- EYE_TEST : string := "FALSE"
- );
- port (
-
- clk_i : in std_logic;
- rst_i : in std_logic_vector(9 downto 0);
- cmd_rdy_o : out std_logic;
- cmd_valid_i : in std_logic;
- cmd_validB_i : in std_logic;
- cmd_validC_i : in std_logic;
- prbs_fseed_i : in std_logic_vector(31 downto 0);
- data_mode_i : in std_logic_vector(3 downto 0);
- m_addr_i : in std_logic_vector(31 downto 0);
- fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
- addr_i : in std_logic_vector(31 downto 0);
-
- bl_i : in std_logic_vector(5 downto 0);
-
- -- input [5:0] port_data_counts_i,// connect to data port fifo counts
-
- data_rdy_i : in std_logic;
- data_valid_o : out std_logic;
- last_word_wr_o : out std_logic;
- data_o : out std_logic_vector(DWIDTH - 1 downto 0);
- data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
- data_wr_end_o : out std_logic );
-end entity write_data_path;
-
-architecture trans of write_data_path is
-
- COMPONENT wr_data_gen IS
- GENERIC (
- TCQ : TIME := 100 ps;
- FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
- MODE : STRING := "WR"; --"WR", "RD"
- MEM_BURST_LEN : integer := 8;
- ADDR_WIDTH : INTEGER := 32;
- BL_WIDTH : INTEGER := 6;
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : INTEGER := 8;
- SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
- COLUMN_WIDTH : INTEGER := 10;
- EYE_TEST : STRING := "FALSE"
- );
- PORT (
- clk_i : IN STD_LOGIC;
- rst_i : in STD_LOGIC_VECTOR(4 downto 0);
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- cmd_rdy_o : OUT STD_LOGIC;
- cmd_valid_i : IN STD_LOGIC;
- cmd_validB_i : IN STD_LOGIC;
- cmd_validC_i : IN STD_LOGIC;
- last_word_o : OUT STD_LOGIC;
- fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-
- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
- data_rdy_i : IN STD_LOGIC;
- data_valid_o : OUT STD_LOGIC;
- data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
- data_wr_end_o : OUT STD_LOGIC
- );
- END COMPONENT;
-
- signal data_valid : std_logic;
- signal cmd_rdy : std_logic;
-
- -- Declare intermediate signals for referenced outputs
- signal cmd_rdy_o_xhdl0 : std_logic;
- signal last_word_wr_o_xhdl3 : std_logic;
- signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
- signal data_wr_end_o_xhdl2 : std_logic;
-begin
- -- Drive referenced outputs
- cmd_rdy_o <= cmd_rdy_o_xhdl0;
- last_word_wr_o <= last_word_wr_o_xhdl3;
- data_o <= data_o_xhdl1;
- data_wr_end_o <= data_wr_end_o_xhdl2;
-
- data_valid_o <= data_valid and data_rdy_i;
--- data_mask_o <= "0000"; -- for now
- data_mask_o <= (others => '0');
-
-
- wr_data_gen_inst : wr_data_gen
- generic map (
- TCQ => TCQ,
- family => FAMILY,
- num_dq_pins => NUM_DQ_PINS,
- sel_victim_line => SEL_VICTIM_LINE,
- MEM_BURST_LEN => MEM_BURST_LEN,
-
- data_pattern => DATA_PATTERN,
- dwidth => DWIDTH,
- column_width => MEM_COL_WIDTH,
- eye_test => EYE_TEST
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(9 downto 5),
- prbs_fseed_i => prbs_fseed_i,
-
- data_mode_i => data_mode_i,
- cmd_rdy_o => cmd_rdy_o_xhdl0,
- cmd_valid_i => cmd_valid_i,
- cmd_validb_i => cmd_validB_i,
- cmd_validc_i => cmd_validC_i,
-
- last_word_o => last_word_wr_o_xhdl3,
- -- .port_data_counts_i (port_data_counts_i),
- m_addr_i => m_addr_i,
- fixed_data_i => fixed_data_i,
- addr_i => addr_i,
- bl_i => bl_i,
- data_rdy_i => data_rdy_i,
- data_valid_o => data_valid,
- data_o => data_o_xhdl1,
- data_wr_end_o => data_wr_end_o_xhdl2
- );
-
-end architecture trans;
-
-
-
-
ipcore_dir/mem0/user_design/sim/write_data_path.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/sim_tb_top.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/sim_tb_top.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/sim_tb_top.vhd (nonexistent)
@@ -1,1036 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : sim_tb_top.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/04/22 12:17:54 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
--- Device : Spartan-6
--- Design Name : DDR/DDR2/DDR3/LPDDR
--- Purpose : This is the simulation testbench which is used to verify the
--- design. The basic clocks and resets to the interface are
--- generated here. This also connects the memory interface to the
--- memory model.
---*****************************************************************************
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity sim_tb_top is
-
-end entity sim_tb_top;
-
-architecture arch of sim_tb_top is
-
-
-
--- ========================================================================== --
--- Parameters --
--- ========================================================================== --
- constant DEBUG_EN : integer :=0;
-
- constant C3_HW_TESTING : string := "FALSE";
-
-function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
- begin
- if (C3_HW_TESTING = "FALSE") then
- return val1;
- else
- return val2;
- end if;
- end function;
-
- constant C3_MEMCLK_PERIOD : integer := 5000;
- constant C3_RST_ACT_LOW : integer := 0;
- constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
- constant C3_CLK_PERIOD_NS : real := 5000.0 / 1000.0;
- constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
- constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
- constant C3_NUM_DQ_PINS : integer := 16;
- constant C3_MEM_ADDR_WIDTH : integer := 13;
- constant C3_MEM_BANKADDR_WIDTH : integer := 2;
- constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
- constant C3_P0_MASK_SIZE : integer := 4;
- constant C3_P0_DATA_PORT_SIZE : integer := 32;
- constant C3_P1_MASK_SIZE : integer := 4;
- constant C3_P1_DATA_PORT_SIZE : integer := 32;
- constant C3_MEM_BURST_LEN : integer := 4;
- constant C3_MEM_NUM_COL_BITS : integer := 10;
- constant C3_SIMULATION : string := "TRUE";
- constant C3_CALIB_SOFT_IP : string := "TRUE";
- constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
- constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
- constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
- constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
- constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
- constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000004ff", x"04ffffff");
- constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
- constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
- constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
- constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff");
- constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
- constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
- constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
- constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
- constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
- constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
- constant C3_p4_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000700", x"07000000");
- constant C3_p4_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant C3_p4_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000008ff", x"08ffffff");
- constant C3_p4_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff000", x"f0000000");
- constant C3_p4_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000700", x"07000000");
- constant C3_p5_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
- constant C3_p5_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- constant C3_p5_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
- constant C3_p5_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
- constant C3_p5_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
-
--- ========================================================================== --
--- Component Declarations
--- ========================================================================== --
-
-
-component mem0 is
-generic
-(
- C3_P0_MASK_SIZE : integer;
- C3_P0_DATA_PORT_SIZE : integer;
- C3_P1_MASK_SIZE : integer;
- C3_P1_DATA_PORT_SIZE : integer;
-
- C3_MEMCLK_PERIOD : integer;
- C3_RST_ACT_LOW : integer;
- C3_INPUT_CLK_TYPE : string;
- DEBUG_EN : integer;
-
- C3_CALIB_SOFT_IP : string;
- C3_SIMULATION : string;
- C3_MEM_ADDR_ORDER : string;
- C3_NUM_DQ_PINS : integer;
- C3_MEM_ADDR_WIDTH : integer;
- C3_MEM_BANKADDR_WIDTH : integer
-);
- port
- (
- mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
- mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
- mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
- mcb3_dram_ras_n : out std_logic;
- mcb3_dram_cas_n : out std_logic;
- mcb3_dram_we_n : out std_logic;
- mcb3_dram_cke : out std_logic;
- mcb3_dram_dm : out std_logic;
- mcb3_rzq : inout std_logic;
-
-
- c3_sys_clk : in std_logic;
- c3_sys_rst_n : in std_logic;
-
- c3_calib_done : out std_logic;
- c3_clk0 : out std_logic;
- c3_rst0 : out std_logic;
-
- mcb3_dram_dqs : inout std_logic;
- mcb3_dram_ck : out std_logic;
- mcb3_dram_udqs : inout std_logic;
- mcb3_dram_udm : out std_logic;
- mcb3_dram_ck_n : out std_logic; c3_p0_cmd_clk : in std_logic;
- c3_p0_cmd_en : in std_logic;
- c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p0_cmd_empty : out std_logic;
- c3_p0_cmd_full : out std_logic;
- c3_p0_wr_clk : in std_logic;
- c3_p0_wr_en : in std_logic;
- c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
- c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- c3_p0_wr_full : out std_logic;
- c3_p0_wr_empty : out std_logic;
- c3_p0_wr_count : out std_logic_vector(6 downto 0);
- c3_p0_wr_underrun : out std_logic;
- c3_p0_wr_error : out std_logic;
- c3_p0_rd_clk : in std_logic;
- c3_p0_rd_en : in std_logic;
- c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- c3_p0_rd_full : out std_logic;
- c3_p0_rd_empty : out std_logic;
- c3_p0_rd_count : out std_logic_vector(6 downto 0);
- c3_p0_rd_overflow : out std_logic;
- c3_p0_rd_error : out std_logic;
- c3_p1_cmd_clk : in std_logic;
- c3_p1_cmd_en : in std_logic;
- c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p1_cmd_empty : out std_logic;
- c3_p1_cmd_full : out std_logic;
- c3_p1_wr_clk : in std_logic;
- c3_p1_wr_en : in std_logic;
- c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
- c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
- c3_p1_wr_full : out std_logic;
- c3_p1_wr_empty : out std_logic;
- c3_p1_wr_count : out std_logic_vector(6 downto 0);
- c3_p1_wr_underrun : out std_logic;
- c3_p1_wr_error : out std_logic;
- c3_p1_rd_clk : in std_logic;
- c3_p1_rd_en : in std_logic;
- c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
- c3_p1_rd_full : out std_logic;
- c3_p1_rd_empty : out std_logic;
- c3_p1_rd_count : out std_logic_vector(6 downto 0);
- c3_p1_rd_overflow : out std_logic;
- c3_p1_rd_error : out std_logic;
- c3_p2_cmd_clk : in std_logic;
- c3_p2_cmd_en : in std_logic;
- c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p2_cmd_empty : out std_logic;
- c3_p2_cmd_full : out std_logic;
- c3_p2_wr_clk : in std_logic;
- c3_p2_wr_en : in std_logic;
- c3_p2_wr_mask : in std_logic_vector(3 downto 0);
- c3_p2_wr_data : in std_logic_vector(31 downto 0);
- c3_p2_wr_full : out std_logic;
- c3_p2_wr_empty : out std_logic;
- c3_p2_wr_count : out std_logic_vector(6 downto 0);
- c3_p2_wr_underrun : out std_logic;
- c3_p2_wr_error : out std_logic;
- c3_p3_cmd_clk : in std_logic;
- c3_p3_cmd_en : in std_logic;
- c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p3_cmd_empty : out std_logic;
- c3_p3_cmd_full : out std_logic;
- c3_p3_rd_clk : in std_logic;
- c3_p3_rd_en : in std_logic;
- c3_p3_rd_data : out std_logic_vector(31 downto 0);
- c3_p3_rd_full : out std_logic;
- c3_p3_rd_empty : out std_logic;
- c3_p3_rd_count : out std_logic_vector(6 downto 0);
- c3_p3_rd_overflow : out std_logic;
- c3_p3_rd_error : out std_logic;
- c3_p4_cmd_clk : in std_logic;
- c3_p4_cmd_en : in std_logic;
- c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p4_cmd_empty : out std_logic;
- c3_p4_cmd_full : out std_logic;
- c3_p4_wr_clk : in std_logic;
- c3_p4_wr_en : in std_logic;
- c3_p4_wr_mask : in std_logic_vector(3 downto 0);
- c3_p4_wr_data : in std_logic_vector(31 downto 0);
- c3_p4_wr_full : out std_logic;
- c3_p4_wr_empty : out std_logic;
- c3_p4_wr_count : out std_logic_vector(6 downto 0);
- c3_p4_wr_underrun : out std_logic;
- c3_p4_wr_error : out std_logic;
- c3_p5_cmd_clk : in std_logic;
- c3_p5_cmd_en : in std_logic;
- c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p5_cmd_empty : out std_logic;
- c3_p5_cmd_full : out std_logic;
- c3_p5_rd_clk : in std_logic;
- c3_p5_rd_en : in std_logic;
- c3_p5_rd_data : out std_logic_vector(31 downto 0);
- c3_p5_rd_full : out std_logic;
- c3_p5_rd_empty : out std_logic;
- c3_p5_rd_count : out std_logic_vector(6 downto 0);
- c3_p5_rd_overflow : out std_logic;
- c3_p5_rd_error : out std_logic
- );
-end component;
-
-
- component ddr_model_c3 is
- port (
- Clk : in std_logic;
- Clk_n : in std_logic;
- Cke : in std_logic;
- Cs_n : in std_logic;
- Ras_n : in std_logic;
- Cas_n : in std_logic;
- We_n : in std_logic;
- Dm : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
- Ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
- Addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
- Dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
- Dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0)
- );
- end component;
-component memc3_tb_top is
-generic
- (
- C_P0_MASK_SIZE : integer := 4;
- C_P0_DATA_PORT_SIZE : integer := 32;
- C_P1_MASK_SIZE : integer := 4;
- C_P1_DATA_PORT_SIZE : integer := 32;
- C_MEM_BURST_LEN : integer := 8;
- C_MEM_NUM_COL_BITS : integer := 11;
- C_NUM_DQ_PINS : integer := 8;
- C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
- C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
- C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
- C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
- C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
- C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
- C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
- C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300";
- C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
- C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
- C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
- C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500";
- C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
- C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
- C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
- C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
- C_p4_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000700";
- C_p4_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p4_END_ADDRESS : std_logic_vector(31 downto 0) := X"000008ff";
- C_p4_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
- C_p4_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000700";
- C_p5_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
- C_p5_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p5_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
- C_p5_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
- C_p5_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
-
- );
-port
-(
-
- clk0 : in std_logic;
- rst0 : in std_logic;
- calib_done : in std_logic;
-
- p0_mcb_cmd_en_o : out std_logic;
- p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p0_mcb_cmd_full_i : in std_logic;
-
- p0_mcb_wr_en_o : out std_logic;
- p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
- p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_mcb_wr_full_i : in std_logic;
- p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p0_mcb_rd_en_o : out std_logic;
- p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_mcb_rd_empty_i : in std_logic;
- p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
- p1_mcb_cmd_en_o : out std_logic;
- p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p1_mcb_cmd_full_i : in std_logic;
-
- p1_mcb_wr_en_o : out std_logic;
- p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
- p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_mcb_wr_full_i : in std_logic;
- p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p1_mcb_rd_en_o : out std_logic;
- p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_mcb_rd_empty_i : in std_logic;
- p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
- p2_mcb_cmd_en_o : out std_logic;
- p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p2_mcb_cmd_full_i : in std_logic;
-
- p2_mcb_wr_en_o : out std_logic;
- p2_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
- p2_mcb_wr_data_o : out std_logic_vector(31 downto 0);
- p2_mcb_wr_full_i : in std_logic;
- p2_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p3_mcb_cmd_en_o : out std_logic;
- p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p3_mcb_cmd_full_i : in std_logic;
-
- p3_mcb_rd_en_o : out std_logic;
- p3_mcb_rd_data_i : in std_logic_vector(31 downto 0);
- p3_mcb_rd_empty_i : in std_logic;
- p3_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
- p4_mcb_cmd_en_o : out std_logic;
- p4_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p4_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p4_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p4_mcb_cmd_full_i : in std_logic;
-
- p4_mcb_wr_en_o : out std_logic;
- p4_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
- p4_mcb_wr_data_o : out std_logic_vector(31 downto 0);
- p4_mcb_wr_full_i : in std_logic;
- p4_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p5_mcb_cmd_en_o : out std_logic;
- p5_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p5_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p5_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p5_mcb_cmd_full_i : in std_logic;
-
- p5_mcb_rd_en_o : out std_logic;
- p5_mcb_rd_data_i : in std_logic_vector(31 downto 0);
- p5_mcb_rd_empty_i : in std_logic;
- p5_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
-
-
- vio_modify_enable : in std_logic;
- vio_data_mode_value : in std_logic_vector(2 downto 0);
- vio_addr_mode_value : in std_logic_vector(2 downto 0);
- cmp_error : out std_logic;
- error : out std_logic;
- error_status : out std_logic_vector(127 downto 0)
-);
-end component;
-
--- ========================================================================== --
--- Signal Declarations --
--- ========================================================================== --
-
--- Clocks
- -- Clocks
- signal c3_sys_clk : std_logic := '0';
- signal c3_sys_clk_p : std_logic;
- signal c3_sys_clk_n : std_logic;
--- System Reset
- signal c3_sys_rst : std_logic := '0';
- signal c3_sys_rst_n : std_logic;
-
-
-
--- Design-Top Port Map
- signal c3_error : std_logic;
- signal c3_calib_done : std_logic;
- signal c3_error_status : std_logic_vector(127 downto 0);
- signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
- signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
- signal mcb3_dram_ck : std_logic;
- signal mcb3_dram_ck_n : std_logic;
- signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
- signal mcb3_dram_dqs : std_logic;
- signal mcb3_dram_dm : std_logic;
- signal mcb3_dram_ras_n : std_logic;
- signal mcb3_dram_cas_n : std_logic;
- signal mcb3_dram_we_n : std_logic;
- signal mcb3_dram_cke : std_logic;
- signal mcb3_dram_udqs : std_logic;
- signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
- signal mcb3_dram_udm :std_logic; -- for X16 parts
- signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-
-
-
--- User design Sim
- signal c3_clk0 : std_logic;
- signal c3_rst0 : std_logic;
- signal c3_cmp_error : std_logic;
- signal c3_vio_modify_enable : std_logic;
- signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
- signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
- signal mcb3_command : std_logic_vector(2 downto 0);
- signal mcb3_enable1 : std_logic;
- signal mcb3_enable2 : std_logic;
-
- signal c3_p0_cmd_en : std_logic;
- signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p0_cmd_empty : std_logic;
- signal c3_p0_cmd_full : std_logic;
- signal c3_p0_wr_en : std_logic;
- signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
- signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- signal c3_p0_wr_full : std_logic;
- signal c3_p0_wr_empty : std_logic;
- signal c3_p0_wr_count : std_logic_vector(6 downto 0);
- signal c3_p0_wr_underrun : std_logic;
- signal c3_p0_wr_error : std_logic;
- signal c3_p0_rd_en : std_logic;
- signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- signal c3_p0_rd_full : std_logic;
- signal c3_p0_rd_empty : std_logic;
- signal c3_p0_rd_count : std_logic_vector(6 downto 0);
- signal c3_p0_rd_overflow : std_logic;
- signal c3_p0_rd_error : std_logic;
-
- signal c3_p1_cmd_en : std_logic;
- signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p1_cmd_empty : std_logic;
- signal c3_p1_cmd_full : std_logic;
- signal c3_p1_wr_en : std_logic;
- signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
- signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
- signal c3_p1_wr_full : std_logic;
- signal c3_p1_wr_empty : std_logic;
- signal c3_p1_wr_count : std_logic_vector(6 downto 0);
- signal c3_p1_wr_underrun : std_logic;
- signal c3_p1_wr_error : std_logic;
- signal c3_p1_rd_en : std_logic;
- signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
- signal c3_p1_rd_full : std_logic;
- signal c3_p1_rd_empty : std_logic;
- signal c3_p1_rd_count : std_logic_vector(6 downto 0);
- signal c3_p1_rd_overflow : std_logic;
- signal c3_p1_rd_error : std_logic;
-
- signal c3_p2_cmd_en : std_logic;
- signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p2_cmd_empty : std_logic;
- signal c3_p2_cmd_full : std_logic;
- signal c3_p2_wr_en : std_logic;
- signal c3_p2_wr_mask : std_logic_vector(3 downto 0);
- signal c3_p2_wr_data : std_logic_vector(31 downto 0);
- signal c3_p2_wr_full : std_logic;
- signal c3_p2_wr_empty : std_logic;
- signal c3_p2_wr_count : std_logic_vector(6 downto 0);
- signal c3_p2_wr_underrun : std_logic;
- signal c3_p2_wr_error : std_logic;
-
- signal c3_p3_cmd_en : std_logic;
- signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p3_cmd_empty : std_logic;
- signal c3_p3_cmd_full : std_logic;
- signal c3_p3_rd_en : std_logic;
- signal c3_p3_rd_data : std_logic_vector(31 downto 0);
- signal c3_p3_rd_full : std_logic;
- signal c3_p3_rd_empty : std_logic;
- signal c3_p3_rd_count : std_logic_vector(6 downto 0);
- signal c3_p3_rd_overflow : std_logic;
- signal c3_p3_rd_error : std_logic;
-
- signal c3_p4_cmd_en : std_logic;
- signal c3_p4_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p4_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p4_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p4_cmd_empty : std_logic;
- signal c3_p4_cmd_full : std_logic;
- signal c3_p4_wr_en : std_logic;
- signal c3_p4_wr_mask : std_logic_vector(3 downto 0);
- signal c3_p4_wr_data : std_logic_vector(31 downto 0);
- signal c3_p4_wr_full : std_logic;
- signal c3_p4_wr_empty : std_logic;
- signal c3_p4_wr_count : std_logic_vector(6 downto 0);
- signal c3_p4_wr_underrun : std_logic;
- signal c3_p4_wr_error : std_logic;
-
- signal c3_p5_cmd_en : std_logic;
- signal c3_p5_cmd_instr : std_logic_vector(2 downto 0);
- signal c3_p5_cmd_bl : std_logic_vector(5 downto 0);
- signal c3_p5_cmd_byte_addr : std_logic_vector(29 downto 0);
- signal c3_p5_cmd_empty : std_logic;
- signal c3_p5_cmd_full : std_logic;
- signal c3_p5_rd_en : std_logic;
- signal c3_p5_rd_data : std_logic_vector(31 downto 0);
- signal c3_p5_rd_full : std_logic;
- signal c3_p5_rd_empty : std_logic;
- signal c3_p5_rd_count : std_logic_vector(6 downto 0);
- signal c3_p5_rd_overflow : std_logic;
- signal c3_p5_rd_error : std_logic;
-
- signal c3_selfrefresh_enter : std_logic;
- signal c3_selfrefresh_mode : std_logic;
-
-
- signal rzq3 : std_logic;
-
-
- signal calib_done : std_logic;
- signal error : std_logic;
-
-
-function vector (asi:std_logic) return std_logic_vector is
- variable v : std_logic_vector(0 downto 0) ;
-begin
- v(0) := asi;
- return(v);
-end function vector;
-
-begin
--- ========================================================================== --
--- Clocks Generation --
--- ========================================================================== --
-
-
- process
- begin
- c3_sys_clk <= not c3_sys_clk;
- wait for (C3_TCYC_SYS_DIV2);
- end process;
-
- c3_sys_clk_p <= c3_sys_clk;
- c3_sys_clk_n <= not c3_sys_clk;
-
--- ========================================================================== --
--- Reset Generation --
--- ========================================================================== --
-
- process
- begin
- c3_sys_rst <= '0';
- wait for 200 ns;
- c3_sys_rst <= '1';
- wait;
- end process;
-
- c3_sys_rst_n <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
-
-
-error <= c3_error;
-calib_done <= c3_calib_done;
-
-
-
-
- rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-
-
--- ========================================================================== --
--- DESIGN TOP INSTANTIATION --
--- ========================================================================== --
-
-design_top : mem0 generic map
-(
-
-C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
-C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
-C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
-C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
- C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
-C3_RST_ACT_LOW => C3_RST_ACT_LOW,
-C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
-DEBUG_EN => DEBUG_EN,
-
-C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
-C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
-C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
-C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
-
-C3_SIMULATION => C3_SIMULATION,
-
-C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
-)
-port map (
-
- c3_sys_clk => c3_sys_clk,
- c3_sys_rst_n => c3_sys_rst_n,
-
- mcb3_dram_dq => mcb3_dram_dq,
- mcb3_dram_a => mcb3_dram_a,
- mcb3_dram_ba => mcb3_dram_ba,
- mcb3_dram_ras_n => mcb3_dram_ras_n,
- mcb3_dram_cas_n => mcb3_dram_cas_n,
- mcb3_dram_we_n => mcb3_dram_we_n,
- mcb3_dram_cke => mcb3_dram_cke,
- mcb3_dram_ck => mcb3_dram_ck,
- mcb3_dram_ck_n => mcb3_dram_ck_n,
- mcb3_dram_dqs => mcb3_dram_dqs,
- mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
- mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
- mcb3_dram_dm => mcb3_dram_dm,
- c3_clk0 => c3_clk0,
- c3_rst0 => c3_rst0,
-
-
- c3_calib_done => c3_calib_done,
- mcb3_rzq => rzq3,
-
-
- c3_p0_cmd_clk => (c3_clk0),
- c3_p0_cmd_en => c3_p0_cmd_en,
- c3_p0_cmd_instr => c3_p0_cmd_instr,
- c3_p0_cmd_bl => c3_p0_cmd_bl,
- c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
- c3_p0_cmd_empty => c3_p0_cmd_empty,
- c3_p0_cmd_full => c3_p0_cmd_full,
- c3_p0_wr_clk => (c3_clk0),
- c3_p0_wr_en => c3_p0_wr_en,
- c3_p0_wr_mask => c3_p0_wr_mask,
- c3_p0_wr_data => c3_p0_wr_data,
- c3_p0_wr_full => c3_p0_wr_full,
- c3_p0_wr_empty => c3_p0_wr_empty,
- c3_p0_wr_count => c3_p0_wr_count,
- c3_p0_wr_underrun => c3_p0_wr_underrun,
- c3_p0_wr_error => c3_p0_wr_error,
- c3_p0_rd_clk => (c3_clk0),
- c3_p0_rd_en => c3_p0_rd_en,
- c3_p0_rd_data => c3_p0_rd_data,
- c3_p0_rd_full => c3_p0_rd_full,
- c3_p0_rd_empty => c3_p0_rd_empty,
- c3_p0_rd_count => c3_p0_rd_count,
- c3_p0_rd_overflow => c3_p0_rd_overflow,
- c3_p0_rd_error => c3_p0_rd_error,
- c3_p1_cmd_clk => (c3_clk0),
- c3_p1_cmd_en => c3_p1_cmd_en,
- c3_p1_cmd_instr => c3_p1_cmd_instr,
- c3_p1_cmd_bl => c3_p1_cmd_bl,
- c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
- c3_p1_cmd_empty => c3_p1_cmd_empty,
- c3_p1_cmd_full => c3_p1_cmd_full,
- c3_p1_wr_clk => (c3_clk0),
- c3_p1_wr_en => c3_p1_wr_en,
- c3_p1_wr_mask => c3_p1_wr_mask,
- c3_p1_wr_data => c3_p1_wr_data,
- c3_p1_wr_full => c3_p1_wr_full,
- c3_p1_wr_empty => c3_p1_wr_empty,
- c3_p1_wr_count => c3_p1_wr_count,
- c3_p1_wr_underrun => c3_p1_wr_underrun,
- c3_p1_wr_error => c3_p1_wr_error,
- c3_p1_rd_clk => (c3_clk0),
- c3_p1_rd_en => c3_p1_rd_en,
- c3_p1_rd_data => c3_p1_rd_data,
- c3_p1_rd_full => c3_p1_rd_full,
- c3_p1_rd_empty => c3_p1_rd_empty,
- c3_p1_rd_count => c3_p1_rd_count,
- c3_p1_rd_overflow => c3_p1_rd_overflow,
- c3_p1_rd_error => c3_p1_rd_error,
- c3_p2_cmd_clk => (c3_clk0),
- c3_p2_cmd_en => c3_p2_cmd_en,
- c3_p2_cmd_instr => c3_p2_cmd_instr,
- c3_p2_cmd_bl => c3_p2_cmd_bl,
- c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
- c3_p2_cmd_empty => c3_p2_cmd_empty,
- c3_p2_cmd_full => c3_p2_cmd_full,
- c3_p2_wr_clk => (c3_clk0),
- c3_p2_wr_en => c3_p2_wr_en,
- c3_p2_wr_mask => c3_p2_wr_mask,
- c3_p2_wr_data => c3_p2_wr_data,
- c3_p2_wr_full => c3_p2_wr_full,
- c3_p2_wr_empty => c3_p2_wr_empty,
- c3_p2_wr_count => c3_p2_wr_count,
- c3_p2_wr_underrun => c3_p2_wr_underrun,
- c3_p2_wr_error => c3_p2_wr_error,
- c3_p3_cmd_clk => (c3_clk0),
- c3_p3_cmd_en => c3_p3_cmd_en,
- c3_p3_cmd_instr => c3_p3_cmd_instr,
- c3_p3_cmd_bl => c3_p3_cmd_bl,
- c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
- c3_p3_cmd_empty => c3_p3_cmd_empty,
- c3_p3_cmd_full => c3_p3_cmd_full,
- c3_p3_rd_clk => (c3_clk0),
- c3_p3_rd_en => c3_p3_rd_en,
- c3_p3_rd_data => c3_p3_rd_data,
- c3_p3_rd_full => c3_p3_rd_full,
- c3_p3_rd_empty => c3_p3_rd_empty,
- c3_p3_rd_count => c3_p3_rd_count,
- c3_p3_rd_overflow => c3_p3_rd_overflow,
- c3_p3_rd_error => c3_p3_rd_error,
- c3_p4_cmd_clk => (c3_clk0),
- c3_p4_cmd_en => c3_p4_cmd_en,
- c3_p4_cmd_instr => c3_p4_cmd_instr,
- c3_p4_cmd_bl => c3_p4_cmd_bl,
- c3_p4_cmd_byte_addr => c3_p4_cmd_byte_addr,
- c3_p4_cmd_empty => c3_p4_cmd_empty,
- c3_p4_cmd_full => c3_p4_cmd_full,
- c3_p4_wr_clk => (c3_clk0),
- c3_p4_wr_en => c3_p4_wr_en,
- c3_p4_wr_mask => c3_p4_wr_mask,
- c3_p4_wr_data => c3_p4_wr_data,
- c3_p4_wr_full => c3_p4_wr_full,
- c3_p4_wr_empty => c3_p4_wr_empty,
- c3_p4_wr_count => c3_p4_wr_count,
- c3_p4_wr_underrun => c3_p4_wr_underrun,
- c3_p4_wr_error => c3_p4_wr_error,
- c3_p5_cmd_clk => (c3_clk0),
- c3_p5_cmd_en => c3_p5_cmd_en,
- c3_p5_cmd_instr => c3_p5_cmd_instr,
- c3_p5_cmd_bl => c3_p5_cmd_bl,
- c3_p5_cmd_byte_addr => c3_p5_cmd_byte_addr,
- c3_p5_cmd_empty => c3_p5_cmd_empty,
- c3_p5_cmd_full => c3_p5_cmd_full,
- c3_p5_rd_clk => (c3_clk0),
- c3_p5_rd_en => c3_p5_rd_en,
- c3_p5_rd_data => c3_p5_rd_data,
- c3_p5_rd_full => c3_p5_rd_full,
- c3_p5_rd_empty => c3_p5_rd_empty,
- c3_p5_rd_count => c3_p5_rd_count,
- c3_p5_rd_overflow => c3_p5_rd_overflow,
- c3_p5_rd_error => c3_p5_rd_error
-);
-
--- user interface
-
-memc3_tb_top_inst : memc3_tb_top generic map
- (
- C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
- C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
- C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
- C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
- C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
- C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
- C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
- C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
- C_p0_DATA_MODE => C3_p0_DATA_MODE,
- C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
- C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
- C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
- C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
- C_p1_DATA_MODE => C3_p1_DATA_MODE,
- C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
- C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
- C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS,
- C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
- C_p2_DATA_MODE => C3_p2_DATA_MODE,
- C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
- C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
- C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS,
- C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS,
- C_p3_DATA_MODE => C3_p3_DATA_MODE,
- C_p3_END_ADDRESS => C3_p3_END_ADDRESS,
- C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS,
- C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS,
- C_p4_BEGIN_ADDRESS => C3_p4_BEGIN_ADDRESS,
- C_p4_DATA_MODE => C3_p4_DATA_MODE,
- C_p4_END_ADDRESS => C3_p4_END_ADDRESS,
- C_p4_PRBS_EADDR_MASK_POS => C3_p4_PRBS_EADDR_MASK_POS,
- C_p4_PRBS_SADDR_MASK_POS => C3_p4_PRBS_SADDR_MASK_POS,
- C_p5_BEGIN_ADDRESS => C3_p5_BEGIN_ADDRESS,
- C_p5_DATA_MODE => C3_p5_DATA_MODE,
- C_p5_END_ADDRESS => C3_p5_END_ADDRESS,
- C_p5_PRBS_EADDR_MASK_POS => C3_p5_PRBS_EADDR_MASK_POS,
- C_p5_PRBS_SADDR_MASK_POS => C3_p5_PRBS_SADDR_MASK_POS
- )
-port map
-(
- clk0 => c3_clk0,
- rst0 => c3_rst0,
- calib_done => c3_calib_done,
- cmp_error => c3_cmp_error,
- error => c3_error,
- error_status => c3_error_status,
- vio_modify_enable => c3_vio_modify_enable,
- vio_data_mode_value => c3_vio_data_mode_value,
- vio_addr_mode_value => c3_vio_addr_mode_value,
- p0_mcb_cmd_en_o => c3_p0_cmd_en,
- p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
- p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
- p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
- p0_mcb_cmd_full_i => c3_p0_cmd_full,
- p0_mcb_wr_en_o => c3_p0_wr_en,
- p0_mcb_wr_mask_o => c3_p0_wr_mask,
- p0_mcb_wr_data_o => c3_p0_wr_data,
- p0_mcb_wr_full_i => c3_p0_wr_full,
- p0_mcb_wr_fifo_counts => c3_p0_wr_count,
- p0_mcb_rd_en_o => c3_p0_rd_en,
- p0_mcb_rd_data_i => c3_p0_rd_data,
- p0_mcb_rd_empty_i => c3_p0_rd_empty,
- p0_mcb_rd_fifo_counts => c3_p0_rd_count,
- p1_mcb_cmd_en_o => c3_p1_cmd_en,
- p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
- p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
- p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
- p1_mcb_cmd_full_i => c3_p1_cmd_full,
- p1_mcb_wr_en_o => c3_p1_wr_en,
- p1_mcb_wr_mask_o => c3_p1_wr_mask,
- p1_mcb_wr_data_o => c3_p1_wr_data,
- p1_mcb_wr_full_i => c3_p1_wr_full,
- p1_mcb_wr_fifo_counts => c3_p1_wr_count,
- p1_mcb_rd_en_o => c3_p1_rd_en,
- p1_mcb_rd_data_i => c3_p1_rd_data,
- p1_mcb_rd_empty_i => c3_p1_rd_empty,
- p1_mcb_rd_fifo_counts => c3_p1_rd_count,
- p2_mcb_cmd_en_o => c3_p2_cmd_en,
- p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
- p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
- p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
- p2_mcb_cmd_full_i => c3_p2_cmd_full,
- p2_mcb_wr_en_o => c3_p2_wr_en,
- p2_mcb_wr_mask_o => c3_p2_wr_mask,
- p2_mcb_wr_data_o => c3_p2_wr_data,
- p2_mcb_wr_full_i => c3_p2_wr_full,
- p2_mcb_wr_fifo_counts => c3_p2_wr_count,
- p3_mcb_cmd_en_o => c3_p3_cmd_en,
- p3_mcb_cmd_instr_o => c3_p3_cmd_instr,
- p3_mcb_cmd_bl_o => c3_p3_cmd_bl,
- p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr,
- p3_mcb_cmd_full_i => c3_p3_cmd_full,
- p3_mcb_rd_en_o => c3_p3_rd_en,
- p3_mcb_rd_data_i => c3_p3_rd_data,
- p3_mcb_rd_empty_i => c3_p3_rd_empty,
- p3_mcb_rd_fifo_counts => c3_p3_rd_count,
- p4_mcb_cmd_en_o => c3_p4_cmd_en,
- p4_mcb_cmd_instr_o => c3_p4_cmd_instr,
- p4_mcb_cmd_bl_o => c3_p4_cmd_bl,
- p4_mcb_cmd_addr_o => c3_p4_cmd_byte_addr,
- p4_mcb_cmd_full_i => c3_p4_cmd_full,
- p4_mcb_wr_en_o => c3_p4_wr_en,
- p4_mcb_wr_mask_o => c3_p4_wr_mask,
- p4_mcb_wr_data_o => c3_p4_wr_data,
- p4_mcb_wr_full_i => c3_p4_wr_full,
- p4_mcb_wr_fifo_counts => c3_p4_wr_count,
- p5_mcb_cmd_en_o => c3_p5_cmd_en,
- p5_mcb_cmd_instr_o => c3_p5_cmd_instr,
- p5_mcb_cmd_bl_o => c3_p5_cmd_bl,
- p5_mcb_cmd_addr_o => c3_p5_cmd_byte_addr,
- p5_mcb_cmd_full_i => c3_p5_cmd_full,
- p5_mcb_rd_en_o => c3_p5_rd_en,
- p5_mcb_rd_data_i => c3_p5_rd_data,
- p5_mcb_rd_empty_i => c3_p5_rd_empty,
- p5_mcb_rd_fifo_counts => c3_p5_rd_count
-
-
- );
-
--- ========================================================================== --
--- Memory model instances --
--- ========================================================================== --
-
- mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
-
- process(mcb3_dram_ck)
- begin
- if (rising_edge(mcb3_dram_ck)) then
- if (c3_sys_rst = '0') then
- mcb3_enable1 <= '0';
- mcb3_enable2 <= '0';
- elsif (mcb3_command = "100") then
- mcb3_enable2 <= '0';
- elsif (mcb3_command = "101") then
- mcb3_enable2 <= '1';
- else
- mcb3_enable2 <= mcb3_enable2;
- end if;
- mcb3_enable1 <= mcb3_enable2;
- end if;
- end process;
-
------------------------------------------------------------------------------
---read
------------------------------------------------------------------------------
- mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
- when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
- else "ZZ";
-
------------------------------------------------------------------------------
---write
------------------------------------------------------------------------------
- mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
- when ( mcb3_enable1 = '1') else 'Z';
-
- mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
- when (mcb3_enable1 = '1') else 'Z';
-
-
-
-
-mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
-
- u_mem_c3 : ddr_model_c3 port map(
- Clk => mcb3_dram_ck,
- Clk_n => mcb3_dram_ck_n,
- Cke => mcb3_dram_cke,
- Cs_n => '0',
- Ras_n => mcb3_dram_ras_n,
- Cas_n => mcb3_dram_cas_n,
- We_n => mcb3_dram_we_n,
- Dm => mcb3_dram_dm_vector ,
- Ba => mcb3_dram_ba,
- Addr => mcb3_dram_a,
- Dq => mcb3_dram_dq,
- Dqs => mcb3_dram_dqs_vector
- );
-
-
------------------------------------------------------------------------------
--- Reporting the test case status
------------------------------------------------------------------------------
- Logging: process
- begin
- wait for 200 us;
- if (calib_done = '1') then
- if (error = '0') then
- report ("****TEST PASSED****");
- else
- report ("****TEST FAILED: DATA ERROR****");
- end if;
- else
- report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
- end if;
- end process;
-
-end architecture;
Index: ipcore_dir/mem0/user_design/sim/isim.tcl
===================================================================
--- ipcore_dir/mem0/user_design/sim/isim.tcl (revision 5)
+++ ipcore_dir/mem0/user_design/sim/isim.tcl (nonexistent)
@@ -1,72 +0,0 @@
-###############################################################################
-## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-###############################################################################
-## ____ ____
-## / /\/ /
-## /___/ \ / Vendor : Xilinx
-## \ \ \/ Version : 3.5
-## \ \ Application : MIG
-## / / Filename : isim.tcl
-## /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:15 $
-## \ \ / \ Date Created : Mon Mar 2 2009
-## \___\/\___\
-##
-## Device : Spartan-6
-## Design Name : DDR/DDR2/DDR3/LPDDR
-## Purpose : To give commands to ISIM Simulator through batch mode
-## Assumptions:
-## - Simulation takes place in \sim folder of MIG output directory
-## Reference :
-## Revision History:
-###############################################################################
-
-onerror {resume}
-isim set radix hex
-wave add /sim_tb_top
-run 200 us
-quit
Index: ipcore_dir/mem0/user_design/sim/ddr_model_c3.v
===================================================================
--- ipcore_dir/mem0/user_design/sim/ddr_model_c3.v (revision 5)
+++ ipcore_dir/mem0/user_design/sim/ddr_model_c3.v (nonexistent)
@@ -1,1436 +0,0 @@
-/****************************************************************************************
-*
-* File Name: ddr.v
-* Version: 6.00
-* Model: BUS Functional
-*
-* Dependencies: ddr_model_parameters.vh
-*
-* Description: Micron SDRAM DDR (Double Data Rate)
-*
-* Limitation: - Doesn't check for 8K-cycle refresh.
-* - Doesn't check power-down entry/exit
-* - Doesn't check self-refresh entry/exit.
-*
-* Note: - Set simulator resolution to "ps" accuracy
-* - Set DEBUG = 0 to disable $display messages
-* - Model assume Clk and Clk# crossing at both edge
-*
-* Disclaimer This software code and all associated documentation, comments or other
-* of Warranty: information (collectively "Software") is provided "AS IS" without
-* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
-* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
-* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
-* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
-* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
-* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
-* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
-* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
-* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
-* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
-* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
-* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
-* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
-* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
-* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
-* DAMAGES. Because some jurisdictions prohibit the exclusion or
-* limitation of liability for consequential or incidental damages, the
-* above limitation may not apply to you.
-*
-* Copyright 2003 Micron Technology, Inc. All rights reserved.
-*
-* Rev Author Date Changes
-* --- ------ ---------- ---------------------------------------
-* 2.1 SPH 03/19/2002 - Second Release
-* - Fix tWR and several incompatability
-* between different simulators
-* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
-* - Added tDQSH and tDQSL timing checks.
-* 3.1 CAH 05/28/2003 - update all models to release version 3.1
-* (no changes to this model)
-* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
-* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
-* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
-* - Fixed tWTR check
-* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade
-* - Fixed mem_sizes parameter
-* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
-* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
-* - Changed Dq_buf size to [15:0]
-* 5.0 JMK 06/16/2004 - Added read to write checking.
-* - Added read with precharge truncation to write checking.
-* - Added associative memory array to reduce memory consumption.
-* - Added checking for required DQS edges during write.
-* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
-* - Fixed wdqs_valid window.
-* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
-* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
-* - Added tRFC checking during Load Mode and Precharge.
-* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
-* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
-* JMK 02/11/2005 - Changed the display format for numbers to hex.
-* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
-* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
-* - Renamed parameters file with .vh extension.
-* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
-* - Added x32 functionality
-* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model
-* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
-****************************************************************************************/
-
-// DO NOT CHANGE THE TIMESCALE
-// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
-`timescale 1ns / 1ps
-
-module ddr_model_c3 (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);
- `include "ddr_model_parameters_c3.vh"
-
- // Port Declarations
- input Clk;
- input Clk_n;
- input Cke;
- input Cs_n;
- input Ras_n;
- input Cas_n;
- input We_n;
- input [1 : 0] Ba;
- input [ADDR_BITS - 1 : 0] Addr;
- input [DM_BITS - 1 : 0] Dm;
- inout [DQ_BITS - 1 : 0] Dq;
- inout [DQS_BITS - 1 : 0] Dqs;
-
- // Internal Wires (fixed width)
- wire [31 : 0] Dq_in;
- wire [3 : 0] Dqs_in;
- wire [3 : 0] Dm_in;
-
- assign Dq_in [DQ_BITS - 1 : 0] = Dq;
- assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
- assign Dm_in [DM_BITS - 1 : 0] = Dm;
-
- // Data pair
- reg [31 : 0] dq_rise;
- reg [3 : 0] dm_rise;
- reg [31 : 0] dq_fall;
- reg [3 : 0] dm_fall;
- reg [7 : 0] dm_pair;
- reg [31 : 0] Dq_buf;
-
- // Mode Register
- reg [ADDR_BITS - 1 : 0] Mode_reg;
-
- // Internal System Clock
- reg CkeZ, Sys_clk;
-
- // Internal Dqs initialize
- reg Dqs_int;
-
- // Dqs buffer
- reg [DQS_BITS - 1 : 0] Dqs_out;
-
- // Dq buffer
- reg [DQ_BITS - 1 : 0] Dq_out;
-
- // Read pipeline variables
- reg Read_cmnd [0 : 6];
- reg [1 : 0] Read_bank [0 : 6];
- reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
-
- // Write pipeline variables
- reg Write_cmnd [0 : 3];
- reg [1 : 0] Write_bank [0 : 3];
- reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
-
- // Auto precharge variables
- reg Read_precharge [0 : 3];
- reg Write_precharge [0 : 3];
- integer Count_precharge [0 : 3];
-
- // Manual precharge variables
- reg A10_precharge [0 : 6];
- reg [1 : 0] Bank_precharge [0 : 6];
- reg Cmnd_precharge [0 : 6];
-
- // Burst terminate variables
- reg Cmnd_bst [0 : 6];
-
- // Memory Banks
-`ifdef FULL_MEM
- reg [DQ_BITS - 1 : 0] mem_array [0 : (1<= 2) begin
- if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
- power_up_done = 1;
- end else begin
- aref_count = 0;
- @ (aref_count >= 2) begin
- if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
- power_up_done = 1;
- end
- end
- end
- end
- end
- end
- end
-
- // Write Memory
- task write_mem;
- input [full_mem_bits - 1 : 0] addr;
- input [DQ_BITS - 1 : 0] data;
- reg [part_mem_bits : 0] i;
- begin
-`ifdef FULL_MEM
- mem_array[addr] = data;
-`else
- begin : loop
- for (i = 0; i < mem_used; i = i + 1) begin
- if (addr_array[i] === addr) begin
- disable loop;
- end
- end
- end
- if (i === mem_used) begin
- if (i === (1<= burst_length) begin
- Data_in_enable = 1'b0;
- Data_out_enable = 1'b0;
- read_precharge_truncation = 4'h0;
- end
-
- end
- endtask
-
- // Manual Precharge Pipeline
- task Manual_Precharge_Pipeline;
- begin
- // A10 Precharge Pipeline
- A10_precharge[0] = A10_precharge[1];
- A10_precharge[1] = A10_precharge[2];
- A10_precharge[2] = A10_precharge[3];
- A10_precharge[3] = A10_precharge[4];
- A10_precharge[4] = A10_precharge[5];
- A10_precharge[5] = A10_precharge[6];
- A10_precharge[6] = 1'b0;
-
- // Bank Precharge Pipeline
- Bank_precharge[0] = Bank_precharge[1];
- Bank_precharge[1] = Bank_precharge[2];
- Bank_precharge[2] = Bank_precharge[3];
- Bank_precharge[3] = Bank_precharge[4];
- Bank_precharge[4] = Bank_precharge[5];
- Bank_precharge[5] = Bank_precharge[6];
- Bank_precharge[6] = 2'b0;
-
- // Command Precharge Pipeline
- Cmnd_precharge[0] = Cmnd_precharge[1];
- Cmnd_precharge[1] = Cmnd_precharge[2];
- Cmnd_precharge[2] = Cmnd_precharge[3];
- Cmnd_precharge[3] = Cmnd_precharge[4];
- Cmnd_precharge[4] = Cmnd_precharge[5];
- Cmnd_precharge[5] = Cmnd_precharge[6];
- Cmnd_precharge[6] = 1'b0;
-
- // Terminate a Read if same bank or all banks
- if (Cmnd_precharge[0] === 1'b1) begin
- if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
- if (Data_out_enable === 1'b1) begin
- Data_out_enable = 1'b0;
- read_precharge_truncation = 4'hF;
- end
- end
- end
- end
- endtask
-
- // Burst Terminate Pipeline
- task Burst_Terminate_Pipeline;
- begin
- // Command Precharge Pipeline
- Cmnd_bst[0] = Cmnd_bst[1];
- Cmnd_bst[1] = Cmnd_bst[2];
- Cmnd_bst[2] = Cmnd_bst[3];
- Cmnd_bst[3] = Cmnd_bst[4];
- Cmnd_bst[4] = Cmnd_bst[5];
- Cmnd_bst[5] = Cmnd_bst[6];
- Cmnd_bst[6] = 1'b0;
-
- // Terminate a Read regardless of banks
- if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
- Data_out_enable = 1'b0;
- end
- end
- endtask
-
- // Dq and Dqs Drivers
- task Dq_Dqs_Drivers;
- begin
- // read command pipeline
- Read_cmnd [0] = Read_cmnd [1];
- Read_cmnd [1] = Read_cmnd [2];
- Read_cmnd [2] = Read_cmnd [3];
- Read_cmnd [3] = Read_cmnd [4];
- Read_cmnd [4] = Read_cmnd [5];
- Read_cmnd [5] = Read_cmnd [6];
- Read_cmnd [6] = 1'b0;
-
- // read bank pipeline
- Read_bank [0] = Read_bank [1];
- Read_bank [1] = Read_bank [2];
- Read_bank [2] = Read_bank [3];
- Read_bank [3] = Read_bank [4];
- Read_bank [4] = Read_bank [5];
- Read_bank [5] = Read_bank [6];
- Read_bank [6] = 2'b0;
-
- // read column pipeline
- Read_cols [0] = Read_cols [1];
- Read_cols [1] = Read_cols [2];
- Read_cols [2] = Read_cols [3];
- Read_cols [3] = Read_cols [4];
- Read_cols [4] = Read_cols [5];
- Read_cols [5] = Read_cols [6];
- Read_cols [6] = 0;
-
- // Initialize Read command
- if (Read_cmnd [0] === 1'b1) begin
- Data_out_enable = 1'b1;
- Bank_addr = Read_bank [0];
- Cols_addr = Read_cols [0];
- Cols_brst = Cols_addr [2 : 0];
- Burst_counter = 0;
-
- // Row Address Mux
- case (Bank_addr)
- 2'd0 : Rows_addr = B0_row_addr;
- 2'd1 : Rows_addr = B1_row_addr;
- 2'd2 : Rows_addr = B2_row_addr;
- 2'd3 : Rows_addr = B3_row_addr;
- default : $display ("At time %t ERROR: Invalid Bank Address", $time);
- endcase
- end
-
- // Toggle Dqs during Read command
- if (Data_out_enable === 1'b1) begin
- Dqs_int = 1'b0;
- if (Dqs_out === {DQS_BITS{1'b0}}) begin
- Dqs_out = {DQS_BITS{1'b1}};
- end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
- Dqs_out = {DQS_BITS{1'b0}};
- end else begin
- Dqs_out = {DQS_BITS{1'b0}};
- end
- end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
- Dqs_out = {DQS_BITS{1'bz}};
- end
-
- // Initialize dqs for Read command
- if (Read_cmnd [2] === 1'b1) begin
- if (Data_out_enable === 1'b0) begin
- Dqs_int = 1'b1;
- Dqs_out = {DQS_BITS{1'b0}};
- end
- end
-
- // Read latch
- if (Data_out_enable === 1'b1) begin
- // output data
- read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
- if (DEBUG) begin
- $display ("At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
- end
- end else begin
- Dq_out = {DQ_BITS{1'bz}};
- end
- end
- endtask
-
- // Write FIFO and DM Mask Logic
- task Write_FIFO_DM_Mask_Logic;
- begin
- // Write command pipeline
- Write_cmnd [0] = Write_cmnd [1];
- Write_cmnd [1] = Write_cmnd [2];
- Write_cmnd [2] = Write_cmnd [3];
- Write_cmnd [3] = 1'b0;
-
- // Write command pipeline
- Write_bank [0] = Write_bank [1];
- Write_bank [1] = Write_bank [2];
- Write_bank [2] = Write_bank [3];
- Write_bank [3] = 2'b0;
-
- // Write column pipeline
- Write_cols [0] = Write_cols [1];
- Write_cols [1] = Write_cols [2];
- Write_cols [2] = Write_cols [3];
- Write_cols [3] = {COL_BITS{1'b0}};
-
- // Initialize Write command
- if (Write_cmnd [0] === 1'b1) begin
- Data_in_enable = 1'b1;
- Bank_addr = Write_bank [0];
- Cols_addr = Write_cols [0];
- Cols_brst = Cols_addr [2 : 0];
- Burst_counter = 0;
-
- // Row address mux
- case (Bank_addr)
- 2'd0 : Rows_addr = B0_row_addr;
- 2'd1 : Rows_addr = B1_row_addr;
- 2'd2 : Rows_addr = B2_row_addr;
- 2'd3 : Rows_addr = B3_row_addr;
- default : $display ("At time %t ERROR: Invalid Row Address", $time);
- endcase
- end
-
- // Write data
- if (Data_in_enable === 1'b1) begin
-
- // Data Buffer
- read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
-
- // write negedge Dqs on posedge Sys_clk
- if (Sys_clk) begin
- if (!dm_fall[0]) begin
- Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
- end
- if (!dm_fall[1]) begin
- Dq_buf [15 : 8] = dq_fall [15 : 8];
- end
- if (!dm_fall[2]) begin
- Dq_buf [23 : 16] = dq_fall [23 : 16];
- end
- if (!dm_fall[3]) begin
- Dq_buf [31 : 24] = dq_fall [31 : 24];
- end
- if (~&dm_fall) begin
- if (DEBUG) begin
- $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
- end
- end
- // write posedge Dqs on negedge Sys_clk
- end else begin
- if (!dm_rise[0]) begin
- Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
- end
- if (!dm_rise[1]) begin
- Dq_buf [15 : 8] = dq_rise [15 : 8];
- end
- if (!dm_rise[2]) begin
- Dq_buf [23 : 16] = dq_rise [23 : 16];
- end
- if (!dm_rise[3]) begin
- Dq_buf [31 : 24] = dq_rise [31 : 24];
- end
- if (~&dm_rise) begin
- if (DEBUG) begin
- $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
- end
- end
- end
-
- // Write Data
- write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
-
- // tWR start and tWTR check
- if (Sys_clk && &dm_pair === 1'b0) begin
- case (Bank_addr)
- 2'd0 : WR_chk0 = $time;
- 2'd1 : WR_chk1 = $time;
- 2'd2 : WR_chk2 = $time;
- 2'd3 : WR_chk3 = $time;
- default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);
- endcase
-
- // tWTR check
- if (Read_enable === 1'b1) begin
- $display ("At time %t ERROR: tWTR violation during Read", $time);
- end
- end
- end
- end
- endtask
-
- // Auto Precharge Calculation
- task Auto_Precharge_Calculation;
- begin
- // Precharge counter
- if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
- Count_precharge [0] = Count_precharge [0] + 1;
- end
- if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
- Count_precharge [1] = Count_precharge [1] + 1;
- end
- if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
- Count_precharge [2] = Count_precharge [2] + 1;
- end
- if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
- Count_precharge [3] = Count_precharge [3] + 1;
- end
-
- // Read with AutoPrecharge Calculation
- // The device start internal precharge when:
- // 1. Meet tRAS requirement
- // 2. BL/2 cycles after command
- if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
- if (Count_precharge[0] >= burst_length/2) begin
- Pc_b0 = 1'b1;
- Act_b0 = 1'b0;
- RP_chk0 = $time;
- Read_precharge[0] = 1'b0;
- end
- end
- if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
- if (Count_precharge[1] >= burst_length/2) begin
- Pc_b1 = 1'b1;
- Act_b1 = 1'b0;
- RP_chk1 = $time;
- Read_precharge[1] = 1'b0;
- end
- end
- if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
- if (Count_precharge[2] >= burst_length/2) begin
- Pc_b2 = 1'b1;
- Act_b2 = 1'b0;
- RP_chk2 = $time;
- Read_precharge[2] = 1'b0;
- end
- end
- if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
- if (Count_precharge[3] >= burst_length/2) begin
- Pc_b3 = 1'b1;
- Act_b3 = 1'b0;
- RP_chk3 = $time;
- Read_precharge[3] = 1'b0;
- end
- end
-
- // Write with AutoPrecharge Calculation
- // The device start internal precharge when:
- // 1. Meet tRAS requirement
- // 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command
-
- if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
- if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
- Pc_b0 = 1'b1;
- Act_b0 = 1'b0;
- RP_chk0 = $time;
- Write_precharge[0] = 1'b0;
- end
- end
- if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
- if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
- Pc_b1 = 1'b1;
- Act_b1 = 1'b0;
- RP_chk1 = $time;
- Write_precharge[1] = 1'b0;
- end
- end
- if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
- if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
- Pc_b2 = 1'b1;
- Act_b2 = 1'b0;
- RP_chk2 = $time;
- Write_precharge[2] = 1'b0;
- end
- end
- if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
- if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
- Pc_b3 = 1'b1;
- Act_b3 = 1'b0;
- RP_chk3 = $time;
- Write_precharge[3] = 1'b0;
- end
- end
- end
- endtask
-
- // DLL Counter
- task DLL_Counter;
- begin
- if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
- DLL_count = DLL_count + 1;
- if (DLL_count >= 200) begin
- DLL_done = 1'b1;
- end
- end
- end
- endtask
-
- // Control Logic
- task Control_Logic;
- begin
- // Auto Refresh
- if (Aref_enable === 1'b1) begin
- // Display DEBUG Message
- if (DEBUG) begin
- $display ("At time %t AREF : Auto Refresh", $time);
- end
-
- // Precharge to Auto Refresh
- if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
- ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
- $display ("At time %t ERROR: tRP violation during Auto Refresh", $time);
- end
-
- // LMR/EMR to Auto Refresh
- if ($time - MRD_chk < tMRD) begin
- $display ("At time %t ERROR: tMRD violation during Auto Refresh", $time);
- end
-
- // Auto Refresh to Auto Refresh
- if ($time - RFC_chk < tRFC) begin
- $display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);
- end
-
- // Precharge to Auto Refresh
- if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
- $display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
- if (!no_halt) $stop (0);
- end else begin
- aref_count = aref_count + 1;
- RFC_chk = $time;
- end
- end
-
- // Extended Mode Register
- if (Ext_mode_enable === 1'b1) begin
- if (DEBUG) begin
- $display ("At time %t EMR : Extended Mode Register", $time);
- end
-
- // Precharge to LMR/EMR
- if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
- ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
- $display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);
- end
-
- // LMR/EMR to LMR/EMR
- if ($time - MRD_chk < tMRD) begin
- $display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);
- end
-
- // Auto Refresh to LMR/EMR
- if ($time - RFC_chk < tRFC) begin
- $display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time);
- end
-
- // Precharge to LMR/EMR
- if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
- $display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
- if (!no_halt) $stop (0);
- end else begin
- if (Addr[0] === 1'b0) begin
- DLL_enable = 1'b1;
- if (DEBUG) begin
- $display ("At time %t EMR : Enable DLL", $time);
- end
- end else begin
- DLL_enable = 1'b0;
- if (DEBUG) begin
- $display ("At time %t EMR : Disable DLL", $time);
- end
- end
- MRD_chk = $time;
- end
- end
-
- // Load Mode Register
- if (Mode_reg_enable === 1'b1) begin
- if (DEBUG) begin
- $display ("At time %t LMR : Load Mode Register", $time);
- end
-
- // Precharge to LMR/EMR
- if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
- ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
- $display ("At time %t ERROR: tRP violation during Load Mode Register", $time);
- end
-
- // LMR/EMR to LMR/EMR
- if ($time - MRD_chk < tMRD) begin
- $display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);
- end
-
- // Auto Refresh to LMR/EMR
- if ($time - RFC_chk < tRFC) begin
- $display ("At time %t ERROR: tRFC violation during Load Mode Register", $time);
- end
-
- // Precharge to LMR/EMR
- if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
- $display ("At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
- end else begin
- // Register Mode
- Mode_reg = Addr;
-
- // DLL Reset
- if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
- DLL_reset = 1'b1;
- DLL_done = 1'b0;
- DLL_count = 0;
- end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
- $display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
- end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
- $display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
- end
-
- // Burst Length
- case (Addr [2 : 0])
- 3'b001 : $display ("At time %t LMR : Burst Length = 2", $time);
- 3'b010 : $display ("At time %t LMR : Burst Length = 4", $time);
- 3'b011 : $display ("At time %t LMR : Burst Length = 8", $time);
- default : $display ("At time %t ERROR: Burst Length not supported", $time);
- endcase
-
- // CAS Latency
- case (Addr [6 : 4])
- 3'b010 : $display ("At time %t LMR : CAS Latency = 2", $time);
- 3'b110 : $display ("At time %t LMR : CAS Latency = 2.5", $time);
- 3'b011 : $display ("At time %t LMR : CAS Latency = 3", $time);
- default : $display ("At time %t ERROR: CAS Latency not supported", $time);
- endcase
-
- // Record current tMRD time
- MRD_chk = $time;
- end
- end
-
- // Activate Block
- if (Active_enable === 1'b1) begin
- if (!(power_up_done)) begin
- $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
- end
- // Display DEBUG Message
- if (DEBUG) begin
- $display ("At time %t ACT : Bank = %h, Row = %h", $time, Ba, Addr);
- end
-
- // Activate to Activate (different bank)
- if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
- $display ("At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
- end
-
- // LMR/EMR to Activate
- if ($time - MRD_chk < tMRD) begin
- $display ("At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
- end
-
- // AutoRefresh to Activate
- if ($time - RFC_chk < tRFC) begin
- $display ("At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
- end
-
- // Precharge to Activate
- if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
- (Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
- $display ("At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
- if (!no_halt) $stop (0);
- end else begin
- // Activate Bank 0
- if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
- // Activate to Activate (same bank)
- if ($time - RC_chk0 < tRC) begin
- $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
- end
-
- // Precharge to Activate
- if ($time - RP_chk0 < tRP) begin
- $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
- end
-
- // Record variables for checking violation
- Act_b0 = 1'b1;
- Pc_b0 = 1'b0;
- B0_row_addr = Addr;
- RC_chk0 = $time;
- RCD_chk0 = $time;
- RAS_chk0 = $time;
- RAP_chk0 = $time;
- end
-
- // Activate Bank 1
- if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
- // Activate to Activate (same bank)
- if ($time - RC_chk1 < tRC) begin
- $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
- end
-
- // Precharge to Activate
- if ($time - RP_chk1 < tRP) begin
- $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
- end
-
- // Record variables for checking violation
- Act_b1 = 1'b1;
- Pc_b1 = 1'b0;
- B1_row_addr = Addr;
- RC_chk1 = $time;
- RCD_chk1 = $time;
- RAS_chk1 = $time;
- RAP_chk1 = $time;
- end
-
- // Activate Bank 2
- if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
- // Activate to Activate (same bank)
- if ($time - RC_chk2 < tRC) begin
- $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
- end
-
- // Precharge to Activate
- if ($time - RP_chk2 < tRP) begin
- $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
- end
-
- // Record variables for checking violation
- Act_b2 = 1'b1;
- Pc_b2 = 1'b0;
- B2_row_addr = Addr;
- RC_chk2 = $time;
- RCD_chk2 = $time;
- RAS_chk2 = $time;
- RAP_chk2 = $time;
- end
-
- // Activate Bank 3
- if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
- // Activate to Activate (same bank)
- if ($time - RC_chk3 < tRC) begin
- $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
- end
-
- // Precharge to Activate
- if ($time - RP_chk3 < tRP) begin
- $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
- end
-
- // Record variables for checking violation
- Act_b3 = 1'b1;
- Pc_b3 = 1'b0;
- B3_row_addr = Addr;
- RC_chk3 = $time;
- RCD_chk3 = $time;
- RAS_chk3 = $time;
- RAP_chk3 = $time;
- end
- // Record variable for checking violation
- RRD_chk = $time;
- Prev_bank = Ba;
- read_precharge_truncation[Ba] = 1'b0;
- end
- end
-
- // Precharge Block - consider NOP if bank already precharged or in process of precharging
- if (Prech_enable === 1'b1) begin
- // Display DEBUG Message
- if (DEBUG) begin
- $display ("At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
- end
-
- // LMR/EMR to Precharge
- if ($time - MRD_chk < tMRD) begin
- $display ("At time %t ERROR: tMRD violation during Precharge", $time);
- end
-
- // AutoRefresh to Precharge
- if ($time - RFC_chk < tRFC) begin
- $display ("At time %t ERROR: tRFC violation during Precharge", $time);
- end
-
- // Precharge bank 0
- if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
- Act_b0 = 1'b0;
- Pc_b0 = 1'b1;
- RP_chk0 = $time;
-
- // Activate to Precharge Bank
- if ($time - RAS_chk0 < tRAS) begin
- $display ("At time %t ERROR: tRAS violation during Precharge", $time);
- end
-
- // tWR violation check for Write
- if ($time - WR_chk0 < tWR) begin
- $display ("At time %t ERROR: tWR violation during Precharge", $time);
- end
- end
-
- // Precharge bank 1
- if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
- Act_b1 = 1'b0;
- Pc_b1 = 1'b1;
- RP_chk1 = $time;
-
- // Activate to Precharge Bank 1
- if ($time - RAS_chk1 < tRAS) begin
- $display ("At time %t ERROR: tRAS violation during Precharge", $time);
- end
-
- // tWR violation check for Write
- if ($time - WR_chk1 < tWR) begin
- $display ("At time %t ERROR: tWR violation during Precharge", $time);
- end
- end
-
- // Precharge bank 2
- if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
- Act_b2 = 1'b0;
- Pc_b2 = 1'b1;
- RP_chk2 = $time;
-
- // Activate to Precharge Bank 2
- if ($time - RAS_chk2 < tRAS) begin
- $display ("At time %t ERROR: tRAS violation during Precharge", $time);
- end
-
- // tWR violation check for Write
- if ($time - WR_chk2 < tWR) begin
- $display ("At time %t ERROR: tWR violation during Precharge", $time);
- end
- end
-
- // Precharge bank 3
- if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
- Act_b3 = 1'b0;
- Pc_b3 = 1'b1;
- RP_chk3 = $time;
-
- // Activate to Precharge Bank 3
- if ($time - RAS_chk3 < tRAS) begin
- $display ("At time %t ERROR: tRAS violation during Precharge", $time);
- end
-
- // tWR violation check for Write
- if ($time - WR_chk3 < tWR) begin
- $display ("At time %t ERROR: tWR violation during Precharge", $time);
- end
- end
-
- // Prech_count is to make sure we have met part of the initialization sequence
- Prech_count = Prech_count + 1;
-
- // Pipeline for READ
- A10_precharge [cas_latency_x2] = Addr[10];
- Bank_precharge[cas_latency_x2] = Ba;
- Cmnd_precharge[cas_latency_x2] = 1'b1;
- end
-
- // Burst terminate
- if (Burst_term === 1'b1) begin
- // Display DEBUG Message
- if (DEBUG) begin
- $display ("At time %t BST : Burst Terminate",$time);
- end
-
- if (Data_in_enable === 1'b1) begin
- // Illegal to burst terminate a Write
- $display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);
- if (!no_halt) $stop (0);
- end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
- // Illegal to burst terminate a Read with Auto Precharge
- Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
- $display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
- if (!no_halt) $stop (0);
- end else begin
- // Burst Terminate Command Pipeline for Read
- Cmnd_bst[cas_latency_x2] = 1'b1;
- end
-
- end
-
- // Read Command
- if (Read_enable === 1'b1) begin
- if (!(power_up_done)) begin
- $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
- end
- // Check for DLL reset before Read
- if (DLL_reset === 1 && DLL_done === 0) begin
- $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
- end
- // Display DEBUG Message
- if (DEBUG) begin
- $display ("At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]});
- end
-
- // Terminate a Write
- if (Data_in_enable === 1'b1) begin
- Data_in_enable = 1'b0;
- end
-
- // Activate to Read without Auto Precharge
- if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
- (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
- (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
- (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
- $display("At time %t ERROR: tRCD violation during Read", $time);
- end
-
- // Activate to Read with Auto Precharge
- if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
- (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
- (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
- (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
- $display ("At time %t ERROR: tRAP violation during Read", $time);
- end
-
- // Interrupt a Read with Auto Precharge (same bank only)
- if (Read_precharge [Ba] === 1'b1) begin
- $display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
- if (!no_halt) $stop (0);
- // Cancel Auto Precharge
- if (Addr[10] === 1'b0) begin
- Read_precharge [Ba]= 1'b0;
- end
- end
- // Activate to Read
- if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
- (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
- $display("At time %t ERROR: Bank is not Activated for Read", $time);
- if (!no_halt) $stop (0);
- end else begin
- // CAS Latency pipeline
- Read_cmnd[cas_latency_x2] = 1'b1;
- Read_bank[cas_latency_x2] = Ba;
- Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
- // Auto Precharge
- if (Addr[10] === 1'b1) begin
- Read_precharge [Ba]= 1'b1;
- Count_precharge [Ba]= 0;
- end
- end
- end
-
- // Write Command
- if (Write_enable === 1'b1) begin
- if (!(power_up_done)) begin
- $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
- if (!no_halt) $stop (0);
- end
- // display DEBUG message
- if (DEBUG) begin
- $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
- end
-
- // Activate to Write
- if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
- (Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
- (Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
- (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
- $display("At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba);
- end
-
- // Read to Write
- if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
- Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
- if (Data_out_enable || read_precharge_truncation[Ba]) begin
- $display("At time %t ERROR: Read to Write violation", $time);
- end
- end
-
- // Interrupt a Write with Auto Precharge (same bank only)
- if (Write_precharge [Ba] === 1'b1) begin
- $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
- if (!no_halt) $stop (0);
- // Cancel Auto Precharge
- if (Addr[10] === 1'b0) begin
- Write_precharge [Ba]= 1'b0;
- end
- end
- // Activate to Write
- if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
- (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
- $display("At time %t ERROR: Bank is not Activated for Write", $time);
- if (!no_halt) $stop (0);
- end else begin
- // Pipeline for Write
- Write_cmnd [3] = 1'b1;
- Write_bank [3] = Ba;
- Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
- // Auto Precharge
- if (Addr[10] === 1'b1) begin
- Write_precharge [Ba]= 1'b1;
- Count_precharge [Ba]= 0;
- end
- end
- end
- end
- endtask
-
- task check_neg_dqs;
- begin
- if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
- for (i=0; i= 256 AND DWIDTH <= 576) THEN
- INC_COUNTS <= "00000100000";
- ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
- INC_COUNTS <= "00000010000";
- ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
- INC_COUNTS <= "00000001000";
- ELSIF (DWIDTH = 32) THEN
- INC_COUNTS <= "00000000100";
- END IF;
- END IF;
- END PROCESS;
-
- END GENERATE;
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i = '1') THEN
- current_address <= BEGIN_ADDRESS;
- ELSIF (
--- ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
- (mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
-
- (mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
- ) THEN
- current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
- ELSE
- current_address <= current_address;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
- AC3_G_E3 <= '1';
- ELSE
- AC3_G_E3 <= '0';
- END IF;
- IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
- AC2_G_E2 <= '1';
- ELSE
- AC2_G_E2 <= '0';
- END IF;
- IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
- AC1_G_E1 <= '1';
- ELSE
- AC1_G_E1 <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i = '1') THEN
- upper_end_matched <= '0';
- ELSIF (mcb_cmd_en_i = '1') THEN
- upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
- END IF;
- END IF;
- END PROCESS;
-
- FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE
- "0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
- ('0' & FIXEDBL);
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
-
-
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
- lower_end_matched <= '1';
- ELSE
- lower_end_matched <= '0';
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (mcb_cmd_en_i = '1') THEN
- mcb_cmd_bl_r <= mcb_cmd_bl_i;
- END IF;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR
- ((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR
- (upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
- ((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
- end_addr_reached <= '1';
- ELSE
- end_addr_reached <= '0';
- END IF;
- END IF;
- END PROCESS;
-
- fixed_addr_o <= "00000000000000000001001000110100";
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- mcb_init_done_reg <= mcb_init_done_i;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- run_traffic_o <= run_traffic;
- END IF;
- END PROCESS;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i = '1') THEN
- current_state <= "00001";
- ELSE
- current_state <= next_state;
- END IF;
- END IF;
- END PROCESS;
-
-
- start_addr_o <= BEGIN_ADDRESS;
- end_addr_o <= END_ADDRESS;
- cmd_seed_o <= CMD_SEED_VALUE;
- data_seed_o <= DATA_SEED_VALUE;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i = '1') THEN
- syn1_vio_data_mode_value <= "011";
- syn1_vio_addr_mode_value <= "011";
- ELSIF (vio_modify_enable = '1') THEN
- syn1_vio_data_mode_value <= vio_data_mode_value;
- syn1_vio_addr_mode_value <= vio_addr_mode_value;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i = '1') THEN
- data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
- addr_mode_sel <= "011";
- ELSIF (vio_modify_enable = '1') THEN
- data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
- addr_mode_sel <= vio_addr_mode_value;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
- fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
- ELSIF (vio_modify_enable = '1') THEN
- fix_bl_value <= vio_fixed_bl_value;
- END IF;
- END IF;
- END PROCESS;
-
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
- IF (FAMILY = "VIRTEX6") THEN
- bl_mode_sel <= FIXED_BL_MODE;
- ELSE
- bl_mode_sel <= PRBS_BL_MODE;
- END IF;
- ELSIF (vio_modify_enable = '1') THEN
- bl_mode_sel <= vio_bl_mode_value;
- END IF;
- END IF;
- END PROCESS;
-
- data_mode_o <= data_mode_reg;
-
- PROCESS (clk_i)
- BEGIN
- IF (clk_i'EVENT AND clk_i = '1') THEN
- data_mode_reg <= data_mode_sel;
- addr_mode_o <= addr_mode;
- IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
- bram_mode_enable <= '1';
- ELSE
- bram_mode_enable <= '0';
- END IF;
-
-
- END IF;
- END PROCESS;
-
-
- PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
- BEGIN
- load_seed_o <= '0';
- IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
- addr_mode <= (others => '0');
- ELSE
- addr_mode <= SEQUENTIAL_ADDR;
- END IF;
-
- IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
- instr_mode_o <= (others => '0');
- ELSE
- instr_mode_o <= FIXED_INSTR_MODE;
- END IF;
-
-
- IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
- bl_mode_o_xhdl0 <= (others => '0');
- ELSE
- bl_mode_o_xhdl0 <= FIXED_BL_MODE;
- END IF;
--- data_mode1 <= WALKING1_DATA_MODE;
-
- IF (FAMILY = "VIRTEX6") THEN
- fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
- -- PRBS mode
- else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
- fixed_bl_o <= "000000";-- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
- else
- fixed_bl_o <= fix_bl_value;
- end if;
- end if;
-
- mode_load_o <= '0';
- run_traffic <= '0';
-
- next_state <= IDLE;
- IF (PORT_MODE = "RD_MODE") THEN
- fixed_instr_o <= RD_INSTR;
- ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
- fixed_instr_o <= WR_INSTR;
- END IF;
-
- CASE current_state IS
-
- WHEN IDLE =>
- IF (mcb_init_done_reg = '1') THEN
- IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
- next_state <= INIT_MEM_WRITE;
- mode_load_o <= '1';
- run_traffic <= '0';
- load_seed_o <= '1';
- ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
- next_state <= INIT_MEM_READ;
- mode_load_o <= '1';
- run_traffic <= '0';
- END IF;
- ELSE
- next_state <= IDLE;
- run_traffic <= '0';
- load_seed_o <= '0';
- END IF;
-
- WHEN INIT_MEM_WRITE =>
- IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
- next_state <= TEST_MEM;
- mode_load_o <= '1';
- load_seed_o <= '1';
- run_traffic <= '1';
- ELSE
- next_state <= INIT_MEM_WRITE;
- run_traffic <= '1';
- mode_load_o <= '0';
- load_seed_o <= '0';
- IF (EYE_TEST = "TRUE") THEN
- addr_mode <= FIXED_ADDR;
- ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
- addr_mode <= "000";
- ELSE
- addr_mode <= SEQUENTIAL_ADDR;
- END IF;
- END IF;
-
- WHEN INIT_MEM_READ =>
- IF (end_addr_reached = '1') THEN
- next_state <= TEST_MEM;
- mode_load_o <= '1';
- load_seed_o <= '1';
- ELSE
- next_state <= INIT_MEM_READ;
- run_traffic <= '0';
- mode_load_o <= '0';
- load_seed_o <= '0';
- END IF;
-
- WHEN TEST_MEM =>
- IF (cmp_error = '1') THEN
- next_state <= CMP_ERROR1;
- ELSE
- next_state <= TEST_MEM;
- END IF;
-
- run_traffic <= '1';
-
-
- IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
- fixed_instr_o <= WR_INSTR;
- ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
- fixed_instr_o <= RD_INSTR;
-
- ELSIF (PORT_MODE = "RD_MODE") THEN
- fixed_instr_o <= RD_INSTR;
- ELSIF (PORT_MODE = "WR_MODE") THEN
- fixed_instr_o <= WR_INSTR;
- END IF;
-
- if (FAMILY = "VIRTEX6") then
- fixed_bl_o <= fix_bl_value; --"000010"; 2
- else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
- fixed_bl_o <= "000000"; -- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
- else
- fixed_bl_o <= fix_bl_value;
- end if;
- end if;
-
- bl_mode_o_xhdl0 <= bl_mode_sel;
- IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
- addr_mode <= PRBS_ADDR;
- ELSE
- addr_mode <= addr_mode_sel;
- END IF;
-
- IF (PORT_MODE = "BI_MODE") THEN
- IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
- instr_mode_o <= BRAM_INSTR_MODE;
- ELSE
- instr_mode_o <= test_mem_instr_mode;
- --R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
- --R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
- END IF;
- ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
- instr_mode_o <= FIXED_INSTR_MODE;
- END IF;
-
- WHEN CMP_ERROR1 =>
- next_state <= CMP_ERROR1;
- bl_mode_o_xhdl0 <= bl_mode_sel;
- fixed_instr_o <= RD_INSTR;
- addr_mode <= SEQUENTIAL_ADDR;
- IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
- instr_mode_o <= BRAM_INSTR_MODE;
- ELSE
- instr_mode_o <= test_mem_instr_mode;
- --R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
- END IF;
- run_traffic <= '1';
-
- WHEN OTHERS =>
- next_state <= IDLE;
- END CASE;
- END PROCESS;
-
-
-END trans;
-
-
-
-
-
ipcore_dir/mem0/user_design/sim/init_mem_pattern_ctr.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/mem0.prj
===================================================================
--- ipcore_dir/mem0/user_design/sim/mem0.prj (revision 5)
+++ ipcore_dir/mem0/user_design/sim/mem0.prj (nonexistent)
@@ -1,30 +0,0 @@
-vhdl work ../rtl/iodrp_controller.vhd
-vhdl work ../rtl/iodrp_mcb_controller.vhd
-vhdl work ../rtl/mcb_raw_wrapper.vhd
-vhdl work ../rtl/mcb_soft_calibration.vhd
-vhdl work ../rtl/mcb_soft_calibration_top.vhd
-vhdl work ../rtl/mem0.vhd
-vhdl work ../rtl/memc3_infrastructure.vhd
-vhdl work ../rtl/memc3_wrapper.vhd
-vhdl work ./afifo.vhd
-vhdl work ./cmd_gen.vhd
-vhdl work ./cmd_prbs_gen.vhd
-vhdl work ./data_prbs_gen.vhd
-vhdl work ./init_mem_pattern_ctr.vhd
-vhdl work ./mcb_flow_control.vhd
-vhdl work ./mcb_traffic_gen.vhd
-vhdl work ./rd_data_gen.vhd
-vhdl work ./read_data_path.vhd
-vhdl work ./read_posted_fifo.vhd
-vhdl work ./sp6_data_gen.vhd
-vhdl work ./tg_status.vhd
-vhdl work ./v6_data_gen.vhd
-vhdl work ./wr_data_gen.vhd
-vhdl work ./write_data_path.vhd
-vhdl work ./memc3_tb_top.vhd
-verilog work $XILINX/verilog/src/glbl.v
-vhdl work ./sim_tb_top.vhd
-verilog work ./ddr_model_c3.v -d x512Mb -d FULL_MEM -d sg5B -d x16 -i ./
-
-
-
Index: ipcore_dir/mem0/user_design/sim/sim.do
===================================================================
--- ipcore_dir/mem0/user_design/sim/sim.do (revision 5)
+++ ipcore_dir/mem0/user_design/sim/sim.do (nonexistent)
@@ -1,140 +0,0 @@
-###############################################################################
-## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-##
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-###############################################################################
-## ____ ____
-## / /\/ /
-## /___/ \ / Vendor : Xilinx
-## \ \ \/ Version : 3.5
-## \ \ Application : MIG
-## / / Filename : sim.do
-## /___/ /\ Date Last Modified : $Date: 2010/04/06 08:27:54 $
-## \ \ / \ Date Created : Mon Mar 2 2009
-## \___\/\___\
-##
-## Device: Spartan-6
-## Design Name : DDR/DDR2/DDR3/LPDDR
-## Purpose:
-## Sample sim .do file to compile and simulate memory interface
-## design and run the simulation for specified period of time. Display the
-## waveforms that are listed with "add wave" command.
-## Assumptions:
-## - Simulation takes place in \sim folder of MIG output directory
-## Reference:
-## Revision History:
-###############################################################################
-
-vlib work
-
-#Map the required libraries here.#
-#vmap unisim
-#vmap secureip
-
-#Compile all rtl modules#
-vcom ../rtl/*.vhd
-
-
-
-
-#Compile files in sim folder (excluding model parameter file)#
-#$XILINX variable must be set
-vlog $env(XILINX)/verilog/src/glbl.v
-vcom ../sim/*.vhd
-
-#Pass the parameters for memory model parameter file#
-vlog +incdir+. +define+x512Mb +define+FULL_MEM +define+sg5B +define+x16 ddr_model_c3.v
-
-#Load the design. Use required libraries.#
-vsim -t ps -novopt +notimingchecks -L unisim -L secureip work.sim_tb_top glbl
-
-onerror {resume}
-
-#Log all the objects in design. These will appear in .wlf file#
-log -r /*
-
-#View sim_tb_top signals in waveform#
-add wave sim:/sim_tb_top/*
-
-#Change radix to Hexadecimal#
-radix hex
-#Supress Numeric Std package and Arith package warnings.#
-#For VHDL designs we get some warnings due to unknown values on some signals at startup#
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
-#We may also get some Arithmetic packeage warnings because of unknown values on#
-#some of the signals that are used in an Arithmetic operation.#
-#In order to suppress these warnings, we use following two commands#
-set NumericStdNoWarnings 1
-set StdArithNoWarnings 1
-
-#Choose simulation run time by inserting a breakpoint and then run for specified #
-#period. Refer simulation_help file.#
-when {/sim_tb_top/calib_done = 1} {
-echo "Calibration Done"
- if {[when -label a_100] == ""} {
- when -label a_100 { $now = 50 us } {
- nowhen a_100
- report simulator control
- report simulator state
- if {[examine /sim_tb_top/error] == 0} {
- echo "TEST PASSED"
- stop
- }
- if {[examine /sim_tb_top/error] != 0} {
- echo "TEST FAILED: DATA ERROR"
- stop
- }
- }
- }
- }
-
-#In case calibration fails to complete, choose the run time and then quit#
-when {$now = @500 us and /sim_tb_top/calib_done != 1} {
-echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
-stop
-}
-run -all
-stop
Index: ipcore_dir/mem0/user_design/sim/wr_data_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/wr_data_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/wr_data_gen.vhd (nonexistent)
@@ -1,511 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: wr_data_gen.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose:
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- use ieee.numeric_std.all;
-
-entity wr_data_gen is
- generic (
-
- TCQ : TIME := 100 ps;
- FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
- MEM_BURST_LEN : integer := 8;
-
- MODE : string := "WR"; --"WR", "RD"
- ADDR_WIDTH : integer := 32;
- BL_WIDTH : integer := 6;
- DWIDTH : integer := 32;
- DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : integer := 8;
- SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
-
- COLUMN_WIDTH : integer := 10;
- EYE_TEST : string := "FALSE"
- );
- port (
-
- clk_i : in std_logic; --
- rst_i : in std_logic_vector(4 downto 0);
- prbs_fseed_i : in std_logic_vector(31 downto 0);
-
- data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
-
- cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
- -- And then it should reasserted when
- -- it is generating the last_word.
- cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
- cmd_validB_i : in std_logic;
- cmd_validC_i : in std_logic;
-
- last_word_o : out std_logic;
-
- -- input [5:0] port_data_counts_i,// connect to data port fifo counts
- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
- bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
-
- data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
- -- connect from mcb_rd_empty when used as rd_data_gen
- -- When both data_rdy and data_valid is asserted, the ouput data is valid.
- data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
- -- pattern is available.
- data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
- data_wr_end_o : out std_logic
- );
-end entity wr_data_gen;
-
-architecture trans of wr_data_gen is
-
-COMPONENT sp6_data_gen IS
- GENERIC (
-
- ADDR_WIDTH : INTEGER := 32;
- BL_WIDTH : INTEGER := 6;
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_PRBS";
- NUM_DQ_PINS : INTEGER := 8;
- COLUMN_WIDTH : INTEGER := 10
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- data_rdy_i : IN STD_LOGIC;
- cmd_startA : IN STD_LOGIC;
- cmd_startB : IN STD_LOGIC;
- cmd_startC : IN STD_LOGIC;
- cmd_startD : IN STD_LOGIC;
- cmd_startE : IN STD_LOGIC;
- fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
-
- addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
-
- fifo_rdy_i : IN STD_LOGIC;
- data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
- );
-END COMPONENT;
-
-COMPONENT v6_data_gen IS
- GENERIC (
-
- ADDR_WIDTH : INTEGER := 32;
- BL_WIDTH : INTEGER := 6;
- MEM_BURST_LEN : integer := 8;
-
- DWIDTH : INTEGER := 32;
- DATA_PATTERN : STRING := "DGEN_PRBS";
- NUM_DQ_PINS : INTEGER := 8;
- SEL_VICTIM_LINE : INTEGER := 3;
- COLUMN_WIDTH : INTEGER := 10;
- EYE_TEST : STRING := "FALSE"
- );
- PORT (
-
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-
- data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- data_rdy_i : IN STD_LOGIC;
- cmd_startA : IN STD_LOGIC;
- cmd_startB : IN STD_LOGIC;
- cmd_startC : IN STD_LOGIC;
- cmd_startD : IN STD_LOGIC;
- fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
- cmd_startE : IN STD_LOGIC;
- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
-
- fifo_rdy_i : IN STD_LOGIC;
- data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
- );
-END COMPONENT;
-
- signal data : std_logic_vector(DWIDTH - 1 downto 0);
-
- signal cmd_rdy : std_logic;
- signal cmd_rdyB : std_logic;
- signal cmd_rdyC : std_logic;
- signal cmd_rdyD : std_logic;
- signal cmd_rdyE : std_logic;
- signal cmd_rdyF : std_logic;
- signal cmd_start : std_logic;
- signal cmd_startB : std_logic;
- signal cmd_startC : std_logic;
- signal cmd_startD : std_logic;
- signal cmd_startE : std_logic;
- signal cmd_startF : std_logic;
-
- signal burst_count_reached2 : std_logic;
-
- signal data_valid : std_logic;
- signal user_burst_cnt : std_logic_vector(6 downto 0);
- signal walk_cnt : std_logic_vector(2 downto 0);
-
- signal fifo_not_full : std_logic;
- signal i : integer;
- signal j : integer;
- signal w3data : std_logic_vector(31 downto 0);
-
- -- counter to count user burst length
-
- -- bl_i;
-
- signal u_bcount_2 : std_logic;
- signal last_word_t : std_logic;
-
- -- Declare intermediate signals for referenced outputs
- signal last_word_o_xhdl1 : std_logic;
- signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
- signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
-begin
- -- Drive referenced outputs
- last_word_o <= last_word_o_xhdl1;
- data_o <= data_o_xhdl0;
- fifo_not_full <= data_rdy_i;
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
- data_wr_end_o <= '1';
- else
- data_wr_end_o <= '0';
- end if;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- cmd_start <= cmd_validC_i and cmd_rdyC;
- cmd_startB <= cmd_valid_i and cmd_rdyB;
- cmd_startC <= cmd_validB_i and cmd_rdyC;
- cmd_startD <= cmd_validB_i and cmd_rdyD;
- cmd_startE <= cmd_validB_i and cmd_rdyE;
- cmd_startF <= cmd_validB_i and cmd_rdyF;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- user_burst_cnt <= "0000000" ;
- elsif (cmd_start = '1') then
- if (FAMILY = "SPARTAN6") then
- if (bl_i = "000000") then
- user_burst_cnt <= "1000000" ;
- else
- user_burst_cnt <= ('0' & bl_i) ;
- end if;
- else
- user_burst_cnt <= ('0' & bl_i) ;
- end if;
- elsif (fifo_not_full = '1') then
- if (user_burst_cnt /= "0000000") then
- user_burst_cnt <= user_burst_cnt - "0000001" ;
- else
- user_burst_cnt <= "0000000" ;
- end if;
- end if;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
- u_bcount_2 <= '1' ;
- elsif (last_word_o_xhdl1 = '1') then
- u_bcount_2 <= '0' ;
- end if;
- end if;
- end process;
-
-
- last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-
- -- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
- -- is assert and reassert during the last data
-
- cmd_rdy_o <= cmd_rdy and fifo_not_full;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdy <= '1' ;
- elsif (cmd_start = '1') then
- if (bl_i = "000001") then
- cmd_rdy <= '1' ;
- else
- cmd_rdy <= '0' ;
- end if;
- elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
-
- cmd_rdy <= '1' ;
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdyB <= '1' ;
- elsif (cmd_startB = '1') then
- if (bl_i = "000001") then
- cmd_rdyB <= '1' ;
- else
- cmd_rdyB <= '0' ;
- end if;
- elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
-
- cmd_rdyB <= '1' ;
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdyC <= '1' ;
- elsif (cmd_startC = '1') then
- if (bl_i = "000001") then
- cmd_rdyC <= '1' ;
- else
- cmd_rdyC <= '0' ;
- end if;
- elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
-
- cmd_rdyC <= '1' ;
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdyD <= '1' ;
- elsif (cmd_startD = '1') then
- if (bl_i = "000001") then
- cmd_rdyD <= '1' ;
- else
- cmd_rdyD <= '0' ;
- end if;
- elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
-
- cmd_rdyD <= '1' ;
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdyE <= '1' ;
- elsif (cmd_startE = '1') then
- if (bl_i = "000001") then
- cmd_rdyE <= '1' ;
- else
- cmd_rdyE <= '0' ;
- end if;
- elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
-
- cmd_rdyE <= '1' ;
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(0)) = '1') then
- cmd_rdyF <= '1' ;
- elsif (cmd_startF = '1') then
- if (bl_i = "000001") then
- cmd_rdyF <= '1' ;
- else
- cmd_rdyF <= '0' ;
- end if;
- elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
-
- cmd_rdyF <= '1' ;
- end if;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ((rst_i(1)) = '1') then
- data_valid <= '0' ;
- elsif (cmd_start = '1') then
- data_valid <= '1' ;
- elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
- data_valid <= '0' ;
- end if;
- end if;
- end process;
-
-
- data_valid_o <= data_valid and fifo_not_full;
-
- s6_wdgen : if (FAMILY = "SPARTAN6") generate
-
-
-
-
- sp6_data_gen_inst : sp6_data_gen
- generic map (
- ADDR_WIDTH => 32,
- BL_WIDTH => BL_WIDTH,
- DWIDTH => DWIDTH,
- DATA_PATTERN => DATA_PATTERN,
- NUM_DQ_PINS => NUM_DQ_PINS,
- COLUMN_WIDTH => COLUMN_WIDTH
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(1),
- data_rdy_i => data_rdy_i,
- prbs_fseed_i => prbs_fseed_i,
-
- data_mode_i => data_mode_i,
- cmd_startA => cmd_start,
- cmd_startB => cmd_startB,
- cmd_startC => cmd_startC,
- cmd_startD => cmd_startD,
- cmd_startE => cmd_startE,
- fixed_data_i => fixed_data_i,
- addr_i => addr_i,
- user_burst_cnt => user_burst_cnt,
- fifo_rdy_i => fifo_not_full,
- data_o => data_o_xhdl0
- );
-
- end generate;
-
- v6_wdgen : if (FAMILY = "VIRTEX6") generate
-
-
-
-
- v6_data_gen_inst : v6_data_gen
- generic map (
- ADDR_WIDTH => 32,
- BL_WIDTH => BL_WIDTH,
- DWIDTH => DWIDTH,
- MEM_BURST_LEN => MEM_BURST_LEN,
-
- DATA_PATTERN => DATA_PATTERN,
- NUM_DQ_PINS => NUM_DQ_PINS,
- SEL_VICTIM_LINE => SEL_VICTIM_LINE,
- COLUMN_WIDTH => COLUMN_WIDTH,
- EYE_TEST => EYE_TEST
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(1),
- data_rdy_i => data_rdy_i,
- prbs_fseed_i => prbs_fseed_i,
-
- data_mode_i => data_mode_i,
- cmd_starta => cmd_start,
- cmd_startb => cmd_startB,
- cmd_startc => cmd_startC,
- cmd_startd => cmd_startD,
- cmd_starte => cmd_startE,
- fixed_data_i => fixed_data_i,
- m_addr_i => m_addr_i,
- addr_i => addr_i,
- user_burst_cnt => user_burst_cnt,
- fifo_rdy_i => fifo_not_full,
- data_o => data_o_xhdl0
- );
- end generate;
-
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/sim/wr_data_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/memc3_tb_top.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/memc3_tb_top.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/memc3_tb_top.vhd (nonexistent)
@@ -1,1457 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : memc3_tb_top.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:16 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
---Device : Spartan-6
---Design Name : DDR/DDR2/DDR3/LPDDR
---Purpose : This is top level module for test bench. which instantiates
--- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
--- port.
---Reference :
---Revision History :
---*****************************************************************************
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity memc3_tb_top is
-generic
- (
- C_P0_MASK_SIZE : integer := 4;
- C_P0_DATA_PORT_SIZE : integer := 32;
- C_P1_MASK_SIZE : integer := 4;
- C_P1_DATA_PORT_SIZE : integer := 32;
- C_MEM_BURST_LEN : integer := 8;
- C_SIMULATION : string := "FALSE";
- C_MEM_NUM_COL_BITS : integer := 11;
- C_NUM_DQ_PINS : integer := 8;
- C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
- C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
- C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
- C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
- C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
- C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
- C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
- C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300";
- C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
- C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
- C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
- C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500";
- C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
- C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
- C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
- C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
- C_p4_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000700";
- C_p4_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p4_END_ADDRESS : std_logic_vector(31 downto 0) := X"000008ff";
- C_p4_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
- C_p4_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000700";
- C_p5_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
- C_p5_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
- C_p5_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
- C_p5_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
- C_p5_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
- );
-port
-(
-
- clk0 : in std_logic;
- rst0 : in std_logic;
- calib_done : in std_logic;
-
-
- p0_mcb_cmd_en_o : out std_logic;
- p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p0_mcb_cmd_full_i : in std_logic;
-
- p0_mcb_wr_en_o : out std_logic;
- p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
- p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_mcb_wr_full_i : in std_logic;
- p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p0_mcb_rd_en_o : out std_logic;
- p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_mcb_rd_empty_i : in std_logic;
- p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
- p1_mcb_cmd_en_o : out std_logic;
- p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p1_mcb_cmd_full_i : in std_logic;
-
- p1_mcb_wr_en_o : out std_logic;
- p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
- p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_mcb_wr_full_i : in std_logic;
- p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p1_mcb_rd_en_o : out std_logic;
- p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_mcb_rd_empty_i : in std_logic;
- p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
- p2_mcb_cmd_en_o : out std_logic;
- p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p2_mcb_cmd_full_i : in std_logic;
-
- p2_mcb_wr_en_o : out std_logic;
- p2_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
- p2_mcb_wr_data_o : out std_logic_vector(31 downto 0);
- p2_mcb_wr_full_i : in std_logic;
- p2_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p3_mcb_cmd_en_o : out std_logic;
- p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p3_mcb_cmd_full_i : in std_logic;
-
- p3_mcb_rd_en_o : out std_logic;
- p3_mcb_rd_data_i : in std_logic_vector(31 downto 0);
- p3_mcb_rd_empty_i : in std_logic;
- p3_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
- p4_mcb_cmd_en_o : out std_logic;
- p4_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p4_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p4_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p4_mcb_cmd_full_i : in std_logic;
-
- p4_mcb_wr_en_o : out std_logic;
- p4_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
- p4_mcb_wr_data_o : out std_logic_vector(31 downto 0);
- p4_mcb_wr_full_i : in std_logic;
- p4_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- p5_mcb_cmd_en_o : out std_logic;
- p5_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- p5_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- p5_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
- p5_mcb_cmd_full_i : in std_logic;
-
- p5_mcb_rd_en_o : out std_logic;
- p5_mcb_rd_data_i : in std_logic_vector(31 downto 0);
- p5_mcb_rd_empty_i : in std_logic;
- p5_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
-
-
-
-
-
- vio_modify_enable : in std_logic;
- vio_data_mode_value : in std_logic_vector(2 downto 0);
- vio_addr_mode_value : in std_logic_vector(2 downto 0);
-
- cmp_error : out std_logic;
- cmp_data : out std_logic_vector(31 downto 0);
- cmp_data_valid : out std_logic;
- error : out std_logic;
- error_status : out std_logic_vector(127 downto 0)
-
-
-);
-end memc3_tb_top;
-
-architecture arc of memc3_tb_top is
-
-function ERROR_DQWIDTH (val_i : integer) return integer is
-begin
- if (val_i = 4) then
- return 1;
- else
- return val_i/8;
- end if;
-end function ERROR_DQWIDTH;
-
-constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
-
-component init_mem_pattern_ctr IS
- generic (
- FAMILY : string;
- BEGIN_ADDRESS : std_logic_vector(31 downto 0);
- END_ADDRESS : std_logic_vector(31 downto 0);
- DWIDTH : integer;
- CMD_SEED_VALUE : std_logic_vector(31 downto 0);
- DATA_SEED_VALUE : std_logic_vector(31 downto 0);
- DATA_MODE : std_logic_vector(3 downto 0);
- PORT_MODE : string
- );
- PORT (
- clk_i : in std_logic;
- rst_i : in std_logic;
- mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
- mcb_cmd_en_i : in std_logic;
- mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
- mcb_init_done_i : in std_logic;
- mcb_wr_en_i : in std_logic;
- vio_modify_enable : in std_logic;
- vio_data_mode_value : in std_logic_vector(2 downto 0);
- vio_addr_mode_value : in std_logic_vector(2 downto 0);
- vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
- vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
- cmp_error : in std_logic;
- run_traffic_o : out std_logic;
- start_addr_o : out std_logic_vector(31 downto 0);
- end_addr_o : out std_logic_vector(31 downto 0);
- cmd_seed_o : out std_logic_vector(31 downto 0);
- data_seed_o : out std_logic_vector(31 downto 0);
- load_seed_o : out std_logic;
- addr_mode_o : out std_logic_vector(2 downto 0);
- instr_mode_o : out std_logic_vector(3 downto 0);
- bl_mode_o : out std_logic_vector(1 downto 0);
- data_mode_o : out std_logic_vector(3 downto 0);
- mode_load_o : out std_logic;
- fixed_bl_o : out std_logic_vector(5 downto 0);
- fixed_instr_o : out std_logic_vector(2 downto 0);
- fixed_addr_o : out std_logic_vector(31 downto 0)
- );
-end component;
-
-component mcb_traffic_gen is
- generic (
-
- FAMILY : string;
- SIMULATION : string;
- MEM_BURST_LEN : integer;
- PORT_MODE : string;
- DATA_PATTERN : string;
- CMD_PATTERN : string;
- ADDR_WIDTH : integer;
- CMP_DATA_PIPE_STAGES : integer;
- MEM_COL_WIDTH : integer;
- NUM_DQ_PINS : integer;
- DQ_ERROR_WIDTH : integer;
- DWIDTH : integer;
- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
- PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
- PRBS_EADDR : std_logic_vector(31 downto 0);
- PRBS_SADDR : std_logic_vector(31 downto 0)
- );
- port (
-
- clk_i : in std_logic;
- rst_i : in std_logic;
- run_traffic_i : in std_logic;
- manual_clear_error : in std_logic;
- -- *** runtime parameter ***
- start_addr_i : in std_logic_vector(31 downto 0);
- end_addr_i : in std_logic_vector(31 downto 0);
- cmd_seed_i : in std_logic_vector(31 downto 0);
- data_seed_i : in std_logic_vector(31 downto 0);
- load_seed_i : in std_logic;
-
- addr_mode_i : in std_logic_vector(2 downto 0);
- instr_mode_i : in std_logic_vector(3 downto 0);
- bl_mode_i : in std_logic_vector(1 downto 0);
- data_mode_i : in std_logic_vector(3 downto 0);
- mode_load_i : in std_logic;
-
- -- fixed pattern inputs interface
- fixed_bl_i : in std_logic_vector(5 downto 0);
- fixed_instr_i : in std_logic_vector(2 downto 0);
- fixed_addr_i : in std_logic_vector(31 downto 0);
- fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
-
- bram_cmd_i : in std_logic_vector(38 downto 0);
- bram_valid_i : in std_logic;
- bram_rdy_o : out std_logic;
-
- --///////////////////////////////////////////////////////////////////////////
- -- MCB INTERFACE
- -- interface to mcb command port
- mcb_cmd_en_o : out std_logic;
- mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
- mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
- mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
- mcb_cmd_full_i : in std_logic;
- -- interface to mcb wr data port
- mcb_wr_en_o : out std_logic;
- mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
- mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
- mcb_wr_data_end_o : OUT std_logic;
-
- mcb_wr_full_i : in std_logic;
- mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-
- -- interface to mcb rd data port
- mcb_rd_en_o : out std_logic;
- mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- mcb_rd_empty_i : in std_logic;
- mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
- --///////////////////////////////////////////////////////////////////////////
- -- status feedback
- counts_rst : in std_logic;
- wr_data_counts : out std_logic_vector(47 downto 0);
- rd_data_counts : out std_logic_vector(47 downto 0);
- cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
- cmp_data_valid : out std_logic;
- cmp_error : out std_logic;
- error : out std_logic;
- error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
- mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
- dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
- cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
-
- );
-end component;
-
-
-
- constant FAMILY : string := "SPARTAN6";
- constant DATA_PATTERN : string := "DGEN_ALL";
- constant CMD_PATTERN : string := "CGEN_ALL";
- constant ADDR_WIDTH : integer := 30;
- constant CMP_DATA_PIPE_STAGES : integer := 0;
- constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
- constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
- constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
- constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
- constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
- constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
- constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
-
-
-
- constant p0_DWIDTH : integer := 32;
-
- constant p1_DWIDTH : integer := 32;
-
- constant p2_DWIDTH : integer := 32;
-
- constant p3_DWIDTH : integer := 32;
-
- constant p4_DWIDTH : integer := 32;
-
- constant p5_DWIDTH : integer := 32;
-
-
- constant p0_PORT_MODE : string := "BI_MODE";
-
- constant p1_PORT_MODE : string := "BI_MODE";
-
-
- constant p2_PORT_MODE : string := "WR_MODE";
-
- constant p3_PORT_MODE : string := "RD_MODE";
-
- constant p4_PORT_MODE : string := "WR_MODE";
-
- constant p5_PORT_MODE : string := "RD_MODE";
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
---p0 Signal declarations
-signal p0_tg_run_traffic : std_logic;
-signal p0_tg_start_addr : std_logic_vector(31 downto 0);
-signal p0_tg_end_addr : std_logic_vector(31 downto 0);
-signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
-signal p0_tg_data_seed : std_logic_vector(31 downto 0);
-signal p0_tg_load_seed : std_logic;
-signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
-signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
-signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
-signal p0_tg_data_mode : std_logic_vector(3 downto 0);
-signal p0_tg_mode_load : std_logic;
-signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
-signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
-signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
-signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
-signal p0_error : std_logic;
-signal p0_cmp_error : std_logic;
-signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
-signal p0_cmp_data_valid : std_logic;
-
-signal p0_mcb_cmd_en_o_int : std_logic;
-signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
-signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
-signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
-signal p0_mcb_wr_en_o_int : std_logic;
-
-
---p1 Signal declarations
-signal p1_tg_run_traffic : std_logic;
-signal p1_tg_start_addr : std_logic_vector(31 downto 0);
-signal p1_tg_end_addr : std_logic_vector(31 downto 0);
-signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
-signal p1_tg_data_seed : std_logic_vector(31 downto 0);
-signal p1_tg_load_seed : std_logic;
-signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
-signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
-signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
-signal p1_tg_data_mode : std_logic_vector(3 downto 0);
-signal p1_tg_mode_load : std_logic;
-signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
-signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
-signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
-signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
-signal p1_error : std_logic;
-signal p1_cmp_error : std_logic;
-signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
-signal p1_cmp_data_valid : std_logic;
-
-signal p1_mcb_cmd_en_o_int : std_logic;
-signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
-signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
-signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
-signal p1_mcb_wr_en_o_int : std_logic;
-
-
---p2 Signal declarations
-signal p2_tg_run_traffic : std_logic;
-signal p2_tg_start_addr : std_logic_vector(31 downto 0);
-signal p2_tg_end_addr : std_logic_vector(31 downto 0);
-signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
-signal p2_tg_data_seed : std_logic_vector(31 downto 0);
-signal p2_tg_load_seed : std_logic;
-signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
-signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
-signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
-signal p2_tg_data_mode : std_logic_vector(3 downto 0);
-signal p2_tg_mode_load : std_logic;
-signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
-signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
-signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
-signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
-signal p2_error : std_logic;
-signal p2_cmp_error : std_logic;
-signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
-signal p2_cmp_data_valid : std_logic;
-
-signal p2_mcb_cmd_en_o_int : std_logic;
-signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
-signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
-signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
-signal p2_mcb_wr_en_o_int : std_logic;
-
-
---p3 Signal declarations
-signal p3_tg_run_traffic : std_logic;
-signal p3_tg_start_addr : std_logic_vector(31 downto 0);
-signal p3_tg_end_addr : std_logic_vector(31 downto 0);
-signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
-signal p3_tg_data_seed : std_logic_vector(31 downto 0);
-signal p3_tg_load_seed : std_logic;
-signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
-signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
-signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
-signal p3_tg_data_mode : std_logic_vector(3 downto 0);
-signal p3_tg_mode_load : std_logic;
-signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
-signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
-signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
-signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
-signal p3_error : std_logic;
-signal p3_cmp_error : std_logic;
-signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
-signal p3_cmp_data_valid : std_logic;
-
-signal p3_mcb_cmd_en_o_int : std_logic;
-signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
-signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
-signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
-signal p3_mcb_wr_en_o_int : std_logic;
-
-
---p4 Signal declarations
-signal p4_tg_run_traffic : std_logic;
-signal p4_tg_start_addr : std_logic_vector(31 downto 0);
-signal p4_tg_end_addr : std_logic_vector(31 downto 0);
-signal p4_tg_cmd_seed : std_logic_vector(31 downto 0);
-signal p4_tg_data_seed : std_logic_vector(31 downto 0);
-signal p4_tg_load_seed : std_logic;
-signal p4_tg_addr_mode : std_logic_vector(2 downto 0);
-signal p4_tg_instr_mode : std_logic_vector(3 downto 0);
-signal p4_tg_bl_mode : std_logic_vector(1 downto 0);
-signal p4_tg_data_mode : std_logic_vector(3 downto 0);
-signal p4_tg_mode_load : std_logic;
-signal p4_tg_fixed_bl : std_logic_vector(5 downto 0);
-signal p4_tg_fixed_instr : std_logic_vector(2 downto 0);
-signal p4_tg_fixed_addr : std_logic_vector(31 downto 0);
-signal p4_error_status : std_logic_vector(64 + (2*p4_DWIDTH - 1) downto 0);
-signal p4_error : std_logic;
-signal p4_cmp_error : std_logic;
-signal p4_cmp_data : std_logic_vector(p4_DWIDTH-1 downto 0);
-signal p4_cmp_data_valid : std_logic;
-
-signal p4_mcb_cmd_en_o_int : std_logic;
-signal p4_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
-signal p4_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
-signal p4_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
-signal p4_mcb_wr_en_o_int : std_logic;
-
-
---p5 Signal declarations
-signal p5_tg_run_traffic : std_logic;
-signal p5_tg_start_addr : std_logic_vector(31 downto 0);
-signal p5_tg_end_addr : std_logic_vector(31 downto 0);
-signal p5_tg_cmd_seed : std_logic_vector(31 downto 0);
-signal p5_tg_data_seed : std_logic_vector(31 downto 0);
-signal p5_tg_load_seed : std_logic;
-signal p5_tg_addr_mode : std_logic_vector(2 downto 0);
-signal p5_tg_instr_mode : std_logic_vector(3 downto 0);
-signal p5_tg_bl_mode : std_logic_vector(1 downto 0);
-signal p5_tg_data_mode : std_logic_vector(3 downto 0);
-signal p5_tg_mode_load : std_logic;
-signal p5_tg_fixed_bl : std_logic_vector(5 downto 0);
-signal p5_tg_fixed_instr : std_logic_vector(2 downto 0);
-signal p5_tg_fixed_addr : std_logic_vector(31 downto 0);
-signal p5_error_status : std_logic_vector(64 + (2*p5_DWIDTH - 1) downto 0);
-signal p5_error : std_logic;
-signal p5_cmp_error : std_logic;
-signal p5_cmp_data : std_logic_vector(p5_DWIDTH-1 downto 0);
-signal p5_cmp_data_valid : std_logic;
-
-signal p5_mcb_cmd_en_o_int : std_logic;
-signal p5_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
-signal p5_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
-signal p5_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
-signal p5_mcb_wr_en_o_int : std_logic;
-
-
-
-
-
-signal p2_mcb_rd_en_o : std_logic;
-signal p2_mcb_rd_empty_i : std_logic;
-signal p2_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
-signal p2_mcb_rd_data_i : std_logic_vector(31 downto 0);
-
-
-
-signal p3_mcb_wr_en_o : std_logic;
-signal p3_mcb_wr_full_i : std_logic;
-signal p3_mcb_wr_data_o : std_logic_vector(31 downto 0);
-signal p3_mcb_wr_mask_o : std_logic_vector(3 downto 0);
-signal p3_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
-
-
-
-
-signal p4_mcb_rd_en_o : std_logic;
-signal p4_mcb_rd_empty_i : std_logic;
-signal p4_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
-signal p4_mcb_rd_data_i : std_logic_vector(31 downto 0);
-
-
-
-signal p5_mcb_wr_en_o : std_logic;
-signal p5_mcb_wr_full_i : std_logic;
-signal p5_mcb_wr_data_o : std_logic_vector(31 downto 0);
-signal p5_mcb_wr_mask_o : std_logic_vector(3 downto 0);
-signal p5_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
-
-
-
---signal cmp_data : std_logic_vector(31 downto 0);
-begin
-
-
- cmp_error <= p0_cmp_error or p1_cmp_error or p2_cmp_error or p3_cmp_error or p4_cmp_error or p5_cmp_error;
- error <= p0_error or p1_error or p2_error or p3_error or p4_error or p5_error;
- error_status <= p0_error_status;
- cmp_data <= p0_cmp_data(31 downto 0);
- cmp_data_valid <= p0_cmp_data_valid;
-
-
-p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
-p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
-p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
-p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
-p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
-
- init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
- generic map
- (
- DWIDTH => p0_DWIDTH,
- FAMILY => FAMILY,
- BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
- END_ADDRESS => C_p0_END_ADDRESS,
- CMD_SEED_VALUE => X"56456783",
- DATA_SEED_VALUE => X"12345678",
- DATA_MODE => C_p0_DATA_MODE,
- PORT_MODE => p0_PORT_MODE
-
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
-
- mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
- mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
- mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
- mcb_wr_en_i => p0_mcb_wr_en_o_int,
-
- vio_modify_enable => vio_modify_enable,
- vio_data_mode_value => vio_data_mode_value,
- vio_addr_mode_value => vio_addr_mode_value,
- vio_bl_mode_value => "10",--vio_bl_mode_value,
- vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
-
- mcb_init_done_i => calib_done,
- cmp_error => p0_error,
- run_traffic_o => p0_tg_run_traffic,
- start_addr_o => p0_tg_start_addr,
- end_addr_o => p0_tg_end_addr ,
- cmd_seed_o => p0_tg_cmd_seed ,
- data_seed_o => p0_tg_data_seed ,
- load_seed_o => p0_tg_load_seed ,
- addr_mode_o => p0_tg_addr_mode ,
- instr_mode_o => p0_tg_instr_mode ,
- bl_mode_o => p0_tg_bl_mode ,
- data_mode_o => p0_tg_data_mode ,
- mode_load_o => p0_tg_mode_load ,
- fixed_bl_o => p0_tg_fixed_bl ,
- fixed_instr_o => p0_tg_fixed_instr,
- fixed_addr_o => p0_tg_fixed_addr
- );
-
- m_traffic_gen_p0 : mcb_traffic_gen
- generic map(
- MEM_BURST_LEN => C_MEM_BURST_LEN,
- MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
- NUM_DQ_PINS => C_NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
-
- PORT_MODE => p0_PORT_MODE,
- DWIDTH => p0_DWIDTH,
- CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
- FAMILY => FAMILY,
- SIMULATION => "FALSE",
- DATA_PATTERN => "DGEN_ADDR",
- CMD_PATTERN => "CGEN_ALL",
- ADDR_WIDTH => 30,
- PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
- PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
- PRBS_SADDR => C_p0_BEGIN_ADDRESS,
- PRBS_EADDR => C_p0_END_ADDRESS
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
- run_traffic_i => p0_tg_run_traffic,
- manual_clear_error => rst0,
- -- runtime parameter
- start_addr_i => p0_tg_start_addr ,
- end_addr_i => p0_tg_end_addr ,
- cmd_seed_i => p0_tg_cmd_seed ,
- data_seed_i => p0_tg_data_seed ,
- load_seed_i => p0_tg_load_seed,
- addr_mode_i => p0_tg_addr_mode,
-
- instr_mode_i => p0_tg_instr_mode ,
- bl_mode_i => p0_tg_bl_mode ,
- data_mode_i => p0_tg_data_mode ,
- mode_load_i => p0_tg_mode_load ,
-
- -- fixed pattern inputs interface
- fixed_bl_i => p0_tg_fixed_bl,
- fixed_instr_i => p0_tg_fixed_instr,
- fixed_addr_i => p0_tg_fixed_addr,
- fixed_data_i => (others => '0'),
- -- BRAM interface.
- bram_cmd_i => (others => '0'),
- bram_valid_i => '0',
- bram_rdy_o => open,
-
- -- MCB INTERFACE
- mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
- mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
- mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
- mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
- mcb_cmd_full_i => p0_mcb_cmd_full_i,
-
- mcb_wr_en_o => p0_mcb_wr_en_o_int,
- mcb_wr_mask_o => p0_mcb_wr_mask_o,
- mcb_wr_data_o => p0_mcb_wr_data_o,
- mcb_wr_data_end_o => open,
- mcb_wr_full_i => p0_mcb_wr_full_i,
- mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
-
- mcb_rd_en_o => p0_mcb_rd_en_o,
- mcb_rd_data_i => p0_mcb_rd_data_i,
- mcb_rd_empty_i => p0_mcb_rd_empty_i,
- mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-
- -- status feedback
- counts_rst => rst0,
- wr_data_counts => open,
- rd_data_counts => open,
- cmp_data => p0_cmp_data,
- cmp_data_valid => p0_cmp_data_valid,
- cmp_error => p0_cmp_error,
- error => p0_error,
- error_status => p0_error_status,
- mem_rd_data => open,
- dq_error_bytelane_cmp => open,
- cumlative_dq_lane_error => open
- );
-
-
-
-p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
-p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
-p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
-p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
-p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
-
- init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
- generic map
- (
- DWIDTH => p1_DWIDTH,
- FAMILY => FAMILY,
- BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
- END_ADDRESS => C_p1_END_ADDRESS,
- CMD_SEED_VALUE => X"56456783",
- DATA_SEED_VALUE => X"12345678",
- DATA_MODE => C_p1_DATA_MODE,
- PORT_MODE => p1_PORT_MODE
-
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
-
- mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
- mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
- mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
- mcb_wr_en_i => p1_mcb_wr_en_o_int,
-
- vio_modify_enable => vio_modify_enable,
- vio_data_mode_value => vio_data_mode_value,
- vio_addr_mode_value => vio_addr_mode_value,
- vio_bl_mode_value => "10",--vio_bl_mode_value,
- vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
-
- mcb_init_done_i => calib_done,
- cmp_error => p1_error,
- run_traffic_o => p1_tg_run_traffic,
- start_addr_o => p1_tg_start_addr,
- end_addr_o => p1_tg_end_addr ,
- cmd_seed_o => p1_tg_cmd_seed ,
- data_seed_o => p1_tg_data_seed ,
- load_seed_o => p1_tg_load_seed ,
- addr_mode_o => p1_tg_addr_mode ,
- instr_mode_o => p1_tg_instr_mode ,
- bl_mode_o => p1_tg_bl_mode ,
- data_mode_o => p1_tg_data_mode ,
- mode_load_o => p1_tg_mode_load ,
- fixed_bl_o => p1_tg_fixed_bl ,
- fixed_instr_o => p1_tg_fixed_instr,
- fixed_addr_o => p1_tg_fixed_addr
- );
-
- m_traffic_gen_p1 : mcb_traffic_gen
- generic map(
- MEM_BURST_LEN => C_MEM_BURST_LEN,
- MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
- NUM_DQ_PINS => C_NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
-
- PORT_MODE => p1_PORT_MODE,
- DWIDTH => p1_DWIDTH,
- CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
- FAMILY => FAMILY,
- SIMULATION => "FALSE",
- DATA_PATTERN => "DGEN_ADDR",
- CMD_PATTERN => "CGEN_ALL",
- ADDR_WIDTH => 30,
- PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
- PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
- PRBS_SADDR => C_p1_BEGIN_ADDRESS,
- PRBS_EADDR => C_p1_END_ADDRESS
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
- run_traffic_i => p1_tg_run_traffic,
- manual_clear_error => rst0,
- -- runtime parameter
- start_addr_i => p1_tg_start_addr ,
- end_addr_i => p1_tg_end_addr ,
- cmd_seed_i => p1_tg_cmd_seed ,
- data_seed_i => p1_tg_data_seed ,
- load_seed_i => p1_tg_load_seed,
- addr_mode_i => p1_tg_addr_mode,
-
- instr_mode_i => p1_tg_instr_mode ,
- bl_mode_i => p1_tg_bl_mode ,
- data_mode_i => p1_tg_data_mode ,
- mode_load_i => p1_tg_mode_load ,
-
- -- fixed pattern inputs interface
- fixed_bl_i => p1_tg_fixed_bl,
- fixed_instr_i => p1_tg_fixed_instr,
- fixed_addr_i => p1_tg_fixed_addr,
- fixed_data_i => (others => '0'),
- -- BRAM interface.
- bram_cmd_i => (others => '0'),
- bram_valid_i => '0',
- bram_rdy_o => open,
-
- -- MCB INTERFACE
- mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
- mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
- mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
- mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
- mcb_cmd_full_i => p1_mcb_cmd_full_i,
-
- mcb_wr_en_o => p1_mcb_wr_en_o_int,
- mcb_wr_mask_o => p1_mcb_wr_mask_o,
- mcb_wr_data_o => p1_mcb_wr_data_o,
- mcb_wr_data_end_o => open,
- mcb_wr_full_i => p1_mcb_wr_full_i,
- mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
-
- mcb_rd_en_o => p1_mcb_rd_en_o,
- mcb_rd_data_i => p1_mcb_rd_data_i,
- mcb_rd_empty_i => p1_mcb_rd_empty_i,
- mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-
- -- status feedback
- counts_rst => rst0,
- wr_data_counts => open,
- rd_data_counts => open,
- cmp_data => p1_cmp_data,
- cmp_data_valid => p1_cmp_data_valid,
- cmp_error => p1_cmp_error,
- error => p1_error,
- error_status => p1_error_status,
- mem_rd_data => open,
- dq_error_bytelane_cmp => open,
- cumlative_dq_lane_error => open
- );
-
-
-
-p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
-p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
-p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
-p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
-p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
-
- init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
- generic map
- (
- DWIDTH => p2_DWIDTH,
- FAMILY => FAMILY,
- BEGIN_ADDRESS => C_p2_BEGIN_ADDRESS,
- END_ADDRESS => C_p2_END_ADDRESS,
- CMD_SEED_VALUE => X"56456783",
- DATA_SEED_VALUE => X"12345678",
- DATA_MODE => C_p2_DATA_MODE,
- PORT_MODE => p2_PORT_MODE
-
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
-
- mcb_cmd_en_i => p2_mcb_cmd_en_o_int,
- mcb_cmd_instr_i => p2_mcb_cmd_instr_o_int,
- mcb_cmd_bl_i => p2_mcb_cmd_bl_o_int,
- mcb_wr_en_i => p2_mcb_wr_en_o_int,
-
- vio_modify_enable => vio_modify_enable,
- vio_data_mode_value => vio_data_mode_value,
- vio_addr_mode_value => vio_addr_mode_value,
- vio_bl_mode_value => "10",--vio_bl_mode_value,
- vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
-
- mcb_init_done_i => calib_done,
- cmp_error => p2_error,
- run_traffic_o => p2_tg_run_traffic,
- start_addr_o => p2_tg_start_addr,
- end_addr_o => p2_tg_end_addr ,
- cmd_seed_o => p2_tg_cmd_seed ,
- data_seed_o => p2_tg_data_seed ,
- load_seed_o => p2_tg_load_seed ,
- addr_mode_o => p2_tg_addr_mode ,
- instr_mode_o => p2_tg_instr_mode ,
- bl_mode_o => p2_tg_bl_mode ,
- data_mode_o => p2_tg_data_mode ,
- mode_load_o => p2_tg_mode_load ,
- fixed_bl_o => p2_tg_fixed_bl ,
- fixed_instr_o => p2_tg_fixed_instr,
- fixed_addr_o => p2_tg_fixed_addr
- );
-
- m_traffic_gen_p2 : mcb_traffic_gen
- generic map(
- MEM_BURST_LEN => C_MEM_BURST_LEN,
- MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
- NUM_DQ_PINS => C_NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
-
- PORT_MODE => p2_PORT_MODE,
- DWIDTH => p2_DWIDTH,
- CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
- FAMILY => FAMILY,
- SIMULATION => "FALSE",
- DATA_PATTERN => "DGEN_ADDR",
- CMD_PATTERN => "CGEN_ALL",
- ADDR_WIDTH => 30,
- PRBS_SADDR_MASK_POS => C_p2_PRBS_SADDR_MASK_POS,
- PRBS_EADDR_MASK_POS => C_p2_PRBS_EADDR_MASK_POS,
- PRBS_SADDR => C_p2_BEGIN_ADDRESS,
- PRBS_EADDR => C_p2_END_ADDRESS
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
- run_traffic_i => p2_tg_run_traffic,
- manual_clear_error => rst0,
- -- runtime parameter
- start_addr_i => p2_tg_start_addr ,
- end_addr_i => p2_tg_end_addr ,
- cmd_seed_i => p2_tg_cmd_seed ,
- data_seed_i => p2_tg_data_seed ,
- load_seed_i => p2_tg_load_seed,
- addr_mode_i => p2_tg_addr_mode,
-
- instr_mode_i => p2_tg_instr_mode ,
- bl_mode_i => p2_tg_bl_mode ,
- data_mode_i => p2_tg_data_mode ,
- mode_load_i => p2_tg_mode_load ,
-
- -- fixed pattern inputs interface
- fixed_bl_i => p2_tg_fixed_bl,
- fixed_instr_i => p2_tg_fixed_instr,
- fixed_addr_i => p2_tg_fixed_addr,
- fixed_data_i => (others => '0'),
- -- BRAM interface.
- bram_cmd_i => (others => '0'),
- bram_valid_i => '0',
- bram_rdy_o => open,
-
- -- MCB INTERFACE
- mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
- mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
- mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
- mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
- mcb_cmd_full_i => p2_mcb_cmd_full_i,
-
- mcb_wr_en_o => p2_mcb_wr_en_o_int,
- mcb_wr_mask_o => p2_mcb_wr_mask_o,
- mcb_wr_data_o => p2_mcb_wr_data_o,
- mcb_wr_data_end_o => open,
- mcb_wr_full_i => p2_mcb_wr_full_i,
- mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
-
- mcb_rd_en_o => p2_mcb_rd_en_o,
- mcb_rd_data_i => p2_mcb_rd_data_i,
- mcb_rd_empty_i => p2_mcb_rd_empty_i,
- mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-
- -- status feedback
- counts_rst => rst0,
- wr_data_counts => open,
- rd_data_counts => open,
- cmp_data => p2_cmp_data,
- cmp_data_valid => p2_cmp_data_valid,
- cmp_error => p2_cmp_error,
- error => p2_error,
- error_status => p2_error_status,
- mem_rd_data => open,
- dq_error_bytelane_cmp => open,
- cumlative_dq_lane_error => open
- );
-
-
-
-p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
-p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
-p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
-p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
-p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
-
- init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
- generic map
- (
- DWIDTH => p3_DWIDTH,
- FAMILY => FAMILY,
- BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
- END_ADDRESS => C_p0_END_ADDRESS,
- CMD_SEED_VALUE => X"56456783",
- DATA_SEED_VALUE => X"12345678",
- DATA_MODE => C_p0_DATA_MODE,
- PORT_MODE => p3_PORT_MODE
-
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
-
- mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
- mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
- mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
- mcb_wr_en_i => p0_mcb_wr_en_o_int,
-
- vio_modify_enable => vio_modify_enable,
- vio_data_mode_value => vio_data_mode_value,
- vio_addr_mode_value => vio_addr_mode_value,
- vio_bl_mode_value => "10",--vio_bl_mode_value,
- vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
-
- mcb_init_done_i => calib_done,
- cmp_error => p3_error,
- run_traffic_o => p3_tg_run_traffic,
- start_addr_o => p3_tg_start_addr,
- end_addr_o => p3_tg_end_addr ,
- cmd_seed_o => p3_tg_cmd_seed ,
- data_seed_o => p3_tg_data_seed ,
- load_seed_o => p3_tg_load_seed ,
- addr_mode_o => p3_tg_addr_mode ,
- instr_mode_o => p3_tg_instr_mode ,
- bl_mode_o => p3_tg_bl_mode ,
- data_mode_o => p3_tg_data_mode ,
- mode_load_o => p3_tg_mode_load ,
- fixed_bl_o => p3_tg_fixed_bl ,
- fixed_instr_o => p3_tg_fixed_instr,
- fixed_addr_o => p3_tg_fixed_addr
- );
-
- m_traffic_gen_p3 : mcb_traffic_gen
- generic map(
- MEM_BURST_LEN => C_MEM_BURST_LEN,
- MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
- NUM_DQ_PINS => C_NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
-
- PORT_MODE => p3_PORT_MODE,
- DWIDTH => p3_DWIDTH,
- CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
- FAMILY => FAMILY,
- SIMULATION => "FALSE",
- DATA_PATTERN => "DGEN_ADDR",
- CMD_PATTERN => "CGEN_ALL",
- ADDR_WIDTH => 30,
- PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
- PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
- PRBS_SADDR => C_p0_BEGIN_ADDRESS,
- PRBS_EADDR => C_p0_END_ADDRESS
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
- run_traffic_i => p3_tg_run_traffic,
- manual_clear_error => rst0,
- -- runtime parameter
- start_addr_i => p3_tg_start_addr ,
- end_addr_i => p3_tg_end_addr ,
- cmd_seed_i => p3_tg_cmd_seed ,
- data_seed_i => p3_tg_data_seed ,
- load_seed_i => p3_tg_load_seed,
- addr_mode_i => p3_tg_addr_mode,
-
- instr_mode_i => p3_tg_instr_mode ,
- bl_mode_i => p3_tg_bl_mode ,
- data_mode_i => p3_tg_data_mode ,
- mode_load_i => p3_tg_mode_load ,
-
- -- fixed pattern inputs interface
- fixed_bl_i => p3_tg_fixed_bl,
- fixed_instr_i => p3_tg_fixed_instr,
- fixed_addr_i => p3_tg_fixed_addr,
- fixed_data_i => (others => '0'),
- -- BRAM interface.
- bram_cmd_i => (others => '0'),
- bram_valid_i => '0',
- bram_rdy_o => open,
-
- -- MCB INTERFACE
- mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
- mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
- mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
- mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
- mcb_cmd_full_i => p3_mcb_cmd_full_i,
-
- mcb_wr_en_o => p3_mcb_wr_en_o_int,
- mcb_wr_mask_o => p3_mcb_wr_mask_o,
- mcb_wr_data_o => p3_mcb_wr_data_o,
- mcb_wr_data_end_o => open,
- mcb_wr_full_i => p3_mcb_wr_full_i,
- mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
-
- mcb_rd_en_o => p3_mcb_rd_en_o,
- mcb_rd_data_i => p3_mcb_rd_data_i,
- mcb_rd_empty_i => p3_mcb_rd_empty_i,
- mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-
- -- status feedback
- counts_rst => rst0,
- wr_data_counts => open,
- rd_data_counts => open,
- cmp_data => p3_cmp_data,
- cmp_data_valid => p3_cmp_data_valid,
- cmp_error => p3_cmp_error,
- error => p3_error,
- error_status => p3_error_status,
- mem_rd_data => open,
- dq_error_bytelane_cmp => open,
- cumlative_dq_lane_error => open
- );
-
-
-
-p4_mcb_cmd_en_o <= p4_mcb_cmd_en_o_int;
-p4_mcb_cmd_instr_o <= p4_mcb_cmd_instr_o_int;
-p4_mcb_cmd_bl_o <= p4_mcb_cmd_bl_o_int;
-p4_mcb_cmd_addr_o <= p4_mcb_cmd_addr_o_int;
-p4_mcb_wr_en_o <= p4_mcb_wr_en_o_int;
-
- init_mem_pattern_ctr_p4 :init_mem_pattern_ctr
- generic map
- (
- DWIDTH => p4_DWIDTH,
- FAMILY => FAMILY,
- BEGIN_ADDRESS => C_p4_BEGIN_ADDRESS,
- END_ADDRESS => C_p4_END_ADDRESS,
- CMD_SEED_VALUE => X"56456783",
- DATA_SEED_VALUE => X"12345678",
- DATA_MODE => C_p4_DATA_MODE,
- PORT_MODE => p4_PORT_MODE
-
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
-
- mcb_cmd_en_i => p4_mcb_cmd_en_o_int,
- mcb_cmd_instr_i => p4_mcb_cmd_instr_o_int,
- mcb_cmd_bl_i => p4_mcb_cmd_bl_o_int,
- mcb_wr_en_i => p4_mcb_wr_en_o_int,
-
- vio_modify_enable => vio_modify_enable,
- vio_data_mode_value => vio_data_mode_value,
- vio_addr_mode_value => vio_addr_mode_value,
- vio_bl_mode_value => "10",--vio_bl_mode_value,
- vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
-
- mcb_init_done_i => calib_done,
- cmp_error => p4_error,
- run_traffic_o => p4_tg_run_traffic,
- start_addr_o => p4_tg_start_addr,
- end_addr_o => p4_tg_end_addr ,
- cmd_seed_o => p4_tg_cmd_seed ,
- data_seed_o => p4_tg_data_seed ,
- load_seed_o => p4_tg_load_seed ,
- addr_mode_o => p4_tg_addr_mode ,
- instr_mode_o => p4_tg_instr_mode ,
- bl_mode_o => p4_tg_bl_mode ,
- data_mode_o => p4_tg_data_mode ,
- mode_load_o => p4_tg_mode_load ,
- fixed_bl_o => p4_tg_fixed_bl ,
- fixed_instr_o => p4_tg_fixed_instr,
- fixed_addr_o => p4_tg_fixed_addr
- );
-
- m_traffic_gen_p4 : mcb_traffic_gen
- generic map(
- MEM_BURST_LEN => C_MEM_BURST_LEN,
- MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
- NUM_DQ_PINS => C_NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
-
- PORT_MODE => p4_PORT_MODE,
- DWIDTH => p4_DWIDTH,
- CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
- FAMILY => FAMILY,
- SIMULATION => "FALSE",
- DATA_PATTERN => "DGEN_ADDR",
- CMD_PATTERN => "CGEN_ALL",
- ADDR_WIDTH => 30,
- PRBS_SADDR_MASK_POS => C_p4_PRBS_SADDR_MASK_POS,
- PRBS_EADDR_MASK_POS => C_p4_PRBS_EADDR_MASK_POS,
- PRBS_SADDR => C_p4_BEGIN_ADDRESS,
- PRBS_EADDR => C_p4_END_ADDRESS
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
- run_traffic_i => p4_tg_run_traffic,
- manual_clear_error => rst0,
- -- runtime parameter
- start_addr_i => p4_tg_start_addr ,
- end_addr_i => p4_tg_end_addr ,
- cmd_seed_i => p4_tg_cmd_seed ,
- data_seed_i => p4_tg_data_seed ,
- load_seed_i => p4_tg_load_seed,
- addr_mode_i => p4_tg_addr_mode,
-
- instr_mode_i => p4_tg_instr_mode ,
- bl_mode_i => p4_tg_bl_mode ,
- data_mode_i => p4_tg_data_mode ,
- mode_load_i => p4_tg_mode_load ,
-
- -- fixed pattern inputs interface
- fixed_bl_i => p4_tg_fixed_bl,
- fixed_instr_i => p4_tg_fixed_instr,
- fixed_addr_i => p4_tg_fixed_addr,
- fixed_data_i => (others => '0'),
- -- BRAM interface.
- bram_cmd_i => (others => '0'),
- bram_valid_i => '0',
- bram_rdy_o => open,
-
- -- MCB INTERFACE
- mcb_cmd_en_o => p4_mcb_cmd_en_o_int,
- mcb_cmd_instr_o => p4_mcb_cmd_instr_o_int,
- mcb_cmd_bl_o => p4_mcb_cmd_bl_o_int,
- mcb_cmd_addr_o => p4_mcb_cmd_addr_o_int,
- mcb_cmd_full_i => p4_mcb_cmd_full_i,
-
- mcb_wr_en_o => p4_mcb_wr_en_o_int,
- mcb_wr_mask_o => p4_mcb_wr_mask_o,
- mcb_wr_data_o => p4_mcb_wr_data_o,
- mcb_wr_data_end_o => open,
- mcb_wr_full_i => p4_mcb_wr_full_i,
- mcb_wr_fifo_counts => p4_mcb_wr_fifo_counts,
-
- mcb_rd_en_o => p4_mcb_rd_en_o,
- mcb_rd_data_i => p4_mcb_rd_data_i,
- mcb_rd_empty_i => p4_mcb_rd_empty_i,
- mcb_rd_fifo_counts => p4_mcb_rd_fifo_counts,
-
- -- status feedback
- counts_rst => rst0,
- wr_data_counts => open,
- rd_data_counts => open,
- cmp_data => p4_cmp_data,
- cmp_data_valid => p4_cmp_data_valid,
- cmp_error => p4_cmp_error,
- error => p4_error,
- error_status => p4_error_status,
- mem_rd_data => open,
- dq_error_bytelane_cmp => open,
- cumlative_dq_lane_error => open
- );
-
-
-
-p5_mcb_cmd_en_o <= p5_mcb_cmd_en_o_int;
-p5_mcb_cmd_instr_o <= p5_mcb_cmd_instr_o_int;
-p5_mcb_cmd_bl_o <= p5_mcb_cmd_bl_o_int;
-p5_mcb_cmd_addr_o <= p5_mcb_cmd_addr_o_int;
-p5_mcb_wr_en_o <= p5_mcb_wr_en_o_int;
-
- init_mem_pattern_ctr_p5 :init_mem_pattern_ctr
- generic map
- (
- DWIDTH => p5_DWIDTH,
- FAMILY => FAMILY,
- BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
- END_ADDRESS => C_p0_END_ADDRESS,
- CMD_SEED_VALUE => X"56456783",
- DATA_SEED_VALUE => X"12345678",
- DATA_MODE => C_p0_DATA_MODE,
- PORT_MODE => p5_PORT_MODE
-
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
-
- mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
- mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
- mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
- mcb_wr_en_i => p0_mcb_wr_en_o_int,
-
- vio_modify_enable => vio_modify_enable,
- vio_data_mode_value => vio_data_mode_value,
- vio_addr_mode_value => vio_addr_mode_value,
- vio_bl_mode_value => "10",--vio_bl_mode_value,
- vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
-
- mcb_init_done_i => calib_done,
- cmp_error => p5_error,
- run_traffic_o => p5_tg_run_traffic,
- start_addr_o => p5_tg_start_addr,
- end_addr_o => p5_tg_end_addr ,
- cmd_seed_o => p5_tg_cmd_seed ,
- data_seed_o => p5_tg_data_seed ,
- load_seed_o => p5_tg_load_seed ,
- addr_mode_o => p5_tg_addr_mode ,
- instr_mode_o => p5_tg_instr_mode ,
- bl_mode_o => p5_tg_bl_mode ,
- data_mode_o => p5_tg_data_mode ,
- mode_load_o => p5_tg_mode_load ,
- fixed_bl_o => p5_tg_fixed_bl ,
- fixed_instr_o => p5_tg_fixed_instr,
- fixed_addr_o => p5_tg_fixed_addr
- );
-
- m_traffic_gen_p5 : mcb_traffic_gen
- generic map(
- MEM_BURST_LEN => C_MEM_BURST_LEN,
- MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
- NUM_DQ_PINS => C_NUM_DQ_PINS,
- DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
-
- PORT_MODE => p5_PORT_MODE,
- DWIDTH => p5_DWIDTH,
- CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
- FAMILY => FAMILY,
- SIMULATION => "FALSE",
- DATA_PATTERN => "DGEN_ADDR",
- CMD_PATTERN => "CGEN_ALL",
- ADDR_WIDTH => 30,
- PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
- PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
- PRBS_SADDR => C_p0_BEGIN_ADDRESS,
- PRBS_EADDR => C_p0_END_ADDRESS
- )
- port map
- (
- clk_i => clk0,
- rst_i => rst0,
- run_traffic_i => p5_tg_run_traffic,
- manual_clear_error => rst0,
- -- runtime parameter
- start_addr_i => p5_tg_start_addr ,
- end_addr_i => p5_tg_end_addr ,
- cmd_seed_i => p5_tg_cmd_seed ,
- data_seed_i => p5_tg_data_seed ,
- load_seed_i => p5_tg_load_seed,
- addr_mode_i => p5_tg_addr_mode,
-
- instr_mode_i => p5_tg_instr_mode ,
- bl_mode_i => p5_tg_bl_mode ,
- data_mode_i => p5_tg_data_mode ,
- mode_load_i => p5_tg_mode_load ,
-
- -- fixed pattern inputs interface
- fixed_bl_i => p5_tg_fixed_bl,
- fixed_instr_i => p5_tg_fixed_instr,
- fixed_addr_i => p5_tg_fixed_addr,
- fixed_data_i => (others => '0'),
- -- BRAM interface.
- bram_cmd_i => (others => '0'),
- bram_valid_i => '0',
- bram_rdy_o => open,
-
- -- MCB INTERFACE
- mcb_cmd_en_o => p5_mcb_cmd_en_o_int,
- mcb_cmd_instr_o => p5_mcb_cmd_instr_o_int,
- mcb_cmd_bl_o => p5_mcb_cmd_bl_o_int,
- mcb_cmd_addr_o => p5_mcb_cmd_addr_o_int,
- mcb_cmd_full_i => p5_mcb_cmd_full_i,
-
- mcb_wr_en_o => p5_mcb_wr_en_o_int,
- mcb_wr_mask_o => p5_mcb_wr_mask_o,
- mcb_wr_data_o => p5_mcb_wr_data_o,
- mcb_wr_data_end_o => open,
- mcb_wr_full_i => p5_mcb_wr_full_i,
- mcb_wr_fifo_counts => p5_mcb_wr_fifo_counts,
-
- mcb_rd_en_o => p5_mcb_rd_en_o,
- mcb_rd_data_i => p5_mcb_rd_data_i,
- mcb_rd_empty_i => p5_mcb_rd_empty_i,
- mcb_rd_fifo_counts => p5_mcb_rd_fifo_counts,
-
- -- status feedback
- counts_rst => rst0,
- wr_data_counts => open,
- rd_data_counts => open,
- cmp_data => p5_cmp_data,
- cmp_data_valid => p5_cmp_data_valid,
- cmp_error => p5_cmp_error,
- error => p5_error,
- error_status => p5_error_status,
- mem_rd_data => open,
- dq_error_bytelane_cmp => open,
- cumlative_dq_lane_error => open
- );
-
-
-end architecture;
-
Index: ipcore_dir/mem0/user_design/sim/v6_data_gen.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/v6_data_gen.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/v6_data_gen.vhd (nonexistent)
@@ -1,3276 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
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--- special, incidental, or consequential loss or damage
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--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
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--- applications related to the deployment of airbags, or any
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--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : %version
--- \ \ Application : MIG
--- / / Filename : v6_data_gen.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
--- Device : Virtex6
--- Design Name : DDR2/DDR3
--- Purpose : This module generates different data pattern as described in
--- parameter DATA_PATTERN and is set up for Virtex 6 family.
--- Reference :
--- Revision History:
---*****************************************************************************
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity v6_data_gen is
- generic (
- EYE_TEST : string := "FALSE";
- ADDR_WIDTH : integer := 32;
- MEM_BURST_LEN : integer := 8;
- BL_WIDTH : integer := 6;
- DWIDTH : integer := 288;
- DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : integer := 72;
- COLUMN_WIDTH : integer := 10;
- SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
- );
- port (
- clk_i : in std_logic;
- rst_i : in std_logic;
- prbs_fseed_i : in std_logic_vector(31 downto 0);
- data_mode_i : in std_logic_vector(3 downto 0);
- data_rdy_i : in std_logic;
- cmd_startA : in std_logic;
- cmd_startB : in std_logic;
- cmd_startC : in std_logic;
- cmd_startD : in std_logic;
- cmd_startE : in std_logic;
- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
- fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
- addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
- user_burst_cnt : in std_logic_vector(6 downto 0);
- fifo_rdy_i : in std_logic;
- data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
- );
-end entity v6_data_gen;
-
-architecture trans of v6_data_gen is
-
-component data_prbs_gen is
- generic (
- EYE_TEST : string := "FALSE";
- PRBS_WIDTH : integer := 32;
- SEED_WIDTH : integer := 32
- );
- port (
- clk_i : in std_logic;
- clk_en : in std_logic;
- rst_i : in std_logic;
- prbs_fseed_i : in std_logic_vector(31 downto 0);
- prbs_seed_init : in std_logic;
- prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
-
- prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
- );
-end component;
-
- constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
- signal prbs_data : std_logic_vector(31 downto 0);
- signal acounts : std_logic_vector(35 downto 0);
- signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal tstpts : std_logic_vector(7 downto 0);
- signal burst_count_reached2 : std_logic;
- signal data_valid : std_logic;
- signal walk_cnt : std_logic_vector(2 downto 0);
- signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
- signal sel_w1gen_logic : std_logic;
- --signal BLANK : std_logic_vector(7 downto 0);
- --signal SHIFT_0 : std_logic_vector(7 downto 0);
- --signal SHIFT_1 : std_logic_vector(7 downto 0);
- --signal SHIFT_2 : std_logic_vector(7 downto 0);
- --signal SHIFT_3 : std_logic_vector(7 downto 0);
- --signal SHIFT_4 : std_logic_vector(7 downto 0);
- --signal SHIFT_5 : std_logic_vector(7 downto 0);
- --signal SHIFT_6 : std_logic_vector(7 downto 0);
- --signal SHIFT_7 : std_logic_vector(7 downto 0);
- signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
- signal data_clk_en : std_logic;
- signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
- signal i : integer;
- signal j : integer;
-
- signal data_mode_rr_a : std_logic_vector(3 downto 0);
- signal data_mode_rr_b : std_logic_vector(3 downto 0);
- signal data_mode_rr_c : std_logic_vector(3 downto 0);
- signal prbs_seed_i : std_logic_vector(31 downto 0);
-
- function concat ( in1 : integer;
- in2 : std_logic_vector) return std_logic_vector is
- variable rang : integer := in2'length;
- variable temp : std_logic_vector(in1*rang-1 downto 0);
- begin
- for i in 0 to in1-1 loop
- temp(rang*(i+1)-1 downto rang*i) := in2;
- end loop;
-
- return temp;
- end function;
-
-
- function Data_Gen ( int : integer
- ) return std_logic_vector is
-
- variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
- variable j : integer;
- begin
- j := int/2;
- if((int mod 2) = 1) then
-
- data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
- data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
- data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
- data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
- else
- data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
- data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
- data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
- data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
- end if;
-
-
-
- return data_bus;
- end function;
-
- function Data_GenW0 ( int : integer) return std_logic_vector is
-
- variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
- variable j : integer;
- begin
- j := int/2;
- if((int mod 2) = 1) then
- data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
- data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
- data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
- data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
- else
- data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
- data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
- data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
- data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
- end if;
-
- return data_bus;
- end function;
-
-
-
-begin
- data_o <= data;
- full_prbs_data <= concat(DWIDTH/32,prbs_data);
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- data_mode_rr_a <= data_mode_i;
- data_mode_rr_b <= data_mode_i;
- data_mode_rr_c <= data_mode_i;
- end if;
- end process;
-
-
- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
- begin
- case data_mode_rr_a is
- when "0000" =>
- data <= h_prbsdata;
- when "0001" => -- "0001" = fixed data
- data <= fixed_data_i;
- when "0010" => -- "0010" = address as data
- data <= adata;
- when "0011" => -- "0011" = hammer
- data <= hdata;
- when "0100" => -- "0100" = neighbour
- data <= ndata;
- when "0101" => -- "0101" = walking 1's
- data <= w1data;
-
- when "0110" => -- "0110" = walking 0's
- data <= w1data;
- when "0111" => -- "0111" = prbs
- data <= full_prbs_data;
- when others =>
- data <= (others => '0');
- end case;
- end process;
-
--- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
--- begin
--- case data_mode_rr_a is
--- when "0000" =>
--- data <= h_prbsdata;
--- when "0001" => -- "0001" = fixed data
--- data <= fixed_data_i;
--- when "0010" => -- "0010" = address as data
--- data <= adata;
--- when "0011" => -- "0011" = hammer
--- data <= hdata;
--- when "0100" => -- "0100" = neighbour
--- data <= ndata;
--- when "0111" => -- "0111" = prbs
--- data <= full_prbs_data;
--- when others =>
--- data <= w1data;
--- end case;
--- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
- sel_w1gen_logic <= '1';
- else
- sel_w1gen_logic <= '0';
- end if;
- end if;
- end process;
-
- WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(3) is
-
- when '0' =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
- when '1' =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- else
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(4 downto 3) is
-
- when "00" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "01" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "10" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "11" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- else
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(7 downto 3) is
-
- when "00000" | "00110" | "01100" |
- "10010" | "11000" | "11110" =>
- -- when "10010" | "11000"=>
-
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "00111" | "01101" |
- "10011" | "11001" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "01000" | "01110" | --2,8,14,20,26
- "10100" | "11010" =>
-
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "01001" | "01111" | --3,9,15,21,27
- "10101" | "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" | "01010" | "10000" |
- "10110" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" | "01011" | "10001" |
- "10111" | "11101" =>
-
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if; -- cmd_startC
- end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
- end if; -- clk
- end process;
- end generate;
-
- WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(6 downto 4) is
-
- when "000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
---
- WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(7 downto 4) is
-
- when "0000" | "1010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "0001" | "1011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "0010" | "1100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "0011" | "1101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "0100" | "1110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "0101" | "1111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "0110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "0111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "1000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "1001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_48_PATTERN :
- if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(7 downto 4) is
-
- when "0000" | "1100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "0001" | "1101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "0010" | "1110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "0011" | "1111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "0100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "0101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "0110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "0111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "1000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "1001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "1010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "1011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
---
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
-
-WALKING_ONE_56_PATTERN:
- if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(8 downto 5) is
-
- when "0000" | "1110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
-
- when "0001" | "1111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
-
- when "0010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
-
- when "0011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
- when "0100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "0101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "0110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "0111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "1000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "1001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "1010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
- when "1011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "1100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "1101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
---
-WALKING_ONE_64_PATTERN :
-if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(8 downto 5) is
-
- when "0000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "0001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "0010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "0011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "0100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "0101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "0110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "0111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "1000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "1001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "1010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "1011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "1100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "1101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "1110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "1111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-WALKING_ONE_72_PATTERN :
- if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" | "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" | "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" | "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" | "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" | "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" | "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" | "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
-WALKING_ONE_80_PATTERN :
-
- if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" | "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" | "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" | "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" | "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" | "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
-WALKING_ONE_88_PATTERN:
- if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" | "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" | "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" | "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
-
-WALKING_ONE_96_PATTERN:
- if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" | "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_104_PATTERN:
- if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(24);
- else
- w1data <= Data_GenW0(24);
- end if;
-
- when "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(25);
- else
- w1data <= Data_GenW0(25);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_112_PATTERN:
- if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(24);
- else
- w1data <= Data_GenW0(24);
- end if;
-
- when "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(25);
- else
- w1data <= Data_GenW0(25);
- end if;
-
- when "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(26);
- else
- w1data <= Data_GenW0(26);
- end if;
-
- when "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(27);
- else
- w1data <= Data_GenW0(27);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_120_PATTERN:
- if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(9 downto 5) is
-
- when "00000" | "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" | "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(24);
- else
- w1data <= Data_GenW0(24);
- end if;
-
- when "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(25);
- else
- w1data <= Data_GenW0(25);
- end if;
-
- when "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(26);
- else
- w1data <= Data_GenW0(26);
- end if;
-
- when "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(27);
- else
- w1data <= Data_GenW0(27);
- end if;
-
- when "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(28);
- else
- w1data <= Data_GenW0(28);
- end if;
-
- when "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(29);
- else
- w1data <= Data_GenW0(29);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_128_PATTERN:
- if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(10 downto 6) is
-
- when "00000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "00001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "00010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "00011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "00100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "00101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "00110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "00111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "01000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "01001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "01010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "01011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "01100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "01101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "01110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "01111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "10000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "10001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "10010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "10011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "10100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "10101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "10110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "10111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when "11000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(24);
- else
- w1data <= Data_GenW0(24);
- end if;
-
- when "11001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(25);
- else
- w1data <= Data_GenW0(25);
- end if;
-
- when "11010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(26);
- else
- w1data <= Data_GenW0(26);
- end if;
-
- when "11011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(27);
- else
- w1data <= Data_GenW0(27);
- end if;
-
- when "11100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(28);
- else
- w1data <= Data_GenW0(28);
- end if;
-
- when "11101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(29);
- else
- w1data <= Data_GenW0(29);
- end if;
-
- when "11110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(30);
- else
- w1data <= Data_GenW0(30);
- end if;
-
- when "11111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(31);
- else
- w1data <= Data_GenW0(31);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_136_PATTERN:
- if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(11 downto 6) is
-
- when "000000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "000001" | "100011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "000010" | "100100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "000011" | "100101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "000100" | "100110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "000101" | "100111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "000110" | "101000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
-
- when "000111" | "101001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "001000" | "101010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "001001" | "101011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "001010" | "101100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "001011" | "101101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "001100" | "101110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "001101" | "101111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "001110" | "110000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "001111" | "110001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "010000" | "110010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "010001" | "110011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "010010" | "110100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "010011" | "110101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "010100" | "110110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "010101" | "110111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "010110" | "111000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "010111" | "111001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when "011000" | "111010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(24);
- else
- w1data <= Data_GenW0(24);
- end if;
-
- when "011001" | "111011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(25);
- else
- w1data <= Data_GenW0(25);
- end if;
-
- when "011010" | "111100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(26);
- else
- w1data <= Data_GenW0(26);
- end if;
-
- when "011011" | "111101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(27);
- else
- w1data <= Data_GenW0(27);
- end if;
-
- when "011100" | "111110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(28);
- else
- w1data <= Data_GenW0(28);
- end if;
-
- when "011101" | "111111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(29);
- else
- w1data <= Data_GenW0(29);
- end if;
-
- when "011110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(30);
- else
- w1data <= Data_GenW0(30);
- end if;
-
- when "011111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(31);
- else
- w1data <= Data_GenW0(31);
- end if;
-
- when "100000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(32);
- else
- w1data <= Data_GenW0(32);
- end if;
-
- when "100001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(33);
- else
- w1data <= Data_GenW0(33);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- WALKING_ONE_144_PATTERN:
- if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if ( fifo_rdy_i = '1' or cmd_startC = '1') then
- if (cmd_startC = '1') then
- if (sel_w1gen_logic = '1') then
- case addr_i(11 downto 6) is
-
- when "000000" | "100100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(0);
- else
- w1data <= Data_GenW0(0);
- end if;
-
- when "000001" | "100101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(1);
- else
- w1data <= Data_GenW0(1);
- end if;
-
- when "000010" | "100110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(2);
- else
- w1data <= Data_GenW0(2);
- end if;
-
- when "000011" | "100111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(3);
- else
- w1data <= Data_GenW0(3);
- end if;
-
- when "000100" | "101000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(4);
- else
- w1data <= Data_GenW0(4);
- end if;
-
- when "000101" | "101001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(5);
- else
- w1data <= Data_GenW0(5);
- end if;
-
- when "000110" | "101010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(6);
- else
- w1data <= Data_GenW0(6);
- end if;
- when "000111" | "101011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(7);
- else
- w1data <= Data_GenW0(7);
- end if;
-
- when "001000" | "101100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(8);
- else
- w1data <= Data_GenW0(8);
- end if;
-
- when "001001" | "101101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(9);
- else
- w1data <= Data_GenW0(9);
- end if;
-
- when "001010" | "101110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(10);
- else
- w1data <= Data_GenW0(10);
- end if;
-
- when "001011" | "101111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(11);
- else
- w1data <= Data_GenW0(11);
- end if;
-
- when "001100" | "110000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(12);
- else
- w1data <= Data_GenW0(12);
- end if;
-
- when "001101" | "110001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(13);
- else
- w1data <= Data_GenW0(13);
- end if;
-
- when "001110" | "110010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(14);
- else
- w1data <= Data_GenW0(14);
- end if;
-
- when "001111" | "110011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(15);
- else
- w1data <= Data_GenW0(15);
- end if;
-
- when "010000" | "110100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(16);
- else
- w1data <= Data_GenW0(16);
- end if;
-
- when "010001" | "110101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(17);
- else
- w1data <= Data_GenW0(17);
- end if;
-
- when "010010" | "110110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(18);
- else
- w1data <= Data_GenW0(18);
- end if;
-
- when "010011" | "110111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(19);
- else
- w1data <= Data_GenW0(19);
- end if;
-
- when "010100" | "111000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(20);
- else
- w1data <= Data_GenW0(20);
- end if;
-
- when "010101" | "111001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(21);
- else
- w1data <= Data_GenW0(21);
- end if;
-
- when "010110" | "111010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(22);
- else
- w1data <= Data_GenW0(22);
- end if;
-
- when "010111" | "111011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(23);
- else
- w1data <= Data_GenW0(23);
- end if;
-
- when "011000" | "111100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(24);
- else
- w1data <= Data_GenW0(24);
- end if;
-
- when "011001" | "111101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(25);
- else
- w1data <= Data_GenW0(25);
- end if;
-
- when "011010" | "111110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(26);
- else
- w1data <= Data_GenW0(26);
- end if;
-
- when "011011" | "111111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(27);
- else
- w1data <= Data_GenW0(27);
- end if;
-
- when "011100" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(28);
- else
- w1data <= Data_GenW0(28);
- end if;
-
- when "011101" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(29);
- else
- w1data <= Data_GenW0(29);
- end if;
-
- when "011110" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(30);
- else
- w1data <= Data_GenW0(30);
- end if;
-
- when "011111" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(31);
- else
- w1data <= Data_GenW0(31);
- end if;
-
- when "100000" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(32);
- else
- w1data <= Data_GenW0(32);
- end if;
-
- when "100001" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(33);
- else
- w1data <= Data_GenW0(33);
- end if;
-
- when "100010" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(34);
- else
- w1data <= Data_GenW0(34);
- end if;
-
- when "100011" =>
- if (data_mode_i = "0101") then
- w1data <= Data_Gen(35);
- else
- w1data <= Data_GenW0(35);
- end if;
-
- when others =>
- w1data <= (others => '0');
-
- end case;
- end if;
- elsif (MEM_BURST_LEN = 8) then
- w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
- w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
- w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
- w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
- end if;
- end if;
- end if;
- end process;
- end generate;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- for i in 0 to 4 * NUM_DQ_PINS - 1 loop
- if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
- hdata(i) <= '1';
- elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
- hdata(i) <= '1';
- elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
- hdata(i) <= '0';
- elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
- hdata(i) <= '1';
- elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
- hdata(i) <= '0';
- else
- hdata(i) <= '1';
- end if;
- end loop;
- end if;
- end process;
-
- process (w1data, hdata)
- begin
- for i in 0 to 4 * NUM_DQ_PINS - 1 loop
- ndata(i) <= hdata(i) xor w1data(i);
- end loop;
- end process;
-
- process (full_prbs_data, hdata)
- begin
- for i in 0 to 4 * NUM_DQ_PINS - 1 loop
- if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
- h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
- else
- h_prbsdata(i) <= hdata(i);
- end if;
- end loop;
- end process;
-
- addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (cmd_startD = '1') then
- acounts <= ("0000" & addr_i);
- elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
- if (NUM_DQ_PINS = 8 ) then
- acounts <= acounts + X"000000004";
- elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
- acounts <= acounts + X"000000008";
- elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
- acounts <= acounts + X"000000010";
- elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
- acounts <= acounts + X"000000020";
- elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
- acounts <= acounts + X"000000040";
- end if;
- end if;
- end if;
- end process;
-
- adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
-
- end generate;
-
- -- When doing eye_test, traffic gen only does write and want to
- -- keep the prbs random and address is fixed at a location.
- d_clk_en1 : if (EYE_TEST = "TRUE") generate
- data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
- end generate;
-
- d_clk_en2 : if (EYE_TEST = "FALSE") generate
- data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
- end generate;
-
- prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-
- -- PRBS DATA GENERATION
- -- xor all the tap positions before feedback to 1st stage.
- prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
-
- data_prbs_gen_inst : data_prbs_gen
- generic map (
- PRBS_WIDTH => 32,
- SEED_WIDTH => 32,
- EYE_TEST => EYE_TEST
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i,
- clk_en => data_clk_en,
- prbs_fseed_i => prbs_fseed_i,
- prbs_seed_init => cmd_startE,
- prbs_seed_i => prbs_seed_i,
- prbs_o => prbs_data
- );
-
- end generate;
-
-end architecture trans;
ipcore_dir/mem0/user_design/sim/v6_data_gen.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/tg_status.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/tg_status.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/tg_status.vhd (nonexistent)
@@ -1,142 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: tg_status.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
--- Error signal will be asserted if the comparsion is not equal.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
-
-entity tg_status is
- generic (
- TCQ : TIME := 100 ps;
- DWIDTH : integer := 32
- );
- port (
-
- clk_i : in std_logic;
- rst_i : in std_logic;
- manual_clear_error : in std_logic;
- data_error_i : in std_logic;
- cmp_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- cmp_addr_i : in std_logic_vector(31 downto 0);
- cmp_bl_i : in std_logic_vector(5 downto 0);
- mcb_cmd_full_i : in std_logic;
- mcb_wr_full_i : in std_logic;
- mcb_rd_empty_i : in std_logic;
- error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
- error : out std_logic
- );
-end entity tg_status;
-
-architecture trans of tg_status is
-
- signal data_error_r : std_logic;
- signal error_set : std_logic;
-begin
- error <= error_set;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
-
- data_error_r <= data_error_i;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
-
- if ((rst_i or manual_clear_error) = '1') then
--- error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
- error_status <= (others => '0');
- error_set <= '0';
- else
- -- latch the first error only
- if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
- error_status(31 downto 0) <= cmp_addr_i;
- error_status(37 downto 32) <= cmp_bl_i;
- error_status(40) <= mcb_cmd_full_i;
- error_status(41) <= mcb_wr_full_i;
- error_status(42) <= mcb_rd_empty_i;
- error_set <= '1';
- error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
-
- error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
- end if;
-
- error_status(39 downto 38) <= "00"; -- reserved
-
- error_status(63 downto 43) <= "000000000000000000000"; -- reserved
- end if;
- end if;
- end process;
-
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/sim/tg_status.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/sim/read_data_path.vhd
===================================================================
--- ipcore_dir/mem0/user_design/sim/read_data_path.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/sim/read_data_path.vhd (nonexistent)
@@ -1,638 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: read_data_path.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:08 $
--- \ \ / \ Date Created: Jul 03 2009
--- \___\/\___\
---
--- Device: Spartan6
--- Design Name: DDR/DDR2/DDR3/LPDDR
--- Purpose: This is top level of read path and also consist of comparison logic
--- for read data.
--- Reference:
--- Revision History:
-
---*****************************************************************************
-
-LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-entity read_data_path is
- generic (
- TCQ : time := 100 ps;
- FAMILY : string := "VIRTEX6";
- MEM_BURST_LEN : integer := 8;
- ADDR_WIDTH : integer := 32;
- CMP_DATA_PIPE_STAGES : integer := 3;
- DWIDTH : integer := 32;
- DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
- NUM_DQ_PINS : integer := 8;
- DQ_ERROR_WIDTH : integer := 1;
- SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
-
- MEM_COL_WIDTH : integer := 10
- );
- port (
-
- clk_i : in std_logic;
- manual_clear_error : in std_logic;
- rst_i : in std_logic_vector(9 downto 0);
- cmd_rdy_o : out std_logic;
- cmd_valid_i : in std_logic;
- prbs_fseed_i : in std_logic_vector(31 downto 0);
-
- data_mode_i : in std_logic_vector(3 downto 0);
- cmd_sent : in std_logic_vector(2 downto 0);
- bl_sent : in std_logic_vector(5 downto 0);
- cmd_en_i : in std_logic;
- m_addr_i : in std_logic_vector(31 downto 0);
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
-
- addr_i : in std_logic_vector(31 downto 0);
- bl_i : in std_logic_vector(5 downto 0);
- -- input [5:0] port_data_counts_i,// connect to data port fifo counts
-
- data_rdy_o : out std_logic;
- data_valid_i : in std_logic;
- data_i : in std_logic_vector(DWIDTH - 1 downto 0);
- last_word_rd_o : out std_logic;
- data_error_o : out std_logic;
- cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
- rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
- cmp_data_valid : out std_logic;
- cmp_addr_o : out std_logic_vector(31 downto 0);
- cmp_bl_o : out std_logic_vector(5 downto 0);
- force_wrcmd_gen_o : out std_logic;
-
- rd_buff_avail_o : out std_logic_vector(6 downto 0);
- dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
- cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
-
-
-
- );
-end entity read_data_path;
-
-architecture trans of read_data_path is
-
-function REDUCTION_OR( A: in std_logic_vector) return std_logic is
- variable tmp : std_logic := '0';
-begin
- for i in A'range loop
- tmp := tmp or A(i);
- end loop;
- return tmp;
-end function REDUCTION_OR;
-
- COMPONENT read_posted_fifo IS
- GENERIC (
- TCQ : time := 100 ps;
- MEM_BURST_LEN : integer := 4;
- FAMILY : STRING := "SPARTAN6";
- ADDR_WIDTH : INTEGER := 32;
- BL_WIDTH : INTEGER := 6
- );
- PORT (
- clk_i : IN STD_LOGIC;
- rst_i : IN STD_LOGIC;
- cmd_rdy_o : OUT STD_LOGIC;
- cmd_valid_i : IN STD_LOGIC;
- data_valid_i : IN STD_LOGIC;
- addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
- user_bl_cnt_is_1 : IN STD_LOGIC;
- cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
- cmd_en_i : IN STD_LOGIC;
- gen_rdy_i : IN STD_LOGIC;
- gen_valid_o : OUT STD_LOGIC;
- gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
- gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
- rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
- rd_mdata_fifo_empty : IN STD_LOGIC;
- rd_mdata_en : OUT STD_LOGIC
- );
- END COMPONENT;
-
- component rd_data_gen is
- generic (
- FAMILY : string := "SPARTAN6";
- MEM_BURST_LEN : integer := 8;
- ADDR_WIDTH : integer := 32;
- BL_WIDTH : integer := 6;
- DWIDTH : integer := 32;
- DATA_PATTERN : string := "DGEN_PRBS";
- NUM_DQ_PINS : integer := 8;
- SEL_VICTIM_LINE : integer := 3;
- COLUMN_WIDTH : integer := 10
- );
- port (
- clk_i : in std_logic;
- rst_i : in std_logic_vector(4 downto 0);
- prbs_fseed_i : in std_logic_vector(31 downto 0);
- rd_mdata_en : in std_logic;
- data_mode_i : in std_logic_vector(3 downto 0);
- cmd_rdy_o : out std_logic;
- cmd_valid_i : in std_logic;
- last_word_o : out std_logic;
- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
- fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
-
- addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
- bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
- user_bl_cnt_is_1_o : out std_logic;
- data_rdy_i : in std_logic;
- data_valid_o : out std_logic;
- data_o : out std_logic_vector(DWIDTH - 1 downto 0)
- );
- end component;
-
- component afifo IS
- GENERIC (
- DSIZE : INTEGER := 32;
- FIFO_DEPTH : INTEGER := 16;
- ASIZE : INTEGER := 5;
- SYNC : INTEGER := 1
- );
- PORT (
- wr_clk : IN STD_LOGIC;
- rst : IN STD_LOGIC;
- wr_en : IN STD_LOGIC;
- wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
- rd_en : IN STD_LOGIC;
- rd_clk : IN STD_LOGIC;
- rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
- almost_full : OUT STD_LOGIC;
- full : OUT STD_LOGIC;
- empty : OUT STD_LOGIC
- );
-END component;
-
- signal gen_rdy : std_logic;
- signal gen_valid : std_logic;
- signal gen_addr : std_logic_vector(31 downto 0);
- signal gen_bl : std_logic_vector(5 downto 0);
-
- signal cmp_rdy : std_logic;
- signal cmp_valid : std_logic;
- signal cmp_addr : std_logic_vector(31 downto 0);
- signal cmp_bl : std_logic_vector(5 downto 0);
-
- signal data_error : std_logic;
- signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
- signal last_word_rd : std_logic;
- signal bl_counter : std_logic_vector(5 downto 0);
- signal cmd_rdy : std_logic;
- signal user_bl_cnt_is_1 : std_logic;
- signal data_rdy : std_logic;
- signal delayed_data : std_logic_vector(DWIDTH downto 0);
--- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
- signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
- signal rd_mdata_en : std_logic;
- signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
- signal force_wrcmd_gen : std_logic;
- signal wait_bl_end : std_logic;
- signal wait_bl_end_r1 : std_logic;
-
- signal v6_data_cmp_valid : std_logic;
- signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
- signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
- signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
- signal l_data_error : std_logic;
- signal u_data_error : std_logic;
- signal cmp_data_en : std_logic;
-
- signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
-
- signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
- signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
- signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
- signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
- signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
- signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
- signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
- signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
- signal rd_mdata_fifo_empty : std_logic;
- signal data_valid_r : std_logic;
- -- Declare intermediate signals for referenced outputs
--- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
--- SIGNAL tmp_sig : STD_LOGIC;
- signal last_word_rd_o_xhdl0 : std_logic;
- signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
-begin
- -- Drive referenced outputs
- last_word_rd_o <= last_word_rd_o_xhdl0;
- rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- wait_bl_end_r1 <= wait_bl_end;
- rd_data_r <= data_i;
- end if;
- end process;
-
- force_wrcmd_gen_o <= force_wrcmd_gen;
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i(0) = '1') then
- force_wrcmd_gen <= '0';
- elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
- force_wrcmd_gen <= '0';
- elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
- force_wrcmd_gen <= '1';
- end if;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i(0) = '1') then
- force_wrcmd_timeout_cnts <= "00000000";
- elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
- force_wrcmd_timeout_cnts <= "00000000";
- elsif (force_wrcmd_gen = '1') then
- force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
- end if;
- end if;
- end process;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (rst_i(0) = '1') then
- wait_bl_end <= '0';
- elsif (force_wrcmd_timeout_cnts = "11111111") then
- wait_bl_end <= '0';
- elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
- wait_bl_end <= '1';
- elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
- wait_bl_end <= '0';
- end if;
- end if;
- end process;
-
- cmd_rdy_o <= cmd_rdy;
-
-
- read_postedfifo : read_posted_fifo
- GENERIC MAP (
- TCQ => TCQ,
- FAMILY => FAMILY,
- MEM_BURST_LEN => MEM_BURST_LEN,
- ADDR_WIDTH => 32,
- BL_WIDTH => 6
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(0),
- cmd_rdy_o => cmd_rdy,
- cmd_valid_i => cmd_valid_i,
- data_valid_i => data_rdy,
- addr_i => addr_i,
- bl_i => bl_i,
- cmd_sent => cmd_sent,
- bl_sent => bl_sent,
- cmd_en_i => cmd_en_i,
- user_bl_cnt_is_1 => user_bl_cnt_is_1,
- gen_rdy_i => gen_rdy,
- gen_valid_o => gen_valid,
- gen_addr_o => gen_addr,
- gen_bl_o => gen_bl,
- rd_buff_avail_o => rd_buff_avail_o_xhdl1,
- rd_mdata_fifo_empty => rd_mdata_fifo_empty,
- rd_mdata_en => rd_mdata_en
- );
-
-
- rd_datagen : rd_data_gen
- generic map (
- FAMILY => FAMILY,
- MEM_BURST_LEN => MEM_BURST_LEN,
- NUM_DQ_PINS => NUM_DQ_PINS,
- SEL_VICTIM_LINE => SEL_VICTIM_LINE,
- DATA_PATTERN => DATA_PATTERN,
- DWIDTH => DWIDTH,
- COLUMN_WIDTH => MEM_COL_WIDTH
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i(4 downto 0),
- prbs_fseed_i => prbs_fseed_i,
- data_mode_i => data_mode_i,
- cmd_rdy_o => gen_rdy,
- cmd_valid_i => gen_valid,
- last_word_o => last_word_rd_o_xhdl0,
- m_addr_i => m_addr_i,
- fixed_data_i => fixed_data_i,
- addr_i => gen_addr,
- bl_i => gen_bl,
- user_bl_cnt_is_1_o => user_bl_cnt_is_1,
- data_rdy_i => data_valid_i,
- data_valid_o => cmp_valid,
- data_o => cmp_data,
- rd_mdata_en => rd_mdata_en
- );
-
- rd_mdata_fifo : afifo
- GENERIC MAP (
- DSIZE => DWIDTH,
- FIFO_DEPTH => 32,
- ASIZE => 5,
- SYNC => 1
- )
- PORT MAP (
- wr_clk => clk_i,
- rst => rst_i(0),
- wr_en => data_valid_i,
- wr_data => data_i,
- rd_en => rd_mdata_en,
- rd_clk => clk_i,
- rd_data => rd_v6_mdata,
- full => open,
- empty => rd_mdata_fifo_empty,
- almost_full => open
- );
-
--- tmp_sig <= cmp_valid AND data_valid_i;
--- xhdl2 <= ( tmp_sig & cmp_data);
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
--- delayed_data <= (tmp_sig & cmp_data);
- cmp_data_r <= cmp_data;
- end if;
- end process;
-
- rd_mdata_o <= rd_mdata;
-
- rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
- WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
-
- cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
- WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
-
-
- cmp_data_o <= cmp_data_r;
- cmp_addr_o <= gen_addr;
- cmp_bl_o <= gen_bl;
-
--- xhdl4 : if (FAMILY = "SPARTAN6") generate
--- rd_data_o <= rd_data_r;
--- end generate;
--- xhdl5 : if (FAMILY /= "SPARTAN6") generate
--- rd_data_o <= data_i;
--- end generate;
-
- data_rdy_o <= data_rdy;
- data_rdy <= cmp_valid and data_valid_i;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- v6_data_cmp_valid <= rd_mdata_en;
- end if;
- end process;
-
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- cmp_data_en <= data_rdy;
- end if;
- end process;
-
- xhdl6 : if (FAMILY = "SPARTAN6") generate
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- if (cmp_data_en = '1') then
- IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
- l_data_error <= '1' ;
- ELSE
- l_data_error <= '0' ;
- END IF;
- else
- l_data_error <= '0' ;
- end if;
- if (cmp_data_en = '1') then
- IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
- u_data_error <= '1' ;
- ELSE
- u_data_error <= '0' ;
- END IF;
- else
- u_data_error <= '0' ;
- end if;
- data_error <= l_data_error or u_data_error;
- --synthesis translate_off
- if (data_error = '1') then
- report ("DATA ERROR");
- end if;
- --synthesis translate_on
-
- end if;
- end process;
-
- end generate;
-
- gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
-
-
- gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
- error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
-
- end generate;
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
- error_byte_r1 <= (others => '0');
- data_error <= '0';
- ELSE
-
- error_byte_r1 <= error_byte;
- -- FOR i IN 0 TO DWIDTH - 1 LOOP
- data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
- -- END LOOP;
-
-
- END IF;
- end if;
- end process;
-
-
- process (data_error)
- begin
-
- --synthesis translate_off
- IF (data_error = '1') THEN
-
- report "DATA ERROR"; -- severity ERROR;
- END IF;
- --synthesis translate_on
- end process;
-
-
- gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
- dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
- error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
- error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
-
- cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
- end generate;
-
-
- process (clk_i)
- begin
- IF (clk_i'event and clk_i = '1') then
- IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
-
- dq_lane_error_r1 <= (others => '0');
- dq_lane_error_r2 <= (others => '0');
- data_valid_r <= '0';
- cumlative_dq_lane_error_reg <= (others => '0');
-
- ELSE
- data_valid_r <= data_valid_i;
-
- dq_lane_error_r1 <= dq_lane_error;
- cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
- END IF;
-
-
- END IF;
- end process;
-
-
-
- end generate;
-
- xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
-
- gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
- error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
- end generate;
-
- process (clk_i)
- begin
- if (clk_i'event and clk_i = '1') then
- IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
- error_byte_r1 <= (others => '0');
- data_error <= '0';
- ELSE
-
- error_byte_r1 <= error_byte;
- --FOR i IN 0 TO DWIDTH - 1 LOOP
- -- data_error <= error_byte_r1(i) OR data_error;
- --END LOOP;
- data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-
- --synthesis translate_off
- IF (data_error = '1') THEN
-
- report "DATA ERROR"; -- severity ERROR;
- end if;
- --synthesis translate_on
- END IF;
- end if;
- end process;
-
-
- gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
- dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
- error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
- error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
-
- cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
- end generate;
-
- process (clk_i)
- begin
- IF (clk_i'event and clk_i = '1') then
- IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
-
- dq_lane_error_r1 <= (others => '0');
- dq_lane_error_r2 <= (others => '0');
- data_valid_r <= '0';
- cumlative_dq_lane_error_reg <= (others => '0');
-
- ELSE
- data_valid_r <= data_valid_i;
-
- dq_lane_error_r1 <= dq_lane_error;
- cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
- END IF;
-
-
- END IF;
- end process;
-
- end generate;
- cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
-
- dq_error_bytelane_cmp <= dq_lane_error_r1;
-
- data_error_o <= data_error;
-
-end architecture trans;
-
-
-
-
ipcore_dir/mem0/user_design/sim/read_data_path.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd (nonexistent)
@@ -1,1384 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: mcb_soft_calibration.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:38 $
--- \ \ / \ Date Created: Mon Feb 9 2009
--- \___\/\___\
---
---Device: Spartan6
---Design Name: DDR/DDR2/DDR3/LPDDR
---Purpose: Xilinx reference design for MCB Soft
--- Calibration
---Reference:
---
--- Revision: Date: Comment
--- 1.0: 2/06/09: Initial version for MIG wrapper.
--- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
--- correctly)
--- 1.2: 2/12/09: Many other changes.
--- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
--- STATE
--- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
--- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
--- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
--- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
--- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
--- RST_DELAY.
--- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
--- 16 clocks. Added PNSKEW option.
--- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
--- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
--- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
--- with 8bit TARGET_DQS_DELAY which
--- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
--- Changed DQS_COUNT* to DQS_DELAY*.
--- Changed MCB_SYSRST port back to wire (from reg).
--- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
--- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
--- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
--- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
--- 3.4: 03/04/10: Recoded the RST_Reg logic.
--- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
--- 3.6 03/10/10: Improvements to Reset logic.
--- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
--- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
--- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-
--- End Revision
---**********************************************************************************
-
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.all;
-
-entity mcb_soft_calibration is
- generic (
- C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
- SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
- SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
- SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
- C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
- -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
- -- (Quarter, etc)
- C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
- C_MEM_TYPE : string := "DDR"
-
-
- );
- port (
- UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
- -- CLK pins
- RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
- DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
- -- hard calib complete)
- PLL_LOCK : in std_logic; -- Lock signal from PLL
- SELFREFRESH_REQ : in std_logic;
- SELFREFRESH_MCB_MODE : in std_logic;
- SELFREFRESH_MCB_REQ : out std_logic;
- SELFREFRESH_MODE : out std_logic;
- IODRP_ADD : out std_logic; -- IODRP ADD port
- IODRP_SDI : out std_logic; -- IODRP SDI port
- RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
- RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
- RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
- ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
- ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
- ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
- MCB_UIADD : out std_logic; -- to MCB's UIADD port
- MCB_UISDI : out std_logic; -- to MCB's UISDI port
- MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
- MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
- MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
- MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
- MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
- -- during IODRP2_MCB writes). Currently just trasnparent
- MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
- MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
- MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
- MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
- MCB_UIDQLOWERDEC : out std_logic := '0';
- MCB_UIDQLOWERINC : out std_logic := '0';
- MCB_UIDQUPPERDEC : out std_logic := '0';
- MCB_UIDQUPPERINC : out std_logic := '0';
- MCB_UILDQSDEC : out std_logic := '0';
- MCB_UILDQSINC : out std_logic := '0';
- MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
- -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
- MCB_UIUDQSDEC : out std_logic := '0';
- MCB_UIUDQSINC : out std_logic := '0';
- MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
- MCB_UICMD : out std_logic;
- MCB_UICMDIN : out std_logic;
- MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
- MCB_UODATA : in std_logic_vector(7 downto 0);
- MCB_UODATAVALID : in std_logic;
- MCB_UOCMDREADY : in std_logic;
- MCB_UO_CAL_START : in std_logic;
- MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
- Max_Value : out std_logic_vector(7 downto 0);
- CKE_Train : out std_logic
- );
-end entity mcb_soft_calibration;
-
-architecture trans of mcb_soft_calibration is
-
- constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
- constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
- constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
- constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
- constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
- constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
- constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
- constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
- constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
- constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
- constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
- constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
- constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
- constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
- constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
- constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
- constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
- constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
- constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
- constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
- constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
- constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
- constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
- constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
- constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
- constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
- constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
- constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
- constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
- constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
- constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
- constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
-
- constant START : std_logic_vector(5 downto 0) := "000000";
- constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
- constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
- constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
- constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
- constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
- constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
- constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
- constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
- constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
- constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
- constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
- constant SKEW : std_logic_vector(5 downto 0) := "001100";
- constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
- constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
- constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
- constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
- constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
- constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "010010";
- constant WAIT7 : std_logic_vector(5 downto 0) := "010011";
- constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "010100";
- constant WAIT8 : std_logic_vector(5 downto 0) := "010101";
- constant RST_DELAY : std_logic_vector(5 downto 0) := "010110";
- constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "010111";
- constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "011000";
- constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "011001";
- constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "011010";
- constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "011011";
- constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "011100";
- constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "011101";
- constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "011110";
- constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "011111";
- constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "100000";
- constant START_DYN_CAL : std_logic_vector(5 downto 0) := "100001";
- constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "100010";
- constant WAIT9 : std_logic_vector(5 downto 0) := "100011";
- constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "100100";
- constant WAIT10 : std_logic_vector(5 downto 0) := "100101";
- constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "100110";
- constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "100111";
- constant INCREMENT : std_logic_vector(5 downto 0) := "101000";
- constant DECREMENT : std_logic_vector(5 downto 0) := "101001";
- constant DONE : std_logic_vector(5 downto 0) := "101010";
-
- constant RZQ : std_logic_vector(1 downto 0) := "00";
- constant ZIO : std_logic_vector(1 downto 0) := "01";
- constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
- constant WRITE_MODE : std_logic := '0';
- constant READ_MODE : std_logic := '1';
-
- -- IOI Registers
- constant NoOp : std_logic_vector(7 downto 0) := "00000000";
- constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
- constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
- constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
- constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
- constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
- constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
- constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
- constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-
- -- IOB Registers
- constant PDrive : std_logic_vector(7 downto 0) := "10000000";
- constant PTerm : std_logic_vector(7 downto 0) := "10000001";
- constant NDrive : std_logic_vector(7 downto 0) := "10000010";
- constant NTerm : std_logic_vector(7 downto 0) := "10000011";
- constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
- constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
- constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
- constant InputControl : std_logic_vector(7 downto 0) := "10000111";
- constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-
--- No multi/divide is required when a 55 ohm resister is used on RZQ
--- localparam MULT = 1;
--- localparam DIV = 1;
--- use 7/4 scaling factor when the 100 ohm RZQ is used
- constant MULT : integer := 7;
- constant DIV : integer := 4;
-
- constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
- constant PSKEW_MULT : integer := 9;
- constant PSKEW_DIV : integer := 8;
- constant NSKEW_MULT : integer := 7;
- constant NSKEW_DIV : integer := 8;
-
- constant DQS_NUMERATOR : integer := 3;
- constant DQS_DENOMINATOR : integer := 8;
- constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
- -- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
- -- 3 for three eighths
-
- constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
- constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := C_MEM_TZQINIT_MAXCNT + RST_CNT;
-
- constant IN_TERM_PASS : std_logic := '0';
- constant DYN_CAL_PASS : std_logic := '1';
-
- component iodrp_mcb_controller is
- port (
- memcell_address : in std_logic_vector(7 downto 0);
- write_data : in std_logic_vector(7 downto 0);
- read_data : out std_logic_vector(7 downto 0);
- rd_not_write : in std_logic;
- cmd_valid : in std_logic;
- rdy_busy_n : out std_logic;
- use_broadcast : in std_logic;
- drp_ioi_addr : in std_logic_vector(4 downto 0);
- sync_rst : in std_logic;
- DRP_CLK : in std_logic;
- DRP_CS : out std_logic;
- DRP_SDI : out std_logic;
- DRP_ADD : out std_logic;
- DRP_BKST : out std_logic;
- DRP_SDO : in std_logic;
- MCB_UIREAD : out std_logic
- );
- end component;
-
- component iodrp_controller is
- port (
- memcell_address : in std_logic_vector(7 downto 0);
- write_data : in std_logic_vector(7 downto 0);
- read_data : out std_logic_vector(7 downto 0);
- rd_not_write : in std_logic;
- cmd_valid : in std_logic;
- rdy_busy_n : out std_logic;
- use_broadcast : in std_logic;
- sync_rst : in std_logic;
- DRP_CLK : in std_logic;
- DRP_CS : out std_logic;
- DRP_SDI : out std_logic;
- DRP_ADD : out std_logic;
- DRP_BKST : out std_logic;
- DRP_SDO : in std_logic
- );
- end component;
-
- signal P_Term : std_logic_vector(5 downto 0) := "000000";
- signal N_Term : std_logic_vector(6 downto 0) := "0000000";
- signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
- signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
-
- signal STATE : std_logic_vector(5 downto 0) := START;
- signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
- signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
- signal Active_IODRP : std_logic_vector(1 downto 0);
- signal IODRPCTRLR_R_WB : std_logic := '0';
- signal IODRPCTRLR_CMD_VALID : std_logic := '0';
- signal IODRPCTRLR_USE_BKST : std_logic := '0';
- signal MCB_CMD_VALID : std_logic := '0';
- signal MCB_USE_BKST : std_logic := '0';
- signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
- -- SYSRST pin (MCB_SYSRST)
- signal IODRP_SDO : std_logic;
- signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
- signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
- signal counter_en : std_logic := '0'; -- counter enable for "count"
- signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
- signal START_BROADCAST : std_logic := '1'; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
- -- state machine will wait for this to be high
- signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
- signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
- signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
- -- the Max Value changes by more than the threshold
- signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
- -- latency on UOREFRSHFLAG)
- signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
- -- latency on UOREFRSHFLAG)
- signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
- signal IODRPCTRLR_RDY_BUSY_N : std_logic;
- signal IODRP_CS : std_logic;
- signal MCB_READ_DATA : std_logic_vector(7 downto 0);
- signal RST_reg : std_logic;
- signal Block_Reset : std_logic;
- signal MCB_UODATAVALID_U : std_logic;
-
- signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
- signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
- signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
- signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
- signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
-
- signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
- signal rst_tmp : std_logic;
- signal LastPass_DynCal : std_logic;
- signal First_In_Term_Done : std_logic;
- signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
- signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
-
- signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
- -- parameter = "CALIBRATION"
- signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
- signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
- signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
- -- one-time or dynamic parameters are 1
- signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
- -- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
- signal Quarter_Max_Value : std_logic_vector(7 downto 0);
- signal Half_Max_Value : std_logic_vector(7 downto 0);
- signal PLL_LOCK_R1 : std_logic;
- signal PLL_LOCK_R2 : std_logic;
- signal MCB_RDY_BUSY_N : std_logic;
-
- signal SELFREFRESH_REQ_R1 : std_logic;
- signal SELFREFRESH_REQ_R2 : std_logic;
- signal SELFREFRESH_REQ_R3 : std_logic;
- signal SELFREFRESH_MCB_MODE_R1 : std_logic;
- signal SELFREFRESH_MCB_MODE_R2 : std_logic;
- signal SELFREFRESH_MCB_MODE_R3 : std_logic;
- signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
- signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
- signal START_DYN_CAL_STATE_R1 : std_logic;
- signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-
- -- Declare intermediate signals for referenced outputs
- signal IODRP_ADD_xilinx0 : std_logic;
- signal IODRP_SDI_xilinx1 : std_logic;
- signal MCB_UIADD_xilinx2 : std_logic;
- signal MCB_UISDI_xilinx11 : std_logic;
- signal MCB_UICS_xilinx6 : std_logic;
- signal MCB_UIBROADCAST_xilinx4 : std_logic;
- signal MCB_UIADDR_xilinx3 : std_logic_vector(4 downto 0);
- signal MCB_UIDONECAL_xilinx7 : std_logic;
- signal MCB_UIREAD_xilinx10 : std_logic;
- signal SELFREFRESH_MODE_xilinx11 : std_logic;
- signal Max_Value_int : std_logic_vector(7 downto 0);
- signal Rst_condition1 : std_logic;
- signal Rst_condition2 : std_logic;
- signal non_violating_rst : std_logic;
- signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
- -- This function multiplies by a constant MULT and then divides by the DIV constant
- function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
- variable Result : integer := 0;
- variable temp : std_logic_vector(14 downto 0) := "000000000000000";
- begin
- for count in 0 to (MULT-1) loop
- temp := temp + ("0000000" & Input);
- end loop;
- Result := (to_integer(unsigned(temp))) / (DIV);
- temp := std_logic_vector(to_unsigned(Result,15));
- return temp(7 downto 0);
- end function Mult_Divide;
-
- attribute syn_preserve : boolean;
- attribute syn_preserve of P_Term : signal is TRUE;
- attribute syn_preserve of N_Term : signal is TRUE;
- attribute syn_preserve of P_Term_Prev : signal is TRUE;
- attribute syn_preserve of N_Term_Prev : signal is TRUE;
- attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
- attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
- attribute syn_preserve of Max_Value_Previous : signal is TRUE;
- attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
-
- attribute iob : string;
- attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
-
-begin
-
- Max_Value <= Max_Value_int;
- -- Drive referenced outputs
- IODRP_ADD <= IODRP_ADD_xilinx0;
- IODRP_SDI <= IODRP_SDI_xilinx1;
- MCB_UIADD <= MCB_UIADD_xilinx2;
- MCB_UISDI <= MCB_UISDI_xilinx11;
- MCB_UICS <= MCB_UICS_xilinx6;
- MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
- MCB_UIADDR <= MCB_UIADDR_xilinx3;
- MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
- MCB_UIREAD <= MCB_UIREAD_xilinx10;
- SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
-
- Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
- Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
- Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
- Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
- Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
- CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
- Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
- Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
- DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
- DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
- SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
- -- skip dynamic input termination if either the one-time or dynamic parameters are 1
- SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
- -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
-
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
- DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
- else
- DONE_SOFTANDHARD_CAL <= '0';
- end if;
- end if;
- end process;
-
- iodrp_controller_inst : iodrp_controller
- port map (
- memcell_address => IODRPCTRLR_MEMCELL_ADDR,
- write_data => IODRPCTRLR_WRITE_DATA,
- read_data => IODRPCTRLR_READ_DATA,
- rd_not_write => IODRPCTRLR_R_WB,
- cmd_valid => IODRPCTRLR_CMD_VALID,
- rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
- use_broadcast => '0',
- sync_rst => RST_reg,
- DRP_CLK => UI_CLK,
- DRP_CS => IODRP_CS,
- DRP_SDI => IODRP_SDI_xilinx1,
- DRP_ADD => IODRP_ADD_xilinx0,
- DRP_SDO => IODRP_SDO,
- DRP_BKST => open
- );
-
- iodrp_mcb_controller_inst : iodrp_mcb_controller
- port map (
- memcell_address => IODRPCTRLR_MEMCELL_ADDR,
- write_data => IODRPCTRLR_WRITE_DATA,
- read_data => MCB_READ_DATA,
- rd_not_write => IODRPCTRLR_R_WB,
- cmd_valid => MCB_CMD_VALID,
- rdy_busy_n => MCB_RDY_BUSY_N,
- use_broadcast => MCB_USE_BKST,
- drp_ioi_addr => MCB_UIADDR_xilinx3,
- sync_rst => RST_reg,
- DRP_CLK => UI_CLK,
- DRP_CS => MCB_UICS_xilinx6,
- DRP_SDI => MCB_UISDI_xilinx11,
- DRP_ADD => MCB_UIADD_xilinx2,
- DRP_BKST => MCB_UIBROADCAST_xilinx4,
- DRP_SDO => MCB_UOSDO,
- MCB_UIREAD => MCB_UIREAD_xilinx10
- );
-
- init_sequence: if (C_SIMULATION = "FALSE") generate
- process (UI_CLK, RST) begin
- if (RST = '1') then
- WAIT_200us_COUNTER <= (others => '0');
- elsif (UI_CLK'event and UI_CLK = '1') then
- if (WAIT_200us_COUNTER(15) = '1') then
- WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
- else
- WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
- end if;
- end if;
- end process;
- end generate;
-
- init_sequence_skip: if (C_SIMULATION = "TRUE") generate
- WAIT_200us_COUNTER <= X"FFFF";
- end generate;
-
-
- gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
- process (UI_CLK, RST) begin
- if (RST = '1') then
- CKE_Train <= '0';
- elsif (UI_CLK'event and UI_CLK = '1') then
- if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
- CKE_Train <= '0';
- elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
- CKE_Train <= '1';
- end if;
- end if;
- end process;
- end generate ;
-
- gen_CKE_Train_b: if (C_MEM_TYPE /= "DDR2") generate
- process (UI_CLK) begin
- if (UI_CLK'event and UI_CLK = '1') then
- CKE_Train <= '0';
- end if;
- end process;
- end generate ;
-
---********************************************
--- PLL_LOCK and RST signals
---********************************************
- MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
- -- SYSRST pin (MCB_SYSRST)
- rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
-
- process (UI_CLK, rst_tmp, RST) begin
- if (rst_tmp = '1') then
- Block_Reset <= '0';
- RstCounter <= (others => '0');
- elsif (RST = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets -- to DDR3)
- Block_Reset <= '0';
- RstCounter <= (others => '0');
- elsif (UI_CLK'event and UI_CLK = '1') then
- Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
- if (Pre_SYSRST = '1') then
- RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
- else
- if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
- Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
- RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
- end if;
- end if;
- end if;
- end process;
-
- non_violating_rst <= RST and Rst_condition1;
- process (UI_CLK) begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RstCounter >= TZQINIT_MAXCNT) then
- Rst_condition1 <= '1';
- else
- Rst_condition1 <= '0';
- end if;
- end if;
- end process;
-
-
-
- process (UI_CLK) begin
- if (UI_CLK'event and UI_CLK = '1') then
-
- if (RstCounter < RST_CNT) then
- Rst_condition2 <= '1';
- else
- Rst_condition2 <= '0';
- end if;
- end if;
- end process;
-
- process (UI_CLK, non_violating_rst) begin
- if (non_violating_rst = '1') then
- RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
- elsif (UI_CLK'event and UI_CLK = '1') then
- if (WAIT_200us_COUNTER(15) = '0') then
- RST_reg <= '0';
- else
- RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
- end if;
- end if;
- end process;
-
-
---********************************************
--- SUSPEND Logic
---********************************************
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
- SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
- SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
- SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-
- -- SELFREFRESH_REQ is clocked by user's application clock
- SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
- SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
- SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
-
- PLL_LOCK_R1 <= PLL_LOCK;
- PLL_LOCK_R2 <= PLL_LOCK_R1;
-
- end if;
- end process;
-
--- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
--- This is to make sure MCB get a locked sys_2x_clk before exiting
--- SELFREFRESH mode.
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RST = '1') then
- SELFREFRESH_MCB_REQ <= '0';
- elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R1 = '0') and (STATE = START_DYN_CAL)) then
- SELFREFRESH_MCB_REQ <= '0';
- elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R1 = '1')) then
- SELFREFRESH_MCB_REQ <= '1';
- end if;
- end if;
- end process;
-
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RST = '1') then
- WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
- elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
- WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
- elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
- -- START_DYN_CAL is next state
- WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
- end if;
- end if;
- end process;
-
--- Need to detect when SM entering START_DYN_CAL
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RST = '1') then
- PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
- START_DYN_CAL_STATE_R1 <= '0';
- else
- -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
- PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
- if (STATE = START_DYN_CAL) then
- START_DYN_CAL_STATE_R1 <= '1';
- else
- START_DYN_CAL_STATE_R1 <= '0';
- end if;
- if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
- PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
- elsif ((STATE = START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '0')) then
- PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
- end if;
- end if;
- end if;
- end process;
-
--- SELFREFRESH_MCB_MODE deasserted status is hold off
--- until Soft_Calib has at least done one loop of DQS update.
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RST = '1') then
- SELFREFRESH_MODE_xilinx11 <= '0';
- elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
- SELFREFRESH_MODE_xilinx11 <= '1';
- elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
- SELFREFRESH_MODE_xilinx11 <= '0';
- end if;
- end if;
- end process;
-
---********************************************
---Comparitor for Dynamic Calibration circuit
---********************************************
- Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
- Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
-
---*********************************************************************************************
---Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
---*********************************************************************************************
- process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RST_reg = '1') then
- count <= "000000";
- elsif (counter_en = '1') then
- count <= count + "000001";
- else
- count <= "000000";
- end if;
- end if;
- end process;
-
---*********************************************************************************************
--- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
---*********************************************************************************************
- process (UI_CLK, MCB_UODATAVALID)
- begin
- if(MCB_UODATAVALID = '1') then
- MCB_UODATAVALID_U <= '1';
- elsif(UI_CLK'event and UI_CLK = '1') then
- MCB_UODATAVALID_U <= MCB_UODATAVALID;
- end if;
- end process;
-
---**************************************************************************************************************
---Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
---**************************************************************************************************************
- process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
- begin
- case Active_IODRP is
- when RZQ =>
- RZQ_IODRP_CS <= IODRP_CS;
- ZIO_IODRP_CS <= '0';
- IODRP_SDO <= RZQ_IODRP_SDO;
- when ZIO =>
- RZQ_IODRP_CS <= '0';
- ZIO_IODRP_CS <= IODRP_CS;
- IODRP_SDO <= ZIO_IODRP_SDO;
- when MCB_PORT =>
- RZQ_IODRP_CS <= '0';
- ZIO_IODRP_CS <= '0';
- IODRP_SDO <= '0';
- when others =>
- RZQ_IODRP_CS <= '0';
- ZIO_IODRP_CS <= '0';
- IODRP_SDO <= '0';
- end case;
- end process;
-
---******************************************************************
---State Machine's Always block / Case statement for Next State Logic
---
---The WAIT1,2,etc states were required after every state where the
---DRP controller was used to do a write to the IODRPs - this is because
---there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
---sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
---soley for the purpose of reducing power, particularly on RZQ as
---that pin is expected to have a permanent external resistor to gnd.
---******************************************************************
- NEXT_STATE_LOGIC: process (UI_CLK)
- begin
- if (UI_CLK'event and UI_CLK = '1') then
- if (RST_reg = '1') then -- Synchronous reset
- MCB_CMD_VALID <= '0';
- MCB_UIADDR_xilinx3 <= "00000"; -- take control of UI/UO port
- MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
- MCB_UIDONECAL_xilinx7 <= '0';
- MCB_USE_BKST <= '0';
- MCB_UIDRPUPDATE <= '1';
- Pre_SYSRST <= '1'; -- keeps MCB in reset
- IODRPCTRLR_CMD_VALID <= '0';
- IODRPCTRLR_MEMCELL_ADDR <= NoOp;
- IODRPCTRLR_WRITE_DATA <= "00000000";
- IODRPCTRLR_R_WB <= WRITE_MODE;
- IODRPCTRLR_USE_BKST <= '0';
- P_Term <= "000000";
- N_Term <= "0000000";
- P_Term_Prev <= "000000";
- N_Term_Prev <= "0000000";
- Active_IODRP <= RZQ;
- MCB_UILDQSINC <= '0'; --no inc or dec
- MCB_UIUDQSINC <= '0'; --no inc or dec
- MCB_UILDQSDEC <= '0'; --no inc or dec
- MCB_UIUDQSDEC <= '0';
- counter_en <= '0'; --flag that the First Dynamic Calibration completed
- First_Dyn_Cal_Done <= '0';
- Max_Value_int <= "00000000";
- Max_Value_Previous <= "00000000";
- STATE <= START;
- DQS_DELAY <= "00000000";
- DQS_DELAY_INITIAL <= "00000000";
- TARGET_DQS_DELAY <= "00000000";
- LastPass_DynCal <= IN_TERM_PASS;
- First_In_Term_Done <= '0';
- MCB_UICMD <= '0';
- MCB_UICMDIN <= '0';
- MCB_UIDQCOUNT <= "0000";
- counter_inc <= "00000000";
- counter_dec <= "00000000";
- else
- counter_en <= '0';
- IODRPCTRLR_CMD_VALID <= '0';
- IODRPCTRLR_MEMCELL_ADDR <= NoOp;
- IODRPCTRLR_R_WB <= READ_MODE;
- IODRPCTRLR_USE_BKST <= '0';
- MCB_CMD_VALID <= '0'; --no inc or dec
- MCB_UILDQSINC <= '0'; --no inc or dec
- MCB_UIUDQSINC <= '0'; --no inc or dec
- MCB_UILDQSDEC <= '0'; --no inc or dec
- MCB_UIUDQSDEC <= '0';
- MCB_USE_BKST <= '0';
- MCB_UICMDIN <= '0';
- DQS_DELAY <= DQS_DELAY;
- TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
-
- case STATE is
- when START => --h00
- MCB_UICMDEN <= '1'; -- take control of UI/UO port
- MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
- P_Term <= "000000";
- N_Term <= "0000000";
- Pre_SYSRST <= '1'; -- keeps MCB in reset
- LastPass_DynCal <= IN_TERM_PASS;
- if (SKIP_IN_TERM_CAL = 1) then
- STATE <= WRITE_CALIBRATE;
- elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= LOAD_RZQ_NTERM;
- else
- STATE <= START;
- end if;
- --***************************
- -- IOB INPUT TERMINATION CAL
- --***************************
- when LOAD_RZQ_NTERM => --h01
- Active_IODRP <= RZQ;
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= NTerm;
- IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
- IODRPCTRLR_R_WB <= WRITE_MODE;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= LOAD_RZQ_NTERM;
- else
- STATE <= WAIT1;
- end if;
-
- when WAIT1 => --h02
- if (IODRPCTRLR_RDY_BUSY_N = '0') then
- STATE <= WAIT1;
- else
- STATE <= LOAD_RZQ_PTERM;
- end if;
-
- when LOAD_RZQ_PTERM => --h03
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= PTerm;
- IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
- IODRPCTRLR_R_WB <= WRITE_MODE;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= LOAD_RZQ_PTERM;
- else
- STATE <= WAIT2;
- end if;
-
- when WAIT2 => --h04
- if (IODRPCTRLR_RDY_BUSY_N = '0') then
- STATE <= WAIT2;
- elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
- STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
- else
- STATE <= INC_PTERM;
- end if;
-
- when INC_PTERM => --h05
- P_Term <= P_Term + "000001";
- STATE <= LOAD_RZQ_PTERM;
-
- when MULTIPLY_DIVIDE => -- h06
- P_Term <= Mult_Divide(("00" & P_Term),MULT,DIV)(5 downto 0);
- STATE <= LOAD_ZIO_PTERM;
-
- when LOAD_ZIO_PTERM => --h07
- Active_IODRP <= ZIO;
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= PTerm;
- IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
- IODRPCTRLR_R_WB <= WRITE_MODE;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= LOAD_ZIO_PTERM;
- else
- STATE <= WAIT3;
- end if;
-
- when WAIT3 => --h08
- if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
- STATE <= WAIT3;
- else
- STATE <= LOAD_ZIO_NTERM;
- end if;
-
- when LOAD_ZIO_NTERM => --h09
- Active_IODRP <= ZIO;
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= NTerm;
- IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
- IODRPCTRLR_R_WB <= WRITE_MODE;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= LOAD_ZIO_NTERM;
- else
- STATE <= WAIT4;
- end if;
-
- when WAIT4 => --h0A
- if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
- STATE <= WAIT4;
- elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
- if (PNSKEW = '1') then
- STATE <= SKEW;
- else
- STATE <= WAIT_FOR_START_BROADCAST;
- end if;
- else
- STATE <= INC_NTERM;
- end if;
-
- when INC_NTERM => --h0B
- N_Term <= N_Term + "0000001";
- STATE <= LOAD_ZIO_NTERM;
-
- when SKEW => -- h0C
- P_Term <= Mult_Divide(("00" & P_Term), PSKEW_MULT, PSKEW_DIV)(5 downto 0);
- N_Term <= Mult_Divide(('0' & N_Term), NSKEW_MULT, NSKEW_DIV)(6 downto 0);
- STATE <= WAIT_FOR_START_BROADCAST;
-
- when WAIT_FOR_START_BROADCAST => --h0D
- Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
- -- keeping the MCB in calibration mode
- Active_IODRP <= MCB_PORT;
- if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
- if (P_Term /= P_Term_Prev) then
- STATE <= BROADCAST_PTERM;
- P_Term_Prev <= P_Term;
- elsif (N_Term /= N_Term_Prev) then
- N_Term_Prev <= N_Term;
- STATE <= BROADCAST_NTERM;
- else
- STATE <= OFF_RZQ_PTERM;
- end if;
- else
- STATE <= WAIT_FOR_START_BROADCAST;
- end if;
-
- when BROADCAST_PTERM => --h0E
- IODRPCTRLR_MEMCELL_ADDR <= PTerm;
- IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
- IODRPCTRLR_R_WB <= WRITE_MODE;
- MCB_CMD_VALID <= '1';
- MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
- MCB_USE_BKST <= '1';
- if (MCB_RDY_BUSY_N = '1') then
- STATE <= BROADCAST_PTERM;
- else
- STATE <= WAIT5;
- end if;
-
- when WAIT5 => --h0F
- if ((not(MCB_RDY_BUSY_N)) = '1') then
- STATE <= WAIT5;
- elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
- if (MCB_UOREFRSHFLAG = '1')then
- MCB_UIDRPUPDATE <= '1';
- if (N_Term /= N_Term_Prev) then
- N_Term_Prev <= N_Term;
- STATE <= BROADCAST_NTERM;
- else
- STATE <= OFF_RZQ_PTERM;
- end if;
- else
- STATE <= WAIT5; -- wait for a Refresh cycle
- end if;
- else
- N_Term_Prev <= N_Term;
- STATE <= BROADCAST_NTERM;
- end if;
-
- when BROADCAST_NTERM => -- h10
- IODRPCTRLR_MEMCELL_ADDR <= NTerm;
- IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
- IODRPCTRLR_R_WB <= WRITE_MODE;
- MCB_CMD_VALID <= '1';
- MCB_USE_BKST <= '1';
- MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
- if (MCB_RDY_BUSY_N = '1') then
- STATE <= BROADCAST_NTERM;
- else
- STATE <= WAIT6;
- end if;
-
- when WAIT6 => -- h11
- if (MCB_RDY_BUSY_N = '0') then
- STATE <= WAIT6;
- elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
- if (MCB_UOREFRSHFLAG = '1')then
- MCB_UIDRPUPDATE <= '1';
- STATE <= OFF_RZQ_PTERM;
- else
- STATE <= WAIT6; -- wait for a Refresh cycle
- end if;
- else
- STATE <= OFF_RZQ_PTERM;
- end if;
-
- when OFF_RZQ_PTERM => -- h12
- Active_IODRP <= RZQ;
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= PTerm;
- IODRPCTRLR_WRITE_DATA <= "00000000";
- IODRPCTRLR_R_WB <= WRITE_MODE;
- P_Term <= "000000";
- N_Term <= "0000000";
- MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= OFF_RZQ_PTERM;
- else
- STATE <= WAIT7;
- end if;
-
- when WAIT7 => -- h13
- if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
- STATE <= WAIT7;
- else
- STATE <= OFF_ZIO_NTERM;
- end if;
-
- when OFF_ZIO_NTERM => -- h14
- Active_IODRP <= ZIO;
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= NTerm;
- IODRPCTRLR_WRITE_DATA <= "00000000";
- IODRPCTRLR_R_WB <= WRITE_MODE;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= OFF_ZIO_NTERM;
- else
- STATE <= WAIT8;
- end if;
-
- when WAIT8 => -- h15
- if (IODRPCTRLR_RDY_BUSY_N = '0') then
- STATE <= WAIT8;
- else
- if (First_In_Term_Done = '1') then
- STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
- else
- STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
- end if;
- end if;
-
- when RST_DELAY => -- h16
- MCB_UICMDEN <= '0'; -- release control of UI/UO port
- if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
- STATE <= RST_DELAY;
- else
- STATE <= START_DYN_CAL_PRE;
- end if;
-
---***************************
---DYNAMIC CALIBRATION PORTION
---***************************
- when START_DYN_CAL_PRE => -- h17
- LastPass_DynCal <= IN_TERM_PASS;
- MCB_UICMDEN <= '0'; -- release UICMDEN
- MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
- Pre_SYSRST <= '1'; -- SYSRST pulse
- if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
- STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
- else
- STATE <= WAIT_FOR_UODONE;
- end if;
-
- when WAIT_FOR_UODONE => -- h18
- Pre_SYSRST <= '0'; -- SYSRST pulse
- if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
- MCB_UICMDEN <= '1'; -- grab UICMDEN
- DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
- STATE <= LDQS_WRITE_POS_INDELAY;
- else
- STATE <= WAIT_FOR_UODONE;
- end if;
-
- when LDQS_WRITE_POS_INDELAY => -- h19
- IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
- IODRPCTRLR_R_WB <= WRITE_MODE;
- IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
- MCB_UIADDR_xilinx3 <= IOI_LDQS_CLK;
- MCB_CMD_VALID <= '1';
- if (MCB_RDY_BUSY_N = '1') then
- STATE <= LDQS_WRITE_POS_INDELAY;
- else
- STATE <= LDQS_WAIT1;
- end if;
-
- when LDQS_WAIT1 => -- h1A
- if (MCB_RDY_BUSY_N = '0')then
- STATE <= LDQS_WAIT1;
- else
- STATE <= LDQS_WRITE_NEG_INDELAY;
- end if;
-
- when LDQS_WRITE_NEG_INDELAY => -- h1B
- IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
- IODRPCTRLR_R_WB <= WRITE_MODE;
- IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
- MCB_UIADDR_xilinx3 <= IOI_LDQS_CLK;
- MCB_CMD_VALID <= '1';
- if (MCB_RDY_BUSY_N = '1')then
- STATE <= LDQS_WRITE_NEG_INDELAY;
- else
- STATE <= LDQS_WAIT2;
- end if;
-
- when LDQS_WAIT2 => -- 7'h1C
- if(MCB_RDY_BUSY_N = '0')then
- STATE <= LDQS_WAIT2;
- else
- STATE <= UDQS_WRITE_POS_INDELAY;
- end if;
-
- when UDQS_WRITE_POS_INDELAY => -- 7'h1D
- IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
- IODRPCTRLR_R_WB <= WRITE_MODE;
- IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
- MCB_UIADDR_xilinx3 <= IOI_UDQS_CLK;
- MCB_CMD_VALID <= '1';
- if (MCB_RDY_BUSY_N = '1')then
- STATE <= UDQS_WRITE_POS_INDELAY;
- else
- STATE <= UDQS_WAIT1;
- end if;
-
- when UDQS_WAIT1 => -- 7'h1E
- if (MCB_RDY_BUSY_N = '0')then
- STATE <= UDQS_WAIT1;
- else
- STATE <= UDQS_WRITE_NEG_INDELAY;
- end if;
-
- when UDQS_WRITE_NEG_INDELAY => -- 7'h1F
- IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
- IODRPCTRLR_R_WB <= WRITE_MODE;
- IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
- MCB_UIADDR_xilinx3 <= IOI_UDQS_CLK;
- MCB_CMD_VALID <= '1';
- if (MCB_RDY_BUSY_N = '1')then
- STATE <= UDQS_WRITE_NEG_INDELAY;
- else
- STATE <= UDQS_WAIT2;
- end if;
-
- when UDQS_WAIT2 => -- 7'h20
- if (MCB_RDY_BUSY_N = '0')then
- STATE <= UDQS_WAIT2;
- else
- DQS_DELAY <= DQS_DELAY_INITIAL;
- TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
- STATE <= START_DYN_CAL;
- end if;
-
- when START_DYN_CAL => -- h21
- Pre_SYSRST <= '0'; -- SYSRST not driven
- counter_inc <= (others => '0');
- counter_dec <= (others => '0');
- if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
- STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
- elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
- --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
- -- Alternate between Dynamic Input Termination and Dynamic Tuning routines
- if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
- LastPass_DynCal <= IN_TERM_PASS;
- STATE <= LOAD_RZQ_NTERM;
- else
- LastPass_DynCal <= DYN_CAL_PASS;
- STATE <= WRITE_CALIBRATE;
- end if;
- else
- STATE <= START_DYN_CAL;
- end if;
-
- when WRITE_CALIBRATE => -- h22
- Pre_SYSRST <= '0';
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
- IODRPCTRLR_WRITE_DATA <= "00100000";
- IODRPCTRLR_R_WB <= WRITE_MODE;
- Active_IODRP <= RZQ;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= WRITE_CALIBRATE;
- else
- STATE <= WAIT9;
- end if;
-
- when WAIT9 => -- h23
- counter_en <= '1';
- if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
- STATE <= WAIT9;
- else
- STATE <= READ_MAX_VALUE;
- end if;
-
- when READ_MAX_VALUE => -- h24
- IODRPCTRLR_CMD_VALID <= '1';
- IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
- IODRPCTRLR_R_WB <= READ_MODE;
- Max_Value_Previous <= Max_Value_int;
- if (IODRPCTRLR_RDY_BUSY_N = '1') then
- STATE <= READ_MAX_VALUE;
- else
- STATE <= WAIT10;
- end if;
-
- when WAIT10 => -- h25
- if (IODRPCTRLR_RDY_BUSY_N = '0') then
- STATE <= WAIT10;
- else
- Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
- if (First_In_Term_Done = '0') then
- STATE <= RST_DELAY;
- First_In_Term_Done <= '1';
- else
- STATE <= ANALYZE_MAX_VALUE;
- end if;
- end if;
-
- when ANALYZE_MAX_VALUE => -- h26 only do a Inc or Dec during a REFRESH cycle.
- if (First_Dyn_Cal_Done = '0')then
- STATE <= FIRST_DYN_CAL;
- elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
- STATE <= DECREMENT; -- May need to Decrement
- TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
- -- DQS_COUNT_VIRTUAL updated (could be negative value)
- elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
- STATE <= INCREMENT; -- May need to Increment
- TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
- else
- Max_Value_int <= Max_Value_Previous;
- STATE <= START_DYN_CAL;
- end if;
-
- when FIRST_DYN_CAL => -- h27
- First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
- STATE <= START_DYN_CAL;
-
- when INCREMENT => -- h28
- STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
- MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
- MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
- MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
- MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
- case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
- when "101" =>
- counter_inc <= counter_inc + '1';
- STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
- if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
- -- if not at the upper limit yet, and you've waited 4 clks, increment
- MCB_UILDQSINC <= '1';
- MCB_UIUDQSINC <= '1';
- DQS_DELAY <= DQS_DELAY + '1';
- end if;
- when "100" =>
- if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
- STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
- end if;
- when others =>
- STATE <= START_DYN_CAL;
- end case;
-
- when DECREMENT => -- h29
- STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
- MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
- MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
- MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
- MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
- if (DQS_DELAY /= "00000000") then
- case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
- when "011" =>
- counter_dec <= counter_dec + '1';
- STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
- if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
- -- if not at the lower limit, and you've waited 4 clks, decrement
- MCB_UILDQSDEC <= '1'; -- decrement
- MCB_UIUDQSDEC <= '1'; -- decrement
- DQS_DELAY <= DQS_DELAY - '1'; -- SBS
- end if;
- when "010" =>
- if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
- STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
- end if;
- when others =>
- STATE <= START_DYN_CAL;
- end case;
- end if;
-
- when DONE => -- h2A
- Pre_SYSRST <= '0'; -- SYSRST cleared
- MCB_UICMDEN <= '0'; -- release UICMDEN
- STATE <= DONE;
-
- when others =>
- MCB_UICMDEN <= '0'; -- release UICMDEN
- MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
- Pre_SYSRST <= '0'; -- SYSRST not driven
- IODRPCTRLR_CMD_VALID <= '0';
- IODRPCTRLR_MEMCELL_ADDR <= "00000000";
- IODRPCTRLR_WRITE_DATA <= "00000000";
- IODRPCTRLR_R_WB <= '0';
- IODRPCTRLR_USE_BKST <= '0';
- P_Term <= "000000";
- N_Term <= "0000000";
- Active_IODRP <= ZIO;
- Max_Value_Previous <= "00000000";
- MCB_UILDQSINC <= '0'; -- no inc or dec
- MCB_UIUDQSINC <= '0'; -- no inc or dec
- MCB_UILDQSDEC <= '0'; -- no inc or dec
- MCB_UIUDQSDEC <= '0'; -- no inc or dec
- counter_en <= '0';
- First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
- Max_Value_int <= Max_Value_int;
- STATE <= START;
- end case;
- end if;
- end if;
- end process;
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd (nonexistent)
@@ -1,372 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
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--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: iodrp_controller.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $
--- \ \ / \ Date Created: Mon Feb 9 2009
--- \___\/\___\
---
---Device: Spartan6
---Design Name: DDR/DDR2/DDR3/LPDDR
---Purpose: Xilinx reference design for IODRP controller for v0.9 device
---
---Reference:
---
--- Revision: Date: Comment
--- 1.0: 02/06/09: Initial version for MIG wrapper.
--- 1.1: 02/01/09: updates to indentations.
--- 1.2: 02/12/09: changed non-blocking assignments to blocking ones
--- for state machine always block. Also, assigned
--- intial value to load_shift_n to avoid latch
--- End Revision
---*******************************************************************************
-
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
-
-entity iodrp_controller is
- --output to IODRP SDI pin
- --input from IODRP SDO pin
-
- -- Register where memcell_address is captured during the READY state
- -- Register which stores the write data until it is ready to be shifted out
- -- The shift register which shifts out SDO and shifts in SDI.
- -- This register is loaded before the address or data phase, but continues
- -- to shift for a writeback of read data
- -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
- -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
- -- The counter for which bit is being shifted during address or data phase
- -- This is set after the first address phase has executed
-
- -- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
-
- -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
- -- added so that DRP_SDI output is only active when DRP_CS is active
-
- port (
- memcell_address : in std_logic_vector(7 downto 0);
- write_data : in std_logic_vector(7 downto 0);
- read_data : out std_logic_vector(7 downto 0);
- rd_not_write : in std_logic;
- cmd_valid : in std_logic;
- rdy_busy_n : out std_logic;
- use_broadcast : in std_logic;
- sync_rst : in std_logic;
- DRP_CLK : in std_logic;
- DRP_CS : out std_logic;
- DRP_SDI : out std_logic;
- DRP_ADD : out std_logic;
- DRP_BKST : out std_logic;
- DRP_SDO : in std_logic
- );
-end entity iodrp_controller;
-
-architecture trans of iodrp_controller is
-
-
- constant READY : std_logic_vector(2 downto 0) := "000";
- constant DECIDE : std_logic_vector(2 downto 0) := "001";
- constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010";
- constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011";
- constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100";
- constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101";
- constant DATA_PHASE : std_logic_vector(2 downto 0) := "110";
- constant ALMOST_READY : std_logic_vector(2 downto 0) := "111";
-
- constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
- constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
- constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
- constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
- constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
- constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
- constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
- constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
- constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
- constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
- constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
- constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
- constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
- constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
- constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
- constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
- constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
- constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
- constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
- constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
-
-
-
-
- signal memcell_addr_reg : std_logic_vector(7 downto 0);
- signal data_reg : std_logic_vector(7 downto 0);
- signal shift_through_reg : std_logic_vector(7 downto 0);
- signal load_shift_n : std_logic;
- signal addr_data_sel_n : std_logic;
- signal bit_cnt : std_logic_vector(2 downto 0);
- signal rd_not_write_reg : std_logic;
- signal AddressPhase : std_logic;
- signal capture_read_data : std_logic;
- signal state : std_logic_vector(2 downto 0);
- signal nextstate : std_logic_vector(2 downto 0);
- signal data_out_mux : std_logic_vector(7 downto 0);
- signal DRP_SDI_pre : std_logic;
-
- signal ALMOST_READY_ST : std_logic;
- signal ADDR_PHASE_ST : std_logic;
- signal BIT_CNT7 : std_logic;
- signal ADDR_PHASE_ST1 : std_logic;
- signal DATA_PHASE_ST : std_logic;
-
- signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-begin
- --synthesis translate_off
-
--- process (state)
--- begin
--- case state is
--- when READY =>
--- state_ascii <= "READY";
--- when DECIDE =>
--- state_ascii <= "DECIDE";
--- when ADDR_PHASE =>
--- state_ascii <= "ADDR_PHASE";
--- when ADDR_TO_DATA_GAP =>
--- state_ascii <= "ADDR_TO_DATA_GAP";
--- when ADDR_TO_DATA_GAP2 =>
--- state_ascii <= "ADDR_TO_DATA_GAP2";
--- when ADDR_TO_DATA_GAP3 =>
--- state_ascii <= "ADDR_TO_DATA_GAP3";
--- when DATA_PHASE =>
--- state_ascii <= "DATA_PHASE";
--- when ALMOST_READY => -- case(state)
--- state_ascii <= "ALMOST_READY";
--- when others =>
--- null;
--- end case;
--- end process;
-
- --synthesis translate_on
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (state = READY) then
- memcell_addr_reg <= memcell_address;
- data_reg <= write_data;
- rd_not_write_reg <= rd_not_write;
- end if;
- end if;
- end process;
-
-
- rdy_busy_n <= '1' when (state = READY) else '0';
-
- data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
- data_reg;
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- shift_through_reg <= "00000000";
- else
- if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
- shift_through_reg <= data_out_mux;
- else
- shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
- end if;
- end if;
- end if;
- end process;
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
- bit_cnt <= bit_cnt + "001";
- else
- bit_cnt <= "000";
- end if;
- end if;
- end process;
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- -- capture_read_data <= 1'b0;
- read_data <= "00000000";
- else
- -- capture_read_data <= (state == DATA_PHASE);
- -- if(capture_read_data)
- if (state = ALMOST_READY) then
- -- else
- -- read_data <= read_data;
- read_data <= shift_through_reg;
- end if;
- end if;
- end if;
- end process;
-
- ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
- ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
- BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- AddressPhase <= '0';
- else
- if (AddressPhase = '1') then
- -- Keep it set until we finish the cycle
- AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
- else
- -- set the address phase when ever we finish the address phase
- AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
- end if;
- end if;
- end if;
- end process;
-
-ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
-DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- DRP_ADD <= ADDR_PHASE_ST1;
- DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
- if (state = READY) then
- DRP_BKST <= use_broadcast;
- end if;
- end if;
- end process;
-
-
- -- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
- -- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
- DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data
-
- process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
- begin
- addr_data_sel_n <= '0';
- load_shift_n <= '0';
- case state is
- when READY =>
- if (cmd_valid = '1') then
- nextstate <= DECIDE;
- else
- nextstate <= READY;
- end if;
- when DECIDE =>
- load_shift_n <= '1';
- addr_data_sel_n <= '1';
- nextstate <= ADDR_PHASE;
- -- After the second pass go to end of statemachine
- -- execute a second address phase for the read access.
- when ADDR_PHASE =>
- if (BIT_CNT7 = '1') then
- if (rd_not_write_reg = '1') then
- if (AddressPhase = '1') then
- nextstate <= ALMOST_READY;
- else
- nextstate <= DECIDE;
- end if;
- else
- nextstate <= ADDR_TO_DATA_GAP;
- end if;
- else
- nextstate <= ADDR_PHASE;
- end if;
- when ADDR_TO_DATA_GAP =>
- load_shift_n <= '1';
- nextstate <= ADDR_TO_DATA_GAP2;
- when ADDR_TO_DATA_GAP2 =>
- load_shift_n <= '1';
- nextstate <= ADDR_TO_DATA_GAP3;
- when ADDR_TO_DATA_GAP3 =>
- load_shift_n <= '1';
- nextstate <= DATA_PHASE;
- when DATA_PHASE =>
- if (BIT_CNT7 = '1') then
- nextstate <= ALMOST_READY;
- else
- nextstate <= DATA_PHASE;
- end if;
- when ALMOST_READY =>
- nextstate <= READY;
- when others =>
- nextstate <= READY;
- end case;
- end process;
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- state <= READY;
- else
- state <= nextstate;
- end if;
- end if;
- end process;
-
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/mem0.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/mem0.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/mem0.vhd (nonexistent)
@@ -1,832 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : mem0.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/05/18 11:08:59 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
---Device : Spartan-6
---Design Name : DDR/DDR2/DDR3/LPDDR
---Purpose : This is the design top level. which instantiates top wrapper,
--- test bench top and infrastructure modules.
---Reference :
---Revision History :
---*****************************************************************************
-library ieee;
-use ieee.std_logic_1164.all;
-entity mem0 is
-generic
- (
- C3_P0_MASK_SIZE : integer := 4;
- C3_P0_DATA_PORT_SIZE : integer := 32;
- C3_P1_MASK_SIZE : integer := 4;
- C3_P1_DATA_PORT_SIZE : integer := 32;
- C3_MEMCLK_PERIOD : integer := 5000;
- C3_RST_ACT_LOW : integer := 0;
- C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
- C3_CALIB_SOFT_IP : string := "TRUE";
- C3_SIMULATION : string := "FALSE";
- DEBUG_EN : integer := 0;
- C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
- C3_NUM_DQ_PINS : integer := 16;
- C3_MEM_ADDR_WIDTH : integer := 13;
- C3_MEM_BANKADDR_WIDTH : integer := 2
- );
-
- port
- (
-
- mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
- mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
- mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
- mcb3_dram_cke : out std_logic;
- mcb3_dram_ras_n : out std_logic;
- mcb3_dram_cas_n : out std_logic;
- mcb3_dram_we_n : out std_logic;
- mcb3_dram_dm : out std_logic;
- mcb3_dram_udqs : inout std_logic;
- mcb3_rzq : inout std_logic;
- mcb3_dram_udm : out std_logic;
- c3_sys_clk : in std_logic;
- c3_sys_rst_n : in std_logic;
- c3_calib_done : out std_logic;
- c3_clk0 : out std_logic;
- c3_rst0 : out std_logic;
- mcb3_dram_dqs : inout std_logic;
- mcb3_dram_ck : out std_logic;
- mcb3_dram_ck_n : out std_logic;
- c3_p0_cmd_clk : in std_logic;
- c3_p0_cmd_en : in std_logic;
- c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p0_cmd_empty : out std_logic;
- c3_p0_cmd_full : out std_logic;
- c3_p0_wr_clk : in std_logic;
- c3_p0_wr_en : in std_logic;
- c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
- c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- c3_p0_wr_full : out std_logic;
- c3_p0_wr_empty : out std_logic;
- c3_p0_wr_count : out std_logic_vector(6 downto 0);
- c3_p0_wr_underrun : out std_logic;
- c3_p0_wr_error : out std_logic;
- c3_p0_rd_clk : in std_logic;
- c3_p0_rd_en : in std_logic;
- c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
- c3_p0_rd_full : out std_logic;
- c3_p0_rd_empty : out std_logic;
- c3_p0_rd_count : out std_logic_vector(6 downto 0);
- c3_p0_rd_overflow : out std_logic;
- c3_p0_rd_error : out std_logic;
- c3_p1_cmd_clk : in std_logic;
- c3_p1_cmd_en : in std_logic;
- c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p1_cmd_empty : out std_logic;
- c3_p1_cmd_full : out std_logic;
- c3_p1_wr_clk : in std_logic;
- c3_p1_wr_en : in std_logic;
- c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
- c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
- c3_p1_wr_full : out std_logic;
- c3_p1_wr_empty : out std_logic;
- c3_p1_wr_count : out std_logic_vector(6 downto 0);
- c3_p1_wr_underrun : out std_logic;
- c3_p1_wr_error : out std_logic;
- c3_p1_rd_clk : in std_logic;
- c3_p1_rd_en : in std_logic;
- c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
- c3_p1_rd_full : out std_logic;
- c3_p1_rd_empty : out std_logic;
- c3_p1_rd_count : out std_logic_vector(6 downto 0);
- c3_p1_rd_overflow : out std_logic;
- c3_p1_rd_error : out std_logic;
- c3_p2_cmd_clk : in std_logic;
- c3_p2_cmd_en : in std_logic;
- c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p2_cmd_empty : out std_logic;
- c3_p2_cmd_full : out std_logic;
- c3_p2_wr_clk : in std_logic;
- c3_p2_wr_en : in std_logic;
- c3_p2_wr_mask : in std_logic_vector(3 downto 0);
- c3_p2_wr_data : in std_logic_vector(31 downto 0);
- c3_p2_wr_full : out std_logic;
- c3_p2_wr_empty : out std_logic;
- c3_p2_wr_count : out std_logic_vector(6 downto 0);
- c3_p2_wr_underrun : out std_logic;
- c3_p2_wr_error : out std_logic;
- c3_p3_cmd_clk : in std_logic;
- c3_p3_cmd_en : in std_logic;
- c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p3_cmd_empty : out std_logic;
- c3_p3_cmd_full : out std_logic;
- c3_p3_rd_clk : in std_logic;
- c3_p3_rd_en : in std_logic;
- c3_p3_rd_data : out std_logic_vector(31 downto 0);
- c3_p3_rd_full : out std_logic;
- c3_p3_rd_empty : out std_logic;
- c3_p3_rd_count : out std_logic_vector(6 downto 0);
- c3_p3_rd_overflow : out std_logic;
- c3_p3_rd_error : out std_logic;
- c3_p4_cmd_clk : in std_logic;
- c3_p4_cmd_en : in std_logic;
- c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p4_cmd_empty : out std_logic;
- c3_p4_cmd_full : out std_logic;
- c3_p4_wr_clk : in std_logic;
- c3_p4_wr_en : in std_logic;
- c3_p4_wr_mask : in std_logic_vector(3 downto 0);
- c3_p4_wr_data : in std_logic_vector(31 downto 0);
- c3_p4_wr_full : out std_logic;
- c3_p4_wr_empty : out std_logic;
- c3_p4_wr_count : out std_logic_vector(6 downto 0);
- c3_p4_wr_underrun : out std_logic;
- c3_p4_wr_error : out std_logic;
- c3_p5_cmd_clk : in std_logic;
- c3_p5_cmd_en : in std_logic;
- c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
- c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
- c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
- c3_p5_cmd_empty : out std_logic;
- c3_p5_cmd_full : out std_logic;
- c3_p5_rd_clk : in std_logic;
- c3_p5_rd_en : in std_logic;
- c3_p5_rd_data : out std_logic_vector(31 downto 0);
- c3_p5_rd_full : out std_logic;
- c3_p5_rd_empty : out std_logic;
- c3_p5_rd_count : out std_logic_vector(6 downto 0);
- c3_p5_rd_overflow : out std_logic;
- c3_p5_rd_error : out std_logic
- );
-end mem0;
-
-architecture arc of mem0 is
-
-
-component memc3_infrastructure is
- generic (
- C_MEMCLK_PERIOD : integer;
- C_RST_ACT_LOW : integer;
- C_INPUT_CLK_TYPE : string;
- C_CLKOUT0_DIVIDE : integer;
- C_CLKOUT1_DIVIDE : integer;
- C_CLKOUT2_DIVIDE : integer;
- C_CLKOUT3_DIVIDE : integer;
- C_CLKFBOUT_MULT : integer;
- C_DIVCLK_DIVIDE : integer
-
- );
- port (
- sys_clk_p : in std_logic;
- sys_clk_n : in std_logic;
- sys_clk : in std_logic;
- sys_rst_n : in std_logic;
- clk0 : out std_logic;
- rst0 : out std_logic;
- async_rst : out std_logic;
- sysclk_2x : out std_logic;
- sysclk_2x_180 : out std_logic;
- pll_ce_0 : out std_logic;
- pll_ce_90 : out std_logic;
- pll_lock : out std_logic;
- mcb_drp_clk : out std_logic
-
- );
- end component;
-
-
-component memc3_wrapper is
- generic (
- C_MEMCLK_PERIOD : integer;
- C_CALIB_SOFT_IP : string;
- C_SIMULATION : string;
- C_P0_MASK_SIZE : integer;
- C_P0_DATA_PORT_SIZE : integer;
- C_P1_MASK_SIZE : integer;
- C_P1_DATA_PORT_SIZE : integer;
- C_ARB_NUM_TIME_SLOTS : integer;
- C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
- C_MEM_TRAS : integer;
- C_MEM_TRCD : integer;
- C_MEM_TREFI : integer;
- C_MEM_TRFC : integer;
- C_MEM_TRP : integer;
- C_MEM_TWR : integer;
- C_MEM_TRTP : integer;
- C_MEM_TWTR : integer;
- C_MEM_ADDR_ORDER : string;
- C_NUM_DQ_PINS : integer;
- C_MEM_TYPE : string;
- C_MEM_DENSITY : string;
- C_MEM_BURST_LEN : integer;
- C_MEM_CAS_LATENCY : integer;
- C_MEM_ADDR_WIDTH : integer;
- C_MEM_BANKADDR_WIDTH : integer;
- C_MEM_NUM_COL_BITS : integer;
- C_MEM_DDR1_2_ODS : string;
- C_MEM_DDR2_RTT : string;
- C_MEM_DDR2_DIFF_DQS_EN : string;
- C_MEM_DDR2_3_PA_SR : string;
- C_MEM_DDR2_3_HIGH_TEMP_SR : string;
- C_MEM_DDR3_CAS_LATENCY : integer;
- C_MEM_DDR3_ODS : string;
- C_MEM_DDR3_RTT : string;
- C_MEM_DDR3_CAS_WR_LATENCY : integer;
- C_MEM_DDR3_AUTO_SR : string;
- C_MEM_DDR3_DYN_WRT_ODT : string;
- C_MEM_MOBILE_PA_SR : string;
- C_MEM_MDDR_ODS : string;
- C_MC_CALIB_BYPASS : string;
- C_MC_CALIBRATION_MODE : string;
- C_MC_CALIBRATION_DELAY : string;
- C_SKIP_IN_TERM_CAL : integer;
- C_SKIP_DYNAMIC_CAL : integer;
- C_LDQSP_TAP_DELAY_VAL : integer;
- C_LDQSN_TAP_DELAY_VAL : integer;
- C_UDQSP_TAP_DELAY_VAL : integer;
- C_UDQSN_TAP_DELAY_VAL : integer;
- C_DQ0_TAP_DELAY_VAL : integer;
- C_DQ1_TAP_DELAY_VAL : integer;
- C_DQ2_TAP_DELAY_VAL : integer;
- C_DQ3_TAP_DELAY_VAL : integer;
- C_DQ4_TAP_DELAY_VAL : integer;
- C_DQ5_TAP_DELAY_VAL : integer;
- C_DQ6_TAP_DELAY_VAL : integer;
- C_DQ7_TAP_DELAY_VAL : integer;
- C_DQ8_TAP_DELAY_VAL : integer;
- C_DQ9_TAP_DELAY_VAL : integer;
- C_DQ10_TAP_DELAY_VAL : integer;
- C_DQ11_TAP_DELAY_VAL : integer;
- C_DQ12_TAP_DELAY_VAL : integer;
- C_DQ13_TAP_DELAY_VAL : integer;
- C_DQ14_TAP_DELAY_VAL : integer;
- C_DQ15_TAP_DELAY_VAL : integer
- );
- port (
- mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
- mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
- mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
- mcb3_dram_cke : out std_logic;
- mcb3_dram_ras_n : out std_logic;
- mcb3_dram_cas_n : out std_logic;
- mcb3_dram_we_n : out std_logic;
- mcb3_dram_dm : out std_logic;
- mcb3_dram_udqs : inout std_logic;
- mcb3_rzq : inout std_logic;
- mcb3_dram_udm : out std_logic;
- calib_done : out std_logic;
- async_rst : in std_logic;
- sysclk_2x : in std_logic;
- sysclk_2x_180 : in std_logic;
- pll_ce_0 : in std_logic;
- pll_ce_90 : in std_logic;
- pll_lock : in std_logic;
- mcb_drp_clk : in std_logic;
- mcb3_dram_dqs : inout std_logic;
- mcb3_dram_ck : out std_logic;
- mcb3_dram_ck_n : out std_logic;
- p0_cmd_clk : in std_logic;
- p0_cmd_en : in std_logic;
- p0_cmd_instr : in std_logic_vector(2 downto 0);
- p0_cmd_bl : in std_logic_vector(5 downto 0);
- p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p0_cmd_empty : out std_logic;
- p0_cmd_full : out std_logic;
- p0_wr_clk : in std_logic;
- p0_wr_en : in std_logic;
- p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
- p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_wr_full : out std_logic;
- p0_wr_empty : out std_logic;
- p0_wr_count : out std_logic_vector(6 downto 0);
- p0_wr_underrun : out std_logic;
- p0_wr_error : out std_logic;
- p0_rd_clk : in std_logic;
- p0_rd_en : in std_logic;
- p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_rd_full : out std_logic;
- p0_rd_empty : out std_logic;
- p0_rd_count : out std_logic_vector(6 downto 0);
- p0_rd_overflow : out std_logic;
- p0_rd_error : out std_logic;
- p1_cmd_clk : in std_logic;
- p1_cmd_en : in std_logic;
- p1_cmd_instr : in std_logic_vector(2 downto 0);
- p1_cmd_bl : in std_logic_vector(5 downto 0);
- p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p1_cmd_empty : out std_logic;
- p1_cmd_full : out std_logic;
- p1_wr_clk : in std_logic;
- p1_wr_en : in std_logic;
- p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
- p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_wr_full : out std_logic;
- p1_wr_empty : out std_logic;
- p1_wr_count : out std_logic_vector(6 downto 0);
- p1_wr_underrun : out std_logic;
- p1_wr_error : out std_logic;
- p1_rd_clk : in std_logic;
- p1_rd_en : in std_logic;
- p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_rd_full : out std_logic;
- p1_rd_empty : out std_logic;
- p1_rd_count : out std_logic_vector(6 downto 0);
- p1_rd_overflow : out std_logic;
- p1_rd_error : out std_logic;
- p2_cmd_clk : in std_logic;
- p2_cmd_en : in std_logic;
- p2_cmd_instr : in std_logic_vector(2 downto 0);
- p2_cmd_bl : in std_logic_vector(5 downto 0);
- p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p2_cmd_empty : out std_logic;
- p2_cmd_full : out std_logic;
- p2_wr_clk : in std_logic;
- p2_wr_en : in std_logic;
- p2_wr_mask : in std_logic_vector(3 downto 0);
- p2_wr_data : in std_logic_vector(31 downto 0);
- p2_wr_full : out std_logic;
- p2_wr_empty : out std_logic;
- p2_wr_count : out std_logic_vector(6 downto 0);
- p2_wr_underrun : out std_logic;
- p2_wr_error : out std_logic;
- p3_cmd_clk : in std_logic;
- p3_cmd_en : in std_logic;
- p3_cmd_instr : in std_logic_vector(2 downto 0);
- p3_cmd_bl : in std_logic_vector(5 downto 0);
- p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p3_cmd_empty : out std_logic;
- p3_cmd_full : out std_logic;
- p3_rd_clk : in std_logic;
- p3_rd_en : in std_logic;
- p3_rd_data : out std_logic_vector(31 downto 0);
- p3_rd_full : out std_logic;
- p3_rd_empty : out std_logic;
- p3_rd_count : out std_logic_vector(6 downto 0);
- p3_rd_overflow : out std_logic;
- p3_rd_error : out std_logic;
- p4_cmd_clk : in std_logic;
- p4_cmd_en : in std_logic;
- p4_cmd_instr : in std_logic_vector(2 downto 0);
- p4_cmd_bl : in std_logic_vector(5 downto 0);
- p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p4_cmd_empty : out std_logic;
- p4_cmd_full : out std_logic;
- p4_wr_clk : in std_logic;
- p4_wr_en : in std_logic;
- p4_wr_mask : in std_logic_vector(3 downto 0);
- p4_wr_data : in std_logic_vector(31 downto 0);
- p4_wr_full : out std_logic;
- p4_wr_empty : out std_logic;
- p4_wr_count : out std_logic_vector(6 downto 0);
- p4_wr_underrun : out std_logic;
- p4_wr_error : out std_logic;
- p5_cmd_clk : in std_logic;
- p5_cmd_en : in std_logic;
- p5_cmd_instr : in std_logic_vector(2 downto 0);
- p5_cmd_bl : in std_logic_vector(5 downto 0);
- p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p5_cmd_empty : out std_logic;
- p5_cmd_full : out std_logic;
- p5_rd_clk : in std_logic;
- p5_rd_en : in std_logic;
- p5_rd_data : out std_logic_vector(31 downto 0);
- p5_rd_full : out std_logic;
- p5_rd_empty : out std_logic;
- p5_rd_count : out std_logic_vector(6 downto 0);
- p5_rd_overflow : out std_logic;
- p5_rd_error : out std_logic;
- selfrefresh_enter : in std_logic;
- selfrefresh_mode : out std_logic
-
- );
- end component;
-
-
-
-
-
-
- constant C3_CLKOUT0_DIVIDE : integer := 2;
- constant C3_CLKOUT1_DIVIDE : integer := 2;
- constant C3_CLKOUT2_DIVIDE : integer := 16;
- constant C3_CLKOUT3_DIVIDE : integer := 8;
- constant C3_CLKFBOUT_MULT : integer := 4;
- constant C3_DIVCLK_DIVIDE : integer := 1;
- constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
- constant C3_ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := o"012345";
- constant C3_ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := o"123450";
- constant C3_ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := o"234501";
- constant C3_ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := o"345012";
- constant C3_ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := o"450123";
- constant C3_ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := o"501234";
- constant C3_ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := o"012345";
- constant C3_ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := o"123450";
- constant C3_ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := o"234501";
- constant C3_ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := o"345012";
- constant C3_ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := o"450123";
- constant C3_ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := o"501234";
- constant C3_MEM_TRAS : integer := 40000;
- constant C3_MEM_TRCD : integer := 15000;
- constant C3_MEM_TREFI : integer := 7800000;
- constant C3_MEM_TRFC : integer := 70000;
- constant C3_MEM_TRP : integer := 15000;
- constant C3_MEM_TWR : integer := 15000;
- constant C3_MEM_TRTP : integer := 7500;
- constant C3_MEM_TWTR : integer := 2;
- constant C3_MEM_TYPE : string := "DDR";
- constant C3_MEM_DENSITY : string := "512Mb";
- constant C3_MEM_BURST_LEN : integer := 4;
- constant C3_MEM_CAS_LATENCY : integer := 3;
- constant C3_MEM_NUM_COL_BITS : integer := 10;
- constant C3_MEM_DDR1_2_ODS : string := "FULL";
- constant C3_MEM_DDR2_RTT : string := "50OHMS";
- constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
- constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
- constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
- constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
- constant C3_MEM_DDR3_ODS : string := "DIV6";
- constant C3_MEM_DDR3_RTT : string := "DIV2";
- constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
- constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
- constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
- constant C3_MEM_MOBILE_PA_SR : string := "FULL";
- constant C3_MEM_MDDR_ODS : string := "FULL";
- constant C3_MC_CALIB_BYPASS : string := "NO";
- constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
- constant C3_MC_CALIBRATION_DELAY : string := "HALF";
- constant C3_SKIP_IN_TERM_CAL : integer := 1;
- constant C3_SKIP_DYNAMIC_CAL : integer := 0;
- constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
- constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
- constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
- constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
- constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
-
- signal c3_sys_clk_p : std_logic;
- signal c3_sys_clk_n : std_logic;
- signal c3_async_rst : std_logic;
- signal c3_sysclk_2x : std_logic;
- signal c3_sysclk_2x_180 : std_logic;
- signal c3_pll_ce_0 : std_logic;
- signal c3_pll_ce_90 : std_logic;
- signal c3_pll_lock : std_logic;
- signal c3_mcb_drp_clk : std_logic;
- signal c3_cmp_error : std_logic;
- signal c3_cmp_data_valid : std_logic;
- signal c3_vio_modify_enable : std_logic;
- signal c3_error_status : std_logic_vector(127 downto 0);
- signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
- signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
- signal c3_cmp_data : std_logic_vector(31 downto 0);
- signal c3_selfrefresh_enter : std_logic;
- signal c3_selfrefresh_mode : std_logic;
-
-
-
-begin
-
-
-c3_sys_clk_p <= '0';
-c3_sys_clk_n <= '0';
-
-memc3_infrastructure_inst : memc3_infrastructure
-
-generic map
- (
- C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
- C_RST_ACT_LOW => C3_RST_ACT_LOW,
- C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
- C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
- C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
- C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
- C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
- C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
- C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE
- )
-port map
- (
- sys_clk_p => c3_sys_clk_p,
- sys_clk_n => c3_sys_clk_n,
- sys_clk => c3_sys_clk,
- sys_rst_n => c3_sys_rst_n,
- clk0 => c3_clk0,
- rst0 => c3_rst0,
- async_rst => c3_async_rst,
- sysclk_2x => c3_sysclk_2x,
- sysclk_2x_180 => c3_sysclk_2x_180,
- pll_ce_0 => c3_pll_ce_0,
- pll_ce_90 => c3_pll_ce_90,
- pll_lock => c3_pll_lock,
- mcb_drp_clk => c3_mcb_drp_clk
- );
-
-
--- wrapper instantiation
- memc3_wrapper_inst : memc3_wrapper
-
-generic map
- (
- C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
- C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
- C_SIMULATION => C3_SIMULATION,
- C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
- C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
- C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
- C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
- C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
- C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
- C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
- C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
- C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
- C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
- C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
- C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
- C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
- C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
- C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
- C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
- C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
- C_MEM_TRAS => C3_MEM_TRAS,
- C_MEM_TRCD => C3_MEM_TRCD,
- C_MEM_TREFI => C3_MEM_TREFI,
- C_MEM_TRFC => C3_MEM_TRFC,
- C_MEM_TRP => C3_MEM_TRP,
- C_MEM_TWR => C3_MEM_TWR,
- C_MEM_TRTP => C3_MEM_TRTP,
- C_MEM_TWTR => C3_MEM_TWTR,
- C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
- C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
- C_MEM_TYPE => C3_MEM_TYPE,
- C_MEM_DENSITY => C3_MEM_DENSITY,
- C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
- C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
- C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
- C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
- C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
- C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
- C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
- C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
- C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
- C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
- C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
- C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
- C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
- C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
- C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
- C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
- C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
- C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
- C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
- C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
- C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
- C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
- C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
- C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
- C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
- C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
- C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
- C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
- C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
- C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
- C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
- C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
- C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
- C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
- C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
- C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
- C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
- C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
- C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
- C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
- C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
- C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
- C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
- )
-port map
-(
- mcb3_dram_dq => mcb3_dram_dq,
- mcb3_dram_a => mcb3_dram_a,
- mcb3_dram_ba => mcb3_dram_ba,
- mcb3_dram_cke => mcb3_dram_cke,
- mcb3_dram_ras_n => mcb3_dram_ras_n,
- mcb3_dram_cas_n => mcb3_dram_cas_n,
- mcb3_dram_we_n => mcb3_dram_we_n,
- mcb3_dram_dm => mcb3_dram_dm,
- mcb3_dram_udqs => mcb3_dram_udqs,
- mcb3_rzq => mcb3_rzq,
- mcb3_dram_udm => mcb3_dram_udm,
- calib_done => c3_calib_done,
- async_rst => c3_async_rst,
- sysclk_2x => c3_sysclk_2x,
- sysclk_2x_180 => c3_sysclk_2x_180,
- pll_ce_0 => c3_pll_ce_0,
- pll_ce_90 => c3_pll_ce_90,
- pll_lock => c3_pll_lock,
- mcb_drp_clk => c3_mcb_drp_clk,
- mcb3_dram_dqs => mcb3_dram_dqs,
- mcb3_dram_ck => mcb3_dram_ck,
- mcb3_dram_ck_n => mcb3_dram_ck_n,
- p0_cmd_clk => c3_p0_cmd_clk,
- p0_cmd_en => c3_p0_cmd_en,
- p0_cmd_instr => c3_p0_cmd_instr,
- p0_cmd_bl => c3_p0_cmd_bl,
- p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
- p0_cmd_empty => c3_p0_cmd_empty,
- p0_cmd_full => c3_p0_cmd_full,
- p0_wr_clk => c3_p0_wr_clk,
- p0_wr_en => c3_p0_wr_en,
- p0_wr_mask => c3_p0_wr_mask,
- p0_wr_data => c3_p0_wr_data,
- p0_wr_full => c3_p0_wr_full,
- p0_wr_empty => c3_p0_wr_empty,
- p0_wr_count => c3_p0_wr_count,
- p0_wr_underrun => c3_p0_wr_underrun,
- p0_wr_error => c3_p0_wr_error,
- p0_rd_clk => c3_p0_rd_clk,
- p0_rd_en => c3_p0_rd_en,
- p0_rd_data => c3_p0_rd_data,
- p0_rd_full => c3_p0_rd_full,
- p0_rd_empty => c3_p0_rd_empty,
- p0_rd_count => c3_p0_rd_count,
- p0_rd_overflow => c3_p0_rd_overflow,
- p0_rd_error => c3_p0_rd_error,
- p1_cmd_clk => c3_p1_cmd_clk,
- p1_cmd_en => c3_p1_cmd_en,
- p1_cmd_instr => c3_p1_cmd_instr,
- p1_cmd_bl => c3_p1_cmd_bl,
- p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
- p1_cmd_empty => c3_p1_cmd_empty,
- p1_cmd_full => c3_p1_cmd_full,
- p1_wr_clk => c3_p1_wr_clk,
- p1_wr_en => c3_p1_wr_en,
- p1_wr_mask => c3_p1_wr_mask,
- p1_wr_data => c3_p1_wr_data,
- p1_wr_full => c3_p1_wr_full,
- p1_wr_empty => c3_p1_wr_empty,
- p1_wr_count => c3_p1_wr_count,
- p1_wr_underrun => c3_p1_wr_underrun,
- p1_wr_error => c3_p1_wr_error,
- p1_rd_clk => c3_p1_rd_clk,
- p1_rd_en => c3_p1_rd_en,
- p1_rd_data => c3_p1_rd_data,
- p1_rd_full => c3_p1_rd_full,
- p1_rd_empty => c3_p1_rd_empty,
- p1_rd_count => c3_p1_rd_count,
- p1_rd_overflow => c3_p1_rd_overflow,
- p1_rd_error => c3_p1_rd_error,
- p2_cmd_clk => c3_p2_cmd_clk,
- p2_cmd_en => c3_p2_cmd_en,
- p2_cmd_instr => c3_p2_cmd_instr,
- p2_cmd_bl => c3_p2_cmd_bl,
- p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
- p2_cmd_empty => c3_p2_cmd_empty,
- p2_cmd_full => c3_p2_cmd_full,
- p2_wr_clk => c3_p2_wr_clk,
- p2_wr_en => c3_p2_wr_en,
- p2_wr_mask => c3_p2_wr_mask,
- p2_wr_data => c3_p2_wr_data,
- p2_wr_full => c3_p2_wr_full,
- p2_wr_empty => c3_p2_wr_empty,
- p2_wr_count => c3_p2_wr_count,
- p2_wr_underrun => c3_p2_wr_underrun,
- p2_wr_error => c3_p2_wr_error,
- p3_cmd_clk => c3_p3_cmd_clk,
- p3_cmd_en => c3_p3_cmd_en,
- p3_cmd_instr => c3_p3_cmd_instr,
- p3_cmd_bl => c3_p3_cmd_bl,
- p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
- p3_cmd_empty => c3_p3_cmd_empty,
- p3_cmd_full => c3_p3_cmd_full,
- p3_rd_clk => c3_p3_rd_clk,
- p3_rd_en => c3_p3_rd_en,
- p3_rd_data => c3_p3_rd_data,
- p3_rd_full => c3_p3_rd_full,
- p3_rd_empty => c3_p3_rd_empty,
- p3_rd_count => c3_p3_rd_count,
- p3_rd_overflow => c3_p3_rd_overflow,
- p3_rd_error => c3_p3_rd_error,
- p4_cmd_clk => c3_p4_cmd_clk,
- p4_cmd_en => c3_p4_cmd_en,
- p4_cmd_instr => c3_p4_cmd_instr,
- p4_cmd_bl => c3_p4_cmd_bl,
- p4_cmd_byte_addr => c3_p4_cmd_byte_addr,
- p4_cmd_empty => c3_p4_cmd_empty,
- p4_cmd_full => c3_p4_cmd_full,
- p4_wr_clk => c3_p4_wr_clk,
- p4_wr_en => c3_p4_wr_en,
- p4_wr_mask => c3_p4_wr_mask,
- p4_wr_data => c3_p4_wr_data,
- p4_wr_full => c3_p4_wr_full,
- p4_wr_empty => c3_p4_wr_empty,
- p4_wr_count => c3_p4_wr_count,
- p4_wr_underrun => c3_p4_wr_underrun,
- p4_wr_error => c3_p4_wr_error,
- p5_cmd_clk => c3_p5_cmd_clk,
- p5_cmd_en => c3_p5_cmd_en,
- p5_cmd_instr => c3_p5_cmd_instr,
- p5_cmd_bl => c3_p5_cmd_bl,
- p5_cmd_byte_addr => c3_p5_cmd_byte_addr,
- p5_cmd_empty => c3_p5_cmd_empty,
- p5_cmd_full => c3_p5_cmd_full,
- p5_rd_clk => c3_p5_rd_clk,
- p5_rd_en => c3_p5_rd_en,
- p5_rd_data => c3_p5_rd_data,
- p5_rd_full => c3_p5_rd_full,
- p5_rd_empty => c3_p5_rd_empty,
- p5_rd_count => c3_p5_rd_count,
- p5_rd_overflow => c3_p5_rd_overflow,
- p5_rd_error => c3_p5_rd_error,
- selfrefresh_enter => c3_selfrefresh_enter,
- selfrefresh_mode => c3_selfrefresh_mode
-);
-
-
-
-
-
- end arc;
Index: ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd (nonexistent)
@@ -1,409 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: mcb_soft_calibration_top.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:38 $
--- \ \ / \ Date Created: Mon Feb 9 2009
--- \___\/\___\
---
---Device: Spartan6
---Design Name: DDR/DDR2/DDR3/LPDDR
---Purpose: Xilinx reference design top-level simulation
--- wrapper file for input termination calibration
---Reference:
---
--- Revision: Date: Comment
--- 1.0: 2/06/09: Initial version for MIG wrapper.
--- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
--- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
--- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
--- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
--- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
--- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
--- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
--- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
--- End Revision
---**********************************************************************************
-
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
-library unisim;
-use unisim.vcomponents.all;
-
-entity mcb_soft_calibration_top is
- generic (
- C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
- C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
- -- and does dynamic recal,
- -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
- -- no dynamic recal will be done
- SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
- SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
- SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
- C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
- C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
-
- );
- port (
- UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
- RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
- -- IODRP (sub)controller
- IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
- DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
- -- (MCB hard calib complete)
- PLL_LOCK : in std_logic; -- Lock signal from PLL
- SELFREFRESH_REQ : in std_logic;
- SELFREFRESH_MCB_MODE : in std_logic;
- SELFREFRESH_MCB_REQ : out std_logic;
- SELFREFRESH_MODE : out std_logic;
- MCB_UIADD : out std_logic; -- to MCB's UIADD port
- MCB_UISDI : out std_logic; -- to MCB's UISDI port
- MCB_UOSDO : in std_logic;
- MCB_UODONECAL : in std_logic;
- MCB_UOREFRSHFLAG : in std_logic;
- MCB_UICS : out std_logic;
- MCB_UIDRPUPDATE : out std_logic;
- MCB_UIBROADCAST : out std_logic;
- MCB_UIADDR : out std_logic_vector(4 downto 0);
- MCB_UICMDEN : out std_logic;
- MCB_UIDONECAL : out std_logic;
- MCB_UIDQLOWERDEC : out std_logic;
- MCB_UIDQLOWERINC : out std_logic;
- MCB_UIDQUPPERDEC : out std_logic;
- MCB_UIDQUPPERINC : out std_logic;
- MCB_UILDQSDEC : out std_logic;
- MCB_UILDQSINC : out std_logic;
- MCB_UIREAD : out std_logic;
- MCB_UIUDQSDEC : out std_logic;
- MCB_UIUDQSINC : out std_logic;
- MCB_RECAL : out std_logic;
- MCB_SYSRST : out std_logic;
-
- MCB_UICMD : out std_logic;
- MCB_UICMDIN : out std_logic;
- MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
- MCB_UODATA : in std_logic_vector(7 downto 0);
- MCB_UODATAVALID : in std_logic;
- MCB_UOCMDREADY : in std_logic;
- MCB_UO_CAL_START : in std_logic;
- RZQ_PIN : inout std_logic;
- ZIO_PIN : inout std_logic;
- CKE_Train : out std_logic
-
- );
-end entity mcb_soft_calibration_top;
-
-architecture trans of mcb_soft_calibration_top is
-
-component mcb_soft_calibration is
- generic (
- C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
- SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
- SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
- SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
- C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
- -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
- -- (Quarter, etc)
-
- C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
- C_MEM_TYPE : string := "DDR"
- );
- port (
- UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
- -- CLK pins
- RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
- DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
- -- hard calib complete)
- PLL_LOCK : in std_logic; -- Lock signal from PLL
- SELFREFRESH_REQ : in std_logic;
- SELFREFRESH_MCB_MODE : in std_logic;
- SELFREFRESH_MCB_REQ : out std_logic;
- SELFREFRESH_MODE : out std_logic;
- IODRP_ADD : out std_logic; -- IODRP ADD port
- IODRP_SDI : out std_logic; -- IODRP SDI port
- RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
- RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
- RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
- ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
- ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
- ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
- MCB_UIADD : out std_logic; -- to MCB's UIADD port
- MCB_UISDI : out std_logic; -- to MCB's UISDI port
- MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
- MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
- MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
- MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
- MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
- -- during IODRP2_MCB writes). Currently just trasnparent
- MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
- MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
- MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
- MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
- MCB_UIDQLOWERDEC : out std_logic := '0';
- MCB_UIDQLOWERINC : out std_logic := '0';
- MCB_UIDQUPPERDEC : out std_logic := '0';
- MCB_UIDQUPPERINC : out std_logic := '0';
- MCB_UILDQSDEC : out std_logic := '0';
- MCB_UILDQSINC : out std_logic := '0';
- MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
- -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
- MCB_UIUDQSDEC : out std_logic := '0';
- MCB_UIUDQSINC : out std_logic := '0';
- MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
- MCB_UICMD : out std_logic;
- MCB_UICMDIN : out std_logic;
- MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
- MCB_UODATA : in std_logic_vector(7 downto 0);
- MCB_UODATAVALID : in std_logic;
- MCB_UOCMDREADY : in std_logic;
- MCB_UO_CAL_START : in std_logic;
- MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
- Max_Value : out std_logic_vector(7 downto 0);
- CKE_Train : out std_logic
-
- );
-end component;
-
- signal IODRP_ADD : std_logic;
- signal IODRP_SDI : std_logic;
- signal RZQ_IODRP_SDO : std_logic;
- signal RZQ_IODRP_CS : std_logic;
- signal ZIO_IODRP_SDO : std_logic;
- signal ZIO_IODRP_CS : std_logic;
- signal IODRP_SDO : std_logic;
- signal IODRP_CS : std_logic;
- signal IODRP_BKST : std_logic;
- signal RZQ_ZIO_ODATAIN : std_logic;
- signal RZQ_ZIO_TRISTATE : std_logic;
- signal RZQ_TOUT : std_logic;
- signal ZIO_TOUT : std_logic;
- signal Max_Value : std_logic_vector(7 downto 0);
-
- signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
- signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
- signal RZQ_OUT : std_logic;
- signal ZIO_OUT : std_logic;
-
- -- Declare intermediate signals for referenced outputs
- signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
- signal MCB_UIADD_xilinx3 : std_logic;
- signal MCB_UISDI_xilinx17 : std_logic;
- signal MCB_UICS_xilinx7 : std_logic;
- signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
- signal MCB_UIBROADCAST_xilinx5 : std_logic;
- signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
- signal MCB_UICMDEN_xilinx6 : std_logic;
- signal MCB_UIDONECAL_xilinx8 : std_logic;
- signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
- signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
- signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
- signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
- signal MCB_UILDQSDEC_xilinx14 : std_logic;
- signal MCB_UILDQSINC_xilinx15 : std_logic;
- signal MCB_UIREAD_xilinx16 : std_logic;
- signal MCB_UIUDQSDEC_xilinx18 : std_logic;
- signal MCB_UIUDQSINC_xilinx19 : std_logic;
- signal MCB_RECAL_xilinx1 : std_logic;
- signal MCB_SYSRST_xilinx2 : std_logic;
-begin
- -- Drive referenced outputs
- DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
- MCB_UIADD <= MCB_UIADD_xilinx3;
- MCB_UISDI <= MCB_UISDI_xilinx17;
- MCB_UICS <= MCB_UICS_xilinx7;
- MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
- MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
- MCB_UIADDR <= MCB_UIADDR_xilinx4;
- MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
- MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
- MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
- MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
- MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
- MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
- MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
- MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
- MCB_UIREAD <= MCB_UIREAD_xilinx16;
- MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
- MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
- MCB_RECAL <= MCB_RECAL_xilinx1;
- MCB_SYSRST <= MCB_SYSRST_xilinx2;
-
- RZQ_ZIO_ODATAIN <= not(RST);
- RZQ_ZIO_TRISTATE <= not(RST);
- IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
-
-
- mcb_soft_calibration_inst : mcb_soft_calibration
- generic map (
- C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
- C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
- SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
- SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
- SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
- C_SIMULATION => C_SIMULATION,
- C_MEM_TYPE => C_MEM_TYPE
-
- )
- port map (
- UI_CLK => UI_CLK,
- RST => RST,
- PLL_LOCK => PLL_LOCK,
- SELFREFRESH_REQ => SELFREFRESH_REQ,
- SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
- SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
- SELFREFRESH_MODE => SELFREFRESH_MODE,
- DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
- IODRP_ADD => IODRP_ADD,
- IODRP_SDI => IODRP_SDI,
- RZQ_IN => RZQ_IN,
- RZQ_IODRP_SDO => RZQ_IODRP_SDO,
- RZQ_IODRP_CS => RZQ_IODRP_CS,
- ZIO_IN => ZIO_IN,
- ZIO_IODRP_SDO => ZIO_IODRP_SDO,
- ZIO_IODRP_CS => ZIO_IODRP_CS,
- MCB_UIADD => MCB_UIADD_xilinx3,
- MCB_UISDI => MCB_UISDI_xilinx17,
- MCB_UOSDO => MCB_UOSDO,
- MCB_UODONECAL => MCB_UODONECAL,
- MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
- MCB_UICS => MCB_UICS_xilinx7,
- MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
- MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
- MCB_UIADDR => MCB_UIADDR_xilinx4,
- MCB_UICMDEN => MCB_UICMDEN_xilinx6,
- MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
- MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
- MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
- MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
- MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
- MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
- MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
- MCB_UIREAD => MCB_UIREAD_xilinx16,
- MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
- MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
- MCB_RECAL => MCB_RECAL_xilinx1,
- MCB_UICMD => MCB_UICMD,
- MCB_UICMDIN => MCB_UICMDIN,
- MCB_UIDQCOUNT => MCB_UIDQCOUNT,
- MCB_UODATA => MCB_UODATA,
- MCB_UODATAVALID => MCB_UODATAVALID,
- MCB_UOCMDREADY => MCB_UOCMDREADY,
- MCB_UO_CAL_START => MCB_UO_CAL_START,
- mcb_sysrst => MCB_SYSRST_xilinx2,
- Max_Value => Max_Value,
- CKE_Train => CKE_Train
- );
-
- IOBUF_RZQ : IOBUF
- port map (
- o => RZQ_IN,
- io => RZQ_PIN,
- i => RZQ_OUT,
- t => RZQ_TOUT
- );
-
- IODRP2_RZQ : IODRP2
- port map (
- dataout => open,
- dataout2 => open,
- dout => RZQ_OUT,
- sdo => RZQ_IODRP_SDO,
- tout => RZQ_TOUT,
- add => IODRP_ADD,
- bkst => IODRP_BKST,
- clk => UI_CLK,
- cs => RZQ_IODRP_CS,
- idatain => RZQ_IN,
- ioclk0 => IOCLK,
- ioclk1 => '1',
- odatain => RZQ_ZIO_ODATAIN,
- sdi => IODRP_SDI,
- t => RZQ_ZIO_TRISTATE
- );
-
-
- gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
- (SKIP_IN_TERM_CAL = 0)) generate
-
- IOBUF_ZIO : IOBUF
- port map (
- o => ZIO_IN,
- io => ZIO_PIN,
- i => ZIO_OUT,
- t => ZIO_TOUT
- );
-
- IODRP2_ZIO : IODRP2
- port map (
- dataout => open,
- dataout2 => open,
- dout => ZIO_OUT,
- sdo => ZIO_IODRP_SDO,
- tout => ZIO_TOUT,
- add => IODRP_ADD,
- bkst => IODRP_BKST,
- clk => UI_CLK,
- cs => ZIO_IODRP_CS,
- idatain => ZIO_IN,
- ioclk0 => IOCLK,
- ioclk1 => '1',
- odatain => RZQ_ZIO_ODATAIN,
- sdi => IODRP_SDI,
- t => RZQ_ZIO_TRISTATE
- );
- end generate;
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd (nonexistent)
@@ -1,310 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : memc3_infrastructure.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
---Device : Spartan-6
---Design Name : DDR/DDR2/DDR3/LPDDR
---Purpose : Clock generation/distribution and reset synchronization
---Reference :
---Revision History :
---*****************************************************************************
-library ieee;
-use ieee.std_logic_1164.all;
-library unisim;
-use unisim.vcomponents.all;
-
-entity memc3_infrastructure is
-generic
- (
- C_MEMCLK_PERIOD : integer := 2500;
- C_RST_ACT_LOW : integer := 1;
- C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
- C_CLKOUT0_DIVIDE : integer := 2;
- C_CLKOUT1_DIVIDE : integer := 2;
- C_CLKOUT2_DIVIDE : integer := 16;
- C_CLKOUT3_DIVIDE : integer := 8;
- C_CLKFBOUT_MULT : integer := 4;
- C_DIVCLK_DIVIDE : integer := 1
-
- );
-port
-(
- sys_clk_p : in std_logic;
- sys_clk_n : in std_logic;
- sys_clk : in std_logic;
- sys_rst_n : in std_logic;
- clk0 : out std_logic;
- rst0 : out std_logic;
- async_rst : out std_logic;
- sysclk_2x : out std_logic;
- sysclk_2x_180 : out std_logic;
- mcb_drp_clk : out std_logic;
- pll_ce_0 : out std_logic;
- pll_ce_90 : out std_logic;
- pll_lock : out std_logic
-
-);
-end entity;
-architecture syn of memc3_infrastructure is
-
- -- # of clock cycles to delay deassertion of reset. Needs to be a fairly
- -- high number not so much for metastability protection, but to give time
- -- for reset (i.e. stable clock cycles) to propagate through all state
- -- machines and to all control signals (i.e. not all control signals have
- -- resets, instead they rely on base state logic being reset, and the effect
- -- of that reset propagating through the logic). Need this because we may not
- -- be getting stable clock cycles while reset asserted (i.e. since reset
- -- depends on PLL/DCM lock status)
-
- constant RST_SYNC_NUM : integer := 25;
- constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0;
- constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000;
-
-
- signal clk_2x_0 : std_logic;
- signal clk_2x_180 : std_logic;
- signal clk0_bufg : std_logic;
- signal clk0_bufg_in : std_logic;
- signal mcb_drp_clk_bufg_in : std_logic;
- signal clkfbout_clkfbin : std_logic;
- signal rst_tmp : std_logic;
- signal sys_clk_ibufg : std_logic;
- signal sys_rst : std_logic;
- signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
- signal powerup_pll_locked : std_logic;
- signal locked : std_logic;
- signal bufpll_mcb_locked : std_logic;
- signal mcb_drp_clk_sig : std_logic;
-
- attribute max_fanout : string;
- attribute syn_maxfan : integer;
- attribute KEEP : string;
- attribute max_fanout of rst0_sync_r : signal is "10";
- attribute syn_maxfan of rst0_sync_r : signal is 10;
- attribute KEEP of sys_clk_ibufg : signal is "TRUE";
-
-begin
-
- sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
- clk0 <= clk0_bufg;
- pll_lock <= bufpll_mcb_locked;
- mcb_drp_clk <= mcb_drp_clk_sig;
-
- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
- --***********************************************************************
- -- Differential input clock input buffers
- --***********************************************************************
- u_ibufg_sys_clk : IBUFGDS
- generic map (
- DIFF_TERM => TRUE
- )
- port map (
- I => sys_clk_p,
- IB => sys_clk_n,
- O => sys_clk_ibufg
- );
- end generate;
-
-
- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
- --***********************************************************************
- -- SINGLE_ENDED input clock input buffers
- --***********************************************************************
- u_ibufg_sys_clk : IBUFG
- port map (
- I => sys_clk,
- O => sys_clk_ibufg
- );
- end generate;
-
- --***************************************************************************
- -- Global clock generation and distribution
- --***************************************************************************
-
- u_pll_adv : PLL_ADV
- generic map
- (
- BANDWIDTH => "OPTIMIZED",
- CLKIN1_PERIOD => CLK_PERIOD_NS,
- CLKIN2_PERIOD => CLK_PERIOD_NS,
- CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
- CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
- CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
- CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
- CLKOUT4_DIVIDE => 1,
- CLKOUT5_DIVIDE => 1,
- CLKOUT0_PHASE => 0.000,
- CLKOUT1_PHASE => 180.000,
- CLKOUT2_PHASE => 0.000,
- CLKOUT3_PHASE => 0.000,
- CLKOUT4_PHASE => 0.000,
- CLKOUT5_PHASE => 0.000,
- CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DUTY_CYCLE => 0.500,
- CLKOUT3_DUTY_CYCLE => 0.500,
- CLKOUT4_DUTY_CYCLE => 0.500,
- CLKOUT5_DUTY_CYCLE => 0.500,
- COMPENSATION => "INTERNAL",
- DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
- CLKFBOUT_MULT => C_CLKFBOUT_MULT,
- CLKFBOUT_PHASE => 0.0,
- REF_JITTER => 0.005000
- )
- port map
- (
- CLKFBIN => clkfbout_clkfbin,
- CLKINSEL => '1',
- CLKIN1 => sys_clk_ibufg,
- CLKIN2 => '0',
- DADDR => (others => '0'),
- DCLK => '0',
- DEN => '0',
- DI => (others => '0'),
- DWE => '0',
- REL => '0',
- RST => sys_rst,
- CLKFBDCM => open,
- CLKFBOUT => clkfbout_clkfbin,
- CLKOUTDCM0 => open,
- CLKOUTDCM1 => open,
- CLKOUTDCM2 => open,
- CLKOUTDCM3 => open,
- CLKOUTDCM4 => open,
- CLKOUTDCM5 => open,
- CLKOUT0 => clk_2x_0,
- CLKOUT1 => clk_2x_180,
- CLKOUT2 => clk0_bufg_in,
- CLKOUT3 => mcb_drp_clk_bufg_in,
- CLKOUT4 => open,
- CLKOUT5 => open,
- DO => open,
- DRDY => open,
- LOCKED => locked
- );
-
- U_BUFG_CLK0 : BUFG
- port map
- (
- O => clk0_bufg,
- I => clk0_bufg_in
- );
-
- U_BUFG_CLK1 : BUFG
- port map (
- O => mcb_drp_clk_sig,
- I => mcb_drp_clk_bufg_in
- );
-
- process (clk0_bufg, sys_rst)
- begin
- if (clk0_bufg'event and clk0_bufg = '1') then
- if(sys_rst = '1') then
- powerup_pll_locked <= '0';
- elsif (bufpll_mcb_locked = '1') then
- powerup_pll_locked <= '1';
- end if;
- end if;
- end process;
-
- --***************************************************************************
- -- Reset synchronization
- -- NOTES:
- -- 1. shut down the whole operation if the PLL hasn't yet locked (and
- -- by inference, this means that external sys_rst has been asserted -
- -- PLL deasserts LOCKED as soon as sys_rst asserted)
- -- 2. asynchronously assert reset. This was we can assert reset even if
- -- there is no clock (needed for things like 3-stating output buffers).
- -- reset deassertion is synchronous.
- -- 3. asynchronous reset only look at pll_lock from PLL during power up. After
- -- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
- -- forever until sys_rst is asserted again. PLL will lose lock when FPGA
- -- enters suspend mode. We don't want reset to MCB get
- -- asserted in the application that needs suspend feature.
- --***************************************************************************
-
- rst_tmp <= sys_rst or not(powerup_pll_locked);
-
- async_rst <= rst_tmp;
-
-process (clk0_bufg, rst_tmp)
- begin
- if (rst_tmp = '1') then
- rst0_sync_r <= (others => '1');
- elsif (rising_edge(clk0_bufg)) then
- rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
- end if;
- end process;
-
- rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
-
-
-BUFPLL_MCB_INST : BUFPLL_MCB
-port map
-( IOCLK0 => sysclk_2x,
- IOCLK1 => sysclk_2x_180,
- LOCKED => locked,
- GCLK => mcb_drp_clk_sig,
- SERDESSTROBE0 => pll_ce_0,
- SERDESSTROBE1 => pll_ce_90,
- PLLIN0 => clk_2x_0,
- PLLIN1 => clk_2x_180,
- LOCK => bufpll_mcb_locked
- );
-
-end architecture syn;
-
Index: ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd (nonexistent)
@@ -1,502 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: iodrp_mcb_controller.vhd
--- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $
--- \ \ / \ Date Created: Mon Feb 9 2009
--- \___\/\___\
---
---Device: Spartan6
---Design Name: DDR/DDR2/DDR3/LPDDR
---Purpose: Xilinx reference design for IODRP controller for v0.9 device
---
---Reference:
---
--- Revision: Date: Comment
--- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
--- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
--- End Revision
---*******************************************************************************
-
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
-
-entity iodrp_mcb_controller is
- --output to IODRP SDI pin
- --input from IODRP SDO pin
-
- -- Register where memcell_address is captured during the READY state
- -- Register which stores the write data until it is ready to be shifted out
- -- The shift register which shifts out SDO and shifts in SDI.
- -- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
- -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
- -- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
- -- The counter for which bit is being shifted during address or data phase
- -- This is set after the first address phase has executed
-
- -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
- --added so that DRP_SDI output is only active when DRP_CS is active
- port (
- memcell_address : in std_logic_vector(7 downto 0);
- write_data : in std_logic_vector(7 downto 0);
- read_data : out std_logic_vector(7 downto 0);
- rd_not_write : in std_logic;
- cmd_valid : in std_logic;
- rdy_busy_n : out std_logic;
- use_broadcast : in std_logic;
- drp_ioi_addr : in std_logic_vector(4 downto 0);
- sync_rst : in std_logic;
- DRP_CLK : in std_logic;
- DRP_CS : out std_logic;
- DRP_SDI : out std_logic;
- DRP_ADD : out std_logic;
- DRP_BKST : out std_logic;
- DRP_SDO : in std_logic;
- MCB_UIREAD : out std_logic
- );
-end entity iodrp_mcb_controller;
-
-architecture trans of iodrp_mcb_controller is
-
- constant READY : std_logic_vector(3 downto 0) := "0000";
- constant DECIDE : std_logic_vector(3 downto 0) := "0001";
- constant ADDR_PHASE : std_logic_vector(3 downto 0) := "0010";
- constant ADDR_TO_DATA_GAP : std_logic_vector(3 downto 0) := "0011";
- constant ADDR_TO_DATA_GAP2 : std_logic_vector(3 downto 0) := "0100";
- constant ADDR_TO_DATA_GAP3 : std_logic_vector(3 downto 0) := "0101";
- constant DATA_PHASE : std_logic_vector(3 downto 0) := "0110";
- constant ALMOST_READY : std_logic_vector(3 downto 0) := "0111";
- constant ALMOST_READY2 : std_logic_vector(3 downto 0) := "1001";
- constant ALMOST_READY3 : std_logic_vector(3 downto 0) := "1010";
-
- constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
- constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
- constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
- constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
- constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
- constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
- constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
- constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
- constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
- constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
- constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
- constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
- constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
- constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
- constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
- constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
- constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
- constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
- constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
- constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
-
-
- signal memcell_addr_reg : std_logic_vector(7 downto 0);
- signal data_reg : std_logic_vector(7 downto 0);
- signal shift_through_reg : std_logic_vector(8 downto 0);
- signal load_shift_n : std_logic;
- signal addr_data_sel_n : std_logic;
- signal bit_cnt : std_logic_vector(2 downto 0);
- signal rd_not_write_reg : std_logic;
- signal AddressPhase : std_logic;
- signal DRP_CS_pre : std_logic;
- signal extra_cs : std_logic;
- signal state : std_logic_vector(3 downto 0);
- signal nextstate : std_logic_vector(3 downto 0);
- signal data_out : std_logic_vector(8 downto 0);
- signal data_out_mux : std_logic_vector(8 downto 0);
- signal DRP_SDI_pre : std_logic;
-
- --synthesis translate_off
- signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
- -- case(state)
- --synthesis translate_on
-
- -- The changes below are to compensate for an issue with 1.0 silicon.
- -- It may still be necessary to add a clock cycle to the ADD and CS signals
-
- --`define DRP_v1_0_FIX // Uncomment out this line for synthesis
-
- procedure shift_n_expand(
- data_in : in std_logic_vector(7 downto 0);
- data_out : out std_logic_vector(8 downto 0)) is
-
- variable data_out_xilinx2 : std_logic_vector(8 downto 0);
- begin
- if ((data_in(0)) = '1') then
- data_out_xilinx2(1 downto 0) := "11";
- else
-
- data_out_xilinx2(1 downto 0) := "00";
- end if;
- if (data_in(1 downto 0) = "10") then
- data_out_xilinx2(2 downto 1) := "11";
- else
-
- data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
- end if;
- if (data_in(2 downto 1) = "10") then
- data_out_xilinx2(3 downto 2) := "11";
- else
-
- data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
- end if;
- if (data_in(3 downto 2) = "10") then
- data_out_xilinx2(4 downto 3) := "11";
- else
-
- data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
- end if;
- if (data_in(4 downto 3) = "10") then
- data_out_xilinx2(5 downto 4) := "11";
- else
-
- data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
- end if;
- if (data_in(5 downto 4) = "10") then
- data_out_xilinx2(6 downto 5) := "11";
- else
-
- data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
- end if;
- if (data_in(6 downto 5) = "10") then
- data_out_xilinx2(7 downto 6) := "11";
- else
-
- data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
- end if;
- if (data_in(7 downto 6) = "10") then
- data_out_xilinx2(8 downto 7) := "11";
- else
- data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
- end if;
- end shift_n_expand;
-
-
- -- Declare intermediate signals for referenced outputs
- signal DRP_CS_xilinx1 : std_logic;
- signal DRP_ADD_xilinx0 : std_logic;
-
- signal ALMOST_READY2_ST : std_logic;
- signal ADDR_PHASE_ST : std_logic;
- signal BIT_CNT7 : std_logic;
- signal ADDR_PHASE_ST1 : std_logic;
- signal DATA_PHASE_ST : std_logic;
-
-begin
- -- Drive referenced outputs
- DRP_CS <= DRP_CS_xilinx1;
- DRP_ADD <= DRP_ADD_xilinx0;
-
-
--- process (state)
--- begin
--- case state is
--- when READY =>
--- state_ascii <= "READY";
--- when DECIDE =>
--- state_ascii <= "DECIDE";
--- when ADDR_PHASE =>
--- state_ascii <= "ADDR_PHASE";
--- when ADDR_TO_DATA_GAP =>
--- state_ascii <= "ADDR_TO_DATA_GAP";
--- when ADDR_TO_DATA_GAP2 =>
--- state_ascii <= "ADDR_TO_DATA_GAP2";
--- when ADDR_TO_DATA_GAP3 =>
--- state_ascii <= "ADDR_TO_DATA_GAP3";
--- when DATA_PHASE =>
--- state_ascii <= "DATA_PHASE";
--- when ALMOST_READY =>
--- state_ascii <= "ALMOST_READY";
--- when ALMOST_READY2 =>
--- state_ascii <= "ALMOST_READY2";
--- when ALMOST_READY3 =>
--- state_ascii <= "ALMOST_READY3";
--- when others =>
--- null;
--- end case;
--- end process;
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (state = READY) then
- memcell_addr_reg <= memcell_address;
- data_reg <= write_data;
- rd_not_write_reg <= rd_not_write;
- end if;
- end if;
- end process;
-
- rdy_busy_n <= '1' when state = READY else '0';
-
- process (drp_ioi_addr, data_out)
- begin
-
- case drp_ioi_addr is
- when IOI_DQ0 =>
- data_out_mux <= data_out;
- when IOI_DQ1 =>
- data_out_mux <= data_out;
- when IOI_DQ2 =>
- data_out_mux <= data_out;
- when IOI_DQ3 =>
- data_out_mux <= data_out;
- when IOI_DQ4 =>
- data_out_mux <= data_out;
- when IOI_DQ5 =>
- data_out_mux <= data_out;
- when IOI_DQ6 =>
- data_out_mux <= data_out;
- when IOI_DQ7 =>
- data_out_mux <= data_out;
- when IOI_DQ8 =>
- data_out_mux <= data_out;
- when IOI_DQ9 =>
- data_out_mux <= data_out;
- when IOI_DQ10 =>
- data_out_mux <= data_out;
- when IOI_DQ11 =>
- data_out_mux <= data_out;
- when IOI_DQ12 =>
- data_out_mux <= data_out;
- when IOI_DQ13 =>
- data_out_mux <= data_out;
- when IOI_DQ14 =>
- data_out_mux <= data_out;
- when IOI_DQ15 =>
- data_out_mux <= data_out;
- when IOI_UDQS_CLK =>
- data_out_mux <= data_out;
- when IOI_UDQS_PIN =>
- data_out_mux <= data_out;
- when IOI_LDQS_CLK =>
- data_out_mux <= data_out;
- when IOI_LDQS_PIN =>
- data_out_mux <= data_out;
- when others =>
- data_out_mux <= data_out;
- end case;
- end process;
-
-
- data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
- ('0' & data_reg);
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- shift_through_reg <= "000000000";
- else
- if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
- shift_through_reg <= data_out_mux;
- else
- shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
- end if;
- end if;
- end if;
- end process;
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
- bit_cnt <= bit_cnt + "001";
- else
- bit_cnt <= "000";
- end if;
- end if;
- end process;
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- read_data <= "00000000";
- else
- if (state = ALMOST_READY3) then
- read_data <= shift_through_reg(7 downto 0);
- end if;
- end if;
- end if;
- end process;
-
- ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
- ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
- BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- AddressPhase <= '0';
- else
- if (AddressPhase = '1') then
- -- Keep it set until we finish the cycle
- AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
- else
- -- set the address phase when ever we finish the address phase
- AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
- end if;
- end if;
- end if;
- end process;
-
-ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
-DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
-
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
- -- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
- DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
- MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
- if (state = READY) then
- DRP_BKST <= use_broadcast;
- end if;
- end if;
- end process;
-
-
- DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
- '0';
- DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
- DRP_SDI_pre;
-
- process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase)
- begin
- addr_data_sel_n <= '0';
- load_shift_n <= '0';
- case state is
- when READY =>
- load_shift_n <= '0';
- if (cmd_valid = '1') then
- nextstate <= DECIDE;
- else
- nextstate <= READY;
- end if;
- when DECIDE =>
- load_shift_n <= '1';
- addr_data_sel_n <= '1';
- nextstate <= ADDR_PHASE;
- -- After the second pass go to end of statemachine
- -- execute a second address phase for the alternative access method.
- when ADDR_PHASE =>
- load_shift_n <= '0';
- if (BIT_CNT7 = '1') then
- if (('1' and rd_not_write_reg) = '1') then
- if (AddressPhase = '1') then
- nextstate <= ALMOST_READY;
- else
- nextstate <= DECIDE;
- end if;
- else
- nextstate <= ADDR_TO_DATA_GAP;
- end if;
- else
- nextstate <= ADDR_PHASE;
- end if;
- when ADDR_TO_DATA_GAP =>
- load_shift_n <= '1';
- nextstate <= ADDR_TO_DATA_GAP2;
- when ADDR_TO_DATA_GAP2 =>
- load_shift_n <= '1';
- nextstate <= ADDR_TO_DATA_GAP3;
- when ADDR_TO_DATA_GAP3 =>
- load_shift_n <= '1';
- nextstate <= DATA_PHASE;
- when DATA_PHASE =>
- load_shift_n <= '0';
- if (BIT_CNT7 = '1') then
- nextstate <= ALMOST_READY;
- else
- nextstate <= DATA_PHASE;
- end if;
- when ALMOST_READY =>
- load_shift_n <= '0';
- nextstate <= ALMOST_READY2;
- when ALMOST_READY2 =>
- load_shift_n <= '0';
- nextstate <= ALMOST_READY3;
- when ALMOST_READY3 =>
- load_shift_n <= '0';
- nextstate <= READY;
- when others =>
- load_shift_n <= '0';
- nextstate <= READY;
- end case;
- end process;
-
-
- process (DRP_CLK)
- begin
- if (DRP_CLK'event and DRP_CLK = '1') then
- if (sync_rst = '1') then
- state <= READY;
- else
- state <= nextstate;
- end if;
- end if;
- end process;
-
-
-end architecture trans;
-
-
ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.bak.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.bak.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.bak.vhd (nonexistent)
@@ -1,281 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : memc3_infrastructure.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
---Device : Spartan-6
---Design Name : DDR/DDR2/DDR3/LPDDR
---Purpose : Clock generation/distribution and reset synchronization
---Reference :
---Revision History :
---*****************************************************************************
-library ieee;
-use ieee.std_logic_1164.all;
-library unisim;
-use unisim.vcomponents.all;
-
-entity memc3_infrastructure is
-generic
- (
- C_MEMCLK_PERIOD : integer := 2500;
- C_RST_ACT_LOW : integer := 1;
- C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
- C_CLKOUT0_DIVIDE : integer := 2;
- C_CLKOUT1_DIVIDE : integer := 2;
- C_CLKOUT2_DIVIDE : integer := 16;
- C_CLKOUT3_DIVIDE : integer := 8;
- C_CLKFBOUT_MULT : integer := 4;
- C_DIVCLK_DIVIDE : integer := 1
-
- );
-port
-(
- sys_clk_p : in std_logic;
- sys_clk_n : in std_logic;
- sys_clk : in std_logic;
- sys_rst_n : in std_logic;
- clk0 : out std_logic;
- rst0 : out std_logic;
- async_rst : out std_logic;
- sysclk_2x : out std_logic;
- sysclk_2x_180 : out std_logic;
- mcb_drp_clk : out std_logic;
- pll_ce_0 : out std_logic;
- pll_ce_90 : out std_logic;
- pll_lock : out std_logic
-
-);
-end entity;
-architecture syn of memc3_infrastructure is
-
- -- # of clock cycles to delay deassertion of reset. Needs to be a fairly
- -- high number not so much for metastability protection, but to give time
- -- for reset (i.e. stable clock cycles) to propagate through all state
- -- machines and to all control signals (i.e. not all control signals have
- -- resets, instead they rely on base state logic being reset, and the effect
- -- of that reset propagating through the logic). Need this because we may not
- -- be getting stable clock cycles while reset asserted (i.e. since reset
- -- depends on PLL/DCM lock status)
-
- constant RST_SYNC_NUM : integer := 25;
- constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0;
- constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000;
-
-
- signal clk_2x_0 : std_logic;
- signal clk_2x_180 : std_logic;
- signal clk0_bufg : std_logic;
- signal clk0_bufg_in : std_logic;
- signal mcb_drp_clk_bufg_in : std_logic;
- signal clkfbout_clkfbin : std_logic;
- signal rst_tmp : std_logic;
- signal sys_rst : std_logic;
- signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
- signal powerup_pll_locked : std_logic;
- signal locked : std_logic;
- signal bufpll_mcb_locked : std_logic;
- signal mcb_drp_clk_sig : std_logic;
-
- attribute max_fanout : string;
- attribute syn_maxfan : integer;
- attribute KEEP : string;
- attribute max_fanout of rst0_sync_r : signal is "10";
- attribute syn_maxfan of rst0_sync_r : signal is 10;
-
-begin
-
- sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
- clk0 <= clk0_bufg;
- pll_lock <= bufpll_mcb_locked;
- mcb_drp_clk <= mcb_drp_clk_sig;
-
- --***************************************************************************
- -- Global clock generation and distribution
- --***************************************************************************
-
- u_pll_adv : PLL_ADV
- generic map
- (
- BANDWIDTH => "OPTIMIZED",
- CLKIN1_PERIOD => CLK_PERIOD_NS,
- CLKIN2_PERIOD => CLK_PERIOD_NS,
- CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
- CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
- CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
- CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
- CLKOUT4_DIVIDE => 1,
- CLKOUT5_DIVIDE => 1,
- CLKOUT0_PHASE => 0.000,
- CLKOUT1_PHASE => 180.000,
- CLKOUT2_PHASE => 0.000,
- CLKOUT3_PHASE => 0.000,
- CLKOUT4_PHASE => 0.000,
- CLKOUT5_PHASE => 0.000,
- CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DUTY_CYCLE => 0.500,
- CLKOUT3_DUTY_CYCLE => 0.500,
- CLKOUT4_DUTY_CYCLE => 0.500,
- CLKOUT5_DUTY_CYCLE => 0.500,
- COMPENSATION => "INTERNAL",
- DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
- CLKFBOUT_MULT => C_CLKFBOUT_MULT,
- CLKFBOUT_PHASE => 0.0,
- REF_JITTER => 0.005000
- )
- port map
- (
- CLKFBIN => clkfbout_clkfbin,
- CLKINSEL => '1',
- CLKIN1 => sys_clk,
- CLKIN2 => '0',
- DADDR => (others => '0'),
- DCLK => '0',
- DEN => '0',
- DI => (others => '0'),
- DWE => '0',
- REL => '0',
- RST => sys_rst,
- CLKFBDCM => open,
- CLKFBOUT => clkfbout_clkfbin,
- CLKOUTDCM0 => open,
- CLKOUTDCM1 => open,
- CLKOUTDCM2 => open,
- CLKOUTDCM3 => open,
- CLKOUTDCM4 => open,
- CLKOUTDCM5 => open,
- CLKOUT0 => clk_2x_0,
- CLKOUT1 => clk_2x_180,
- CLKOUT2 => clk0_bufg_in,
- CLKOUT3 => mcb_drp_clk_bufg_in,
- CLKOUT4 => open,
- CLKOUT5 => open,
- DO => open,
- DRDY => open,
- LOCKED => locked
- );
-
- U_BUFG_CLK0 : BUFG
- port map
- (
- O => clk0_bufg,
- I => clk0_bufg_in
- );
-
- U_BUFG_CLK1 : BUFG
- port map (
- O => mcb_drp_clk_sig,
- I => mcb_drp_clk_bufg_in
- );
-
- process (clk0_bufg, sys_rst)
- begin
- if (clk0_bufg'event and clk0_bufg = '1') then
- if(sys_rst = '1') then
- powerup_pll_locked <= '0';
- elsif (bufpll_mcb_locked = '1') then
- powerup_pll_locked <= '1';
- end if;
- end if;
- end process;
-
- --***************************************************************************
- -- Reset synchronization
- -- NOTES:
- -- 1. shut down the whole operation if the PLL hasn't yet locked (and
- -- by inference, this means that external sys_rst has been asserted -
- -- PLL deasserts LOCKED as soon as sys_rst asserted)
- -- 2. asynchronously assert reset. This was we can assert reset even if
- -- there is no clock (needed for things like 3-stating output buffers).
- -- reset deassertion is synchronous.
- -- 3. asynchronous reset only look at pll_lock from PLL during power up. After
- -- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
- -- forever until sys_rst is asserted again. PLL will lose lock when FPGA
- -- enters suspend mode. We don't want reset to MCB get
- -- asserted in the application that needs suspend feature.
- --***************************************************************************
-
- rst_tmp <= sys_rst or not(powerup_pll_locked);
-
- async_rst <= rst_tmp;
-
-process (clk0_bufg, rst_tmp)
- begin
- if (rst_tmp = '1') then
- rst0_sync_r <= (others => '1');
- elsif (rising_edge(clk0_bufg)) then
- rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
- end if;
- end process;
-
- rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
-
-
-BUFPLL_MCB_INST : BUFPLL_MCB
-port map
-( IOCLK0 => sysclk_2x,
- IOCLK1 => sysclk_2x_180,
- LOCKED => locked,
- GCLK => mcb_drp_clk_sig,
- SERDESSTROBE0 => pll_ce_0,
- SERDESSTROBE1 => pll_ce_90,
- PLLIN0 => clk_2x_0,
- PLLIN1 => clk_2x_180,
- LOCK => bufpll_mcb_locked
- );
-
-end architecture syn;
-
Index: ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd (nonexistent)
@@ -1,1022 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : memc3_wrapper.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/06/04 11:24:37 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
---Device : Spartan-6
---Design Name : DDR/DDR2/DDR3/LPDDR
---Purpose : This module instantiates mcb_raw_wrapper module.
---Reference :
---Revision History :
---*****************************************************************************
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity memc3_wrapper is
-generic (
-
- C_MEMCLK_PERIOD : integer := 2500;
- C_P0_MASK_SIZE : integer := 4;
- C_P0_DATA_PORT_SIZE : integer := 32;
- C_P1_MASK_SIZE : integer := 4;
- C_P1_DATA_PORT_SIZE : integer := 32;
-
- C_ARB_NUM_TIME_SLOTS : integer := 12;
- C_ARB_TIME_SLOT_0 : bit_vector := "000";
- C_ARB_TIME_SLOT_1 : bit_vector := "000";
- C_ARB_TIME_SLOT_2 : bit_vector := "000";
- C_ARB_TIME_SLOT_3 : bit_vector := "000";
- C_ARB_TIME_SLOT_4 : bit_vector := "000";
- C_ARB_TIME_SLOT_5 : bit_vector := "000";
- C_ARB_TIME_SLOT_6 : bit_vector := "000";
- C_ARB_TIME_SLOT_7 : bit_vector := "000";
- C_ARB_TIME_SLOT_8 : bit_vector := "000";
- C_ARB_TIME_SLOT_9 : bit_vector := "000";
- C_ARB_TIME_SLOT_10 : bit_vector := "000";
- C_ARB_TIME_SLOT_11 : bit_vector := "000";
-
- C_MEM_TRAS : integer := 45000;
- C_MEM_TRCD : integer := 12500;
- C_MEM_TREFI : integer := 7800000;
- C_MEM_TRFC : integer := 127500;
- C_MEM_TRP : integer := 12500;
- C_MEM_TWR : integer := 15000;
- C_MEM_TRTP : integer := 7500;
- C_MEM_TWTR : integer := 7500;
-
- C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
- C_MEM_TYPE : string :="DDR2";
- C_MEM_DENSITY : string :="1Gb";
- C_NUM_DQ_PINS : integer := 4;
- C_MEM_BURST_LEN : integer := 8;
- C_MEM_CAS_LATENCY : integer := 5;
- C_MEM_ADDR_WIDTH : integer := 14;
- C_MEM_BANKADDR_WIDTH : integer := 3;
- C_MEM_NUM_COL_BITS : integer := 11;
-
- C_MEM_DDR1_2_ODS : string := "FULL";
- C_MEM_DDR2_RTT : string := "50OHMS";
- C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
- C_MEM_DDR2_3_PA_SR : string := "FULL";
- C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
-
- C_MEM_DDR3_CAS_LATENCY : integer:= 7;
- C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
- C_MEM_DDR3_ODS : string := "DIV6";
- C_MEM_DDR3_RTT : string := "DIV2";
- C_MEM_DDR3_AUTO_SR : string := "ENABLED";
- C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
- C_MEM_MOBILE_PA_SR : string := "FULL";
- C_MEM_MDDR_ODS : string := "FULL";
-
- C_MC_CALIB_BYPASS : string := "NO";
- C_LDQSP_TAP_DELAY_VAL : integer := 0;
- C_UDQSP_TAP_DELAY_VAL : integer := 0;
- C_LDQSN_TAP_DELAY_VAL : integer := 0;
- C_UDQSN_TAP_DELAY_VAL : integer := 0;
- C_DQ0_TAP_DELAY_VAL : integer := 0;
- C_DQ1_TAP_DELAY_VAL : integer := 0;
- C_DQ2_TAP_DELAY_VAL : integer := 0;
- C_DQ3_TAP_DELAY_VAL : integer := 0;
- C_DQ4_TAP_DELAY_VAL : integer := 0;
- C_DQ5_TAP_DELAY_VAL : integer := 0;
- C_DQ6_TAP_DELAY_VAL : integer := 0;
- C_DQ7_TAP_DELAY_VAL : integer := 0;
- C_DQ8_TAP_DELAY_VAL : integer := 0;
- C_DQ9_TAP_DELAY_VAL : integer := 0;
- C_DQ10_TAP_DELAY_VAL : integer := 0;
- C_DQ11_TAP_DELAY_VAL : integer := 0;
- C_DQ12_TAP_DELAY_VAL : integer := 0;
- C_DQ13_TAP_DELAY_VAL : integer := 0;
- C_DQ14_TAP_DELAY_VAL : integer := 0;
- C_DQ15_TAP_DELAY_VAL : integer := 0;
-
-
- C_SKIP_IN_TERM_CAL : integer := 0;
- C_SKIP_DYNAMIC_CAL : integer := 0;
-
- C_SIMULATION : string := "FALSE";
- C_MC_CALIBRATION_MODE : string := "CALIBRATION";
- C_MC_CALIBRATION_DELAY : string := "QUARTER";
- C_CALIB_SOFT_IP : string := "TRUE"
-
-
- );
- port
- (
-
- -- high-speed PLL clock interface
- sysclk_2x : in std_logic;
- sysclk_2x_180 : in std_logic;
- pll_ce_0 : in std_logic;
- pll_ce_90 : in std_logic;
- pll_lock : in std_logic;
- async_rst : in std_logic;
-
- --User Port0 Interface Signals
-
- p0_cmd_clk : in std_logic;
- p0_cmd_en : in std_logic;
- p0_cmd_instr : in std_logic_vector(2 downto 0) ;
- p0_cmd_bl : in std_logic_vector(5 downto 0) ;
- p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
- p0_cmd_empty : out std_logic;
- p0_cmd_full : out std_logic;
-
- -- Data Wr Port signals
- p0_wr_clk : in std_logic;
- p0_wr_en : in std_logic;
- p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
- p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
- p0_wr_full : out std_logic;
- p0_wr_empty : out std_logic;
- p0_wr_count : out std_logic_vector(6 downto 0) ;
- p0_wr_underrun : out std_logic;
- p0_wr_error : out std_logic;
-
- --Data Rd Port signals
- p0_rd_clk : in std_logic;
- p0_rd_en : in std_logic;
- p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
- p0_rd_full : out std_logic;
- p0_rd_empty : out std_logic;
- p0_rd_count : out std_logic_vector(6 downto 0) ;
- p0_rd_overflow : out std_logic;
- p0_rd_error : out std_logic;
-
- --User Port1 Interface Signals
-
- p1_cmd_clk : in std_logic;
- p1_cmd_en : in std_logic;
- p1_cmd_instr : in std_logic_vector(2 downto 0) ;
- p1_cmd_bl : in std_logic_vector(5 downto 0) ;
- p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
- p1_cmd_empty : out std_logic;
- p1_cmd_full : out std_logic;
-
- -- Data Wr Port signals
- p1_wr_clk : in std_logic;
- p1_wr_en : in std_logic;
- p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
- p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
- p1_wr_full : out std_logic;
- p1_wr_empty : out std_logic;
- p1_wr_count : out std_logic_vector(6 downto 0) ;
- p1_wr_underrun : out std_logic;
- p1_wr_error : out std_logic;
-
- --Data Rd Port signals
- p1_rd_clk : in std_logic;
- p1_rd_en : in std_logic;
- p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
- p1_rd_full : out std_logic;
- p1_rd_empty : out std_logic;
- p1_rd_count : out std_logic_vector(6 downto 0) ;
- p1_rd_overflow : out std_logic;
- p1_rd_error : out std_logic;
-
- --User Port2 Interface Signals
-
- p2_cmd_clk : in std_logic;
- p2_cmd_en : in std_logic;
- p2_cmd_instr : in std_logic_vector(2 downto 0) ;
- p2_cmd_bl : in std_logic_vector(5 downto 0) ;
- p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
- p2_cmd_empty : out std_logic;
- p2_cmd_full : out std_logic;
-
- --Data Wr Port signals
- p2_wr_clk : in std_logic;
- p2_wr_en : in std_logic;
- p2_wr_mask : in std_logic_vector(3 downto 0) ;
- p2_wr_data : in std_logic_vector(31 downto 0) ;
- p2_wr_full : out std_logic;
- p2_wr_empty : out std_logic;
- p2_wr_count : out std_logic_vector(6 downto 0) ;
- p2_wr_underrun : out std_logic;
- p2_wr_error : out std_logic;
-
- --User Port3 Interface Signals
-
- p3_cmd_clk : in std_logic;
- p3_cmd_en : in std_logic;
- p3_cmd_instr : in std_logic_vector(2 downto 0) ;
- p3_cmd_bl : in std_logic_vector(5 downto 0) ;
- p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
- p3_cmd_empty : out std_logic;
- p3_cmd_full : out std_logic;
-
- --Data Rd Port signals
- p3_rd_clk : in std_logic;
- p3_rd_en : in std_logic;
- p3_rd_data : out std_logic_vector(31 downto 0) ;
- p3_rd_full : out std_logic;
- p3_rd_empty : out std_logic;
- p3_rd_count : out std_logic_vector(6 downto 0) ;
- p3_rd_overflow : out std_logic;
- p3_rd_error : out std_logic;
-
- --User Port4 Interface Signals
-
- p4_cmd_clk : in std_logic;
- p4_cmd_en : in std_logic;
- p4_cmd_instr : in std_logic_vector(2 downto 0) ;
- p4_cmd_bl : in std_logic_vector(5 downto 0) ;
- p4_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
- p4_cmd_empty : out std_logic;
- p4_cmd_full : out std_logic;
-
- --Data Wr Port signals
- p4_wr_clk : in std_logic;
- p4_wr_en : in std_logic;
- p4_wr_mask : in std_logic_vector(3 downto 0) ;
- p4_wr_data : in std_logic_vector(31 downto 0) ;
- p4_wr_full : out std_logic;
- p4_wr_empty : out std_logic;
- p4_wr_count : out std_logic_vector(6 downto 0) ;
- p4_wr_underrun : out std_logic;
- p4_wr_error : out std_logic;
-
- --User Port5 Interface Signals
-
- p5_cmd_clk : in std_logic;
- p5_cmd_en : in std_logic;
- p5_cmd_instr : in std_logic_vector(2 downto 0) ;
- p5_cmd_bl : in std_logic_vector(5 downto 0) ;
- p5_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
- p5_cmd_empty : out std_logic;
- p5_cmd_full : out std_logic;
-
- --Data Rd Port signals
- p5_rd_clk : in std_logic;
- p5_rd_en : in std_logic;
- p5_rd_data : out std_logic_vector(31 downto 0) ;
- p5_rd_full : out std_logic;
- p5_rd_empty : out std_logic;
- p5_rd_count : out std_logic_vector(6 downto 0) ;
- p5_rd_overflow : out std_logic;
- p5_rd_error : out std_logic;
-
-
-
- -- memory interface signals
- mcb3_dram_ck : out std_logic;
- mcb3_dram_ck_n : out std_logic;
- mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
- mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
- mcb3_dram_ras_n : out std_logic;
- mcb3_dram_cas_n : out std_logic;
- mcb3_dram_we_n : out std_logic;
- mcb3_dram_cke : out std_logic;
- mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
- mcb3_dram_dqs : inout std_logic;
-
-
-mcb3_dram_udqs : inout std_logic;
-mcb3_dram_udm : out std_logic;
-
-
-
-mcb3_dram_dm : out std_logic;
-
- mcb3_rzq : inout std_logic;
-
-
- -- Calibration signals
- mcb_drp_clk : in std_logic;
- calib_done : out std_logic;
- selfrefresh_enter : in std_logic;
- selfrefresh_mode : out std_logic
-
- );
-end entity;
-architecture acch of memc3_wrapper is
-component mcb_raw_wrapper IS
- GENERIC (
-
- C_MEMCLK_PERIOD : integer;
- C_PORT_ENABLE : std_logic_vector(5 downto 0);
- C_MEM_ADDR_ORDER : string;
- C_ARB_NUM_TIME_SLOTS : integer;
- C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
- C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
- C_PORT_CONFIG : string;
-
-
- C_MEM_TRAS : integer;
- C_MEM_TRCD : integer;
- C_MEM_TREFI : integer;
- C_MEM_TRFC : integer;
- C_MEM_TRP : integer;
- C_MEM_TWR : integer;
- C_MEM_TRTP : integer;
- C_MEM_TWTR : integer;
-
- C_NUM_DQ_PINS : integer;
- C_MEM_TYPE : string;
- C_MEM_DENSITY : string;
- C_MEM_BURST_LEN : integer;
-
- C_MEM_CAS_LATENCY : integer;
- C_MEM_ADDR_WIDTH : integer;
- C_MEM_BANKADDR_WIDTH : integer;
- C_MEM_NUM_COL_BITS : integer;
-
- C_MEM_DDR3_CAS_LATENCY : integer;
- C_MEM_MOBILE_PA_SR : string;
- C_MEM_DDR1_2_ODS : string;
- C_MEM_DDR3_ODS : string;
- C_MEM_DDR2_RTT : string;
- C_MEM_DDR3_RTT : string;
- C_MEM_MDDR_ODS : string;
-
- C_MEM_DDR2_DIFF_DQS_EN : string;
- C_MEM_DDR2_3_PA_SR : string;
- C_MEM_DDR3_CAS_WR_LATENCY : integer;
-
- C_MEM_DDR3_AUTO_SR : string;
- C_MEM_DDR2_3_HIGH_TEMP_SR : string;
- C_MEM_DDR3_DYN_WRT_ODT : string;
-
- C_MC_CALIB_BYPASS : string;
- C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
- C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
- C_CALIB_SOFT_IP : string;
- C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
- C_MC_CALIBRATION_CLK_DIV : integer;
- C_MC_CALIBRATION_MODE : string;
- C_MC_CALIBRATION_DELAY : string;
-
- LDQSP_TAP_DELAY_VAL : integer;
- UDQSP_TAP_DELAY_VAL : integer;
- LDQSN_TAP_DELAY_VAL : integer;
- UDQSN_TAP_DELAY_VAL : integer;
- DQ0_TAP_DELAY_VAL : integer;
- DQ1_TAP_DELAY_VAL : integer;
- DQ2_TAP_DELAY_VAL : integer;
- DQ3_TAP_DELAY_VAL : integer;
- DQ4_TAP_DELAY_VAL : integer;
- DQ5_TAP_DELAY_VAL : integer;
- DQ6_TAP_DELAY_VAL : integer;
- DQ7_TAP_DELAY_VAL : integer;
- DQ8_TAP_DELAY_VAL : integer;
- DQ9_TAP_DELAY_VAL : integer;
- DQ10_TAP_DELAY_VAL : integer;
- DQ11_TAP_DELAY_VAL : integer;
- DQ12_TAP_DELAY_VAL : integer;
- DQ13_TAP_DELAY_VAL : integer;
- DQ14_TAP_DELAY_VAL : integer;
- DQ15_TAP_DELAY_VAL : integer;
-
- C_P0_MASK_SIZE : integer;
- C_P0_DATA_PORT_SIZE : integer;
- C_P1_MASK_SIZE : integer;
- C_P1_DATA_PORT_SIZE : integer;
-
- C_SIMULATION : string ;
- C_SKIP_IN_TERM_CAL : integer;
- C_SKIP_DYNAMIC_CAL : integer;
- C_SKIP_DYN_IN_TERM : integer;
-
- C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
- );
- PORT (
- -- HIGH-SPEED PLL clock interface
-
- sysclk_2x : in std_logic;
- sysclk_2x_180 : in std_logic;
- pll_ce_0 : in std_logic;
- pll_ce_90 : in std_logic;
- pll_lock : in std_logic;
- sys_rst : in std_logic;
-
- p0_arb_en : in std_logic;
- p0_cmd_clk : in std_logic;
- p0_cmd_en : in std_logic;
- p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
- p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
- p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
- p0_cmd_empty : out std_logic;
- p0_cmd_full : out std_logic;
- p0_wr_clk : in std_logic;
- p0_wr_en : in std_logic;
- p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
- p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
- p0_wr_full : out std_logic;
- p0_wr_empty : out std_logic;
- p0_wr_count : out std_logic_vector(6 DOWNTO 0);
- p0_wr_underrun : out std_logic;
- p0_wr_error : out std_logic;
- p0_rd_clk : in std_logic;
- p0_rd_en : in std_logic;
- p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
- p0_rd_full : out std_logic;
- p0_rd_empty : out std_logic;
- p0_rd_count : out std_logic_vector(6 DOWNTO 0);
- p0_rd_overflow : out std_logic;
- p0_rd_error : out std_logic;
- p1_arb_en : in std_logic;
- p1_cmd_clk : in std_logic;
- p1_cmd_en : in std_logic;
- p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
- p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
- p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
- p1_cmd_empty : out std_logic;
- p1_cmd_full : out std_logic;
- p1_wr_clk : in std_logic;
- p1_wr_en : in std_logic;
- p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
- p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
- p1_wr_full : out std_logic;
- p1_wr_empty : out std_logic;
- p1_wr_count : out std_logic_vector(6 DOWNTO 0);
- p1_wr_underrun : out std_logic;
- p1_wr_error : out std_logic;
- p1_rd_clk : in std_logic;
- p1_rd_en : in std_logic;
- p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
- p1_rd_full : out std_logic;
- p1_rd_empty : out std_logic;
- p1_rd_count : out std_logic_vector(6 DOWNTO 0);
- p1_rd_overflow : out std_logic;
- p1_rd_error : out std_logic;
- p2_arb_en : in std_logic;
- p2_cmd_clk : in std_logic;
- p2_cmd_en : in std_logic;
- p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
- p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
- p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
- p2_cmd_empty : out std_logic;
- p2_cmd_full : out std_logic;
- p2_wr_clk : in std_logic;
- p2_wr_en : in std_logic;
- p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
- p2_wr_data : in std_logic_vector(31 DOWNTO 0);
- p2_wr_full : out std_logic;
- p2_wr_empty : out std_logic;
- p2_wr_count : out std_logic_vector(6 DOWNTO 0);
- p2_wr_underrun : out std_logic;
- p2_wr_error : out std_logic;
- p2_rd_clk : in std_logic;
- p2_rd_en : in std_logic;
- p2_rd_data : out std_logic_vector(31 DOWNTO 0);
- p2_rd_full : out std_logic;
- p2_rd_empty : out std_logic;
- p2_rd_count : out std_logic_vector(6 DOWNTO 0);
- p2_rd_overflow : out std_logic;
- p2_rd_error : out std_logic;
- p3_arb_en : in std_logic;
- p3_cmd_clk : in std_logic;
- p3_cmd_en : in std_logic;
- p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
- p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
- p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
- p3_cmd_empty : out std_logic;
- p3_cmd_full : out std_logic;
- p3_wr_clk : in std_logic;
- p3_wr_en : in std_logic;
- p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
- p3_wr_data : in std_logic_vector(31 DOWNTO 0);
- p3_wr_full : out std_logic;
- p3_wr_empty : out std_logic;
- p3_wr_count : out std_logic_vector(6 DOWNTO 0);
- p3_wr_underrun : out std_logic;
- p3_wr_error : out std_logic;
- p3_rd_clk : in std_logic;
- p3_rd_en : in std_logic;
- p3_rd_data : out std_logic_vector(31 DOWNTO 0);
- p3_rd_full : out std_logic;
- p3_rd_empty : out std_logic;
- p3_rd_count : out std_logic_vector(6 DOWNTO 0);
- p3_rd_overflow : out std_logic;
- p3_rd_error : out std_logic;
- p4_arb_en : in std_logic;
- p4_cmd_clk : in std_logic;
- p4_cmd_en : in std_logic;
- p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
- p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
- p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
- p4_cmd_empty : out std_logic;
- p4_cmd_full : out std_logic;
- p4_wr_clk : in std_logic;
- p4_wr_en : in std_logic;
- p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
- p4_wr_data : in std_logic_vector(31 DOWNTO 0);
- p4_wr_full : out std_logic;
- p4_wr_empty : out std_logic;
- p4_wr_count : out std_logic_vector(6 DOWNTO 0);
- p4_wr_underrun : out std_logic;
- p4_wr_error : out std_logic;
- p4_rd_clk : in std_logic;
- p4_rd_en : in std_logic;
- p4_rd_data : out std_logic_vector(31 DOWNTO 0);
- p4_rd_full : out std_logic;
- p4_rd_empty : out std_logic;
- p4_rd_count : out std_logic_vector(6 DOWNTO 0);
- p4_rd_overflow : out std_logic;
- p4_rd_error : out std_logic;
- p5_arb_en : in std_logic;
- p5_cmd_clk : in std_logic;
- p5_cmd_en : in std_logic;
- p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
- p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
- p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
- p5_cmd_empty : out std_logic;
- p5_cmd_full : out std_logic;
- p5_wr_clk : in std_logic;
- p5_wr_en : in std_logic;
- p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
- p5_wr_data : in std_logic_vector(31 DOWNTO 0);
- p5_wr_full : out std_logic;
- p5_wr_empty : out std_logic;
- p5_wr_count : out std_logic_vector(6 DOWNTO 0);
- p5_wr_underrun : out std_logic;
- p5_wr_error : out std_logic;
- p5_rd_clk : in std_logic;
- p5_rd_en : in std_logic;
- p5_rd_data : out std_logic_vector(31 DOWNTO 0);
- p5_rd_full : out std_logic;
- p5_rd_empty : out std_logic;
- p5_rd_count : out std_logic_vector(6 DOWNTO 0);
- p5_rd_overflow : out std_logic;
- p5_rd_error : out std_logic;
-
- mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
- mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
- mcbx_dram_ras_n : out std_logic;
- mcbx_dram_cas_n : out std_logic;
- mcbx_dram_we_n : out std_logic;
- mcbx_dram_cke : out std_logic;
- mcbx_dram_clk : out std_logic;
- mcbx_dram_clk_n : out std_logic;
- mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
- mcbx_dram_dqs : inout std_logic;
- mcbx_dram_dqs_n : inout std_logic;
- mcbx_dram_udqs : inout std_logic;
- mcbx_dram_udqs_n : inout std_logic;
- mcbx_dram_udm : out std_logic;
- mcbx_dram_ldm : out std_logic;
- mcbx_dram_odt : out std_logic;
- mcbx_dram_ddr3_rst : out std_logic;
- calib_recal : in std_logic;
- rzq : inout std_logic;
- zio : inout std_logic;
- ui_read : in std_logic;
- ui_add : in std_logic;
- ui_cs : in std_logic;
- ui_clk : in std_logic;
- ui_sdi : in std_logic;
- ui_addr : in std_logic_vector(4 DOWNTO 0);
- ui_broadcast : in std_logic;
- ui_drp_update : in std_logic;
- ui_done_cal : in std_logic;
- ui_cmd : in std_logic;
- ui_cmd_in : in std_logic;
- ui_cmd_en : in std_logic;
- ui_dqcount : in std_logic_vector(3 DOWNTO 0);
- ui_dq_lower_dec : in std_logic;
- ui_dq_lower_inc : in std_logic;
- ui_dq_upper_dec : in std_logic;
- ui_dq_upper_inc : in std_logic;
- ui_udqs_inc : in std_logic;
- ui_udqs_dec : in std_logic;
- ui_ldqs_inc : in std_logic;
- ui_ldqs_dec : in std_logic;
- uo_data : out std_logic_vector(7 DOWNTO 0);
- uo_data_valid : out std_logic;
- uo_done_cal : out std_logic;
- uo_cmd_ready_in : out std_logic;
- uo_refrsh_flag : out std_logic;
- uo_cal_start : out std_logic;
- uo_sdo : out std_logic;
- status : out std_logic_vector(31 DOWNTO 0);
- selfrefresh_enter : in std_logic;
- selfrefresh_mode : out std_logic
- );
-end component;
-
-signal uo_data : std_logic_vector(7 downto 0);
-
- constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "111111";
-
-constant C_PORT_CONFIG : string := "B32_B32_W32_R32_W32_R32";
-
-
-constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_0(2 downto 0) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(14 downto 12) & C_ARB_TIME_SLOT_0(17 downto 15));
-constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_1(2 downto 0) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(14 downto 12) & C_ARB_TIME_SLOT_1(17 downto 15));
-constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_2(2 downto 0) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(14 downto 12) & C_ARB_TIME_SLOT_2(17 downto 15));
-constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_3(2 downto 0) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(14 downto 12) & C_ARB_TIME_SLOT_3(17 downto 15));
-constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_4(2 downto 0) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(14 downto 12) & C_ARB_TIME_SLOT_4(17 downto 15));
-constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_5(2 downto 0) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(14 downto 12) & C_ARB_TIME_SLOT_5(17 downto 15));
-constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_6(2 downto 0) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(14 downto 12) & C_ARB_TIME_SLOT_6(17 downto 15));
-constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_7(2 downto 0) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(14 downto 12) & C_ARB_TIME_SLOT_7(17 downto 15));
-constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_8(2 downto 0) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(14 downto 12) & C_ARB_TIME_SLOT_8(17 downto 15));
-constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_9(2 downto 0) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(14 downto 12) & C_ARB_TIME_SLOT_9(17 downto 15));
-constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_10(2 downto 0) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(14 downto 12) & C_ARB_TIME_SLOT_10(17 downto 15));
-constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_11(2 downto 0) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(14 downto 12) & C_ARB_TIME_SLOT_11(17 downto 15));
-
-
-constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
-constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000";
-constant C_SKIP_DYN_IN_TERM : integer := 1;
-
-constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
-constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
-constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
-
-signal status : std_logic_vector(31 downto 0);
-signal uo_data_valid : std_logic;
-signal uo_cmd_ready_in : std_logic;
-signal uo_refrsh_flag : std_logic;
-signal uo_cal_start : std_logic;
-signal uo_sdo : std_logic;
-signal mcb3_zio : std_logic;
-
-
-attribute X_CORE_INFO : string;
-attribute X_CORE_INFO of acch : architecture IS
- "mig_v3_5_ddr_s6, Coregen 12.2";
-
-attribute CORE_GENERATION_INFO : string;
-attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr_s6,mig_v3_5,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR_SDRAM,CLK_PERIOD=5000, MEMORY_PART=mt46v32m16xx-5b-it, OUTPUT_DRV=FULL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1_Port2_Port3_Port4_Port5, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=UNCALIB_TERM, DATA_TERMINATION=50 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
-
-begin
-
-
-memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
-generic map
- (
- C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
- C_P0_MASK_SIZE => C_P0_MASK_SIZE,
- C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
- C_P1_MASK_SIZE => C_P1_MASK_SIZE,
- C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
-
- C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
- C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
- C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
- C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
- C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
- C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
- C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
- C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
- C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
- C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
- C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
- C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
- C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
-
- C_PORT_CONFIG => C_PORT_CONFIG,
- C_PORT_ENABLE => C_PORT_ENABLE,
-
- C_MEM_TRAS => C_MEM_TRAS,
- C_MEM_TRCD => C_MEM_TRCD,
- C_MEM_TREFI => C_MEM_TREFI,
- C_MEM_TRFC => C_MEM_TRFC,
- C_MEM_TRP => C_MEM_TRP,
- C_MEM_TWR => C_MEM_TWR,
- C_MEM_TRTP => C_MEM_TRTP,
- C_MEM_TWTR => C_MEM_TWTR,
-
- C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
- C_NUM_DQ_PINS => C_NUM_DQ_PINS,
- C_MEM_TYPE => C_MEM_TYPE,
- C_MEM_DENSITY => C_MEM_DENSITY,
- C_MEM_BURST_LEN => C_MEM_BURST_LEN,
- C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
- C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
- C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
- C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
-
- C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
- C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
- C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
- C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
- C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
-
- C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
- C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
- C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
- C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
- C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
- C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
- C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
- C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
- C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
- C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
- C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
-
- C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
- C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
- C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
- C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
- C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
-
- C_SIMULATION => C_SIMULATION,
- C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
- C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
- C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
- C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
-
- LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
- UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
- LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
- UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
- DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
- DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
- DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
- DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
- DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
- DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
- DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
- DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
- DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
- DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
- DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
- DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
- DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
- DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
- DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
- DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
- )
-
-port map
-(
- sys_rst => async_rst,
- sysclk_2x => sysclk_2x,
- sysclk_2x_180 => sysclk_2x_180,
- pll_ce_0 => pll_ce_0,
- pll_ce_90 => pll_ce_90,
- pll_lock => pll_lock,
- mcbx_dram_addr => mcb3_dram_a,
- mcbx_dram_ba => mcb3_dram_ba,
- mcbx_dram_ras_n => mcb3_dram_ras_n,
- mcbx_dram_cas_n => mcb3_dram_cas_n,
- mcbx_dram_we_n => mcb3_dram_we_n,
- mcbx_dram_cke => mcb3_dram_cke,
- mcbx_dram_clk => mcb3_dram_ck,
- mcbx_dram_clk_n => mcb3_dram_ck_n,
- mcbx_dram_dq => mcb3_dram_dq,
- mcbx_dram_odt => open,
- mcbx_dram_ldm => mcb3_dram_dm,
- mcbx_dram_udm => mcb3_dram_udm,
- mcbx_dram_dqs => mcb3_dram_dqs,
- mcbx_dram_dqs_n => open,
- mcbx_dram_udqs => mcb3_dram_udqs,
- mcbx_dram_udqs_n => open,
- mcbx_dram_ddr3_rst => open,
- calib_recal => '0',
- rzq => mcb3_rzq,
- zio => mcb3_zio,
- ui_read => '0',
- ui_add => '0',
- ui_cs => '0',
- ui_clk => mcb_drp_clk,
- ui_sdi => '0',
- ui_addr => (others => '0'),
- ui_broadcast => '0',
- ui_drp_update => '0',
- ui_done_cal => '1',
- ui_cmd => '0',
- ui_cmd_in => '0',
- ui_cmd_en => '0',
- ui_dqcount => (others => '0'),
- ui_dq_lower_dec => '0',
- ui_dq_lower_inc => '0',
- ui_dq_upper_dec => '0',
- ui_dq_upper_inc => '0',
- ui_udqs_inc => '0',
- ui_udqs_dec => '0',
- ui_ldqs_inc => '0',
- ui_ldqs_dec => '0',
- uo_data => uo_data,
- uo_data_valid => uo_data_valid,
- uo_done_cal => calib_done,
- uo_cmd_ready_in => uo_cmd_ready_in,
- uo_refrsh_flag => uo_refrsh_flag,
- uo_cal_start => uo_cal_start,
- uo_sdo => uo_sdo,
- status => status,
- selfrefresh_enter => '0',
- selfrefresh_mode => selfrefresh_mode,
-
-
- p0_arb_en => '1',
- p0_cmd_clk => p0_cmd_clk,
- p0_cmd_en => p0_cmd_en,
- p0_cmd_instr => p0_cmd_instr,
- p0_cmd_bl => p0_cmd_bl,
- p0_cmd_byte_addr => p0_cmd_byte_addr,
- p0_cmd_empty => p0_cmd_empty,
- p0_cmd_full => p0_cmd_full,
- p0_wr_clk => p0_wr_clk,
- p0_wr_en => p0_wr_en,
- p0_wr_mask => p0_wr_mask,
- p0_wr_data => p0_wr_data,
- p0_wr_full => p0_wr_full,
- p0_wr_empty => p0_wr_empty,
- p0_wr_count => p0_wr_count,
- p0_wr_underrun => p0_wr_underrun,
- p0_wr_error => p0_wr_error,
- p0_rd_clk => p0_rd_clk,
- p0_rd_en => p0_rd_en,
- p0_rd_data => p0_rd_data,
- p0_rd_full => p0_rd_full,
- p0_rd_empty => p0_rd_empty,
- p0_rd_count => p0_rd_count,
- p0_rd_overflow => p0_rd_overflow,
- p0_rd_error => p0_rd_error,
- p1_arb_en => '1',
- p1_cmd_clk => p1_cmd_clk,
- p1_cmd_en => p1_cmd_en,
- p1_cmd_instr => p1_cmd_instr,
- p1_cmd_bl => p1_cmd_bl,
- p1_cmd_byte_addr => p1_cmd_byte_addr,
- p1_cmd_empty => p1_cmd_empty,
- p1_cmd_full => p1_cmd_full,
- p1_wr_clk => p1_wr_clk,
- p1_wr_en => p1_wr_en,
- p1_wr_mask => p1_wr_mask,
- p1_wr_data => p1_wr_data,
- p1_wr_full => p1_wr_full,
- p1_wr_empty => p1_wr_empty,
- p1_wr_count => p1_wr_count,
- p1_wr_underrun => p1_wr_underrun,
- p1_wr_error => p1_wr_error,
- p1_rd_clk => p1_rd_clk,
- p1_rd_en => p1_rd_en,
- p1_rd_data => p1_rd_data,
- p1_rd_full => p1_rd_full,
- p1_rd_empty => p1_rd_empty,
- p1_rd_count => p1_rd_count,
- p1_rd_overflow => p1_rd_overflow,
- p1_rd_error => p1_rd_error,
- p2_arb_en => '1',
- p2_cmd_clk => p2_cmd_clk,
- p2_cmd_en => p2_cmd_en,
- p2_cmd_instr => p2_cmd_instr,
- p2_cmd_bl => p2_cmd_bl,
- p2_cmd_byte_addr => p2_cmd_byte_addr,
- p2_cmd_empty => p2_cmd_empty,
- p2_cmd_full => p2_cmd_full,
- p2_rd_clk => '0',
- p2_rd_en => '0',
- p2_rd_data => open,
- p2_rd_full => open,
- p2_rd_empty => open,
- p2_rd_count => open,
- p2_rd_overflow => open,
- p2_rd_error => open,
- p2_wr_clk => p2_wr_clk,
- p2_wr_en => p2_wr_en,
- p2_wr_mask => p2_wr_mask,
- p2_wr_data => p2_wr_data,
- p2_wr_full => p2_wr_full,
- p2_wr_empty => p2_wr_empty,
- p2_wr_count => p2_wr_count,
- p2_wr_underrun => p2_wr_underrun,
- p2_wr_error => p2_wr_error,
- p3_arb_en => '1',
- p3_cmd_clk => p3_cmd_clk,
- p3_cmd_en => p3_cmd_en,
- p3_cmd_instr => p3_cmd_instr,
- p3_cmd_bl => p3_cmd_bl,
- p3_cmd_byte_addr => p3_cmd_byte_addr,
- p3_cmd_empty => p3_cmd_empty,
- p3_cmd_full => p3_cmd_full,
- p3_rd_clk => p3_rd_clk,
- p3_rd_en => p3_rd_en,
- p3_rd_data => p3_rd_data,
- p3_rd_full => p3_rd_full,
- p3_rd_empty => p3_rd_empty,
- p3_rd_count => p3_rd_count,
- p3_rd_overflow => p3_rd_overflow,
- p3_rd_error => p3_rd_error,
- p3_wr_clk => '0',
- p3_wr_en => '0',
- p3_wr_mask => (others => '0'),
- p3_wr_data => (others => '0'),
- p3_wr_full => open,
- p3_wr_empty => open,
- p3_wr_count => open,
- p3_wr_underrun => open,
- p3_wr_error => open,
- p4_arb_en => '1',
- p4_cmd_clk => p4_cmd_clk,
- p4_cmd_en => p4_cmd_en,
- p4_cmd_instr => p4_cmd_instr,
- p4_cmd_bl => p4_cmd_bl,
- p4_cmd_byte_addr => p4_cmd_byte_addr,
- p4_cmd_empty => p4_cmd_empty,
- p4_cmd_full => p4_cmd_full,
- p4_rd_clk => '0',
- p4_rd_en => '0',
- p4_rd_data => open,
- p4_rd_full => open,
- p4_rd_empty => open,
- p4_rd_count => open,
- p4_rd_overflow => open,
- p4_rd_error => open,
- p4_wr_clk => p4_wr_clk,
- p4_wr_en => p4_wr_en,
- p4_wr_mask => p4_wr_mask,
- p4_wr_data => p4_wr_data,
- p4_wr_full => p4_wr_full,
- p4_wr_empty => p4_wr_empty,
- p4_wr_count => p4_wr_count,
- p4_wr_underrun => p4_wr_underrun,
- p4_wr_error => p4_wr_error,
- p5_arb_en => '1',
- p5_cmd_clk => p5_cmd_clk,
- p5_cmd_en => p5_cmd_en,
- p5_cmd_instr => p5_cmd_instr,
- p5_cmd_bl => p5_cmd_bl,
- p5_cmd_byte_addr => p5_cmd_byte_addr,
- p5_cmd_empty => p5_cmd_empty,
- p5_cmd_full => p5_cmd_full,
- p5_rd_clk => p5_rd_clk,
- p5_rd_en => p5_rd_en,
- p5_rd_data => p5_rd_data,
- p5_rd_full => p5_rd_full,
- p5_rd_empty => p5_rd_empty,
- p5_rd_count => p5_rd_count,
- p5_rd_overflow => p5_rd_overflow,
- p5_rd_error => p5_rd_error,
- p5_wr_clk => '0',
- p5_wr_en => '0',
- p5_wr_mask => (others => '0'),
- p5_wr_data => (others => '0'),
- p5_wr_full => open,
- p5_wr_empty => open,
- p5_wr_count => open,
- p5_wr_underrun => open,
- p5_wr_error => open
-);
-
-
-
-end architecture;
-
Index: ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd (nonexistent)
@@ -1,6943 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version: %version
--- \ \ Application: MIG
--- / / Filename: mcb_raw_wrapper.v
--- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:37 $
--- \ \ / \ Date Created: Thu June 24 2008
--- \___\/\___\
---
---Device: Spartan6
---Design Name: DDR/DDR2/DDR3/LPDDR
---Purpose:
---Reference:
--- This module is the intialization control logic of the memory interface.
--- All commands are issued from here acoording to the burst, CAS Latency and
--- the user commands.
---
--- Revised History:
--- Rev 1.1 - added port_enable assignment for all configurations and rearrange
--- assignment siganls according to port number
--- - added timescale directive -SN 7-28-08
--- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
--- 15 -SN 7-28-08
--- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
--- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
--- For now tb need to force the signals inside the MCB and Wrapper
--- until a glbl.v is ready. Not sure how to do this in NCVerilog
--- flow. -SN 7-28-08
---
--- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
--- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
--- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
--- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
--- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
--- delay_we_90 ,delay_address,delay_ba_90 =
--- --removed :assign #50 delay_dqnum = dqnum;
--- --removed :assign #50 delay_dqpum = dqpum;
--- --removed :assign #50 delay_dqnlm = dqnlm;
--- --removed :assign #50 delay_dqplm = dqplm;
--- --removed : delay_dqsIO_w_en_90_n
--- --removed : delay_dqsIO_w_en_90_p
--- --removed : delay_dqsIO_w_en_0
--- -- corrected spelling error: C_MEM_RTRAS
--- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
--- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
--- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
--- -- connection has been updated
--- Rev 1.8 -- update memory parameter equations. 1-30_2009
--- -- added portion of Soft IP
--- -- CAL_CLK_DIV is not used but MCB still has it
--- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
--- Rev 1.10 -- changed the backend connection so that Simulation will work while
--- sw tools try to fix the model issues. 2-3-2009
--- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
--- It is acutally 180 degree difference.
--- Rev 1.11 -- Added MCB_Soft_Calibration_top.
--- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
--- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
--- Rev 1.14 -- Added minium condition for tRTP valud/
--- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
--- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
--- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
--- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
--- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
--- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
--- Dynamic DQS calibration in Soft Calibration module.
--- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
--- RTT value is set to "disabled"
--- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
--- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
--- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
--- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
---*************************************************************************************************************************
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
-library unisim;
-use unisim.vcomponents.all;
-
-entity mcb_raw_wrapper is
-generic(
- C_MEMCLK_PERIOD : integer := 2500;
- C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
-
- C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
-
- C_ARB_NUM_TIME_SLOTS : integer := 12;
- C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
- C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
- C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
- C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
- C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
- C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
- C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
- C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
- C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
- C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
- C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
- C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
- C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
-
-
- C_MEM_TRAS : integer := 45000;
- C_MEM_TRCD : integer := 12500;
- C_MEM_TREFI : integer := 7800;
- C_MEM_TRFC : integer := 127500;
- C_MEM_TRP : integer := 12500;
- C_MEM_TWR : integer := 15000;
- C_MEM_TRTP : integer := 7500;
- C_MEM_TWTR : integer := 7500;
-
- C_NUM_DQ_PINS : integer := 8;
- C_MEM_TYPE : string := "DDR3";
- C_MEM_DENSITY : string := "512M";
- C_MEM_BURST_LEN : integer := 8;
-
- C_MEM_CAS_LATENCY : integer := 4;
- C_MEM_ADDR_WIDTH : integer := 13;
- C_MEM_BANKADDR_WIDTH : integer := 3;
- C_MEM_NUM_COL_BITS : integer := 11;
-
- C_MEM_DDR3_CAS_LATENCY : integer := 7;
- C_MEM_MOBILE_PA_SR : string := "FULL";
- C_MEM_DDR1_2_ODS : string := "FULL";
- C_MEM_DDR3_ODS : string := "DIV6";
- C_MEM_DDR2_RTT : string := "50OHMS";
- C_MEM_DDR3_RTT : string := "DIV2";
- C_MEM_MDDR_ODS : string := "FULL";
-
- C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
- C_MEM_DDR2_3_PA_SR : string := "OFF";
- C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
-
- C_MEM_DDR3_AUTO_SR : string := "ENABLED";
- C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
- C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
- C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
-
- C_MC_CALIB_BYPASS : string := "NO";
- C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
- C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
-
- C_CALIB_SOFT_IP : string := "TRUE";
- C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
- C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
- C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
- C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
-
-
---- ADDED for 1.0 silicon support to bypass Calibration //////
--- 07-10-09 chipl
---////////////////////////////////////////////////////////////
- LDQSP_TAP_DELAY_VAL : integer := 0;
- UDQSP_TAP_DELAY_VAL : integer := 0;
- LDQSN_TAP_DELAY_VAL : integer := 0;
- UDQSN_TAP_DELAY_VAL : integer := 0;
- DQ0_TAP_DELAY_VAL : integer := 0;
- DQ1_TAP_DELAY_VAL : integer := 0;
- DQ2_TAP_DELAY_VAL : integer := 0;
- DQ3_TAP_DELAY_VAL : integer := 0;
- DQ4_TAP_DELAY_VAL : integer := 0;
- DQ5_TAP_DELAY_VAL : integer := 0;
- DQ6_TAP_DELAY_VAL : integer := 0;
- DQ7_TAP_DELAY_VAL : integer := 0;
- DQ8_TAP_DELAY_VAL : integer := 0;
- DQ9_TAP_DELAY_VAL : integer := 0;
- DQ10_TAP_DELAY_VAL : integer := 0;
- DQ11_TAP_DELAY_VAL : integer := 0;
- DQ12_TAP_DELAY_VAL : integer := 0;
- DQ13_TAP_DELAY_VAL : integer := 0;
- DQ14_TAP_DELAY_VAL : integer := 0;
- DQ15_TAP_DELAY_VAL : integer := 0;
-
- C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
- C_MC_CALIBRATION_CLK_DIV : integer := 1;
- C_MC_CALIBRATION_MODE : string := "CALIBRATION";
- C_MC_CALIBRATION_DELAY : string := "HALF";
-
- C_P0_MASK_SIZE : integer := 4;
- C_P0_DATA_PORT_SIZE : integer := 32;
- C_P1_MASK_SIZE : integer := 4;
- C_P1_DATA_PORT_SIZE : integer := 32
- );
- PORT (
-
- sysclk_2x : in std_logic;
- sysclk_2x_180 : in std_logic;
- pll_ce_0 : in std_logic;
- pll_ce_90 : in std_logic;
- pll_lock : in std_logic;
- sys_rst : in std_logic;
-
- p0_arb_en : in std_logic;
- p0_cmd_clk : in std_logic;
- p0_cmd_en : in std_logic;
- p0_cmd_instr : in std_logic_vector(2 downto 0);
- p0_cmd_bl : in std_logic_vector(5 downto 0);
- p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p0_cmd_empty : out std_logic;
- p0_cmd_full : out std_logic;
-
- p0_wr_clk : in std_logic;
- p0_wr_en : in std_logic;
- p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
- p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_wr_full : out std_logic;
- p0_wr_empty : out std_logic;
- p0_wr_count : out std_logic_vector(6 downto 0);
- p0_wr_underrun : out std_logic;
- p0_wr_error : out std_logic;
-
- p0_rd_clk : in std_logic;
- p0_rd_en : in std_logic;
- p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
- p0_rd_full : out std_logic;
- p0_rd_empty : out std_logic;
- p0_rd_count : out std_logic_vector(6 downto 0);
- p0_rd_overflow : out std_logic;
- p0_rd_error : out std_logic;
-
- p1_arb_en : in std_logic;
- p1_cmd_clk : in std_logic;
- p1_cmd_en : in std_logic;
- p1_cmd_instr : in std_logic_vector(2 downto 0);
- p1_cmd_bl : in std_logic_vector(5 downto 0);
- p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p1_cmd_empty : out std_logic;
- p1_cmd_full : out std_logic;
- p1_wr_clk : in std_logic;
- p1_wr_en : in std_logic;
- p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
- p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_wr_full : out std_logic;
- p1_wr_empty : out std_logic;
- p1_wr_count : out std_logic_vector(6 downto 0);
- p1_wr_underrun : out std_logic;
- p1_wr_error : out std_logic;
- p1_rd_clk : in std_logic;
- p1_rd_en : in std_logic;
- p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
- p1_rd_full : out std_logic;
- p1_rd_empty : out std_logic;
- p1_rd_count : out std_logic_vector(6 downto 0);
- p1_rd_overflow : out std_logic;
- p1_rd_error : out std_logic;
-
- p2_arb_en : in std_logic;
- p2_cmd_clk : in std_logic;
- p2_cmd_en : in std_logic;
- p2_cmd_instr : in std_logic_vector(2 downto 0);
- p2_cmd_bl : in std_logic_vector(5 downto 0);
- p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p2_cmd_empty : out std_logic;
- p2_cmd_full : out std_logic;
- p2_wr_clk : in std_logic;
- p2_wr_en : in std_logic;
- p2_wr_mask : in std_logic_vector(3 downto 0);
- p2_wr_data : in std_logic_vector(31 downto 0);
- p2_wr_full : out std_logic;
- p2_wr_empty : out std_logic;
- p2_wr_count : out std_logic_vector(6 downto 0);
- p2_wr_underrun : out std_logic;
- p2_wr_error : out std_logic;
- p2_rd_clk : in std_logic;
- p2_rd_en : in std_logic;
- p2_rd_data : out std_logic_vector(31 downto 0);
- p2_rd_full : out std_logic;
- p2_rd_empty : out std_logic;
- p2_rd_count : out std_logic_vector(6 downto 0);
- p2_rd_overflow : out std_logic;
- p2_rd_error : out std_logic;
-
- p3_arb_en : in std_logic;
- p3_cmd_clk : in std_logic;
- p3_cmd_en : in std_logic;
- p3_cmd_instr : in std_logic_vector(2 downto 0);
- p3_cmd_bl : in std_logic_vector(5 downto 0);
- p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p3_cmd_empty : out std_logic;
- p3_cmd_full : out std_logic;
- p3_wr_clk : in std_logic;
- p3_wr_en : in std_logic;
- p3_wr_mask : in std_logic_vector(3 downto 0);
- p3_wr_data : in std_logic_vector(31 downto 0);
- p3_wr_full : out std_logic;
- p3_wr_empty : out std_logic;
- p3_wr_count : out std_logic_vector(6 downto 0);
- p3_wr_underrun : out std_logic;
- p3_wr_error : out std_logic;
- p3_rd_clk : in std_logic;
- p3_rd_en : in std_logic;
- p3_rd_data : out std_logic_vector(31 downto 0);
- p3_rd_full : out std_logic;
- p3_rd_empty : out std_logic;
- p3_rd_count : out std_logic_vector(6 downto 0);
- p3_rd_overflow : out std_logic;
- p3_rd_error : out std_logic;
-
- p4_arb_en : in std_logic;
- p4_cmd_clk : in std_logic;
- p4_cmd_en : in std_logic;
- p4_cmd_instr : in std_logic_vector(2 downto 0);
- p4_cmd_bl : in std_logic_vector(5 downto 0);
- p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p4_cmd_empty : out std_logic;
- p4_cmd_full : out std_logic;
- p4_wr_clk : in std_logic;
- p4_wr_en : in std_logic;
- p4_wr_mask : in std_logic_vector(3 downto 0);
- p4_wr_data : in std_logic_vector(31 downto 0);
- p4_wr_full : out std_logic;
- p4_wr_empty : out std_logic;
- p4_wr_count : out std_logic_vector(6 downto 0);
- p4_wr_underrun : out std_logic;
- p4_wr_error : out std_logic;
- p4_rd_clk : in std_logic;
- p4_rd_en : in std_logic;
- p4_rd_data : out std_logic_vector(31 downto 0);
- p4_rd_full : out std_logic;
- p4_rd_empty : out std_logic;
- p4_rd_count : out std_logic_vector(6 downto 0);
- p4_rd_overflow : out std_logic;
- p4_rd_error : out std_logic;
-
- p5_arb_en : in std_logic;
- p5_cmd_clk : in std_logic;
- p5_cmd_en : in std_logic;
- p5_cmd_instr : in std_logic_vector(2 downto 0);
- p5_cmd_bl : in std_logic_vector(5 downto 0);
- p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
- p5_cmd_empty : out std_logic;
- p5_cmd_full : out std_logic;
- p5_wr_clk : in std_logic;
- p5_wr_en : in std_logic;
- p5_wr_mask : in std_logic_vector(3 downto 0);
- p5_wr_data : in std_logic_vector(31 downto 0);
- p5_wr_full : out std_logic;
- p5_wr_empty : out std_logic;
- p5_wr_count : out std_logic_vector(6 downto 0);
- p5_wr_underrun : out std_logic;
- p5_wr_error : out std_logic;
- p5_rd_clk : in std_logic;
- p5_rd_en : in std_logic;
- p5_rd_data : out std_logic_vector(31 downto 0);
- p5_rd_full : out std_logic;
- p5_rd_empty : out std_logic;
- p5_rd_count : out std_logic_vector(6 downto 0);
- p5_rd_overflow : out std_logic;
- p5_rd_error : out std_logic;
-
- mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
- mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
- mcbx_dram_ras_n : out std_logic;
- mcbx_dram_cas_n : out std_logic;
- mcbx_dram_we_n : out std_logic;
- mcbx_dram_cke : out std_logic;
- mcbx_dram_clk : out std_logic;
- mcbx_dram_clk_n : out std_logic;
- mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
- mcbx_dram_dqs : INOUT std_logic;
- mcbx_dram_dqs_n : INOUT std_logic;
- mcbx_dram_udqs : INOUT std_logic;
- mcbx_dram_udqs_n : INOUT std_logic;
- mcbx_dram_udm : out std_logic;
- mcbx_dram_ldm : out std_logic;
- mcbx_dram_odt : out std_logic;
- mcbx_dram_ddr3_rst : out std_logic;
-
- calib_recal : in std_logic;
- rzq : INOUT std_logic;
- zio : INOUT std_logic;
- ui_read : in std_logic;
- ui_add : in std_logic;
- ui_cs : in std_logic;
- ui_clk : in std_logic;
- ui_sdi : in std_logic;
- ui_addr : in std_logic_vector(4 downto 0);
- ui_broadcast : in std_logic;
- ui_drp_update : in std_logic;
- ui_done_cal : in std_logic;
- ui_cmd : in std_logic;
- ui_cmd_in : in std_logic;
- ui_cmd_en : in std_logic;
- ui_dqcount : in std_logic_vector(3 downto 0);
- ui_dq_lower_dec : in std_logic;
- ui_dq_lower_inc : in std_logic;
- ui_dq_upper_dec : in std_logic;
- ui_dq_upper_inc : in std_logic;
- ui_udqs_inc : in std_logic;
- ui_udqs_dec : in std_logic;
- ui_ldqs_inc : in std_logic;
- ui_ldqs_dec : in std_logic;
- uo_data : out std_logic_vector(7 downto 0);
- uo_data_valid : out std_logic;
- uo_done_cal : out std_logic;
- uo_cmd_ready_in : out std_logic;
- uo_refrsh_flag : out std_logic;
- uo_cal_start : out std_logic;
- uo_sdo : out std_logic;
- status : out std_logic_vector(31 downto 0);
- selfrefresh_enter : in std_logic;
- selfrefresh_mode : out std_logic
- );
-end mcb_raw_wrapper;
-
- architecture aarch of mcb_raw_wrapper is
-
-component mcb_soft_calibration_top is
- generic (
- C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
- C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
- -- and does dynamic recal,
- -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
- -- no dynamic recal will be done
- SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
- SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
- SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
- C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
- C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
-
- );
- port (
- UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
- RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
- -- IODRP (sub)controller
- IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
- DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
- -- (MCB hard calib complete)
- PLL_LOCK : in std_logic; -- Lock signal from PLL
- SELFREFRESH_REQ : in std_logic;
- SELFREFRESH_MCB_MODE : in std_logic;
- SELFREFRESH_MCB_REQ : out std_logic;
- SELFREFRESH_MODE : out std_logic;
- MCB_UIADD : out std_logic; -- to MCB's UIADD port
- MCB_UISDI : out std_logic; -- to MCB's UISDI port
- MCB_UOSDO : in std_logic;
- MCB_UODONECAL : in std_logic;
- MCB_UOREFRSHFLAG : in std_logic;
- MCB_UICS : out std_logic;
- MCB_UIDRPUPDATE : out std_logic;
- MCB_UIBROADCAST : out std_logic;
- MCB_UIADDR : out std_logic_vector(4 downto 0);
- MCB_UICMDEN : out std_logic;
- MCB_UIDONECAL : out std_logic;
- MCB_UIDQLOWERDEC : out std_logic;
- MCB_UIDQLOWERINC : out std_logic;
- MCB_UIDQUPPERDEC : out std_logic;
- MCB_UIDQUPPERINC : out std_logic;
- MCB_UILDQSDEC : out std_logic;
- MCB_UILDQSINC : out std_logic;
- MCB_UIREAD : out std_logic;
- MCB_UIUDQSDEC : out std_logic;
- MCB_UIUDQSINC : out std_logic;
- MCB_RECAL : out std_logic;
- MCB_SYSRST : out std_logic;
- MCB_UICMD : out std_logic;
- MCB_UICMDIN : out std_logic;
- MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
- MCB_UODATA : in std_logic_vector(7 downto 0);
- MCB_UODATAVALID : in std_logic;
- MCB_UOCMDREADY : in std_logic;
- MCB_UO_CAL_START : in std_logic;
- RZQ_PIN : inout std_logic;
- ZIO_PIN : inout std_logic;
- CKE_Train : out std_logic
- );
-end component;
-
-constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
-constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
-constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
-constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
-constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
-
-constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
-
-constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
-constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
-constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-
-constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
-constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
-constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-
--- MIG always set the below ADD_LATENCY to zero
-constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
-constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
-constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-
--- convert the memory timing to memory clock units. I
-constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
-constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
-constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
-constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
-constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
-constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
-
- function cdiv return integer is
- begin
- if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
- return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
- else
- return (C_MEM_TRTP/C_MEMCLK_PERIOD);
- end if;
- end function cdiv;
-
-constant MEM_RTP_VAL1 : INTEGER := cdiv;
-
-
-function MEM_RTP_CYC1 return integer is
- begin
- if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
- return 4;
- else if(MEM_RTP_VAL1 < 2) then
- return 2;
- else
- return MEM_RTP_VAL1;
- end if;
- end if;
- end function MEM_RTP_CYC1;
-
-constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
-
-function MEM_WTR_CYC return integer is
- begin
- if (C_MEM_TYPE = "DDR") then
- return 2;
- elsif (C_MEM_TYPE = "DDR3") then
- return 4;
- elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
- return C_MEM_TWTR;
- elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
- return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
- elsif (C_MEM_TYPE = "DDR2")then
- return 2;
- else
- return 3;
- end if;
- end function MEM_WTR_CYC;
-
-constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
-
-function DDR2_WRT_RECOVERY_CYC return integer is
- begin
- if (not(C_MEM_TYPE = "DDR2")) then
- return 5;
- else
- return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
- end if;
- end function DDR2_WRT_RECOVERY_CYC;
-
-
-constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
-
-function DDR3_WRT_RECOVERY_CYC return integer is
- begin
- if (not(C_MEM_TYPE = "DDR3")) then
- return 5;
- else
- return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
- end if;
- end function DDR3_WRT_RECOVERY_CYC;
-
-constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
-----------------------------------------------------------------------------
--- signla Declarations
-----------------------------------------------------------------------------
-signal addr_in0 : std_logic_vector(31 downto 0);
-signal allzero : std_logic_vector(127 downto 0) := (others => '0');
-signal dqs_out_p : std_logic;
-signal dqs_out_n : std_logic;
-signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
-signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
-signal udqs_sys_p: std_logic;
-signal udqs_sys_n: std_logic;
-signal dqs_p : std_logic; -- open net now ?
-signal dqs_n : std_logic; -- open net now ?
-
--- IOI and IOB enable/tristate interface
-signal dqIO_w_en_0 : std_logic; --enable DQ pads
-signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
-signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
-
---memory chip control interface
-signal address_90 : std_logic_vector(14 downto 0);
-signal ba_90 : std_logic_vector(2 downto 0);
-signal ras_90 : std_logic;
-signal cas_90 : std_logic;
-signal we_90 : std_logic;
-signal cke_90 : std_logic;
-signal odt_90 : std_logic;
-signal rst_90 : std_logic;
-
--- calibration IDELAY control signals
-signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
-signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
-signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
-signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
-signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
-signal ioi_drp_add : std_logic; --DRP interface - serial address signal
-signal ioi_drp_broadcast : std_logic;
-signal ioi_drp_train : std_logic;
-
--- Calibration datacapture siganls
-signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
-signal dq_in_p : std_logic; --positive signal sent to calibration logic
-signal dq_in_n : std_logic; --negative signal sent to calibration logic
-signal cal_done: std_logic;
-
---DQS calibration interface
-signal udqs_n : std_logic;
-signal udqs_p : std_logic;
-signal udqs_dqocal_p : std_logic;
-signal udqs_dqocal_n : std_logic;
-
--- MUI enable interface
-signal df_en_n90 : std_logic;
-
---INTERNAL signal FOR DRP chain
--- IOI <-> MUI
-signal ioi_int_tmp : std_logic;
-
-signal dqo_n : std_logic_vector(15 downto 0);
-signal dqo_p : std_logic_vector(15 downto 0);
-signal dqnlm : std_logic;
-signal dqplm : std_logic;
-signal dqnum : std_logic;
-signal dqpum : std_logic;
-
--- IOI <-> IOB routes
-signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
-signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
-signal ioi_cas : std_logic;
-signal ioi_ck : std_logic;
-signal ioi_ckn : std_logic;
-signal ioi_cke : std_logic;
-signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
-signal ioi_dqs : std_logic;
-signal ioi_dqsn : std_logic;
-signal ioi_udqs : std_logic;
-signal ioi_udqsn : std_logic;
-signal ioi_odt : std_logic;
-signal ioi_ras : std_logic;
-signal ioi_rst : std_logic;
-signal ioi_we : std_logic;
-signal ioi_udm : std_logic;
-signal ioi_ldm : std_logic;
-
-signal in_dq : std_logic_vector(15 downto 0);
-signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
-signal in_dqs : std_logic;
-signal in_pre_dqsp : std_logic;
-signal in_pre_dqsn : std_logic;
-signal in_pre_udqsp : std_logic;
-signal in_pre_udqsn : std_logic;
-signal in_udqs : std_logic;
-
--- Memory tri-state control signals
-signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
-signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
-signal t_cas : std_logic;
-signal t_ck : std_logic;
-signal t_ckn : std_logic;
-signal t_cke : std_logic;
-signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
-signal t_dqs : std_logic;
-signal t_dqsn : std_logic;
-signal t_udqs : std_logic;
-signal t_udqsn : std_logic;
-signal t_odt : std_logic;
-signal t_ras : std_logic;
-signal t_rst : std_logic;
-signal t_we : std_logic;
-
-signal t_udm : std_logic;
-signal t_ldm : std_logic;
-
-signal idelay_dqs_ioi_s : std_logic;
-signal idelay_dqs_ioi_m : std_logic;
-signal idelay_udqs_ioi_s : std_logic;
-signal idelay_udqs_ioi_m : std_logic;
-
-signal dqs_pin : std_logic;
-signal udqs_pin : std_logic;
-
--- USER Interface signals
--- translated memory addresses
-signal p0_cmd_ra : std_logic_vector(14 downto 0);
-signal p0_cmd_ba : std_logic_vector(2 downto 0);
-signal p0_cmd_ca : std_logic_vector(11 downto 0);
-signal p1_cmd_ra : std_logic_vector(14 downto 0);
-signal p1_cmd_ba : std_logic_vector(2 downto 0);
-signal p1_cmd_ca : std_logic_vector(11 downto 0);
-signal p2_cmd_ra : std_logic_vector(14 downto 0);
-signal p2_cmd_ba : std_logic_vector(2 downto 0);
-signal p2_cmd_ca : std_logic_vector(11 downto 0);
-signal p3_cmd_ra : std_logic_vector(14 downto 0);
-signal p3_cmd_ba : std_logic_vector(2 downto 0);
-signal p3_cmd_ca : std_logic_vector(11 downto 0);
-signal p4_cmd_ra : std_logic_vector(14 downto 0);
-signal p4_cmd_ba : std_logic_vector(2 downto 0);
-signal p4_cmd_ca : std_logic_vector(11 downto 0);
-signal p5_cmd_ra : std_logic_vector(14 downto 0);
-signal p5_cmd_ba : std_logic_vector(2 downto 0);
-signal p5_cmd_ca : std_logic_vector(11 downto 0);
-
- -- user command wires mapped from logical ports to physical ports
-signal mig_p0_arb_en : std_logic;
-signal mig_p0_cmd_clk : std_logic;
-signal mig_p0_cmd_en : std_logic;
-signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
-signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
-signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
-
-signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
-signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
-signal mig_p0_cmd_empty : std_logic;
-signal mig_p0_cmd_full : std_logic;
-
-signal mig_p1_arb_en : std_logic;
-signal mig_p1_cmd_clk : std_logic;
-signal mig_p1_cmd_en : std_logic;
-signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
-signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
-signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
-
-signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
-signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
-signal mig_p1_cmd_empty : std_logic;
-signal mig_p1_cmd_full : std_logic;
-
-signal mig_p2_arb_en : std_logic;
-signal mig_p2_cmd_clk : std_logic;
-signal mig_p2_cmd_en : std_logic;
-signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
-signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
-signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
-
-signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
-signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
-signal mig_p2_cmd_empty : std_logic;
-signal mig_p2_cmd_full : std_logic;
-
-signal mig_p3_arb_en : std_logic;
-signal mig_p3_cmd_clk : std_logic;
-signal mig_p3_cmd_en : std_logic;
-signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
-signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
-signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
-
-signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
-signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
-signal mig_p3_cmd_empty : std_logic;
-signal mig_p3_cmd_full : std_logic;
-
-signal mig_p4_arb_en : std_logic;
-signal mig_p4_cmd_clk : std_logic;
-signal mig_p4_cmd_en : std_logic;
-signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
-signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
-signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
-
-signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
-signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
-signal mig_p4_cmd_empty : std_logic;
-signal mig_p4_cmd_full : std_logic;
-
-signal mig_p5_arb_en : std_logic;
-signal mig_p5_cmd_clk : std_logic;
-signal mig_p5_cmd_en : std_logic;
-signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
-signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
-signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
-
-signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
-signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
-signal mig_p5_cmd_empty : std_logic;
-signal mig_p5_cmd_full : std_logic;
-
-signal mig_p0_wr_clk : std_logic;
-signal mig_p0_rd_clk : std_logic;
-signal mig_p1_wr_clk : std_logic;
-signal mig_p1_rd_clk : std_logic;
-signal mig_p2_clk : std_logic;
-signal mig_p3_clk : std_logic;
-signal mig_p4_clk : std_logic;
-signal mig_p5_clk : std_logic;
-
-signal mig_p0_wr_en : std_logic;
-signal mig_p0_rd_en : std_logic;
-signal mig_p1_wr_en : std_logic;
-signal mig_p1_rd_en : std_logic;
-signal mig_p2_en : std_logic;
-signal mig_p3_en : std_logic;
-signal mig_p4_en : std_logic;
-signal mig_p5_en : std_logic;
-
-signal mig_p0_wr_data : std_logic_vector(31 downto 0);
-signal mig_p1_wr_data : std_logic_vector(31 downto 0);
-signal mig_p2_wr_data : std_logic_vector(31 downto 0);
-signal mig_p3_wr_data : std_logic_vector(31 downto 0);
-signal mig_p4_wr_data : std_logic_vector(31 downto 0);
-signal mig_p5_wr_data : std_logic_vector(31 downto 0);
-
-signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
-signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
-signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
-signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
-signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
-signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
-
-signal mig_p0_rd_data : std_logic_vector(31 downto 0);
-signal mig_p1_rd_data : std_logic_vector(31 downto 0);
-signal mig_p2_rd_data : std_logic_vector(31 downto 0);
-signal mig_p3_rd_data : std_logic_vector(31 downto 0);
-signal mig_p4_rd_data : std_logic_vector(31 downto 0);
-signal mig_p5_rd_data : std_logic_vector(31 downto 0);
-
-signal mig_p0_rd_overflow : std_logic;
-signal mig_p1_rd_overflow : std_logic;
-signal mig_p2_overflow : std_logic;
-signal mig_p3_overflow : std_logic;
-
-signal mig_p4_overflow : std_logic;
-signal mig_p5_overflow : std_logic;
-
-signal mig_p0_wr_underrun : std_logic;
-signal mig_p1_wr_underrun : std_logic;
-signal mig_p2_underrun : std_logic;
-signal mig_p3_underrun : std_logic;
-signal mig_p4_underrun : std_logic;
-signal mig_p5_underrun : std_logic;
-
-signal mig_p0_rd_error : std_logic;
-signal mig_p0_wr_error : std_logic;
-signal mig_p1_rd_error : std_logic;
-signal mig_p1_wr_error : std_logic;
-signal mig_p2_error : std_logic;
-signal mig_p3_error : std_logic;
-signal mig_p4_error : std_logic;
-signal mig_p5_error : std_logic;
-
-signal mig_p0_wr_count : std_logic_vector(6 downto 0);
-signal mig_p1_wr_count : std_logic_vector(6 downto 0);
-signal mig_p0_rd_count : std_logic_vector(6 downto 0);
-signal mig_p1_rd_count : std_logic_vector(6 downto 0);
-
-signal mig_p2_count : std_logic_vector(6 downto 0);
-signal mig_p3_count : std_logic_vector(6 downto 0);
-signal mig_p4_count : std_logic_vector(6 downto 0);
-signal mig_p5_count : std_logic_vector(6 downto 0);
-
-signal mig_p0_wr_full : std_logic;
-signal mig_p1_wr_full : std_logic;
-
-signal mig_p0_rd_empty : std_logic;
-signal mig_p1_rd_empty : std_logic;
-signal mig_p0_wr_empty : std_logic;
-signal mig_p1_wr_empty : std_logic;
-signal mig_p0_rd_full : std_logic;
-signal mig_p1_rd_full : std_logic;
-signal mig_p2_full : std_logic;
-signal mig_p3_full : std_logic;
-signal mig_p4_full : std_logic;
-signal mig_p5_full : std_logic;
-signal mig_p2_empty : std_logic;
-signal mig_p3_empty : std_logic;
-signal mig_p4_empty : std_logic;
-signal mig_p5_empty : std_logic;
-
--- SELFREESH control signal for suspend feature
-signal selfrefresh_mcb_enter : std_logic;
-signal selfrefresh_mcb_mode : std_logic;
-
-signal MCB_SYSRST : std_logic;
-signal ioclk0 : std_logic;
-signal ioclk90 : std_logic;
-signal hard_done_cal : std_logic;
-signal uo_data_int : std_logic_vector(7 downto 0);
-signal uo_data_valid_int : std_logic;
-signal uo_cmd_ready_in_int : std_logic;
-signal syn_uiclk_pll_lock : std_logic;
-signal int_sys_rst : std_logic;
-
---testing
-signal ioi_drp_update : std_logic;
-signal aux_sdi_sdo : std_logic_vector(7 downto 0);
-
-
- signal mcb_recal : std_logic;
- signal mcb_ui_read : std_logic;
- signal mcb_ui_add : std_logic;
- signal mcb_ui_cs : std_logic;
- signal mcb_ui_clk : std_logic;
- signal mcb_ui_sdi : std_logic;
- signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
- signal mcb_ui_broadcast : std_logic;
- signal mcb_ui_drp_update : std_logic;
- signal mcb_ui_done_cal : std_logic;
- signal mcb_ui_cmd : std_logic;
- signal mcb_ui_cmd_in : std_logic;
- signal mcb_ui_cmd_en : std_logic;
- signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
- signal mcb_ui_dq_lower_dec : std_logic;
- signal mcb_ui_dq_lower_inc : std_logic;
- signal mcb_ui_dq_upper_dec : std_logic;
- signal mcb_ui_dq_upper_inc : std_logic;
- signal mcb_ui_udqs_inc : std_logic;
- signal mcb_ui_udqs_dec : std_logic;
- signal mcb_ui_ldqs_inc : std_logic;
- signal mcb_ui_ldqs_dec : std_logic;
-
- signal DONE_SOFTANDHARD_CAL : std_logic;
-
-
- signal ck_shiftout0_1 : std_logic;
- signal ck_shiftout0_2 : std_logic;
- signal ck_shiftout1_3 : std_logic;
- signal ck_shiftout1_4 : std_logic;
-
- signal udm_oq : std_logic;
- signal udm_t : std_logic;
- signal ldm_oq : std_logic;
- signal ldm_t : std_logic;
- signal dqsp_oq : std_logic;
- signal dqsp_tq : std_logic;
- signal dqs_shiftout0_1 : std_logic;
- signal dqs_shiftout0_2 : std_logic;
- signal dqs_shiftout1_3 : std_logic;
- signal dqs_shiftout1_4 : std_logic;
-
- signal dqsn_oq : std_logic;
- signal dqsn_tq : std_logic;
-
- signal udqsp_oq : std_logic;
- signal udqsp_tq : std_logic;
- signal udqs_shiftout0_1 : std_logic;
- signal udqs_shiftout0_2 : std_logic;
- signal udqs_shiftout1_3 : std_logic;
- signal udqs_shiftout1_4 : std_logic;
-
- signal udqsn_oq : std_logic;
- signal udqsn_tq : std_logic;
-
- signal aux_sdi_out_dqsp : std_logic;
- signal aux_sdi_out_udqsp : std_logic;
- signal aux_sdi_out_udqsn : std_logic;
- signal aux_sdi_out_0 : std_logic;
- signal aux_sdi_out_1 : std_logic;
- signal aux_sdi_out_2 : std_logic;
- signal aux_sdi_out_3 : std_logic;
- signal aux_sdi_out_5 : std_logic;
- signal aux_sdi_out_6 : std_logic;
- signal aux_sdi_out_7 : std_logic;
- signal aux_sdi_out_9 : std_logic;
- signal aux_sdi_out_10 : std_logic;
- signal aux_sdi_out_11 : std_logic;
- signal aux_sdi_out_12 : std_logic;
- signal aux_sdi_out_13 : std_logic;
- signal aux_sdi_out_14 : std_logic;
- signal aux_sdi_out_15 : std_logic;
- signal aux_sdi_out_8 : std_logic;
- signal aux_sdi_out_dqsn : std_logic;
- signal aux_sdi_out_4 : std_logic;
- signal aux_sdi_out_udm : std_logic;
- signal aux_sdi_out_ldm : std_logic;
- signal uo_cal_start_int : std_logic;
-
- signal cke_train : std_logic;
- signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
- signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
-
- signal p0_wr_full_i : std_logic;
- signal p0_rd_empty_i : std_logic;
- signal p1_wr_full_i : std_logic;
- signal p1_rd_empty_i : std_logic;
- signal pllclk1 : std_logic_vector(1 downto 0);
- signal pllce1 : std_logic_vector(1 downto 0);
- signal uo_refrsh_flag_xhdl23 : std_logic;
- SIGNAL uo_sdo_xhdl24 : STD_LOGIC;
- signal Max_Value_Cal_Error : std_logic;
-
- attribute max_fanout : string;
- attribute syn_maxfan : integer;
- attribute max_fanout of int_sys_rst : signal is "1";
- attribute syn_maxfan of int_sys_rst : signal is 1;
-
-begin
- uo_cmd_ready_in <= uo_cmd_ready_in_int;
- uo_data_valid <= uo_data_valid_int;
- uo_data <= uo_data_int;
- uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
- uo_sdo <= uo_sdo_xhdl24;
-
- p0_wr_full <= p0_wr_full_i;
- p0_rd_empty <= p0_rd_empty_i;
- p1_wr_full <= p1_wr_full_i;
- p1_rd_empty <= p1_rd_empty_i;
- ioclk0 <= sysclk_2x;
- ioclk90 <= sysclk_2x_180;
- pllclk1 <= (ioclk90 & ioclk0);
- pllce1 <= (pll_ce_90 & pll_ce_0);
-
- -- Added 2/22 - Add flop to pll_lock status signal to improve timing
- process (ui_clk)
- begin
- if (ui_clk'event and ui_clk = '1') then
- syn_uiclk_pll_lock <= pll_lock;
- end if;
- end process;
-
- int_sys_rst <= sys_rst or not(syn_uiclk_pll_lock);
-
---Address Remapping
--- Byte Address remapping
---
--- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
--- column address remap for port 0
-
-x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
-x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-
--- port 0 address remapping
-
- x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
- p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
- p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
- end generate;
-
- x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
- end generate;
-
--- port 1 address remapping
-
- x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
- p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-
- x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
- x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
-
- end generate;
-
- -- port 2 address remapping
- x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
- p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
- x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
-
- end generate;
-
-
--- port 3 address remapping
- x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
- p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
- x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
- x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-
- x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
- x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
- end generate;
-
-
-
-
- -- port 4 address remapping
-
- x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
- p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
- x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
- x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
- end generate;
-
-
-
--- port 5 address remapping
- x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
- p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
- x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-
- x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
- end generate;
-
- x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
- end generate;
-end generate; --x16_addr_rbc
-
-x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-
-
- -- port 0 address remapping
-
-x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
-x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
- p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
-x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
- p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
- p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
-x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
- p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
- end generate;
-
-
-
-
-
--- port 1 address remapping
- x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
-x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
- p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
-x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
- p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
- p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
- end generate;
-
-x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
- p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
- end generate;
-
-
-
- -- port 2 address remapping
-x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
- end generate;
-
-x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
- p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
-x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
- p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
- p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
-x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
- p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
-
- end generate;
-
-
- -- port 3 address remapping
-x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
-x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
- p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
-x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
- p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
- p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
-x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
- p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
-
- end generate;
-
-
- -- port 4 address remapping
-x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
-x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
- p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
-x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
- p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
- end generate;
-
-x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
- p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
-x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
- p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
-
- end generate;
-
- -- port 5 address remapping
-x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
-
- end generate;
-
-x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
- p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
- end generate;
-
-x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
- p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
-
- end generate;
-
-x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
- p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
-
- end generate;
-
-x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
- p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
-
- end generate;
- end generate;--x16_addr_rbc_n
-end generate; --x16_addr
-
-
-
-
-
-
-x8_addr : if(C_NUM_DQ_PINS = 8) generate
-x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
--- port 0 address remapping
-
-x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
-
- end generate;
-
- x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
-
- end generate;
-
-
- x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
-
-
--- port 1 address remapping
- x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
-
- end generate;
-
- x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
-
- end generate;
-
-
- x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
-
- -- port 2 address remapping
- x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
-
- end generate;
-
- x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
-
- end generate;
-
-
- x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
-
-
--- port 3 address remapping
- x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
-
- end generate;
-
- x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
-
- end generate;
-
-
- x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
--- port 4 address remapping
- x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
-
- end generate;
-
- x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
-
- end generate;
-
-
- x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
-
- -- port 5 address remapping
- x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
-
- end generate;
-
- x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
-
- end generate;
-
-
- x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
- end generate; --x8_addr_rbc
-
-
-
-x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
- -- port 0 address remapping
- x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
- x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
- -- port 1 address remapping
- x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
- x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
---port 2 address remapping
- x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
- x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
- -- port 3 address remapping
- x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
- x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
-
--- port 4 address remapping
- x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
- p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
- end generate;
-
- x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
-
-
--- port 5 address remapping
- x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
- p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
-
- end generate;
-
- x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
-
- end generate;
-
- x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
-
- end generate;
-
-
- x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
-
- end generate;
-
- x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
-
- end generate;
- end generate; --x8_addr_rbc_n
- end generate; --x8_addr
-
-
-
-
-
-
-
-
-
-x4_addr : if(C_NUM_DQ_PINS = 4) generate
-x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-
--- port 0 address remapping
-x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
-
- end generate;
-
- x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
- end generate;
-
-
--- port 1 address remapping
-x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
-
- end generate;
-
- x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
- end generate;
-
-
--- port 2 address remapping
-x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
- end generate;
-
-
- x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
-
- end generate;
-
- x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
- end generate;
-
-
--- port 3 address remapping
-x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
- x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
- x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
-
- end generate;
-
- x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
- end generate;
-
-
-
-
-
-
- x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
- ) generate
--- port 4 address remapping
-
-x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
-x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
-x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
-x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
-x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
-
- end generate;
-
-x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
- end generate;
--- port 5 address remapping
-
-
-x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
-x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
-x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
- end generate;
-
-x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
-
-x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
-
- end generate;
-
-x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
- end generate;
- end generate; --x4_p4_p5
- end generate; --x4_addr_rbc
-
-
-
-
-x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-
--- port 0 address remapping
- x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
- end generate;
-
- x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
- end generate;
-
- x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
- end generate;
-
- x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
- end generate;
-
-
- x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
- end generate;
-
- x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
- end generate;
-
-
--- port 1 address remapping
- x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
- x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
-
- end generate;
-
-
- x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
- x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
--- port 2 address remapping
- x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
- x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
-
- end generate;
-
-
- x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
- x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
--- port 3 address remapping
- x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
- x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
-
- end generate;
-
-
- x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
- x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
-
- x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
- ) generate
--- port 4 address remapping
-
- x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
- x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
-
- end generate;
-
-
- x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
- x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
- end generate;
-
-
--- port 5 address remapping
-
- x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
- p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
- p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
-
- end generate;
-
- x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
- p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
-
-
- end generate;
-
- x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
- p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
-
-
- end generate;
-
-
- x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
- p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
- x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
- p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
-
-
- end generate;
-
-end generate; --x4_p4_p5_n
-
-end generate; --x4_addr_rbc_n
-end generate; --x4_addr
-
-
-
-
- -- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
-u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
- ) generate
-
- --synthesis translate_off
- -- PORT2
- process (p2_cmd_en,p2_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
- p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
- report "ERROR - Invalid Command for write only port 2";
- end if;
- end process;
-
- process (p2_cmd_en,p2_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
- p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
- report "ERROR - Invalid Command for read only port 2";
- end if;
- end process;
-
- -- PORT3
- process (p3_cmd_en,p3_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
- p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
- report "ERROR - Invalid Command for write only port 3";
- end if;
- end process;
-
- process (p3_cmd_en,p3_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
- p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
- report "ERROR - Invalid Command for read only port 3";
- end if;
- end process;
-
- -- PORT4
- process (p4_cmd_en,p4_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
- p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
- report "ERROR - Invalid Command for write only port 4";
- end if;
- end process;
-
- process (p4_cmd_en,p4_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
- p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
- report "ERROR - Invalid Command for read only port 4";
- end if;
- end process;
-
- -- PORT5
- process (p5_cmd_en,p5_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
- p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
- report "ERROR - Invalid Command for write only port 5";
- end if;
- end process;
-
- process (p5_cmd_en,p5_cmd_instr)
- begin
- if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
- p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
- report "ERROR - Invalid Command for read only port 5";
- end if;
- end process;
-
-
-
-
- --synthesis translate_on
-
-
- -- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
- -- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
- -- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
- --
-
- -- Inputs from Application CMD Port
-
- p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
-
- mig_p0_arb_en <= p0_arb_en ;
- mig_p0_cmd_clk <= p0_cmd_clk ;
- mig_p0_cmd_en <= p0_cmd_en ;
- mig_p0_cmd_ra <= p0_cmd_ra ;
- mig_p0_cmd_ba <= p0_cmd_ba ;
- mig_p0_cmd_ca <= p0_cmd_ca ;
- mig_p0_cmd_instr <= p0_cmd_instr;
- mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
- p0_cmd_empty <= mig_p0_cmd_empty;
- p0_cmd_full <= mig_p0_cmd_full ;
- end generate;
-
- p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
- mig_p0_arb_en <= '0';
- mig_p0_cmd_clk <= '0';
- mig_p0_cmd_en <= '0';
- mig_p0_cmd_ra <= (others => '0');
- mig_p0_cmd_ba <= (others => '0');
- mig_p0_cmd_ca <= (others => '0');
- mig_p0_cmd_instr <= (others => '0');
- mig_p0_cmd_bl <= (others => '0');
- p0_cmd_empty <= '0';
- p0_cmd_full <= '0';
-
- end generate;
-
- p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
- mig_p1_arb_en <= p1_arb_en ;
- mig_p1_cmd_clk <= p1_cmd_clk ;
- mig_p1_cmd_en <= p1_cmd_en ;
- mig_p1_cmd_ra <= p1_cmd_ra ;
- mig_p1_cmd_ba <= p1_cmd_ba ;
- mig_p1_cmd_ca <= p1_cmd_ca ;
- mig_p1_cmd_instr <= p1_cmd_instr;
- mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
- p1_cmd_empty <= mig_p1_cmd_empty;
- p1_cmd_full <= mig_p1_cmd_full ;
- end generate;
-
- p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
-
- mig_p1_arb_en <= '0';
- mig_p1_cmd_clk <= '0';
- mig_p1_cmd_en <= '0';
- mig_p1_cmd_ra <= (others => '0');
- mig_p1_cmd_ba <= (others => '0');
- mig_p1_cmd_ca <= (others => '0');
- mig_p1_cmd_instr <= (others => '0');
- mig_p1_cmd_bl <= (others => '0');
- p1_cmd_empty <= '0';
- p1_cmd_full <= '0';
- end generate;
-
-
- p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
- mig_p2_arb_en <= p2_arb_en ;
- mig_p2_cmd_clk <= p2_cmd_clk ;
- mig_p2_cmd_en <= p2_cmd_en ;
- mig_p2_cmd_ra <= p2_cmd_ra ;
- mig_p2_cmd_ba <= p2_cmd_ba ;
- mig_p2_cmd_ca <= p2_cmd_ca ;
- mig_p2_cmd_instr <= p2_cmd_instr;
- mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
-
- p2_cmd_empty <= mig_p2_cmd_empty;
- p2_cmd_full <= mig_p2_cmd_full ;
- end generate;
-
- p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
- mig_p2_arb_en <= '0';
- mig_p2_cmd_clk <= '0';
- mig_p2_cmd_en <= '0';
- mig_p2_cmd_ra <= (others => '0');
- mig_p2_cmd_ba <= (others => '0');
- mig_p2_cmd_ca <= (others => '0');
- mig_p2_cmd_instr <= (others => '0');
- mig_p2_cmd_bl <= (others => '0');
- p2_cmd_empty <= '0';
- p2_cmd_full <= '0';
- end generate;
-
- p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
-
- mig_p3_arb_en <= p3_arb_en ;
- mig_p3_cmd_clk <= p3_cmd_clk ;
- mig_p3_cmd_en <= p3_cmd_en ;
- mig_p3_cmd_ra <= p3_cmd_ra ;
- mig_p3_cmd_ba <= p3_cmd_ba ;
- mig_p3_cmd_ca <= p3_cmd_ca ;
- mig_p3_cmd_instr <= p3_cmd_instr;
- mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
- p3_cmd_empty <= mig_p3_cmd_empty;
- p3_cmd_full <= mig_p3_cmd_full ;
- end generate;
-
- p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
- mig_p3_arb_en <= '0';
- mig_p3_cmd_clk <= '0';
- mig_p3_cmd_en <= '0';
- mig_p3_cmd_ra <= (others => '0');
- mig_p3_cmd_ba <= (others => '0');
- mig_p3_cmd_ca <= (others => '0');
- mig_p3_cmd_instr <= (others => '0');
- mig_p3_cmd_bl <= (others => '0');
- p3_cmd_empty <= '0';
- p3_cmd_full <= '0';
- end generate;
-
-
- p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
-
- mig_p4_arb_en <= p4_arb_en ;
- mig_p4_cmd_clk <= p4_cmd_clk ;
- mig_p4_cmd_en <= p4_cmd_en ;
- mig_p4_cmd_ra <= p4_cmd_ra ;
- mig_p4_cmd_ba <= p4_cmd_ba ;
- mig_p4_cmd_ca <= p4_cmd_ca ;
- mig_p4_cmd_instr <= p4_cmd_instr;
- mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
-
- p4_cmd_empty <= mig_p4_cmd_empty;
- p4_cmd_full <= mig_p4_cmd_full ;
-end generate;
-
- p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
-
- mig_p4_arb_en <= '0';
- mig_p4_cmd_clk <= '0';
- mig_p4_cmd_en <= '0';
- mig_p4_cmd_ra <= (others => '0');
- mig_p4_cmd_ba <= (others => '0');
- mig_p4_cmd_ca <= (others => '0');
- mig_p4_cmd_instr <= (others => '0');
- mig_p4_cmd_bl <= (others => '0');
- p4_cmd_empty <= '0';
- p4_cmd_full <= '0';
-end generate;
-
- p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
- mig_p5_arb_en <= p5_arb_en ;
- mig_p5_cmd_clk <= p5_cmd_clk ;
- mig_p5_cmd_en <= p5_cmd_en ;
- mig_p5_cmd_ra <= p5_cmd_ra ;
- mig_p5_cmd_ba <= p5_cmd_ba ;
- mig_p5_cmd_ca <= p5_cmd_ca ;
- mig_p5_cmd_instr <= p5_cmd_instr;
- mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
-
- p5_cmd_empty <= mig_p5_cmd_empty;
- p5_cmd_full <= mig_p5_cmd_full ;
-
-end generate;
-
- p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
-
- mig_p5_arb_en <= '0';
- mig_p5_cmd_clk <= '0';
- mig_p5_cmd_en <= '0';
- mig_p5_cmd_ra <= (others => '0');
- mig_p5_cmd_ba <= (others => '0');
- mig_p5_cmd_ca <= (others => '0');
- mig_p5_cmd_instr <= (others => '0');
- mig_p5_cmd_bl <= (others => '0');
- p5_cmd_empty <= '0';
- p5_cmd_full <= '0';
-end generate;
-
-
-
-p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
- mig_p0_wr_clk <= p0_wr_clk;
- mig_p0_rd_clk <= p0_rd_clk;
- mig_p0_wr_en <= p0_wr_en;
- mig_p0_rd_en <= p0_rd_en;
- mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
- mig_p0_wr_data <= p0_wr_data(31 downto 0);
- p0_rd_data <= mig_p0_rd_data;
- p0_rd_full <= mig_p0_rd_full;
- p0_rd_empty_i <= mig_p0_rd_empty;
- p0_rd_error <= mig_p0_rd_error;
- p0_wr_error <= mig_p0_wr_error;
- p0_rd_overflow <= mig_p0_rd_overflow;
- p0_wr_underrun <= mig_p0_wr_underrun;
- p0_wr_empty <= mig_p0_wr_empty;
- p0_wr_full_i <= mig_p0_wr_full;
- p0_wr_count <= mig_p0_wr_count;
- p0_rd_count <= mig_p0_rd_count ;
-end generate;
-p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
- mig_p0_wr_clk <= '0';
- mig_p0_rd_clk <= '0';
- mig_p0_wr_en <= '0';
- mig_p0_rd_en <= '0';
- mig_p0_wr_mask <= (others => '0');
- mig_p0_wr_data <= (others => '0');
- p0_rd_data <= (others => '0');
- p0_rd_full <= '0';
- p0_rd_empty_i <= '0';
- p0_rd_error <= '0';
- p0_wr_error <= '0';
- p0_rd_overflow <= '0';
- p0_wr_underrun <= '0';
- p0_wr_empty <= '0';
- p0_wr_full_i <= '0';
- p0_wr_count <= (others => '0');
- p0_rd_count <= (others => '0');
-end generate;
-
-p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
-
- mig_p1_wr_clk <= p1_wr_clk;
- mig_p1_rd_clk <= p1_rd_clk;
- mig_p1_wr_en <= p1_wr_en;
- mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
- mig_p1_wr_data <= p1_wr_data(31 downto 0);
- mig_p1_rd_en <= p1_rd_en;
- p1_rd_data <= mig_p1_rd_data;
- p1_rd_empty_i <= mig_p1_rd_empty;
- p1_rd_full <= mig_p1_rd_full;
- p1_rd_error <= mig_p1_rd_error;
- p1_wr_error <= mig_p1_wr_error;
- p1_rd_overflow <= mig_p1_rd_overflow;
- p1_wr_underrun <= mig_p1_wr_underrun;
- p1_wr_empty <= mig_p1_wr_empty;
- p1_wr_full_i <= mig_p1_wr_full;
- p1_wr_count <= mig_p1_wr_count;
- p1_rd_count <= mig_p1_rd_count ;
-
-end generate;
-p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
-
- mig_p1_wr_clk <= '0';
- mig_p1_rd_clk <= '0';
- mig_p1_wr_en <= '0';
- mig_p1_wr_mask <= (others => '0');
- mig_p1_wr_data <= (others => '0');
- mig_p1_rd_en <= '0';
- p1_rd_data <= (others => '0');
- p1_rd_empty_i <= '0';
- p1_rd_full <= '0';
- p1_rd_error <= '0';
- p1_wr_error <= '0';
- p1_rd_overflow <= '0';
- p1_wr_underrun <= '0';
- p1_wr_empty <= '0';
- p1_wr_full_i <= '0';
- p1_wr_count <= (others => '0');
- p1_rd_count <= (others => '0');
-end generate;
-end generate;
-
-
-
-
---whenever PORT 2 is in Write mode
--- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
---u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
-
-u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
- ) generate
-
-p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
- mig_p2_clk <= p2_wr_clk;
- mig_p2_wr_data <= p2_wr_data(31 downto 0);
- mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
- mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
- p2_wr_error <= mig_p2_error;
- p2_wr_full <= mig_p2_full;
- p2_wr_empty <= mig_p2_empty;
- p2_wr_underrun <= mig_p2_underrun;
- p2_wr_count <= mig_p2_count ;-- wr port
- end generate;
-p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
- mig_p2_clk <= '0';
- mig_p2_wr_data <= (others => '0');
- mig_p2_wr_mask <= (others => '0');
- mig_p2_en <= '0';
- p2_wr_error <= '0';
- p2_wr_full <= '0';
- p2_wr_empty <= '0';
- p2_wr_underrun <= '0';
- p2_wr_count <= (others => '0');
-end generate;
- p2_rd_data <= (others => '0');
- p2_rd_overflow <= '0';
- p2_rd_error <= '0';
- p2_rd_full <= '0';
- p2_rd_empty <= '0';
- p2_rd_count <= (others => '0');
--- p2_rd_error <= '0';
- end generate;
---u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
-
-u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
-
- p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
- mig_p2_clk <= p2_rd_clk;
- p2_rd_data <= mig_p2_rd_data;
- mig_p2_en <= p2_rd_en;
- p2_rd_overflow <= mig_p2_overflow;
- p2_rd_error <= mig_p2_error;
- p2_rd_full <= mig_p2_full;
- p2_rd_empty <= mig_p2_empty;
- p2_rd_count <= mig_p2_count ;-- wr port
- end generate;
- p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
- mig_p2_clk <= '0';
- p2_rd_data <= (others => '0');
- mig_p2_en <= '0';
-
- p2_rd_overflow <= '0';
- p2_rd_error <= '0';
- p2_rd_full <= '0';
- p2_rd_empty <= '0';
- p2_rd_count <= (others => '0');
- end generate;
- mig_p2_wr_data <= (others => '0');
- mig_p2_wr_mask <= (others => '0');
- p2_wr_error <= '0';
- p2_wr_full <= '0';
- p2_wr_empty <= '0';
- p2_wr_underrun <= '0';
- p2_wr_count <= (others => '0');
-
- end generate;
---u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
-
-u_config1_3W: if(
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
-
-p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
-
- mig_p3_clk <= p3_wr_clk;
- mig_p3_wr_data <= p3_wr_data(31 downto 0);
- mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
- mig_p3_en <= p3_wr_en;
- p3_wr_full <= mig_p3_full;
- p3_wr_empty <= mig_p3_empty;
- p3_wr_underrun <= mig_p3_underrun;
- p3_wr_count <= mig_p3_count ;-- wr port
- p3_wr_error <= mig_p3_error;
- end generate;
-
-p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
- mig_p3_clk <= '0';
- mig_p3_wr_data <= (others => '0');
- mig_p3_wr_mask <= (others => '0');
- mig_p3_en <= '0';
- p3_wr_full <= '0';
- p3_wr_empty <= '0';
- p3_wr_underrun <= '0';
- p3_wr_count <= (others => '0');
- p3_wr_error <= '0';
-
- end generate;
- p3_rd_overflow <= '0';
- p3_rd_error <= '0';
- p3_rd_full <= '0';
- p3_rd_empty <= '0';
- p3_rd_count <= (others => '0');
- p3_rd_data <= (others => '0');
- end generate;
-
-u_config1_3R : if(
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
-
-p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
-
- mig_p3_clk <= p3_rd_clk;
- p3_rd_data <= mig_p3_rd_data;
- mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
- p3_rd_overflow <= mig_p3_overflow;
- p3_rd_error <= mig_p3_error;
- p3_rd_full <= mig_p3_full;
- p3_rd_empty <= mig_p3_empty;
- p3_rd_count <= mig_p3_count ;-- wr port
- end generate;
-p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
- mig_p3_clk <= '0';
- mig_p3_en <= '0';
- p3_rd_overflow <= '0';
- p3_rd_full <= '0';
- p3_rd_empty <= '0';
- p3_rd_count <= (others => '0');
- p3_rd_error <= '0';
- p3_rd_data <= (others => '0');
- end generate;
- p3_wr_full <= '0';
- p3_wr_empty <= '0';
- p3_wr_underrun <= '0';
- p3_wr_count <= (others => '0');
- p3_wr_error <= '0';
- mig_p3_wr_data <= (others => '0');
- mig_p3_wr_mask <= (others => '0');
- end generate;
-
-
-u_config1_4W: if(
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
- -- whenever PORT 4 is in Write mode
-
-p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
- mig_p4_clk <= p4_wr_clk;
- mig_p4_wr_data <= p4_wr_data(31 downto 0);
- mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
- mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
- p4_wr_full <= mig_p4_full;
- p4_wr_empty <= mig_p4_empty;
- p4_wr_underrun <= mig_p4_underrun;
- p4_wr_count <= mig_p4_count ;-- wr port
- p4_wr_error <= mig_p4_error;
- end generate;
-
-p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
- mig_p4_clk <= '0';
- mig_p4_wr_data <= (others => '0');
- mig_p4_wr_mask <= (others => '0');
- mig_p4_en <= '0';
- p4_wr_full <= '0';
- p4_wr_empty <= '0';
- p4_wr_underrun <= '0';
- p4_wr_count <= (others => '0');
- p4_wr_error <= '0';
- end generate;
-
- p4_rd_overflow <= '0';
- p4_rd_error <= '0';
- p4_rd_full <= '0';
- p4_rd_empty <= '0';
- p4_rd_count <= (others => '0');
- p4_rd_data <= (others => '0');
- end generate;
-
-u_config1_4R : if(
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
-
-p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
- mig_p4_clk <= p4_rd_clk;
- p4_rd_data <= mig_p4_rd_data;
- mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
- p4_rd_overflow <= mig_p4_overflow;
- p4_rd_error <= mig_p4_error;
- p4_rd_full <= mig_p4_full;
- p4_rd_empty <= mig_p4_empty;
- p4_rd_count <= mig_p4_count ;-- wr port
- end generate;
-p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
- mig_p4_clk <= '0';
- p4_rd_data <= (others => '0');
- mig_p4_en <= '0';
- p4_rd_overflow <= '0';
- p4_rd_error <= '0';
- p4_rd_full <= '0';
- p4_rd_empty <= '0';
- p4_rd_count <= (others => '0');
- end generate;
- p4_wr_full <= '0';
- p4_wr_empty <= '0';
- p4_wr_underrun <= '0';
- p4_wr_count <= (others => '0');
- p4_wr_error <= '0';
- mig_p4_wr_data <= (others => '0');
- mig_p4_wr_mask <= (others => '0');
- end generate;
-
-u_config1_5W: if(
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
- -- whenever PORT 5 is in Write mode
-
-
-p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
- mig_p5_clk <= p5_wr_clk;
- mig_p5_wr_data <= p5_wr_data(31 downto 0);
- mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
- mig_p5_en <= p5_wr_en;
- p5_wr_full <= mig_p5_full;
- p5_wr_empty <= mig_p5_empty;
- p5_wr_underrun <= mig_p5_underrun;
- p5_wr_count <= mig_p5_count ;
- p5_wr_error <= mig_p5_error;
-
-end generate;
-p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
- mig_p5_clk <= '0';
- mig_p5_wr_data <= (others => '0');
- mig_p5_wr_mask <= (others => '0');
- mig_p5_en <= '0';
- p5_wr_full <= '0';
- p5_wr_empty <= '0';
- p5_wr_underrun <= '0';
- p5_wr_count <= (others => '0');
- p5_wr_error <= '0';
-end generate;
- p5_rd_data <= (others => '0');
- p5_rd_overflow <= '0';
- p5_rd_error <= '0';
- p5_rd_full <= '0';
- p5_rd_empty <= '0';
- p5_rd_count <= (others => '0');
-end generate;
-
-
-
-u_config1_5R :if(
- C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
- C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
-
-p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
- mig_p5_clk <= p5_rd_clk;
- p5_rd_data <= mig_p5_rd_data;
- mig_p5_en <= p5_rd_en;
- p5_rd_overflow <= mig_p5_overflow;
- p5_rd_error <= mig_p5_error;
- p5_rd_full <= mig_p5_full;
- p5_rd_empty <= mig_p5_empty;
- p5_rd_count <= mig_p5_count ;
-
-end generate;
-
-p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
-
- mig_p5_clk <= '0';
- p5_rd_data <= (others => '0');
- mig_p5_en <= '0';
- p5_rd_overflow <= '0';
- p5_rd_error <= '0';
- p5_rd_full <= '0';
- p5_rd_empty <= '0';
- p5_rd_count <= (others => '0');
-
-end generate;
- p5_wr_full <= '0';
- p5_wr_empty <= '0';
- p5_wr_underrun <= '0';
- p5_wr_count <= (others => '0');
- p5_wr_error <= '0';
- mig_p5_wr_data <= (others => '0');
- mig_p5_wr_mask <= (others => '0');
-
-end generate;
-
- --//////////////////////////////////////////////////////////////////////////
- --///////////////////////////////////////////////////////////////////////////
- ----
- ---- B32_B32_B32_B32
- ----
- --///////////////////////////////////////////////////////////////////////////
- --//////////////////////////////////////////////////////////////////////////
-
-u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-
-
- -- Inputs from Application CMD Port
- -- ************* need to hook up rd /wr error outputs
-
-p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
- -- command port signals
- mig_p0_arb_en <= p0_arb_en ;
- mig_p0_cmd_clk <= p0_cmd_clk ;
- mig_p0_cmd_en <= p0_cmd_en ;
- mig_p0_cmd_ra <= p0_cmd_ra ;
- mig_p0_cmd_ba <= p0_cmd_ba ;
- mig_p0_cmd_ca <= p0_cmd_ca ;
- mig_p0_cmd_instr <= p0_cmd_instr;
- mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
- -- Data port signals
- mig_p0_rd_en <= p0_rd_en;
- mig_p0_wr_clk <= p0_wr_clk;
- mig_p0_rd_clk <= p0_rd_clk;
- mig_p0_wr_en <= p0_wr_en;
- mig_p0_wr_data <= p0_wr_data(31 downto 0);
- mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
- p0_wr_count <= mig_p0_wr_count;
- p0_rd_count <= mig_p0_rd_count ;
-end generate;
-
-p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
-
- mig_p0_arb_en <= '0';
- mig_p0_cmd_clk <= '0';
- mig_p0_cmd_en <= '0';
- mig_p0_cmd_ra <= (others => '0');
- mig_p0_cmd_ba <= (others => '0');
- mig_p0_cmd_ca <= (others => '0');
- mig_p0_cmd_instr <= (others => '0');
- mig_p0_cmd_bl <= (others => '0');
-
- mig_p0_rd_en <= '0';
- mig_p0_wr_clk <= '0';
- mig_p0_rd_clk <= '0';
- mig_p0_wr_en <= '0';
- mig_p0_wr_data <= (others => '0');
- mig_p0_wr_mask <= (others => '0');
- p0_wr_count <= (others => '0');
- p0_rd_count <= (others => '0');
-
-
-end generate;
-
-
-
-p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
- -- command port signals
-
- mig_p1_arb_en <= p1_arb_en ;
- mig_p1_cmd_clk <= p1_cmd_clk ;
- mig_p1_cmd_en <= p1_cmd_en ;
- mig_p1_cmd_ra <= p1_cmd_ra ;
- mig_p1_cmd_ba <= p1_cmd_ba ;
- mig_p1_cmd_ca <= p1_cmd_ca ;
- mig_p1_cmd_instr <= p1_cmd_instr;
- mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-
- -- Data port signals
-
- mig_p1_wr_en <= p1_wr_en;
- mig_p1_wr_clk <= p1_wr_clk;
- mig_p1_rd_en <= p1_rd_en;
- mig_p1_wr_data <= p1_wr_data(31 downto 0);
- mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
- mig_p1_rd_clk <= p1_rd_clk;
- p1_wr_count <= mig_p1_wr_count;
- p1_rd_count <= mig_p1_rd_count;
-
-end generate;
-p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
-
- mig_p1_arb_en <= '0';
- mig_p1_cmd_clk <= '0';
- mig_p1_cmd_en <= '0';
- mig_p1_cmd_ra <= (others => '0');
- mig_p1_cmd_ba <= (others => '0');
- mig_p1_cmd_ca <= (others => '0');
- mig_p1_cmd_instr <= (others => '0');
- mig_p1_cmd_bl <= (others => '0');
- -- Data port signals
- mig_p1_wr_en <= '0';
- mig_p1_wr_clk <= '0';
- mig_p1_rd_en <= '0';
- mig_p1_wr_data <= (others => '0');
- mig_p1_wr_mask <= (others => '0');
- mig_p1_rd_clk <= '0';
- p1_wr_count <= (others => '0');
- p1_rd_count <= (others => '0');
-
-end generate;
-
-
-
-p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
- --MCB Physical port Logical Port
- mig_p2_arb_en <= p2_arb_en ;
- mig_p2_cmd_clk <= p2_cmd_clk ;
- mig_p2_cmd_en <= p2_cmd_en ;
- mig_p2_cmd_ra <= p2_cmd_ra ;
- mig_p2_cmd_ba <= p2_cmd_ba ;
- mig_p2_cmd_ca <= p2_cmd_ca ;
- mig_p2_cmd_instr <= p2_cmd_instr;
- mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
-
- mig_p2_en <= p2_rd_en;
- mig_p2_clk <= p2_rd_clk;
- mig_p3_en <= p2_wr_en;
- mig_p3_clk <= p2_wr_clk;
- mig_p3_wr_data <= p2_wr_data(31 downto 0);
- mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
- p2_wr_count <= mig_p3_count;
- p2_rd_count <= mig_p2_count;
-end generate;
-p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
-
- mig_p2_arb_en <= '0';
- mig_p2_cmd_clk <= '0';
- mig_p2_cmd_en <= '0';
- mig_p2_cmd_ra <= (others => '0');
- mig_p2_cmd_ba <= (others => '0');
- mig_p2_cmd_ca <= (others => '0');
- mig_p2_cmd_instr <= (others => '0');
- mig_p2_cmd_bl <= (others => '0');
-
- mig_p2_en <= '0';
- mig_p2_clk <= '0';
- mig_p3_en <= '0';
- mig_p3_clk <= '0';
- mig_p3_wr_data <= (others => '0');
- mig_p3_wr_mask <= (others => '0');
- p2_rd_count <= (others => '0');
- p2_wr_count <= (others => '0');
-
-end generate;
-
-
-p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
- --MCB Physical port Logical Port
- mig_p4_arb_en <= p3_arb_en ;
- mig_p4_cmd_clk <= p3_cmd_clk ;
- mig_p4_cmd_en <= p3_cmd_en ;
- mig_p4_cmd_ra <= p3_cmd_ra ;
- mig_p4_cmd_ba <= p3_cmd_ba ;
- mig_p4_cmd_ca <= p3_cmd_ca ;
- mig_p4_cmd_instr <= p3_cmd_instr;
- mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
-
- mig_p4_clk <= p3_rd_clk;
- mig_p4_en <= p3_rd_en;
- mig_p5_clk <= p3_wr_clk;
- mig_p5_en <= p3_wr_en;
- mig_p5_wr_data <= p3_wr_data(31 downto 0);
- mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
- p3_rd_count <= mig_p4_count;
- p3_wr_count <= mig_p5_count;
-end generate;
-
-p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
- mig_p4_arb_en <= '0';
- mig_p4_cmd_clk <= '0';
- mig_p4_cmd_en <= '0';
- mig_p4_cmd_ra <= (others => '0');
- mig_p4_cmd_ba <= (others => '0');
- mig_p4_cmd_ca <= (others => '0');
- mig_p4_cmd_instr <= (others => '0');
- mig_p4_cmd_bl <= (others => '0');
-
- mig_p4_clk <= '0';
- mig_p4_en <= '0';
- mig_p5_clk <= '0';
- mig_p5_en <= '0';
- mig_p5_wr_data <= (others => '0');
- mig_p5_wr_mask <= (others => '0');
- p3_rd_count <= (others => '0');
- p3_wr_count <= (others => '0');
-end generate;
-
- p0_cmd_empty <= mig_p0_cmd_empty ;
- p0_cmd_full <= mig_p0_cmd_full ;
- p1_cmd_empty <= mig_p1_cmd_empty ;
- p1_cmd_full <= mig_p1_cmd_full ;
- p2_cmd_empty <= mig_p2_cmd_empty ;
- p2_cmd_full <= mig_p2_cmd_full ;
- p3_cmd_empty <= mig_p4_cmd_empty ;
- p3_cmd_full <= mig_p4_cmd_full ;
-
-
- -- outputs to Applications User Port
- p0_rd_data <= mig_p0_rd_data;
- p1_rd_data <= mig_p1_rd_data;
- p2_rd_data <= mig_p2_rd_data;
- p3_rd_data <= mig_p4_rd_data;
-
- p0_rd_empty_i <= mig_p0_rd_empty;
- p1_rd_empty_i <= mig_p1_rd_empty;
- p2_rd_empty <= mig_p2_empty;
- p3_rd_empty <= mig_p4_empty;
-
- p0_rd_full <= mig_p0_rd_full;
- p1_rd_full <= mig_p1_rd_full;
- p2_rd_full <= mig_p2_full;
- p3_rd_full <= mig_p4_full;
-
- p0_rd_error <= mig_p0_rd_error;
- p1_rd_error <= mig_p1_rd_error;
- p2_rd_error <= mig_p2_error;
- p3_rd_error <= mig_p4_error;
-
- p0_rd_overflow <= mig_p0_rd_overflow;
- p1_rd_overflow <= mig_p1_rd_overflow;
- p2_rd_overflow <= mig_p2_overflow;
- p3_rd_overflow <= mig_p4_overflow;
-
- p0_wr_underrun <= mig_p0_wr_underrun;
- p1_wr_underrun <= mig_p1_wr_underrun;
- p2_wr_underrun <= mig_p3_underrun;
- p3_wr_underrun <= mig_p5_underrun;
-
- p0_wr_empty <= mig_p0_wr_empty;
- p1_wr_empty <= mig_p1_wr_empty;
- p2_wr_empty <= mig_p3_empty;
- p3_wr_empty <= mig_p5_empty;
-
- p0_wr_full_i <= mig_p0_wr_full;
- p1_wr_full_i <= mig_p1_wr_full;
- p2_wr_full <= mig_p3_full;
- p3_wr_full <= mig_p5_full;
-
- p0_wr_error <= mig_p0_wr_error;
- p1_wr_error <= mig_p1_wr_error;
- p2_wr_error <= mig_p3_error;
- p3_wr_error <= mig_p5_error;
-
- -- unused ports signals
- p4_cmd_empty <= '0';
- p4_cmd_full <= '0';
- mig_p2_wr_mask <= (others => '0');
- mig_p4_wr_mask <= (others => '0');
-
- mig_p2_wr_data <= (others => '0');
- mig_p4_wr_data <= (others => '0');
-
-
- p5_cmd_empty <= '0';
- p5_cmd_full <= '0';
-
-
- mig_p3_cmd_clk <= '0';
- mig_p3_cmd_en <= '0';
- mig_p3_cmd_ra <= (others => '0');
- mig_p3_cmd_ba <= (others => '0');
- mig_p3_cmd_ca <= (others => '0');
- mig_p3_cmd_instr <= (others => '0');
- mig_p3_cmd_bl <= (others => '0');
- mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
-
-
-
-
- mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
- mig_p5_cmd_clk <= '0';
- mig_p5_cmd_en <= '0';
- mig_p5_cmd_ra <= (others => '0');
- mig_p5_cmd_ba <= (others => '0');
- mig_p5_cmd_ca <= (others => '0');
- mig_p5_cmd_instr <= (others => '0');
- mig_p5_cmd_bl <= (others => '0');
-
-end generate;
---
---
--- --//////////////////////////////////////////////////////////////////////////
--- --///////////////////////////////////////////////////////////////////////////
--- ----
--- ---- B64_B32_B32
--- ----
--- --///////////////////////////////////////////////////////////////////////////
--- --//////////////////////////////////////////////////////////////////////////
---
---
---
-u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-
- -- Inputs from Application CMD Port
-
-
-p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
- mig_p0_arb_en <= p0_arb_en ;
- mig_p0_cmd_clk <= p0_cmd_clk ;
- mig_p0_cmd_en <= p0_cmd_en ;
- mig_p0_cmd_ra <= p0_cmd_ra ;
- mig_p0_cmd_ba <= p0_cmd_ba ;
- mig_p0_cmd_ca <= p0_cmd_ca ;
- mig_p0_cmd_instr <= p0_cmd_instr;
- mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
- p0_cmd_empty <= mig_p0_cmd_empty ;
- p0_cmd_full <= mig_p0_cmd_full ;
-
- mig_p0_wr_clk <= p0_wr_clk;
- mig_p0_rd_clk <= p0_rd_clk;
- mig_p1_wr_clk <= p0_wr_clk;
- mig_p1_rd_clk <= p0_rd_clk;
-
- mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
- mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
- mig_p0_wr_data <= p0_wr_data(31 downto 0);
- mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
- mig_p1_wr_data <= p0_wr_data(63 downto 32);
- mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
-
- p0_rd_empty_i <= mig_p1_rd_empty;
- p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
- mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
- mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
-
-
- p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
- p0_rd_count <= mig_p1_rd_count;
- p0_wr_empty <= mig_p1_wr_empty;
- p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
- p0_wr_full_i <= mig_p1_wr_full;
- p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
- p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
- p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
- p0_rd_full <= mig_p1_rd_full;
-
-end generate;
-p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
-
- mig_p0_arb_en <= '0';
- mig_p0_cmd_clk <= '0';
- mig_p0_cmd_en <= '0';
- mig_p0_cmd_ra <= (others => '0');
- mig_p0_cmd_ba <= (others => '0');
- mig_p0_cmd_ca <= (others => '0');
- mig_p0_cmd_instr <= (others => '0');
- mig_p0_cmd_bl <= (others => '0');
- p0_cmd_empty <= '0';
- p0_cmd_full <= '0';
-
-
- mig_p0_wr_clk <= '0';
- mig_p0_rd_clk <= '0';
- mig_p1_wr_clk <= '0';
- mig_p1_rd_clk <= '0';
-
- mig_p0_wr_en <= '0';
- mig_p1_wr_en <= '0';
- mig_p0_wr_data <= (others => '0');
- mig_p0_wr_mask <= (others => '0');
- mig_p1_wr_data <= (others => '0');
- mig_p1_wr_mask <= (others => '0');
-
- p0_rd_empty_i <= '0';
- p0_rd_data <= (others => '0');
- mig_p0_rd_en <= '0';
- mig_p1_rd_en <= '0';
-
-
- p0_wr_count <= (others => '0');
- p0_rd_count <= (others => '0');
- p0_wr_empty <= '0';
- p0_wr_error <= '0';
- p0_wr_full_i <= '0';
- p0_wr_underrun <= '0';
- p0_rd_overflow <= '0';
- p0_rd_error <= '0';
- p0_rd_full <= '0';
-end generate;
-
-
-
-
-p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
-
- mig_p2_arb_en <= p1_arb_en ;
- mig_p2_cmd_clk <= p1_cmd_clk ;
- mig_p2_cmd_en <= p1_cmd_en ;
- mig_p2_cmd_ra <= p1_cmd_ra ;
- mig_p2_cmd_ba <= p1_cmd_ba ;
- mig_p2_cmd_ca <= p1_cmd_ca ;
- mig_p2_cmd_instr <= p1_cmd_instr;
- mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-
- p1_cmd_empty <= mig_p2_cmd_empty;
- p1_cmd_full <= mig_p2_cmd_full;
-
- mig_p2_clk <= p1_rd_clk;
- mig_p3_clk <= p1_wr_clk;
-
- mig_p3_en <= p1_wr_en;
- mig_p3_wr_data <= p1_wr_data(31 downto 0);
- mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
- mig_p2_en <= p1_rd_en;
-
- p1_rd_data <= mig_p2_rd_data;
- p1_wr_count <= mig_p3_count;
- p1_rd_count <= mig_p2_count;
- p1_wr_empty <= mig_p3_empty;
- p1_wr_error <= mig_p3_error;
- p1_wr_full_i <= mig_p3_full;
- p1_wr_underrun <= mig_p3_underrun;
- p1_rd_overflow <= mig_p2_overflow;
- p1_rd_error <= mig_p2_error;
- p1_rd_full <= mig_p2_full;
- p1_rd_empty_i <= mig_p2_empty;
- end generate;
-
-p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
-
- mig_p2_arb_en <= '0';
- mig_p2_cmd_clk <= '0';
- mig_p2_cmd_en <= '0';
- mig_p2_cmd_ra <= (others => '0');
- mig_p2_cmd_ba <= (others => '0');
- mig_p2_cmd_ca <= (others => '0');
- mig_p2_cmd_instr <= (others => '0');
- mig_p2_cmd_bl <= (others => '0');
- p1_cmd_empty <= '0';
- p1_cmd_full <= '0';
- mig_p3_en <= '0';
- mig_p3_wr_data <= (others => '0');
- mig_p3_wr_mask <= (others => '0');
- mig_p2_en <= '0';
-
- mig_p2_clk <= '0';
- mig_p3_clk <= '0';
-
- p1_rd_data <= (others => '0');
- p1_wr_count <= (others => '0');
- p1_rd_count <= (others => '0');
- p1_wr_empty <= '0';
- p1_wr_error <= '0';
- p1_wr_full_i <= '0';
- p1_wr_underrun <= '0';
- p1_rd_overflow <= '0';
- p1_rd_error <= '0';
- p1_rd_full <= '0';
- p1_rd_empty_i <= '0';
-
-end generate;
-
-p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
- mig_p4_arb_en <= p2_arb_en ;
- mig_p4_cmd_clk <= p2_cmd_clk ;
- mig_p4_cmd_en <= p2_cmd_en ;
- mig_p4_cmd_ra <= p2_cmd_ra ;
- mig_p4_cmd_ba <= p2_cmd_ba ;
- mig_p4_cmd_ca <= p2_cmd_ca ;
- mig_p4_cmd_instr <= p2_cmd_instr;
- mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
-
- p2_cmd_empty <= mig_p4_cmd_empty ;
- p2_cmd_full <= mig_p4_cmd_full ;
- mig_p5_en <= p2_wr_en;
- mig_p5_wr_data <= p2_wr_data(31 downto 0);
- mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
- mig_p4_en <= p2_rd_en;
-
- mig_p4_clk <= p2_rd_clk;
- mig_p5_clk <= p2_wr_clk;
-
- p2_rd_data <= mig_p4_rd_data;
- p2_wr_count <= mig_p5_count;
- p2_rd_count <= mig_p4_count;
- p2_wr_empty <= mig_p5_empty;
- p2_wr_full <= mig_p5_full;
- p2_wr_error <= mig_p5_error;
- p2_wr_underrun <= mig_p5_underrun;
- p2_rd_overflow <= mig_p4_overflow;
- p2_rd_error <= mig_p4_error;
- p2_rd_full <= mig_p4_full;
- p2_rd_empty <= mig_p4_empty;
-
-end generate;
-
-p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
-
- mig_p4_arb_en <= '0';
- mig_p4_cmd_clk <= '0';
- mig_p4_cmd_en <= '0';
- mig_p4_cmd_ra <= (others => '0');
- mig_p4_cmd_ba <= (others => '0');
- mig_p4_cmd_ca <= (others => '0');
- mig_p4_cmd_instr <= (others => '0');
- mig_p4_cmd_bl <= (others => '0');
- p2_cmd_empty <= '0';
- p2_cmd_full <= '0';
- mig_p5_en <= '0';
- mig_p5_wr_data <= (others => '0');
- mig_p5_wr_mask <= (others => '0');
- mig_p4_en <= '0';
-
- mig_p4_clk <= '0';
- mig_p5_clk <= '0';
-
- p2_rd_data <= (others => '0');
- p2_wr_count <= (others => '0');
- p2_rd_count <= (others => '0');
- p2_wr_empty <= '0';
- p2_wr_full <= '0';
- p2_wr_error <= '0';
- p2_wr_underrun <= '0';
- p2_rd_overflow <= '0';
- p2_rd_error <= '0';
- p2_rd_full <= '0';
- p2_rd_empty <= '0';
-
-end generate;
-
- -- MCB's port 1,3,5 is not used in this Config mode
- mig_p1_arb_en <= '0';
- mig_p1_cmd_clk <= '0';
- mig_p1_cmd_en <= '0';
- mig_p1_cmd_ra <= (others => '0');
- mig_p1_cmd_ba <= (others => '0');
- mig_p1_cmd_ca <= (others => '0');
-
- mig_p1_cmd_instr <= (others => '0');
- mig_p1_cmd_bl <= (others => '0');
-
- mig_p3_arb_en <= '0';
- mig_p3_cmd_clk <= '0';
- mig_p3_cmd_en <= '0';
- mig_p3_cmd_ra <= (others => '0');
- mig_p3_cmd_ba <= (others => '0');
- mig_p3_cmd_ca <= (others => '0');
-
- mig_p3_cmd_instr <= (others => '0');
- mig_p3_cmd_bl <= (others => '0');
-
- mig_p5_arb_en <= '0';
- mig_p5_cmd_clk <= '0';
- mig_p5_cmd_en <= '0';
- mig_p5_cmd_ra <= (others => '0');
- mig_p5_cmd_ba <= (others => '0');
- mig_p5_cmd_ca <= (others => '0');
-
- mig_p5_cmd_instr <= (others => '0');
- mig_p5_cmd_bl <= (others => '0');
-
-end generate;
-
-u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-
- -- Inputs from Application CMD Port
-
-p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
-
- mig_p0_arb_en <= p0_arb_en ;
- mig_p1_arb_en <= p0_arb_en ;
-
- mig_p0_cmd_clk <= p0_cmd_clk ;
- mig_p0_cmd_en <= p0_cmd_en ;
- mig_p0_cmd_ra <= p0_cmd_ra ;
- mig_p0_cmd_ba <= p0_cmd_ba ;
- mig_p0_cmd_ca <= p0_cmd_ca ;
- mig_p0_cmd_instr <= p0_cmd_instr;
- mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-
- mig_p0_wr_clk <= p0_wr_clk;
- mig_p0_rd_clk <= p0_rd_clk;
- mig_p1_wr_clk <= p0_wr_clk;
- mig_p1_rd_clk <= p0_rd_clk;
- mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
- mig_p0_wr_data <= p0_wr_data(31 downto 0);
- mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
- mig_p1_wr_data <= p0_wr_data(63 downto 32);
- mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
- mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
- mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
- mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
- p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
-
- p0_cmd_empty <= mig_p0_cmd_empty ;
- p0_cmd_full <= mig_p0_cmd_full ;
- p0_wr_empty <= mig_p1_wr_empty;
- p0_wr_full_i <= mig_p1_wr_full;
- p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
- p0_wr_count <= mig_p1_wr_count;
- p0_rd_count <= mig_p1_rd_count;
- p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
- p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
- p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
- p0_rd_full <= mig_p1_rd_full;
- p0_rd_empty_i <= mig_p1_rd_empty;
-end generate;
-
-p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
- mig_p0_arb_en <= '0';
- mig_p0_cmd_clk <= '0';
- mig_p0_cmd_en <= '0';
- mig_p0_cmd_ra <= (others => '0');
- mig_p0_cmd_ba <= (others => '0');
- mig_p0_cmd_ca <= (others => '0');
- mig_p0_cmd_instr <= (others => '0');
- mig_p0_cmd_bl <= (others => '0');
-
- mig_p0_wr_clk <= '0';
- mig_p0_rd_clk <= '0';
- mig_p1_wr_clk <= '0';
- mig_p1_rd_clk <= '0';
- mig_p0_wr_en <= '0';
- mig_p1_wr_en <= '0';
- mig_p0_wr_data <= (others => '0');
- mig_p0_wr_mask <= (others => '0');
- mig_p1_wr_data <= (others => '0');
- mig_p1_wr_mask <= (others => '0');
- -- mig_p1_wr_en <= (others => '0');
- mig_p0_rd_en <= '0';
- mig_p1_rd_en <= '0';
- p0_rd_data <= (others => '0');
-
-
- p0_cmd_empty <= '0';
- p0_cmd_full <= '0';
- p0_wr_empty <= '0';
- p0_wr_full_i <= '0';
- p0_wr_error <= '0';
- p0_wr_count <= (others => '0');
- p0_rd_count <= (others => '0');
- p0_wr_underrun <= '0';
- p0_rd_overflow <= '0';
- p0_rd_error <= '0';
- p0_rd_full <= '0';
- p0_rd_empty_i <= '0';
-
-
-end generate;
-
-
-p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
-
- mig_p2_arb_en <= p1_arb_en ;
-
- mig_p2_cmd_clk <= p1_cmd_clk ;
- mig_p2_cmd_en <= p1_cmd_en ;
- mig_p2_cmd_ra <= p1_cmd_ra ;
- mig_p2_cmd_ba <= p1_cmd_ba ;
- mig_p2_cmd_ca <= p1_cmd_ca ;
- mig_p2_cmd_instr <= p1_cmd_instr;
- mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-
-
- mig_p2_clk <= p1_rd_clk;
- mig_p3_clk <= p1_wr_clk;
- mig_p4_clk <= p1_rd_clk;
- mig_p5_clk <= p1_wr_clk;
- mig_p3_en <= p1_wr_en and not p1_wr_full_i;
- mig_p5_en <= p1_wr_en and not p1_wr_full_i;
- mig_p3_wr_data <= p1_wr_data(31 downto 0);
- mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
- mig_p5_wr_data <= p1_wr_data(63 downto 32);
- mig_p5_wr_mask <= p1_wr_mask(3 downto 0);
- mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
- mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
-
- p1_cmd_empty <= mig_p2_cmd_empty ;
- p1_cmd_full <= mig_p2_cmd_full ;
-
- p1_wr_count <= mig_p5_count;
- p1_rd_count <= mig_p4_count;
- p1_wr_full_i <= mig_p5_full;
- p1_wr_error <= mig_p5_error or mig_p5_error;
- p1_wr_empty <= mig_p5_empty;
- p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
- p1_rd_overflow <= mig_p4_overflow;
- p1_rd_error <= mig_p4_error;
- p1_rd_full <= mig_p4_full;
- p1_rd_empty_i <= mig_p4_empty;
-
- p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
-
-end generate;
-p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
-
- mig_p2_arb_en <= '0';
- -- mig_p3_arb_en <= (others => '0');
- -- mig_p4_arb_en <= (others => '0');
- -- mig_p5_arb_en <= (others => '0');
-
- mig_p2_cmd_clk <= '0';
- mig_p2_cmd_en <= '0';
- mig_p2_cmd_ra <= (others => '0');
- mig_p2_cmd_ba <= (others => '0');
- mig_p2_cmd_ca <= (others => '0');
- mig_p2_cmd_instr <= (others => '0');
- mig_p2_cmd_bl <= (others => '0');
- mig_p2_clk <= '0';
- mig_p3_clk <= '0';
- mig_p4_clk <= '0';
- mig_p5_clk <= '0';
- mig_p3_en <= '0';
- mig_p5_en <= '0';
- mig_p3_wr_data <= (others => '0');
- mig_p3_wr_mask <= (others => '0');
- mig_p5_wr_data <= (others => '0');
- mig_p5_wr_mask <= (others => '0');
- mig_p2_en <= '0';
- mig_p4_en <= '0';
- p1_cmd_empty <= '0';
- p1_cmd_full <= '0';
-
- p1_wr_count <= (others => '0');
- p1_rd_count <= (others => '0');
- p1_wr_full_i <= '0';
- p1_wr_error <= '0';
- p1_wr_empty <= '0';
- p1_wr_underrun <= '0';
- p1_rd_overflow <= '0';
- p1_rd_error <= '0';
- p1_rd_full <= '0';
- p1_rd_empty_i <= '0';
- p1_rd_data <= (others => '0');
-
-end generate;
-
- -- unused MCB's signals in this configuration
- mig_p3_arb_en <= '0';
- mig_p4_arb_en <= '0';
- mig_p5_arb_en <= '0';
-
- mig_p3_cmd_clk <= '0';
- mig_p3_cmd_en <= '0';
- mig_p3_cmd_ra <= (others => '0');
- mig_p3_cmd_ba <= (others => '0');
- mig_p3_cmd_ca <= (others => '0');
- mig_p3_cmd_instr <= (others => '0');
-
- mig_p4_cmd_clk <= '0';
- mig_p4_cmd_en <= '0';
- mig_p4_cmd_ra <= (others => '0');
- mig_p4_cmd_ba <= (others => '0');
- mig_p4_cmd_ca <= (others => '0');
- mig_p4_cmd_instr <= (others => '0');
- mig_p4_cmd_bl <= (others => '0');
-
- mig_p5_cmd_clk <= '0';
- mig_p5_cmd_en <= '0';
- mig_p5_cmd_ra <= (others => '0');
- mig_p5_cmd_ba <= (others => '0');
- mig_p5_cmd_ca <= (others => '0');
- mig_p5_cmd_instr <= (others => '0');
- mig_p5_cmd_bl <= (others => '0');
-
- end generate;
-
-
---*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
-
-u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-
-
- -- Inputs from Application CMD Port
-
- mig_p0_arb_en <= p0_arb_en ;
- mig_p0_cmd_clk <= p0_cmd_clk ;
- mig_p0_cmd_en <= p0_cmd_en ;
- mig_p0_cmd_ra <= p0_cmd_ra ;
- mig_p0_cmd_ba <= p0_cmd_ba ;
- mig_p0_cmd_ca <= p0_cmd_ca ;
- mig_p0_cmd_instr <= p0_cmd_instr;
- mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
- p0_cmd_empty <= mig_p0_cmd_empty ;
- p0_cmd_full <= mig_p0_cmd_full ;
-
-
-
- -- Inputs from Application User Port
-
- mig_p0_wr_clk <= p0_wr_clk;
- mig_p0_rd_clk <= p0_rd_clk;
- mig_p1_wr_clk <= p0_wr_clk;
- mig_p1_rd_clk <= p0_rd_clk;
-
- mig_p2_clk <= p0_rd_clk;
- mig_p3_clk <= p0_wr_clk;
- mig_p4_clk <= p0_rd_clk;
- mig_p5_clk <= p0_wr_clk;
-
-
-
- mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
- mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
- mig_p3_en <= p0_wr_en and not p0_wr_full_i;
- mig_p5_en <= p0_wr_en and not p0_wr_full_i;
-
-
-
- mig_p0_wr_data <= p0_wr_data(31 downto 0);
- mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
- mig_p1_wr_data <= p0_wr_data(63 downto 32);
- mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
- mig_p3_wr_data <= p0_wr_data(95 downto 64);
- mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
- mig_p5_wr_data <= p0_wr_data(127 downto 96);
- mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
-
- mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
- mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
- mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
- mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-
- -- outputs to Applications User Port
- p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
- p0_rd_empty_i <= mig_p4_empty;
- p0_rd_full <= mig_p4_full;
- p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
- p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
-
- p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
- p0_wr_empty <= mig_p5_empty;
- p0_wr_full_i <= mig_p5_full;
- p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
-
- p0_wr_count <= mig_p5_count;
- p0_rd_count <= mig_p4_count;
-
-
- -- unused MCB's siganls in this configuration
-
- mig_p1_arb_en <= '0';
- mig_p1_cmd_clk <= '0';
- mig_p1_cmd_en <= '0';
- mig_p1_cmd_ra <= (others => '0');
- mig_p1_cmd_ba <= (others => '0');
- mig_p1_cmd_ca <= (others => '0');
-
- mig_p1_cmd_instr <= (others => '0');
- mig_p1_cmd_bl <= (others => '0');
-
- mig_p2_arb_en <= '0';
- mig_p2_cmd_clk <= '0';
- mig_p2_cmd_en <= '0';
- mig_p2_cmd_ra <= (others => '0');
- mig_p2_cmd_ba <= (others => '0');
- mig_p2_cmd_ca <= (others => '0');
-
- mig_p2_cmd_instr <= (others => '0');
- mig_p2_cmd_bl <= (others => '0');
-
- mig_p3_arb_en <= '0';
- mig_p3_cmd_clk <= '0';
- mig_p3_cmd_en <= '0';
- mig_p3_cmd_ra <= (others => '0');
- mig_p3_cmd_ba <= (others => '0');
- mig_p3_cmd_ca <= (others => '0');
-
- mig_p3_cmd_instr <= (others => '0');
- mig_p3_cmd_bl <= (others => '0');
-
- mig_p4_arb_en <= '0';
- mig_p4_cmd_clk <= '0';
- mig_p4_cmd_en <= '0';
- mig_p4_cmd_ra <= (others => '0');
- mig_p4_cmd_ba <= (others => '0');
- mig_p4_cmd_ca <= (others => '0');
-
- mig_p4_cmd_instr <= (others => '0');
- mig_p4_cmd_bl <= (others => '0');
-
- mig_p5_arb_en <= '0';
- mig_p5_cmd_clk <= '0';
- mig_p5_cmd_en <= '0';
- mig_p5_cmd_ra <= (others => '0');
- mig_p5_cmd_ba <= (others => '0');
- mig_p5_cmd_ca <= (others => '0');
-
- mig_p5_cmd_instr <= (others => '0');
- mig_p5_cmd_bl <= (others => '0');
-
---*******************************END OF CONFIG 5 SIGNALS ********************************
-
-end generate;
-
-uo_cal_start <= uo_cal_start_int;
-
-
-
-samc_0: MCB
- GENERIC MAP
- ( PORT_CONFIG => C_PORT_CONFIG,
- MEM_WIDTH => C_NUM_DQ_PINS ,
- MEM_TYPE => C_MEM_TYPE ,
- MEM_BURST_LEN => C_MEM_BURST_LEN ,
- MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
- MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
- MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
- MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
- MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
- MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
- MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
- MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
- MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
- MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
- MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
- MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
- MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
- MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
- MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
- MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
- MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
- MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
- MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
- MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
- MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
- MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
- MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
- MEM_RAS_VAL => MEM_RAS_VAL ,
- MEM_RCD_VAL => MEM_RCD_VAL ,
- MEM_REFI_VAL => MEM_REFI_VAL ,
- MEM_RFC_VAL => MEM_RFC_VAL ,
- MEM_RP_VAL => MEM_RP_VAL ,
- MEM_WR_VAL => MEM_WR_VAL ,
- MEM_RTP_VAL => MEM_RTP_VAL ,
- MEM_WTR_VAL => MEM_WTR_VAL ,
- CAL_BYPASS => C_MC_CALIB_BYPASS,
- CAL_RA => C_MC_CALIBRATION_RA,
- CAL_BA => C_MC_CALIBRATION_BA ,
- CAL_CA => C_MC_CALIBRATION_CA,
- CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
- CAL_DELAY => C_MC_CALIBRATION_DELAY,
--- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
- ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
- ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
- ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
- ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
- ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
- ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
- ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
- ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
- ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
- ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
- ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
- ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
- ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
- ) PORT MAP
- (
-
- -- HIGH-SPEED PLL clock interface
-
- PLLCLK => pllclk1,
- PLLCE => pllce1,
-
- PLLLOCK => '1',
-
- -- DQS CLOCK NETWork interface
-
- DQSIOIN => idelay_dqs_ioi_s,
- DQSIOIP => idelay_dqs_ioi_m,
- UDQSIOIN => idelay_udqs_ioi_s,
- UDQSIOIP => idelay_udqs_ioi_m,
-
-
- --DQSPIN => in_pre_dqsp,
- DQI => in_dq,
- -- RESETS - GLOBAl and local
- SYSRST => MCB_SYSRST ,
-
- -- command port 0
- P0ARBEN => mig_p0_arb_en,
- P0CMDCLK => mig_p0_cmd_clk,
- P0CMDEN => mig_p0_cmd_en,
- P0CMDRA => mig_p0_cmd_ra,
- P0CMDBA => mig_p0_cmd_ba,
- P0CMDCA => mig_p0_cmd_ca,
-
- P0CMDINSTR => mig_p0_cmd_instr,
- P0CMDBL => mig_p0_cmd_bl,
- P0CMDEMPTY => mig_p0_cmd_empty,
- P0CMDFULL => mig_p0_cmd_full,
-
- -- command port 1
-
- P1ARBEN => mig_p1_arb_en,
- P1CMDCLK => mig_p1_cmd_clk,
- P1CMDEN => mig_p1_cmd_en,
- P1CMDRA => mig_p1_cmd_ra,
- P1CMDBA => mig_p1_cmd_ba,
- P1CMDCA => mig_p1_cmd_ca,
-
- P1CMDINSTR => mig_p1_cmd_instr,
- P1CMDBL => mig_p1_cmd_bl,
- P1CMDEMPTY => mig_p1_cmd_empty,
- P1CMDFULL => mig_p1_cmd_full,
-
- -- command port 2
-
- P2ARBEN => mig_p2_arb_en,
- P2CMDCLK => mig_p2_cmd_clk,
- P2CMDEN => mig_p2_cmd_en,
- P2CMDRA => mig_p2_cmd_ra,
- P2CMDBA => mig_p2_cmd_ba,
- P2CMDCA => mig_p2_cmd_ca,
-
- P2CMDINSTR => mig_p2_cmd_instr,
- P2CMDBL => mig_p2_cmd_bl,
- P2CMDEMPTY => mig_p2_cmd_empty,
- P2CMDFULL => mig_p2_cmd_full,
-
- -- command port 3
-
- P3ARBEN => mig_p3_arb_en,
- P3CMDCLK => mig_p3_cmd_clk,
- P3CMDEN => mig_p3_cmd_en,
- P3CMDRA => mig_p3_cmd_ra,
- P3CMDBA => mig_p3_cmd_ba,
- P3CMDCA => mig_p3_cmd_ca,
-
- P3CMDINSTR => mig_p3_cmd_instr,
- P3CMDBL => mig_p3_cmd_bl,
- P3CMDEMPTY => mig_p3_cmd_empty,
- P3CMDFULL => mig_p3_cmd_full,
-
- -- command port 4 -- don't care in config 2
-
- P4ARBEN => mig_p4_arb_en,
- P4CMDCLK => mig_p4_cmd_clk,
- P4CMDEN => mig_p4_cmd_en,
- P4CMDRA => mig_p4_cmd_ra,
- P4CMDBA => mig_p4_cmd_ba,
- P4CMDCA => mig_p4_cmd_ca,
-
- P4CMDINSTR => mig_p4_cmd_instr,
- P4CMDBL => mig_p4_cmd_bl,
- P4CMDEMPTY => mig_p4_cmd_empty,
- P4CMDFULL => mig_p4_cmd_full,
-
- -- command port 5-- don't care in config 2
-
- P5ARBEN => mig_p5_arb_en,
- P5CMDCLK => mig_p5_cmd_clk,
- P5CMDEN => mig_p5_cmd_en,
- P5CMDRA => mig_p5_cmd_ra,
- P5CMDBA => mig_p5_cmd_ba,
- P5CMDCA => mig_p5_cmd_ca,
-
- P5CMDINSTR => mig_p5_cmd_instr,
- P5CMDBL => mig_p5_cmd_bl,
- P5CMDEMPTY => mig_p5_cmd_empty,
- P5CMDFULL => mig_p5_cmd_full,
-
-
- -- IOI & IOB SIGNals/tristate interface
-
- DQIOWEN0 => dqIO_w_en_0,
- DQSIOWEN90P => dqsIO_w_en_90_p,
- DQSIOWEN90N => dqsIO_w_en_90_n,
-
-
- -- IOB MEMORY INTerface signals
- ADDR => address_90,
- BA => ba_90 ,
- RAS => ras_90 ,
- CAS => cas_90 ,
- WE => we_90 ,
- CKE => cke_90 ,
- ODT => odt_90 ,
- RST => rst_90 ,
-
- -- CALIBRATION DRP interface
- IOIDRPCLK => ioi_drp_clk ,
- IOIDRPADDR => ioi_drp_addr ,
- IOIDRPSDO => ioi_drp_sdo ,
- IOIDRPSDI => ioi_drp_sdi ,
- IOIDRPCS => ioi_drp_cs ,
- IOIDRPADD => ioi_drp_add ,
- IOIDRPBROADCAST => ioi_drp_broadcast ,
- IOIDRPTRAIN => ioi_drp_train ,
- IOIDRPUPDATE => ioi_drp_update ,
-
- -- CALIBRATION DAtacapture interface
- --SPECIAL COMMANDs
- RECAL => mcb_recal ,
- UIREAD => mcb_ui_read,
- UIADD => mcb_ui_add ,
- UICS => mcb_ui_cs ,
- UICLK => mcb_ui_clk ,
- UISDI => mcb_ui_sdi ,
- UIADDR => mcb_ui_addr ,
- UIBROADCAST => mcb_ui_broadcast,
- UIDRPUPDATE => mcb_ui_drp_update,
- UIDONECAL => mcb_ui_done_cal,
- UICMD => mcb_ui_cmd,
- UICMDIN => mcb_ui_cmd_in,
- UICMDEN => mcb_ui_cmd_en,
- UIDQCOUNT => mcb_ui_dqcount,
- UIDQLOWERDEC => mcb_ui_dq_lower_dec,
- UIDQLOWERINC => mcb_ui_dq_lower_inc,
- UIDQUPPERDEC => mcb_ui_dq_upper_dec,
- UIDQUPPERINC => mcb_ui_dq_upper_inc,
- UIUDQSDEC => mcb_ui_udqs_dec,
- UIUDQSINC => mcb_ui_udqs_inc,
- UILDQSDEC => mcb_ui_ldqs_dec,
- UILDQSINC => mcb_ui_ldqs_inc,
- UODATA => uo_data_int,
- UODATAVALID => uo_data_valid_int,
- UODONECAL => hard_done_cal ,
- UOCMDREADYIN => uo_cmd_ready_in_int,
- UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
- UOCALSTART => uo_cal_start_int,
- UOSDO => uo_sdo_xhdl24,
-
- --CONTROL SIGNALS
- STATUS => status,
- SELFREFRESHENTER => selfrefresh_mcb_enter,
- SELFREFRESHMODE => selfrefresh_mcb_mode,
-------------------------------------------------
---MUIs
-------------------------------------------------
-
- P0RDDATA => mig_p0_rd_data ( 31 downto 0),
- P1RDDATA => mig_p1_rd_data ( 31 downto 0),
- P2RDDATA => mig_p2_rd_data ( 31 downto 0),
- P3RDDATA => mig_p3_rd_data ( 31 downto 0),
- P4RDDATA => mig_p4_rd_data ( 31 downto 0),
- P5RDDATA => mig_p5_rd_data ( 31 downto 0),
- LDMN => dqnlm ,
- UDMN => dqnum ,
- DQON => dqo_n ,
- DQOP => dqo_p ,
- LDMP => dqplm ,
- UDMP => dqpum ,
-
- P0RDCOUNT => mig_p0_rd_count ,
- P0WRCOUNT => mig_p0_wr_count ,
- P1RDCOUNT => mig_p1_rd_count ,
- P1WRCOUNT => mig_p1_wr_count ,
- P2COUNT => mig_p2_count ,
- P3COUNT => mig_p3_count ,
- P4COUNT => mig_p4_count ,
- P5COUNT => mig_p5_count ,
-
- -- NEW ADDED FIFo status siganls
- -- MIG USER PORT 0
- P0RDEMPTY => mig_p0_rd_empty,
- P0RDFULL => mig_p0_rd_full,
- P0RDOVERFLOW => mig_p0_rd_overflow,
- P0WREMPTY => mig_p0_wr_empty,
- P0WRFULL => mig_p0_wr_full,
- P0WRUNDERRUN => mig_p0_wr_underrun,
- -- MIG USER PORT 1
- P1RDEMPTY => mig_p1_rd_empty,
- P1RDFULL => mig_p1_rd_full,
- P1RDOVERFLOW => mig_p1_rd_overflow,
- P1WREMPTY => mig_p1_wr_empty,
- P1WRFULL => mig_p1_wr_full,
- P1WRUNDERRUN => mig_p1_wr_underrun,
-
- -- MIG USER PORT 2
- P2EMPTY => mig_p2_empty,
- P2FULL => mig_p2_full,
- P2RDOVERFLOW => mig_p2_overflow,
- P2WRUNDERRUN => mig_p2_underrun,
-
- P3EMPTY => mig_p3_empty ,
- P3FULL => mig_p3_full ,
- P3RDOVERFLOW => mig_p3_overflow,
- P3WRUNDERRUN => mig_p3_underrun ,
- -- MIG USER PORT 3
- P4EMPTY => mig_p4_empty,
- P4FULL => mig_p4_full,
- P4RDOVERFLOW => mig_p4_overflow,
- P4WRUNDERRUN => mig_p4_underrun,
-
- P5EMPTY => mig_p5_empty ,
- P5FULL => mig_p5_full ,
- P5RDOVERFLOW => mig_p5_overflow,
- P5WRUNDERRUN => mig_p5_underrun,
-
- ---------------------------------------------------------
- P0WREN => mig_p0_wr_en,
- P0RDEN => mig_p0_rd_en,
- P1WREN => mig_p1_wr_en,
- P1RDEN => mig_p1_rd_en,
- P2EN => mig_p2_en,
- P3EN => mig_p3_en,
- P4EN => mig_p4_en,
- P5EN => mig_p5_en,
- -- WRITE MASK BIts connection
- P0RWRMASK => mig_p0_wr_mask(3 downto 0),
- P1RWRMASK => mig_p1_wr_mask(3 downto 0),
- P2WRMASK => mig_p2_wr_mask(3 downto 0),
- P3WRMASK => mig_p3_wr_mask(3 downto 0),
- P4WRMASK => mig_p4_wr_mask(3 downto 0),
- P5WRMASK => mig_p5_wr_mask(3 downto 0),
- -- DATA WRITE COnnection
- P0WRDATA => mig_p0_wr_data(31 downto 0),
- P1WRDATA => mig_p1_wr_data(31 downto 0),
- P2WRDATA => mig_p2_wr_data(31 downto 0),
- P3WRDATA => mig_p3_wr_data(31 downto 0),
- P4WRDATA => mig_p4_wr_data(31 downto 0),
- P5WRDATA => mig_p5_wr_data(31 downto 0),
-
- P0WRERROR => mig_p0_wr_error,
- P1WRERROR => mig_p1_wr_error,
- P0RDERROR => mig_p0_rd_error,
- P1RDERROR => mig_p1_rd_error,
-
- P2ERROR => mig_p2_error,
- P3ERROR => mig_p3_error,
- P4ERROR => mig_p4_error,
- P5ERROR => mig_p5_error,
-
- -- USER SIDE DAta ports clock
- -- 128 BITS CONnections
- P0WRCLK => mig_p0_wr_clk ,
- P1WRCLK => mig_p1_wr_clk ,
- P0RDCLK => mig_p0_rd_clk ,
- P1RDCLK => mig_p1_rd_clk ,
- P2CLK => mig_p2_clk ,
- P3CLK => mig_p3_clk ,
- P4CLK => mig_p4_clk ,
- P5CLK => mig_p5_clk
- );
-
---//////////////////////////////////////////////////////
---// Input Termination Calibration
---//////////////////////////////////////////////////////
-
- uo_done_cal <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
- hard_done_cal;
-
-
- gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
- mcb_soft_calibration_top_inst : mcb_soft_calibration_top
- generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
- C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
- SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
- SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
- SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
- C_SIMULATION => C_SIMULATION,
- C_MEM_TYPE => C_MEM_TYPE
- )
-
- PORT MAP (
- UI_CLK => ui_clk,
- RST => int_sys_rst,
- IOCLK => ioclk0,
- DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
- PLL_LOCK => pll_lock,
-
- SELFREFRESH_REQ => selfrefresh_enter, -- from user app
- SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
- SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
- SELFREFRESH_MODE => selfrefresh_mode, -- to user app
-
- MCB_UIADD => mcb_ui_add,
- MCB_UISDI => mcb_ui_sdi,
- MCB_UOSDO => uo_sdo_xhdl24,
- MCB_UODONECAL => hard_done_cal,
- MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
- MCB_UICS => mcb_ui_cs,
- MCB_UIDRPUPDATE => mcb_ui_drp_update,
- MCB_UIBROADCAST => mcb_ui_broadcast,
- MCB_UIADDR => mcb_ui_addr,
- MCB_UICMDEN => mcb_ui_cmd_en,
- MCB_UIDONECAL => mcb_ui_done_cal,
- MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
- MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
- MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
- MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
- MCB_UILDQSDEC => mcb_ui_ldqs_dec,
- MCB_UILDQSINC => mcb_ui_ldqs_inc,
- MCB_UIREAD => mcb_ui_read,
- MCB_UIUDQSDEC => mcb_ui_udqs_dec,
- MCB_UIUDQSINC => mcb_ui_udqs_inc,
- MCB_RECAL => mcb_recal,
- MCB_SYSRST => MCB_SYSRST,
- MCB_UICMD => mcb_ui_cmd,
- MCB_UICMDIN => mcb_ui_cmd_in,
- MCB_UIDQCOUNT => mcb_ui_dqcount,
- MCB_UODATA => uo_data_int,
- MCB_UODATAVALID => uo_data_valid_int,
- MCB_UOCMDREADY => uo_cmd_ready_in_int,
- MCB_UO_CAL_START => uo_cal_start_int,
- RZQ_PIN => rzq,
- ZIO_PIN => zio,
- CKE_Train => cke_train
- );
- mcb_ui_clk <= ui_clk;
- END GENERATE;
-
-
- gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
- DONE_SOFTANDHARD_CAL <= '0';
- MCB_SYSRST <= int_sys_rst;
- mcb_recal <= calib_recal;
- mcb_ui_read <= ui_read;
- mcb_ui_add <= ui_add;
- mcb_ui_cs <= ui_cs;
- mcb_ui_clk <= ui_clk;
- mcb_ui_sdi <= ui_sdi;
- mcb_ui_addr <= ui_addr;
- mcb_ui_broadcast <= ui_broadcast;
- mcb_ui_drp_update <= ui_drp_update;
- mcb_ui_done_cal <= ui_done_cal;
- mcb_ui_cmd <= ui_cmd;
- mcb_ui_cmd_in <= ui_cmd_in;
- mcb_ui_cmd_en <= ui_cmd_en;
- mcb_ui_dqcount <= ui_dqcount;
- mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
- mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
- mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
- mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
- mcb_ui_udqs_inc <= ui_udqs_inc;
- mcb_ui_udqs_dec <= ui_udqs_dec;
- mcb_ui_ldqs_inc <= ui_ldqs_inc;
- mcb_ui_ldqs_dec <= ui_ldqs_dec;
- end generate;
-
-
-
---//////////////////////////////////////////////////////
---//ODDRDES2 instantiations
---//////////////////////////////////////////////////////
-
---------
---ADDR
---------
-
- gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
-
-
- ioi_addr_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_addr(addr_ioi),
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_addr(addr_ioi),
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => address_90(addr_ioi),
- D2 => address_90(addr_ioi),
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
- END GENERATE;
-
---------
---BA
---------
-
- gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
-
-
- ioi_ba_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_ba(ba_ioi),
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_ba(ba_ioi),
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => ba_90(ba_ioi),
- D2 => ba_90(ba_ioi),
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
- END GENERATE;
-
---------
---CAS
---------
- ioi_cas_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_cas,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_cas,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => cas_90,
- D2 => cas_90,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
---------
---CKE
---------
- ioi_cke_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2,
- TRAIN_PATTERN => 15
- )
- PORT MAP (
- OQ => ioi_cke,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_cke,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => cke_90,
- D2 => cke_90,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => '0', --int_sys_rst
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => cke_train
- );
---------
---ODT
---------
- xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
-
- ioi_odt_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
--- TRAIN_PATTERN => 0
- )
- PORT MAP (
- OQ => ioi_odt,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_odt,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => odt_90,
- D2 => odt_90,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
- END GENERATE;
-
---------
---RAS
---------
- ioi_ras_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_ras,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_ras,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => ras_90,
- D2 => ras_90,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
---------
---RST
---------
- xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
- ioi_rst_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_rst,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_rst,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => rst_90,
- D2 => rst_90,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
- END GENERATE;
---------
---WE
---------
- ioi_we_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_we,
- TQ => t_we,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => we_90,
- D2 => we_90,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
---------
---CK
---------
- ioi_ck_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ioi_ck,
- SHIFTOUT1 => open,--ck_shiftout0_1,
- SHIFTOUT2 => open,--ck_shiftout0_2,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => t_ck,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => '0',
- D2 => '1',
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => '0', --int_sys_rst
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => '0',
- T2 => '0',
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
-----------
-----CKN
-----------
--- ioi_ckn_0 : OSERDES2
--- GENERIC MAP (
--- BYPASS_GCLK_FF => TRUE,
--- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
--- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
--- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
--- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
--- DATA_WIDTH => 2
--- )
--- PORT MAP (
--- OQ => ioi_ckn,
--- SHIFTOUT1 => open,
--- SHIFTOUT2 => open,
--- SHIFTOUT3 => open,--ck_shiftout1_3,
--- SHIFTOUT4 => open,--ck_shiftout1_4,
--- TQ => t_ckn,
--- CLK0 => ioclk0,
--- CLK1 => '0',
--- CLKDIV => '0',
--- D1 => '1',
--- D2 => '0',
--- D3 => '0',
--- D4 => '0',
--- IOCE => pll_ce_0,
--- OCE => '1',
--- RST => '0',
--- SHIFTIN1 => '0',
--- SHIFTIN2 => '0',
--- SHIFTIN3 => '0',
--- SHIFTIN4 => '0',
--- T1 => '0',
--- T2 => '0',
--- T3 => '0',
--- T4 => '0',
--- TCE => '1',
--- TRAIN => '0'
--- );
---
---------
---UDM
---------
-
- ioi_udm_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => udm_oq,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => udm_t,
- CLK0 => ioclk90,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => dqpum,
- D2 => dqnum,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_90,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => dqIO_w_en_0,
- T2 => dqIO_w_en_0,
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
---------
---LDM
---------
- ioi_ldm_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- )
- PORT MAP (
- OQ => ldm_oq,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => ldm_t,
- CLK0 => ioclk90,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => dqplm,
- D2 => dqnlm,
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_90,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => dqIO_w_en_0,
- T2 => dqIO_w_en_0,
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
---------
---DQ
---------
- gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
- oserdes2_dq_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2,
- TRAIN_PATTERN => 5
- )
- PORT MAP (
- OQ => dq_oq(dq),
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => dq_tq(dq),
- CLK0 => ioclk90,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => dqo_p(dq),
- D2 => dqo_n(dq),
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_90,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => dqIO_w_en_0,
- T2 => dqIO_w_en_0,
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => ioi_drp_train
- );
- END GENERATE;
-
---------
---DQSP
---------
-
-
- oserdes2_dqsp_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
- -- TRAIN_PATTERN => 0
- )
- PORT MAP (
- OQ => dqsp_oq,
- SHIFTOUT1 => open,--dqs_shiftout0_1,
- SHIFTOUT2 => open,--dqs_shiftout0_2,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => dqsp_tq,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => '0',
- D2 => '1',
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',--dqs_shiftout1_3,
- SHIFTIN4 => '0',--dqs_shiftout1_4,
- T1 => dqsIO_w_en_90_n,
- T2 => dqsIO_w_en_90_p,
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
---------
---DQSN
---------
-
- oserdes2_dqsn_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
- DATA_WIDTH => 2
- -- TRAIN_PATTERN => 0
- )
- PORT MAP (
- OQ => dqsn_oq,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,--dqs_shiftout1_3,
- SHIFTOUT4 => open,--dqs_shiftout1_4,
- TQ => dqsn_tq,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => '1',
- D2 => '0',
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',--dqs_shiftout0_1,
- SHIFTIN2 => '0',--dqs_shiftout0_2,
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => dqsIO_w_en_90_n,
- T2 => dqsIO_w_en_90_p,
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
---------
---UDQSP
---------
-
- oserdeS2_UDQSP_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
- DATA_WIDTH => 2
--- TRAIN_PATTERN => 0
- )
- PORT MAP (
- OQ => udqsp_oq,
- SHIFTOUT1 => open,--udqs_shiftout0_1,
- SHIFTOUT2 => open,--udqs_shiftout0_2,
- SHIFTOUT3 => open,
- SHIFTOUT4 => open,
- TQ => udqsp_tq,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => '0',
- D2 => '1',
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',
- SHIFTIN2 => '0',
- SHIFTIN3 => '0',--udqs_shiftout1_3,
- SHIFTIN4 => '0',--udqs_shiftout1_4,
- T1 => dqsIO_w_en_90_n,
- t2 => dqsIO_w_en_90_p,
- T3 => '0',
- T4 => '0',
- tce => '1',
- train => '0'
- );
-
---------
---UDQSN
---------
-
- oserdes2_udqsn_0 : OSERDES2
- GENERIC MAP (
- BYPASS_GCLK_FF => TRUE,
- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
- DATA_WIDTH => 2
--- TRAIN_PATTERN => 0
- )
- PORT MAP (
- OQ => udqsn_oq,
- SHIFTOUT1 => open,
- SHIFTOUT2 => open,
- SHIFTOUT3 => open,--udqs_shiftout1_3,
- SHIFTOUT4 => open,--udqs_shiftout1_4,
- TQ => udqsn_tq,
- CLK0 => ioclk0,
- CLK1 => '0',
- CLKDIV => '0',
- D1 => '1',
- D2 => '0',
- D3 => '0',
- D4 => '0',
- IOCE => pll_ce_0,
- OCE => '1',
- RST => int_sys_rst,
- SHIFTIN1 => '0',--udqs_shiftout0_1,
- SHIFTIN2 => '0',--udqs_shiftout0_2,
- SHIFTIN3 => '0',
- SHIFTIN4 => '0',
- T1 => dqsIO_w_en_90_n,
- T2 => dqsIO_w_en_90_p,
- T3 => '0',
- T4 => '0',
- TCE => '1',
- TRAIN => '0'
- );
-
-------------------------------------------------------
---*********************************** OSERDES2 instantiations end *******************************************
-------------------------------------------------------
-
-------------------------------------------------
---&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
-------------------------------------------------
----#####################################--X16 MEMORY WIDTH-#############################################
-
- dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
-
---////////////////////////////////////////////////
---DQ14
---////////////////////////////////////////////////
-
- iodrp2_DQ_14 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
- MCB_ADDRESS => 7,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_14,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(14),
- DQSOUTN => open,
- DQSOUTP => in_dq(14),
- SDO => open,
- TOUT => t_dq(14),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_15,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(14),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(14),
- SDI => ioi_drp_sdo,
- T => dq_tq(14)
- );
-
---////////////////////////////////////////////////
---DQ15
---////////////////////////////////////////////////
-
-
- iodrp2_dq_15 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
- MCB_ADDRESS => 7,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_15,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(15),
- DQSOUTN => open,
- DQSOUTP => in_dq(15),
- SDO => open,
- TOUT => t_dq(15),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => '0',
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(15),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(15),
- SDI => ioi_drp_sdo,
- T => dq_tq(15)
- );
-
---////////////////////////////////////////////////
---DQ12
---////////////////////////////////////////////////
-
- iodrp2_DQ_12 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
- MCB_ADDRESS => 6,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_12,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(12),
- DQSOUTN => open,
- DQSOUTP => in_dq(12),
- SDO => open,
- TOUT => t_dq(12),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_13,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(12),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(12),
- SDI => ioi_drp_sdo,
- T => dq_tq(12)
- );
-
---////////////////////////////////////////////////
---DQ13
---////////////////////////////////////////////////
-
- iodrp2_dq_13 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
- MCB_ADDRESS => 6,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_13,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(13),
- DQSOUTN => open,
- DQSOUTP => in_dq(13),
- SDO => open,
- TOUT => t_dq(13),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_14,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(13),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(13),
- SDI => ioi_drp_sdo,
- T => dq_tq(13)
- );
-
---/////////
---UDQSP
---/////////
-
- iodrp2_UDQSP_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
- MCB_ADDRESS => 14,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_udqsp,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_udqs,
- DQSOUTN => open,
- DQSOUTP => idelay_udqs_ioi_m,
- SDO => open,
- TOUT => t_udqs,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_udqsn,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_udqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => udqsp_oq,
- SDI => ioi_drp_sdo,
- T => udqsp_tq
- );
-
---/////////
---UDQSN
---/////////
-
- iodrp2_udqsn_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
- MCB_ADDRESS => 14,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_udqsn,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_udqsn,
- DQSOUTN => open,
- DQSOUTP => idelay_udqs_ioi_s,
- SDO => open,
- TOUT => t_udqsn,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_12,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_udqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => udqsn_oq,
- SDI => ioi_drp_sdo,
- T => udqsn_tq
- );
-
---/////////////////////////////////////////////////
---//DQ10
---////////////////////////////////////////////////
- iodrp2_DQ_10 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
- MCB_ADDRESS => 5,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_10,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(10),
- DQSOUTN => open,
- DQSOUTP => in_dq(10),
- SDO => open,
- TOUT => t_dq(10),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_11,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(10),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(10),
- SDI => ioi_drp_sdo,
- T => dq_tq(10)
- );
-
---/////////////////////////////////////////////////
---//DQ11
---////////////////////////////////////////////////
-
- iodrp2_dq_11 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
- MCB_ADDRESS => 5,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_11,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(11),
- DQSOUTN => open,
- DQSOUTP => in_dq(11),
- SDO => open,
- TOUT => t_dq(11),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_udqsp,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(11),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(11),
- SDI => ioi_drp_sdo,
- T => dq_tq(11)
- );
-
---/////////////////////////////////////////////////
---//DQ8
---////////////////////////////////////////////////
-
- iodrp2_DQ_8 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
- MCB_ADDRESS => 4,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_8,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(8),
- DQSOUTN => open,
- DQSOUTP => in_dq(8),
- SDO => open,
- TOUT => t_dq(8),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_9,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(8),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(8),
- SDI => ioi_drp_sdo,
- T => dq_tq(8)
- );
-
---/////////////////////////////////////////////////
---//DQ9
---////////////////////////////////////////////////
-
- iodrp2_dq_9 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
- MCB_ADDRESS => 4,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_9,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(9),
- DQSOUTN => open,
- DQSOUTP => in_dq(9),
- SDO => open,
- TOUT => t_dq(9),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_10,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(9),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(9),
- SDI => ioi_drp_sdo,
- T => dq_tq(9)
- );
-
---/////////////////////////////////////////////////
---//DQ0
---////////////////////////////////////////////////
-
- iodrp2_DQ_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
- MCB_ADDRESS => 0,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_0,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(0),
- DQSOUTN => open,
- DQSOUTP => in_dq(0),
- SDO => open,
- TOUT => t_dq(0),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_1,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(0),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(0),
- SDI => ioi_drp_sdo,
- T => dq_tq(0)
- );
-
---/////////////////////////////////////////////////
---//DQ1
---////////////////////////////////////////////////
-
- iodrp2_dq_1 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
- MCB_ADDRESS => 0,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_1,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(1),
- DQSOUTN => open,
- DQSOUTP => in_dq(1),
- SDO => open,
- TOUT => t_dq(1),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_8,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(1),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(1),
- SDI => ioi_drp_sdo,
- T => dq_tq(1)
- );
-
---/////////////////////////////////////////////////
---//DQ2
---////////////////////////////////////////////////
-
- iodrp2_DQ_2 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
- MCB_ADDRESS => 1,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_2,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(2),
- DQSOUTN => open,
- DQSOUTP => in_dq(2),
- SDO => open,
- TOUT => t_dq(2),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_3,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(2),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(2),
- SDI => ioi_drp_sdo,
- T => dq_tq(2)
- );
-
---/////////////////////////////////////////////////
---//DQ3
---////////////////////////////////////////////////
-
- iodrp2_dq_3 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
- MCB_ADDRESS => 1,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_3,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(3),
- DQSOUTN => open,
- DQSOUTP => in_dq(3),
- SDO => open,
- TOUT => t_dq(3),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_0,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(3),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(3),
- SDI => ioi_drp_sdo,
- T => dq_tq(3)
- );
-
---/////////
---//DQSP
---/////////
-
- iodrp2_DQSP_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
- MCB_ADDRESS => 15,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_dqsp,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dqs,
- DQSOUTN => open,
- DQSOUTP => idelay_dqs_ioi_m,
- SDO => open,
- TOUT => t_dqs,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_dqsn,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dqsp_oq,
- SDI => ioi_drp_sdo,
- T => dqsp_tq
- );
-
---/////////
---//DQSN
---/////////
-
- iodrp2_dqsn_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
- MCB_ADDRESS => 15,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_dqsn,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dqsn,
- DQSOUTN => open,
- DQSOUTP => idelay_dqs_ioi_s,
- SDO => open,
- TOUT => t_dqsn,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_2,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dqsn_oq,
- SDI => ioi_drp_sdo,
- T => dqsn_tq
- );
-
---/////////////////////////////////////////////////
---//DQ6
---////////////////////////////////////////////////
-
- iodrp2_DQ_6 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
- MCB_ADDRESS => 3,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_6,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(6),
- DQSOUTN => open,
- DQSOUTP => in_dq(6),
- SDO => open,
- TOUT => t_dq(6),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_7,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(6),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(6),
- SDI => ioi_drp_sdo,
- T => dq_tq(6)
- );
-
---/////////////////////////////////////////////////
---//DQ7
---////////////////////////////////////////////////
-
- iodrp2_dq_7 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
- MCB_ADDRESS => 3,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_7,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(7),
- DQSOUTN => open,
- DQSOUTP => in_dq(7),
- SDO => open,
- TOUT => t_dq(7),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_dqsp,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(7),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(7),
- SDI => ioi_drp_sdo,
- T => dq_tq(7)
- );
-
---/////////////////////////////////////////////////
---//DQ4
---////////////////////////////////////////////////
-
- iodrp2_DQ_4 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
- MCB_ADDRESS => 2,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_4,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(4),
- DQSOUTN => open,
- DQSOUTP => in_dq(4),
- SDO => open,
- TOUT => t_dq(4),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_5,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(4),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(4),
- SDI => ioi_drp_sdo,
- T => dq_tq(4)
- );
-
---/////////////////////////////////////////////////
---//DQ5
---////////////////////////////////////////////////
-
- iodrp2_dq_5 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
- MCB_ADDRESS => 2,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_5,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(5),
- DQSOUTN => open,
- DQSOUTP => in_dq(5),
- SDO => open,
- TOUT => t_dq(5),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_6,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(5),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(5),
- SDI => ioi_drp_sdo,
- T => dq_tq(5)
- );
-
-
-
-
---/////////////////////////////////////////////////
---//UDM
---////////////////////////////////////////////////
-
- iodrp2_dq_udm : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => 0,
- MCB_ADDRESS => 8,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => ioi_drp_sdi,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_udm,
- DQSOUTN => open,
- DQSOUTP => open,
- SDO => open,
- TOUT => t_udm,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_ldm,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => '0',
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => udm_oq,
- SDI => ioi_drp_sdo,
- T => udm_t
- );
-
---/////////////////////////////////////////////////
---//LDM
---////////////////////////////////////////////////
-
- iodrp2_dq_ldm : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => 0,
- MCB_ADDRESS => 8,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_ldm,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_ldm,
- DQSOUTN => open,
- DQSOUTP => open,
- SDO => open,
- TOUT => t_ldm,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_4,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => '0',
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => ldm_oq,
- SDI => ioi_drp_sdo,
- T => ldm_t
- );
-
-end generate;
-
----#####################################--X8 MEMORY WIDTH-#############################################
-
- dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
---/////////////////////////////////////////////////
---//DQ0
---////////////////////////////////////////////////
- iodrp2_DQ_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
- MCB_ADDRESS => 0,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_0,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(0),
- DQSOUTN => open,
- DQSOUTP => in_dq(0),
- SDO => open,
- TOUT => t_dq(0),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_1,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(0),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(0),
- SDI => ioi_drp_sdo,
- T => dq_tq(0)
- );
-
---/////////////////////////////////////////////////
---//DQ1
---////////////////////////////////////////////////
-
- iodrp2_dq_1 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
- MCB_ADDRESS => 0,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_1,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(1),
- DQSOUTN => open,
- DQSOUTP => in_dq(1),
- SDO => open,
- TOUT => t_dq(1),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => '0',
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(1),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(1),
- SDI => ioi_drp_sdo,
- T => dq_tq(1)
- );
-
---/////////////////////////////////////////////////
---//DQ2
---////////////////////////////////////////////////
-
- iodrp2_DQ_2 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
- MCB_ADDRESS => 1,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_2,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(2),
- DQSOUTN => open,
- DQSOUTP => in_dq(2),
- SDO => open,
- TOUT => t_dq(2),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_3,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(2),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(2),
- SDI => ioi_drp_sdo,
- T => dq_tq(2)
- );
-
---/////////////////////////////////////////////////
---//DQ3
---////////////////////////////////////////////////
-
- iodrp2_dq_3 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
- MCB_ADDRESS => 1,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_3,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(3),
- DQSOUTN => open,
- DQSOUTP => in_dq(3),
- SDO => open,
- TOUT => t_dq(3),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_0,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(3),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(3),
- SDI => ioi_drp_sdo,
- T => dq_tq(3)
- );
-
---/////////
---//DQSP
---/////////
-
- iodrp2_DQSP_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
- MCB_ADDRESS => 15,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_dqsp,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dqs,
- DQSOUTN => open,
- DQSOUTP => idelay_dqs_ioi_m,
- SDO => open,
- TOUT => t_dqs,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_dqsn,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dqsp_oq,
- SDI => ioi_drp_sdo,
- T => dqsp_tq
- );
-
---/////////
---//DQSN
---/////////
- iodrp2_dqsn_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
- MCB_ADDRESS => 15,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_dqsn,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dqsn,
- DQSOUTN => open,
- DQSOUTP => idelay_dqs_ioi_s,
- SDO => open,
- TOUT => t_dqsn,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_2,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dqsn_oq,
- SDI => ioi_drp_sdo,
- T => dqsn_tq
- );
-
---/////////////////////////////////////////////////
---//DQ6
---////////////////////////////////////////////////
-
- iodrp2_DQ_6 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
- MCB_ADDRESS => 3,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_6,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(6),
- DQSOUTN => open,
- DQSOUTP => in_dq(6),
- SDO => open,
- TOUT => t_dq(6),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_7,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(6),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(6),
- SDI => ioi_drp_sdo,
- T => dq_tq(6)
- );
-
---/////////////////////////////////////////////////
---//DQ7
---////////////////////////////////////////////////
-
- iodrp2_dq_7 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
- MCB_ADDRESS => 3,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_7,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(7),
- DQSOUTN => open,
- DQSOUTP => in_dq(7),
- SDO => open,
- TOUT => t_dq(7),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_dqsp,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(7),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(7),
- SDI => ioi_drp_sdo,
- T => dq_tq(7)
- );
-
---/////////////////////////////////////////////////
---//DQ4
---////////////////////////////////////////////////
-
- iodrp2_DQ_4 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
- MCB_ADDRESS => 2,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_4,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(4),
- DQSOUTN => open,
- DQSOUTP => in_dq(4),
- SDO => open,
- TOUT => t_dq(4),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_5,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(4),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(4),
- SDI => ioi_drp_sdo,
- T => dq_tq(4)
- );
---/////////////////////////////////////////////////
---//DQ5
---////////////////////////////////////////////////
-
-
- iodrp2_dq_5 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
- MCB_ADDRESS => 2,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_5,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(5),
- DQSOUTN => open,
- DQSOUTP => in_dq(5),
- SDO => open,
- TOUT => t_dq(5),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_6,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(5),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(5),
- SDI => ioi_drp_sdo,
- T => dq_tq(5)
- );
-
-
-
---NEED TO GENERATE UDM so that user won't instantiate in this location
-
---/////////////////////////////////////////////////
---//UDM
---////////////////////////////////////////////////
-
- iodrp2_dq_udm : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => 0,
- MCB_ADDRESS => 8,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => ioi_drp_sdi,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_udm,
- DQSOUTN => open,
- DQSOUTP => open,
- SDO => open,
- TOUT => t_udm,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_ldm,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => '0',
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => udm_oq,
- SDI => ioi_drp_sdo,
- T => udm_t
- );
-
---/////////////////////////////////////////////////
---//LDM
---////////////////////////////////////////////////
-
- iodrp2_dq_ldm : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => 0,
- MCB_ADDRESS => 8,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_ldm,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_ldm,
- DQSOUTN => open,
- DQSOUTP => open,
- SDO => open,
- TOUT => t_ldm,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_4,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => '0',
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => ldm_oq,
- SDI => ioi_drp_sdo,
- T => ldm_t
- );
-
-end generate;
-
----#####################################--X4 MEMORY WIDTH-#############################################
-
- dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
---/////////////////////////////////////////////////
---//DQ0
---////////////////////////////////////////////////
-
- iodrp2_DQ_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
- MCB_ADDRESS => 0,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_0,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(0),
- DQSOUTN => open,
- DQSOUTP => in_dq(0),
- SDO => open,
- TOUT => t_dq(0),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_1,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(0),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(0),
- SDI => ioi_drp_sdo,
- T => dq_tq(0)
- );
-
- --/////////////////////////////////////////////////
---//DQ1
---////////////////////////////////////////////////
-
- iodrp2_dq_1 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
- MCB_ADDRESS => 0,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_1,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(1),
- DQSOUTN => open,
- DQSOUTP => in_dq(1),
- SDO => open,
- TOUT => t_dq(1),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => '0',
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(1),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(1),
- SDI => ioi_drp_sdo,
- T => dq_tq(1)
- );
-
- --/////////////////////////////////////////////////
---//DQ2
---////////////////////////////////////////////////
-
- iodrp2_DQ_2 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
- MCB_ADDRESS => 1,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_2,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(2),
- DQSOUTN => open,
- DQSOUTP => in_dq(2),
- SDO => open,
- TOUT => t_dq(2),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_3,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(2),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(2),
- SDI => ioi_drp_sdo,
- T => dq_tq(2)
- );
-
---/////////////////////////////////////////////////
---//DQ3
---////////////////////////////////////////////////
-
- iodrp2_dq_3 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
- MCB_ADDRESS => 1,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_3,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dq(3),
- DQSOUTN => open,
- DQSOUTP => in_dq(3),
- SDO => open,
- TOUT => t_dq(3),
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_0,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dq(3),
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dq_oq(3),
- SDI => ioi_drp_sdo,
- T => dq_tq(3)
- );
-
---///////////////////////////////////////////////
---DQSP
---///////////////////////////////////////////////
- iodrp2_DQSP_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
- MCB_ADDRESS => 15,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_dqsp,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dqs,
- DQSOUTN => open,
- DQSOUTP => idelay_dqs_ioi_m,
- SDO => open,
- TOUT => t_dqs,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_dqsn,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dqsp_oq,
- SDI => ioi_drp_sdo,
- T => dqsp_tq
- );
-
---///////////////////////////////////////////////
---DQSN
---///////////////////////////////////////////////
-
- iodrp2_dqsn_0 : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQS_IODRP2_DATA_RATE,
- IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
- MCB_ADDRESS => 15,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_dqsn,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_dqsn,
- DQSOUTN => open,
- DQSOUTP => idelay_dqs_ioi_s,
- SDO => open,
- TOUT => t_dqsn,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_2,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => in_pre_dqsp,
- IOCLK0 => ioclk0,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => dqsn_oq,
- SDI => ioi_drp_sdo,
- T => dqsn_tq
- );
---///////////////////////////////////////////////
---UDM
---//////////////////////////////////////////////
- --NEED TO GENERATE UDM so that user won't instantiate in this location
-
-
- iodrp2_dq_udm : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => 0,
- MCB_ADDRESS => 8,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => ioi_drp_sdi,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_udm,
- DQSOUTN => open,
- DQSOUTP => open,
- SDO => open,
- TOUT => t_udm,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_ldm,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => '0',
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => udm_oq,
- SDI => ioi_drp_sdo,
- T => udm_t
- );
-
---///////////////////////////////////////////////
---LDM
---//////////////////////////////////////////////
-
-
- iodrp2_dq_ldm : IODRP2_MCB
- GENERIC MAP (
- DATA_RATE => C_DQ_IODRP2_DATA_RATE,
- IDELAY_VALUE => 0,
- MCB_ADDRESS => 8,
- ODELAY_VALUE => 0,
- SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
- SIM_TAPDELAY_VALUE => 10
- )
- PORT MAP (
- AUXSDO => aux_sdi_out_ldm,
- DATAOUT => open,
- DATAOUT2 => open,
- DOUT => ioi_ldm,
- DQSOUTN => open,
- DQSOUTP => open,
- SDO => open,
- TOUT => t_ldm,
- ADD => ioi_drp_add,
- AUXADDR => ioi_drp_addr,
- AUXSDOIN => aux_sdi_out_4,
- BKST => ioi_drp_broadcast,
- CLK => ioi_drp_clk,
- CS => ioi_drp_cs,
- IDATAIN => '0',
- IOCLK0 => ioclk90,
- IOCLK1 => '0',
- MEMUPDATE => ioi_drp_update,
- ODATAIN => ldm_oq,
- SDI => ioi_drp_sdo,
- T => ldm_t
- );
-
-end generate;
-
-------------------------------------------------
---&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
-------------------------------------------------
-
- -------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- --IOBs instantiations
- -- this part need more inputs from design team
- -- for now just use as listed in fpga.v
- -----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
--- DRAM Address
- gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
- iob_addr_inst : OBUFT
- PORT MAP (
- I => ioi_addr(addr_i),
- T => t_addr(addr_i),
- O => mcbx_dram_addr(addr_i)
- );
- END GENERATE;
-
- gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
- iob_ba_inst : OBUFT
- PORT MAP (
- I => ioi_ba(ba_i),
- T => t_ba(ba_i),
- O => mcbx_dram_ba(ba_i)
- );
- END GENERATE;
-
--- DRAM control
---RAS
- iob_ras : OBUFT
- PORT MAP (
- O => mcbx_dram_ras_n,
- I => ioi_ras,
- T => t_ras
- );
-
---CAS
- iob_cas : OBUFT
- PORT MAP (
- O => mcbx_dram_cas_n,
- I => ioi_cas,
- T => t_cas
- );
-
---WE
- iob_we : OBUFT
- PORT MAP (
- O => mcbx_dram_we_n,
- I => ioi_we,
- T => t_we
- );
-
---CKE
- iob_cke : OBUFT
- PORT MAP (
- O => mcbx_dram_cke,
- I => ioi_cke,
- T => t_cke
- );
-
---DDR3 RST
- gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
- iob_rst : OBUFT
- PORT MAP (
- O => mcbx_dram_ddr3_rst,
- I => ioi_rst,
- T => t_rst
- );
- END GENERATE;
-
---ODT
- gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
- OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
- iob_odt : OBUFT
- PORT MAP (
- O => mcbx_dram_odt,
- I => ioi_odt,
- t => t_odt
- );
- END GENERATE;
-
---MEMORY CLOCK
- iob_clk : OBUFTDS
- PORT MAP (
- I => ioi_ck,
- T => t_ck,
- O => mcbx_dram_clk,
- OB => mcbx_dram_clk_n
- );
-
---DQ
- gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
- gen_iob_dq_inst : IOBUF
- PORT MAP (
- IO => mcbx_dram_dq(dq_i),
- I => ioi_dq(dq_i),
- T => t_dq(dq_i),
- O => in_pre_dq(dq_i)
- );
- END GENERATE;
-
--- x4 and x8
---DQS
-gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
-(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
- iob_dqs : IOBUF
- PORT MAP (
- IO => mcbx_dram_dqs,
- I => ioi_dqs,
- T => t_dqs,
- O => in_pre_dqsp
- );
-end generate;
-
---DQSP/DQSN
-gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
-(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
- iob_dqs : IOBUFDS
- PORT MAP (
- IO => mcbx_dram_dqs,
- IOB => mcbx_dram_dqs_n,
- I => ioi_dqs,
- T => t_dqs,
- O => in_pre_dqsp
- );
-end generate;
-
--- x16
---UDQS
-gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
-(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
- iob_udqs : IOBUF
- PORT MAP (
- IO => mcbx_dram_udqs,
- I => ioi_udqs,
- T => t_udqs,
- O => in_pre_udqsp
- );
-end generate;
-
-----UDQSP/UDQSN
-gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
-(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
- iob_udqs : IOBUFDS
- PORT MAP (
- IO => mcbx_dram_udqs,
- IOB => mcbx_dram_udqs_n,
- I => ioi_udqs,
- T => t_udqs,
- O => in_pre_udqsp
- );
-end generate;
-
--- DQS PULLDWON
-gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
-dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
-end generate;
-
-gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
-(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
-dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
-dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
-end generate;
-
--- DQSN PULLUP
-gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
-(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
-udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
-end generate;
-
-gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
- (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
-udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
-udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
-end generate;
-
---UDM
-gen_udm : if(C_NUM_DQ_PINS = 16) generate
- iob_udm : OBUFT
- PORT MAP (
- I => ioi_udm,
- T => t_udm,
- O => mcbx_dram_udm
- );
-end generate;
---LDM
- iob_ldm : OBUFT
- PORT MAP (
- I => ioi_ldm,
- T => t_ldm,
- O => mcbx_dram_ldm
- );
-
- end aarch;
-
ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd
===================================================================
--- ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd (revision 5)
+++ ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd (nonexistent)
@@ -1,281 +0,0 @@
---*****************************************************************************
--- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
---*****************************************************************************
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor : Xilinx
--- \ \ \/ Version : 3.5
--- \ \ Application : MIG
--- / / Filename : memc3_infrastructure.vhd
--- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $
--- \ \ / \ Date Created : Jul 03 2009
--- \___\/\___\
---
---Device : Spartan-6
---Design Name : DDR/DDR2/DDR3/LPDDR
---Purpose : Clock generation/distribution and reset synchronization
---Reference :
---Revision History :
---*****************************************************************************
-library ieee;
-use ieee.std_logic_1164.all;
-library unisim;
-use unisim.vcomponents.all;
-
-entity memc3_infrastructure is
-generic
- (
- C_MEMCLK_PERIOD : integer := 2500;
- C_RST_ACT_LOW : integer := 1;
- C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
- C_CLKOUT0_DIVIDE : integer := 2;
- C_CLKOUT1_DIVIDE : integer := 2;
- C_CLKOUT2_DIVIDE : integer := 16;
- C_CLKOUT3_DIVIDE : integer := 8;
- C_CLKFBOUT_MULT : integer := 4;
- C_DIVCLK_DIVIDE : integer := 1
-
- );
-port
-(
- sys_clk_p : in std_logic;
- sys_clk_n : in std_logic;
- sys_clk : in std_logic;
- sys_rst_n : in std_logic;
- clk0 : out std_logic;
- rst0 : out std_logic;
- async_rst : out std_logic;
- sysclk_2x : out std_logic;
- sysclk_2x_180 : out std_logic;
- mcb_drp_clk : out std_logic;
- pll_ce_0 : out std_logic;
- pll_ce_90 : out std_logic;
- pll_lock : out std_logic
-
-);
-end entity;
-architecture syn of memc3_infrastructure is
-
- -- # of clock cycles to delay deassertion of reset. Needs to be a fairly
- -- high number not so much for metastability protection, but to give time
- -- for reset (i.e. stable clock cycles) to propagate through all state
- -- machines and to all control signals (i.e. not all control signals have
- -- resets, instead they rely on base state logic being reset, and the effect
- -- of that reset propagating through the logic). Need this because we may not
- -- be getting stable clock cycles while reset asserted (i.e. since reset
- -- depends on PLL/DCM lock status)
-
- constant RST_SYNC_NUM : integer := 25;
- constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0;
- constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000;
-
-
- signal clk_2x_0 : std_logic;
- signal clk_2x_180 : std_logic;
- signal clk0_bufg : std_logic;
- signal clk0_bufg_in : std_logic;
- signal mcb_drp_clk_bufg_in : std_logic;
- signal clkfbout_clkfbin : std_logic;
- signal rst_tmp : std_logic;
- signal sys_rst : std_logic;
- signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
- signal powerup_pll_locked : std_logic;
- signal locked : std_logic;
- signal bufpll_mcb_locked : std_logic;
- signal mcb_drp_clk_sig : std_logic;
-
- attribute max_fanout : string;
- attribute syn_maxfan : integer;
- attribute KEEP : string;
- attribute max_fanout of rst0_sync_r : signal is "10";
- attribute syn_maxfan of rst0_sync_r : signal is 10;
-
-begin
-
- sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
- clk0 <= clk0_bufg;
- pll_lock <= bufpll_mcb_locked;
- mcb_drp_clk <= mcb_drp_clk_sig;
-
- --***************************************************************************
- -- Global clock generation and distribution
- --***************************************************************************
-
- u_pll_adv : PLL_ADV
- generic map
- (
- BANDWIDTH => "OPTIMIZED",
- CLKIN1_PERIOD => CLK_PERIOD_NS,
- CLKIN2_PERIOD => CLK_PERIOD_NS,
- CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
- CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
- CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
- CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
- CLKOUT4_DIVIDE => 1,
- CLKOUT5_DIVIDE => 1,
- CLKOUT0_PHASE => 0.000,
- CLKOUT1_PHASE => 180.000,
- CLKOUT2_PHASE => 0.000,
- CLKOUT3_PHASE => 0.000,
- CLKOUT4_PHASE => 0.000,
- CLKOUT5_PHASE => 0.000,
- CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DUTY_CYCLE => 0.500,
- CLKOUT3_DUTY_CYCLE => 0.500,
- CLKOUT4_DUTY_CYCLE => 0.500,
- CLKOUT5_DUTY_CYCLE => 0.500,
- COMPENSATION => "INTERNAL",
- DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
- CLKFBOUT_MULT => C_CLKFBOUT_MULT,
- CLKFBOUT_PHASE => 0.0,
- REF_JITTER => 0.005000
- )
- port map
- (
- CLKFBIN => clkfbout_clkfbin,
- CLKINSEL => '1',
- CLKIN1 => sys_clk,
- CLKIN2 => '0',
- DADDR => (others => '0'),
- DCLK => '0',
- DEN => '0',
- DI => (others => '0'),
- DWE => '0',
- REL => '0',
- RST => sys_rst,
- CLKFBDCM => open,
- CLKFBOUT => clkfbout_clkfbin,
- CLKOUTDCM0 => open,
- CLKOUTDCM1 => open,
- CLKOUTDCM2 => open,
- CLKOUTDCM3 => open,
- CLKOUTDCM4 => open,
- CLKOUTDCM5 => open,
- CLKOUT0 => clk_2x_0,
- CLKOUT1 => clk_2x_180,
- CLKOUT2 => clk0_bufg_in,
- CLKOUT3 => mcb_drp_clk_bufg_in,
- CLKOUT4 => open,
- CLKOUT5 => open,
- DO => open,
- DRDY => open,
- LOCKED => locked
- );
-
- U_BUFG_CLK0 : BUFG
- port map
- (
- O => clk0_bufg,
- I => clk0_bufg_in
- );
-
- U_BUFG_CLK1 : BUFG
- port map (
- O => mcb_drp_clk_sig,
- I => mcb_drp_clk_bufg_in
- );
-
- process (clk0_bufg, sys_rst)
- begin
- if (clk0_bufg'event and clk0_bufg = '1') then
- if(sys_rst = '1') then
- powerup_pll_locked <= '0';
- elsif (bufpll_mcb_locked = '1') then
- powerup_pll_locked <= '1';
- end if;
- end if;
- end process;
-
- --***************************************************************************
- -- Reset synchronization
- -- NOTES:
- -- 1. shut down the whole operation if the PLL hasn't yet locked (and
- -- by inference, this means that external sys_rst has been asserted -
- -- PLL deasserts LOCKED as soon as sys_rst asserted)
- -- 2. asynchronously assert reset. This was we can assert reset even if
- -- there is no clock (needed for things like 3-stating output buffers).
- -- reset deassertion is synchronous.
- -- 3. asynchronous reset only look at pll_lock from PLL during power up. After
- -- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
- -- forever until sys_rst is asserted again. PLL will lose lock when FPGA
- -- enters suspend mode. We don't want reset to MCB get
- -- asserted in the application that needs suspend feature.
- --***************************************************************************
-
- rst_tmp <= sys_rst or not(powerup_pll_locked);
-
- async_rst <= rst_tmp;
-
-process (clk0_bufg, rst_tmp)
- begin
- if (rst_tmp = '1') then
- rst0_sync_r <= (others => '1');
- elsif (rising_edge(clk0_bufg)) then
- rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
- end if;
- end process;
-
- rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
-
-
-BUFPLL_MCB_INST : BUFPLL_MCB
-port map
-( IOCLK0 => sysclk_2x,
- IOCLK1 => sysclk_2x_180,
- LOCKED => locked,
- GCLK => mcb_drp_clk_sig,
- SERDESSTROBE0 => pll_ce_0,
- SERDESSTROBE1 => pll_ce_90,
- PLLIN0 => clk_2x_0,
- PLLIN1 => clk_2x_180,
- LOCK => bufpll_mcb_locked
- );
-
-end architecture syn;
-
Index: ipcore_dir/mem0/user_design/par/mem_interface_top.ut
===================================================================
--- ipcore_dir/mem0/user_design/par/mem_interface_top.ut (revision 5)
+++ ipcore_dir/mem0/user_design/par/mem_interface_top.ut (nonexistent)
@@ -1,22 +0,0 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g M2Pin:PullUp
--g ProgPin:PullUp
--g DonePin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullNone
--g UserID:0xFFFFFFFF
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g ConfigRate:6
Index: ipcore_dir/mem0/user_design/par/mem0.ucf
===================================================================
--- ipcore_dir/mem0/user_design/par/mem0.ucf (revision 5)
+++ ipcore_dir/mem0/user_design/par/mem0.ucf (nonexistent)
@@ -1,139 +0,0 @@
-############################################################################
-##
-## Xilinx, Inc. 2006 www.xilinx.com
-## Tue Oct 5 23:28:56 2010
-## Generated by MIG Version 3.5
-##
-############################################################################
-## File name : mem0.ucf
-##
-## Details : Constraints file
-## FPGA family: spartan6
-## FPGA: xc6slx25-ftg256
-## Speedgrade: -3
-## Design Entry: VHDL
-## Design: without Test bench
-## DCM Used: Enable
-## No.Of Memory Controllers: 1
-##
-############################################################################
-############################################################################
-# VCC AUX VOLTAGE
-############################################################################
-CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
-
-############################################################################
-# Extended MCB performance mode requires a different Vccint specification to
-# achieve higher maximum frequencies for DDR2 and DDR3.Consult the Spartan-6
-#datasheet (DS162) table 2 and 24 for more information
-############################################################################
-CONFIG MCB_PERFORMANCE= STANDARD;
-
-
-##################################################################################
-# Timing Ignore constraints for paths crossing the clock domain
-##################################################################################
-NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
-NET "c?_pll_lock" TIG;
-
-
-############################################################################
-## Memory Controller 3
-## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT
-## Frequency: 200 MHz
-## Time Period: 5000 ps
-## Supported Part Numbers: MT46V32M16BN-5B-IT
-############################################################################
-
-############################################################################
-## Clock constraints
-############################################################################
-NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
-TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 5 ns HIGH 50 %;
-############################################################################
-
-############################################################################
-## I/O TERMINATION
-############################################################################
-NET "mcb3_dram_dq[*]" IN_TERM = UNTUNED_SPLIT_50;
-NET "mcb3_dram_dqs" IN_TERM = UNTUNED_SPLIT_50;
-NET "mcb3_dram_udqs" IN_TERM = UNTUNED_SPLIT_50;
-
-############################################################################
-# I/O STANDARDS
-############################################################################
-
-NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_a[*]" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_dqs" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_udqs" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL2_II;
-NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL2_II;
-NET "mcb3_dram_cke" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_ras_n" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_cas_n" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_we_n" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_dm" IOSTANDARD = SSTL2_II;
-NET "mcb3_dram_udm" IOSTANDARD = SSTL2_II;
-NET "mcb3_rzq" IOSTANDARD = SSTL2_II;
-NET "c3_sys_clk" IOSTANDARD = LVCMOS25;
-NET "c3_sys_rst_n" IOSTANDARD = LVCMOS25;
-############################################################################
-# MCB 3
-# Pin Location Constraints for Clock, Masks, Address, and Controls
-############################################################################
-
-NET "mcb3_dram_a[0]" LOC = "K5" ;
-NET "mcb3_dram_a[10]" LOC = "G6" ;
-NET "mcb3_dram_a[11]" LOC = "E3" ;
-NET "mcb3_dram_a[12]" LOC = "F3" ;
-NET "mcb3_dram_a[1]" LOC = "K6" ;
-NET "mcb3_dram_a[2]" LOC = "D1" ;
-NET "mcb3_dram_a[3]" LOC = "L4" ;
-NET "mcb3_dram_a[4]" LOC = "G5" ;
-NET "mcb3_dram_a[5]" LOC = "H4" ;
-NET "mcb3_dram_a[6]" LOC = "H3" ;
-NET "mcb3_dram_a[7]" LOC = "D3" ;
-NET "mcb3_dram_a[8]" LOC = "B2" ;
-NET "mcb3_dram_a[9]" LOC = "A2" ;
-NET "mcb3_dram_ba[0]" LOC = "C3" ;
-NET "mcb3_dram_ba[1]" LOC = "C2" ;
-NET "mcb3_dram_cas_n" LOC = "H5" ;
-NET "mcb3_dram_ck" LOC = "E2" ;
-NET "mcb3_dram_ck_n" LOC = "E1" ;
-NET "mcb3_dram_cke" LOC = "F4" ;
-NET "mcb3_dram_dm" LOC = "J4" ;
-NET "mcb3_dram_dq[0]" LOC = "K2" ;
-NET "mcb3_dram_dq[10]" LOC = "M2" ;
-NET "mcb3_dram_dq[11]" LOC = "M1" ;
-NET "mcb3_dram_dq[12]" LOC = "P2" ;
-NET "mcb3_dram_dq[13]" LOC = "P1" ;
-NET "mcb3_dram_dq[14]" LOC = "R2" ;
-NET "mcb3_dram_dq[15]" LOC = "R1" ;
-NET "mcb3_dram_dq[1]" LOC = "K1" ;
-NET "mcb3_dram_dq[2]" LOC = "J3" ;
-NET "mcb3_dram_dq[3]" LOC = "J1" ;
-NET "mcb3_dram_dq[4]" LOC = "F2" ;
-NET "mcb3_dram_dq[5]" LOC = "F1" ;
-NET "mcb3_dram_dq[6]" LOC = "G3" ;
-NET "mcb3_dram_dq[7]" LOC = "G1" ;
-NET "mcb3_dram_dq[8]" LOC = "L3" ;
-NET "mcb3_dram_dq[9]" LOC = "L1" ;
-NET "mcb3_dram_dqs" LOC = "H2" ;
-NET "mcb3_dram_ras_n" LOC = "J6" ;
-NET "c3_sys_clk" LOC = "M9" ;
-NET "c3_sys_rst_n" LOC = "P6" ;
-NET "mcb3_dram_udm" LOC = "K3" ;
-NET "mcb3_dram_udqs" LOC = "N3" ;
-NET "mcb3_dram_we_n" LOC = "C1" ;
-
-##################################################################################
-#RZQ is required for all MCB designs. Do not move the location #
-#of this pin for ES devices.For production devices, RZQ can be moved to any #
-#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
-#a 2R resistor should be connected between RZQand ground, where R is the desired#
-#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
-##################################################################################
-NET "mcb3_rzq" LOC = "M4" ;
-
Index: ipcore_dir/mem0/user_design/par/readme.txt
===================================================================
--- ipcore_dir/mem0/user_design/par/readme.txt (revision 5)
+++ ipcore_dir/mem0/user_design/par/readme.txt (nonexistent)
@@ -1,146 +0,0 @@
-::****************************************************************************
-:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-::
-:: This file contains confidential and proprietary information
-:: of Xilinx, Inc. and is protected under U.S. and
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-::
-::****************************************************************************
-:: ____ ____
-:: / /\/ /
-:: /___/ \ / Vendor : Xilinx
-:: \ \ \/ Version : 3.5
-:: \ \ Application : MIG
-:: / / Filename : readme.txt
-:: /___/ /\ Date Last Modified : $Date: 2010/05/21 09:18:32 $
-:: \ \ / \ Date Created : Fri Feb 06 2009
-:: \___\/\___\
-::
-:: Device : Spartan-6
-:: Design Name : DDR/DDR2/DDR3/LPDDR
-:: Purpose : Information about par folder
-:: Reference :
-:: Revision History :
-::****************************************************************************
-
-This folder has the batch files to synthesize using XST or Synplify Pro and
-implement the design either in "Command Line Mode" or in "GUI Mode".
-
-Steps to run the design using the ise_flow (batch mode):
-
-1. Executing the "ise_flow.bat" file synthesizes the design using XST or
- Synplify Pro and does implement the design.
- a. First it removes the XST/Synplify Pro report files, implementation
- files, supporting scripts, the generated chipscope designs (if
- enabled) and the ISE project files (if exist any on previous runs)
- b. Synthesizes the design either with XST or Synplicity
- c. Implements the design with ISE.
-
-2. After the design is run, it creates ise_flow_results.txt file that will have
- the ISE log information.
-
-Steps to run the design using the create_ise (GUI mode - for XST cases only):
-
-1. This file will appear for XST cases only.
-
-2. On executing the "create_ise.bat" file creates "test.xise" project file
- and set all the properties of the design selected.
-
-3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
-
-4. In Linux operating systems, test.xise project can be invoked by executing the command
- 'ise test.xise' from the terminal.
-
-Other files in PAR folder :
-
-* "mem0.ucf" file is the constraint file for the design.
- It has clock constraints, location constraints and IO standards.
-
-* "mem_interface_top.ut" file has the options for the Configuration file
- generation i.e. the "mem0.bit" file to run in batch mode.
-
-* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
- implementation files, supporting scripts, the generated chipscope designs
- (if enabled) and the ISE project files.
-
-* "set_ise_prop.tcl" file has all the properties that are to be
- set in GUI mode.
-
-* "ise_run.txt" file has synthesis options for the XST tool.
- This file is used for batch mode.
-
-* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
- generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
- EDIF/NGC files, you must execute the following commands before starting
- synthesis and PAR.
-
- coregen -b ila_coregen.xco
- coregen -b icon_coregen.xco
- coregen -b vio_coregen.xco
-
-Note : When you generate the design using "Debug Signals for Memory Controller"
- option Enable, the above mentioned ChipScope coregen commands are printed
- into ise_flow.bat and create_ise.bat files. The mem0 rtl file
- will have the design debug signals portmapped to vio and icon
- ChipScope modules.
-
-* At the start of a Chip Scope Analyzer project, all of the signals in
- every core have generic names. "mem0.cdc" is a file that contains
- all the signal names of all cores. Upon importing this file, signal names are
- renamed to the specified names in "mem0.cdc" file. This file will work
- for the generated designs from MIG. If any of the design parameter values
- are changed after generating the design, this file will not work.
- For Multiple Controller designs, signal names provided in CDC file are of
- the controller that is enabled for Debug in the GUI.
-
-synth folder:
-
-1. mem_interface_top_synp.sdc
-2. script_synp.tcl
-3. mem0.prj
-4. mem0.lso
-
- mem_interface_top_synp.sdc and script_synp.tcl files are being used by
- Synplify Pro and mem0.prj and mem0.lso are being used by XST.
-
-
Index: ipcore_dir/mem0/user_design/par/ise_run.txt
===================================================================
--- ipcore_dir/mem0/user_design/par/ise_run.txt (revision 5)
+++ ipcore_dir/mem0/user_design/par/ise_run.txt (nonexistent)
@@ -1,57 +0,0 @@
-set -tmpdir ../synth/__projnav
-set -xsthdpdir ../synth/xst
-run
-#Source Parameters
--ifn ../synth/mem0.prj
--ifmt mixed
--iuc No
-#Target Parameters
--ofn mem0
--ofmt NGC
--p xc6slx25-3ftg256
-#Source Options
--top mem0
--fsm_extract Yes
--fsm_encoding Auto
--safe_implementation No
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--rom_style Auto
--shreg_extract Yes
--resource_sharing Yes
--async_to_sync no
--mult_style auto
--register_balancing No
-#Target Options
--iobuf Yes
-#Max fanout value shouldn't be set below 64 for MCB design
--max_fanout 500
--bufg 16
--register_duplication yes
--optimize_primitives No
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob auto
--equivalent_register_removal yes
-#General Options
--opt_mode Speed
--opt_level 1
--lso ../synth/mem0.lso
--keep_hierarchy NO
--netlist_hierarchy as_optimized
--rtlview Yes
--glob_opt allclocknets
--read_cores Yes
--write_timing_constraints No
--cross_clock_analysis No
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--auto_bram_packing No
--slice_utilization_ratio_maxmargin 5
-quit
Index: ipcore_dir/mem0/user_design/par/set_ise_prop.tcl
===================================================================
--- ipcore_dir/mem0/user_design/par/set_ise_prop.tcl (revision 5)
+++ ipcore_dir/mem0/user_design/par/set_ise_prop.tcl (nonexistent)
@@ -1,89 +0,0 @@
-project new test.xise
-
-project set "Device Family" "spartan6"
-
-project set "Device" "xc6slx25"
-
-project set "Package" "ftg256"
-
-project set "Speed Grade" "-3"
-
-project set "Synthesis Tool" "XST (VHDL/Verilog)"
-
-project set "Simulator" "ISim (VHDL/Verilog)"
-
-xfile add "../rtl/iodrp_controller.vhd"
-xfile add "../rtl/iodrp_mcb_controller.vhd"
-xfile add "../rtl/mcb_raw_wrapper.vhd"
-xfile add "../rtl/mcb_soft_calibration.vhd"
-xfile add "../rtl/mcb_soft_calibration_top.vhd"
-xfile add "../rtl/mem0.vhd"
-xfile add "../rtl/memc3_infrastructure.vhd"
-xfile add "../rtl/memc3_wrapper.vhd"
-
-xfile add "mem0.ucf"
-
-project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
-project set "Safe Implementation" "No" -process "Synthesize - XST"
-project set "FSM Style" "LUT" -process "Synthesize - XST"
-project set "RAM Extraction" "True" -process "Synthesize - XST"
-project set "RAM Style" "Auto" -process "Synthesize - XST"
-project set "ROM Extraction" "True" -process "Synthesize - XST"
-project set "ROM Style" "Auto" -process "Synthesize - XST"
-project set "Resource Sharing" "True" -process "Synthesize - XST"
-project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
-project set "Register Balancing" "No" -process "Synthesize - XST"
-project set "Add I/O Buffers" "True" -process "Synthesize - XST"
-project set "Max Fanout" "500" -process "Synthesize - XST"
-project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
-project set "Register Duplication" "True" -process "Synthesize - XST"
-project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
-project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
-project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
-project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
-project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
-project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
-project set "Optimization Goal" "Speed" -process "Synthesize - XST"
-project set "Optimization Effort" "Normal" -process "Synthesize - XST"
-project set "Library Search Order" "../synth/mem0.lso" -process "Synthesize - XST"
-project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
-project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
-project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
-project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
-project set "Read Cores" "True" -process "Synthesize - XST"
-project set "Write Timing Constraints" "False" -process "Synthesize - XST"
-project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
-project set "Hierarchy Separator" "/" -process "Synthesize - XST"
-project set "Bus Delimiter" "<>" -process "Synthesize - XST"
-project set "Case" "Maintain" -process "Synthesize - XST"
-project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
-project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
-project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
-
-project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
-
-project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
-
-project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
-project set "Create Binary Configuration File" "False" -process "Generate Programming File"
-project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
-project set "Configuration Rate" "6" -process "Generate Programming File"
-project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
-project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
-project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
-project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
-project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
-project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
-project set "Unused IOB Pins" "Float" -process "Generate Programming File"
-project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
-project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
-project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
-project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
-project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
-project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
-project set "Drive Done Pin High" "False" -process "Generate Programming File"
-project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
-
-project close
-
-
Index: ipcore_dir/mem0/user_design/synth/mem0.lso
===================================================================
--- ipcore_dir/mem0/user_design/synth/mem0.lso (revision 5)
+++ ipcore_dir/mem0/user_design/synth/mem0.lso (nonexistent)
@@ -1 +0,0 @@
-work
Index: ipcore_dir/mem0/user_design/synth/mem_interface_top_synp.sdc
===================================================================
--- ipcore_dir/mem0/user_design/synth/mem_interface_top_synp.sdc (revision 5)
+++ ipcore_dir/mem0/user_design/synth/mem_interface_top_synp.sdc (nonexistent)
@@ -1,20 +0,0 @@
-# Synplicity, Inc. constraint file
-# Written on Mon Jun 27 15:50:39 2005
-
-define_attribute {v:work.iodrp_controller} syn_hier {hard}
-define_attribute {v:work.iodrp_mcb_controller} syn_hier {hard}
-define_attribute {v:work.mcb_raw_wrapper} syn_hier {hard}
-define_attribute {v:work.mcb_soft_calibration} syn_hier {hard}
-define_attribute {v:work.mcb_soft_calibration_top} syn_hier {hard}
-define_attribute {v:work.mem0} syn_hier {hard}
-define_attribute {v:work.memc3_infrastructure} syn_hier {hard}
-define_attribute {v:work.memc3_wrapper} syn_hier {hard}
-
-# clock Constraints
-define_clock -disable -name {memc3_infrastructure_inst} -period 5000 -clockgroup default_clkgroup_1
-define_clock -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 5000 -clockgroup default_clkgroup_2
-define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 5000 -clockgroup default_clkgroup_3
-
-
-
-
Index: ipcore_dir/mem0/user_design/synth/script_synp.tcl
===================================================================
--- ipcore_dir/mem0/user_design/synth/script_synp.tcl (revision 5)
+++ ipcore_dir/mem0/user_design/synth/script_synp.tcl (nonexistent)
@@ -1,39 +0,0 @@
-project -new
-add_file -vhdl "../rtl/iodrp_controller.vhd"
-add_file -vhdl "../rtl/iodrp_mcb_controller.vhd"
-add_file -vhdl "../rtl/mcb_raw_wrapper.vhd"
-add_file -vhdl "../rtl/mcb_soft_calibration.vhd"
-add_file -vhdl "../rtl/mcb_soft_calibration_top.vhd"
-add_file -vhdl "../rtl/mem0.vhd"
-add_file -vhdl "../rtl/memc3_infrastructure.vhd"
-add_file -vhdl "../rtl/memc3_wrapper.vhd"
-add_file -constraint "../synth/mem_interface_top_synp.sdc"
-impl -add rev_1
-set_option -technology spartan6
-set_option -part xc6slx25
-set_option -package ftg256
-set_option -speed_grade -3
-set_option -default_enum_encoding default
-set_option -symbolic_fsm_compiler 1
-set_option -resource_sharing 0
-set_option -use_fsm_explorer 0
-set_option -top_module "mem0"
-set_option -frequency 200
-set_option -fanout_limit 1000
-set_option -disable_io_insertion 0
-set_option -pipe 1
-set_option -fixgatedclocks 0
-set_option -retiming 0
-set_option -modular 0
-set_option -update_models_cp 0
-set_option -verification_mode 0
-set_option -write_verilog 0
-set_option -write_vhdl 0
-set_option -write_apr_constraint 0
-project -result_file "../synth/rev_1/mem0.edf"
-set_option -vlog_std v2001
-set_option -auto_constrain_io 0
-impl -active "../synth/rev_1"
-project -run
-project -save
-