URL
https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk
Subversion Repositories usb_fpga_1_11
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb_fpga_1_11/trunk/examples/usb-fpga-1.2/intraffic
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/InTraffic.java
1,6 → 1,6
/*! |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB FPGA Module 1.2 |
Copyright (C) 2009-2010 ZTEX e.K. |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.2 |
Copyright (C) 2009-2011 ZTEX GmbH. |
http://www.ztex.de |
|
This program is free software; you can redistribute it and/or modify |
/intraffic.c
1,6 → 1,6
/*! |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB FPGA Module 1.2 |
Copyright (C) 2009-2010 ZTEX e.K. |
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.2 |
Copyright (C) 2009-2011 ZTEX GmbH. |
http://www.ztex.de |
|
This program is free software; you can redistribute it and/or modify |
21,7 → 21,7
|
// 1024 (instead of 512) byte bulk transfers. |
// According to USB standard they are invalid but usually supported and 25% faster. |
#define[fastmode] |
//#define[fastmode] |
|
#ifdef[fastmode] |
// configure endpoint 2, in, quad buffered, 1024 bytes, interface 0 |
/fpga/intraffic.ise
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/fpga/intraffic.xise
80,7 → 80,7
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/> |