OpenCores
URL https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk

Subversion Repositories usb_fpga_1_11

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  • This comparison shows the changes necessary to convert path 
    /usb_fpga_1_11/trunk/include
    from Rev 5 to Rev 6
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  •

Rev 5 → Rev 6

/ztex-descriptors.h
50,9 → 50,12
10.*.*.* // used for ZTEX products
10.11.*.* // ZTEX USB-FPGA-Module 1.2
10.12.*.* // ZTEX USB-FPGA-Module 1.11
10.13.*.* // ZTEX USB-FPGA-Module 1.15
10.13.*.* // ZTEX USB-FPGA-Module 1.15 (not 1.15y)
10.14.*.* // ZTEX USB-FPGA-Module 1.15x
10.15.*.* // ZTEX USB-FPGA-Module 1.15y
10.20.*.* // ZTEX USB-Module 1.0
10.30.*.* // ZTEX USB-XMEGA-Module 1.0
10.0.1.1 // ZTEX bitminer firmware
Please contact me (http://www.ztex.de --> Impressum/Kontakt) if you want to register/reserve a Product ID (range).
*/
71,6 → 74,9
0.2 : Flash memory support, see ztex-flash1.h
0.3 : Debug helper, see ztex-debug.h
0.4 : AVR XMEGA support, see ztex-xmega.h
0.5 : High speed FPGA configuration support
0.6 : MAC EEPROM support
0.7 : Multi-FPGA support
*/
__xdata __at ZTEX_DESCRIPTOR_OFFS+12 BYTE INTERFACE_CAPABILITIES[6];
 
172,6 → 178,10
#nolf
+ 64
#endif
#ifdef[@CAPABILITY_MULTI_FPGA;]
#nolf
+ 128
#endif
.db 0
.db 0
.db 0
/ztex-fpga4.h
17,7 → 17,7
!*/
 
/*
FPGA support for ZTEX USB FPGA Modules 1.15
FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)
*/
 
#ifndef[ZTEX_FPGA_H]
86,8 → 86,8
***** finish_fpga_configuration *************************************
********************************************************************* */
static void finish_fpga_configuration () {
WORD w;
fpga_init_b += IOC2 ? 20 : 10;
BYTE w;
fpga_init_b += IOC2 ? 22 : 11;
 
for ( w=0; w<64; w++ ) {
IOA4 = 1; IOA4 = 0;
100,7 → 100,6
 
OEA = 0;
OEC &= ~bmBIT3;
fpga_init_b += IOC2 ? 2 : 1;
if ( IOA1 ) {
IOA1 = 1;
post_fpga_config();
207,7 → 206,129
EP0BCL = 2;
,,));;
 
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
/* *********************************************************************
***** interrupt routine for EPn *************************************
********************************************************************* */
xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
static void fpga_hs_send_isr () __interrupt {
BYTE oOEB;
oOEB = OEB;
 
EUSB = 0; // block all USB interrupts
 
fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) | EPHS_FPGA_CONF_EPBCL;
 
OEB = 255;
__asm
mov dptr,#_EPHS_FPGA_CONF_EPBCL
movx a,@dptr
mov r2,a
anl a,#7
mov r3,a
mov dptr,#_EPHS_FPGA_CONF_EPBCH
movx a,@dptr
addc a,#0
rrc a
mov r1,a
mov a,r2
rrc a
mov r2,a
 
mov a,r1
rrc a
mov r1,a
mov a,r2
rrc a
mov r2,a
 
mov a,r1
rrc a
mov r1,a
mov a,r2
rrc a
mov r2,a
mov _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)
mov _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)
mov _AUTOPTRSETUP,#0x07
mov dptr,#_XAUTODAT1
 
mov a,r3
jz 010011$
010012$:
movx a,@dptr // 2, 1
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
djnz r3, 010012$ // 4
 
mov a,r2
jz 010010$
010011$:
movx a,@dptr // 2, 1
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 2
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 3
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 4
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 5
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 6
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 7
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
movx a,@dptr // 2, 8
mov _IOB,a // 2
setb _IOA4 // 2
clr _IOA4 // 2
 
djnz r2, 010011$ // 4
010010$:
__endasm;
OEB = oOEB;
 
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
// EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
SYNCDELAY;
 
EXIF &= ~bmBIT4;
EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
 
EUSB = 1;
}
#endif
 
/* *********************************************************************
***** EP0 vendor command 0x34 ***************************************
********************************************************************* */
// FIFO write wave form
215,7 → 336,7
{
/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04
/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
};
 
223,19 → 344,12
{
/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04
/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
};
 
 
 
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
init_fpga_configuration();
 
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
 
GPIFABORT = 0xFF; // abort pendig
void init_cpld_fpga_configuration() {
IFCONFIG = bmBIT7 | bmBIT6 | bmBIT5 | 2; // Internal source, 48MHz, GPIF
 
GPIFREADYCFG = 0; //bmBIT7 | bmBIT6 | bmBIT5;
245,7 → 359,7
GPIFWFSELECT = 0x4E;
GPIFREADYSTAT = 0;
 
MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_12MHZ,GPIF_WAVE3_DATA,32);
MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
 
FLOWSTATE = 0;
FLOWLOGIC = 0x10;
287,9 → 401,69
OEA &= ~bmBIT4; // disable CCLK output
OEA |= bmBIT0; // enable GPIF mode of CPLD
IOA0 = 0;
}
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
 
void init_epn_fpga_configuration() {
 
IFCONFIG = bmBIT7;
 
REVCTL = 0x03; // reset fifo
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = HS_FPGA_CONF_EP;
SYNCDELAY;
FIFORESET = 0x0;
SYNCDELAY;
 
EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
SYNCDELAY;
// OEA |= bmBIT7;
// IOA7 = 0;
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
SYNCDELAY;
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
SYNCDELAY;
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
SYNCDELAY;
OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP
SYNCDELAY;
 
/* EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
SYNCDELAY;
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
SYNCDELAY;
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
SYNCDELAY;
EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP
SYNCDELAY; */
 
old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;
old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;
INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;
INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);
 
EXIF &= ~bmBIT4;
EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
}
#endif
 
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
init_fpga_configuration();
 
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
 
GPIFABORT = 0xFF; // abort pendig
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
if ( is_ufm_1_15x )
init_epn_fpga_configuration();
else
#endif
init_cpld_fpga_configuration();
,,));;
 
 
297,14 → 471,24
***** EP0 vendor command 0x35 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
IOA0 = 1; // disable GPIF mode of CPLD
IOA4 = 1; // enable CCLK output
OEA |= bmBIT4;
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
if ( is_ufm_1_15x ) {
INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;
INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;
}
else
#endif
{
IOA0 = 1; // disable GPIF mode of CPLD
IOA4 = 1; // enable CCLK output
OEA |= bmBIT4;
 
GPIFABORT = 0xFF;
SYNCDELAY;
IFCONFIG &= 0xf0;
SYNCDELAY;
GPIFABORT = 0xFF;
SYNCDELAY;
IFCONFIG &= 0xf0;
SYNCDELAY;
 
}
finish_fpga_configuration();
,,));;
 
/ztex-fpga5.h
0,0 → 1,386
/*!
ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
Copyright (C) 2009-2011 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
 
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
/*
FPGA support for ZTEX USB FPGA Modules 1.15y
*/
 
#ifndef[ZTEX_FPGA_H]
#define[ZTEX_FPGA_H]
 
#define[@CAPABILITY_FPGA;]
#define[@CAPABILITY_MULTI_FPGA;]
__xdata BYTE fpga_checksum; // checksum
__xdata DWORD fpga_bytes; // transferred bytes
__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
 
__xdata BYTE select_num;
__xdata BYTE prev_select_num;
__xdata BYTE select_mask;
__xdata BYTE config_mask_h;
__xdata BYTE config_mask_l;
 
 
/* *********************************************************************
***** init_fpga *****************************************************
********************************************************************* */
void init_fpga () {
IOE = 0x1f;
OEE = 0xff;
 
prev_select_num = 0;
select_num = 0;
select_mask = 0x10;
config_mask_h = 0x10;
config_mask_l = 0x01;
}
 
 
/* *********************************************************************
***** reset_fpga ****************************************************
********************************************************************* */
static void reset_fpga () { // reset FPGA
WORD k;
IFCONFIG = bmBIT7;
SYNCDELAY;
PORTACFG = 0;
PORTCCFG = 0;
 
IOC2 = 1; // out: INIT_B
OEC |= bmBIT2;
OEA &= ~bmBIT6; // in: CSO
OEC &= ~bmBIT1; // in: DOUT
 
IOC3 = 0;
OEC |= bmBIT3; // out: RDWR_B
 
// out: CCLK, M1, GPIF, M0, CSI
OEA |= bmBIT1 | bmBIT2 | bmBIT3 | bmBIT5 | bmBIT7;
IOA5 = 0;
IOA |= bmBIT1 | bmBIT2 | bmBIT3 | bmBIT7;
IOE = config_mask_h | ((~config_mask_l) & 0x0f);
OEE = 0xff;
wait(1);
 
IOA7 = 0;
IOA1 = 0;
IOE = config_mask_h | 0x0f;
k=0;
OEC &= ~bmBIT2; // in: INIT_B
while ( (!IOC2) && (k<65535) ) {
k++;
}
 
fpga_init_b = IOC2 ? 200 : 100;
fpga_bytes = 0;
fpga_checksum = 0;
}
 
/* *********************************************************************
***** init_fpga_configuration ***************************************
********************************************************************* */
static void init_fpga_configuration () {
{
PRE_FPGA_RESET
}
reset_fpga(); // reset FPGA
}
 
/* *********************************************************************
***** post_fpga_confog **********************************************
********************************************************************* */
static void post_fpga_config () {
POST_FPGA_CONFIG
}
 
/* *********************************************************************
***** finish_fpga_configuration *************************************
********************************************************************* */
static void finish_fpga_configuration () {
BYTE b;
fpga_init_b += 22;
 
for ( b=0; b<255; b++ ) {
IOA1 = 1; IOA1 = 0;
}
IOA7 = 1;
IOA4 = 1; IOA4 = 0;
IOA4 = 1; IOA4 = 0;
IOA4 = 1; IOA4 = 0;
IOA4 = 1; IOA4 = 0;
 
OEA &= ~(bmBIT1 | bmBIT2 | bmBIT3 | bmBIT7);
OEC &= ~bmBIT3;
OEE = 0xf0;
if ( (IOE & config_mask_l) == config_mask_l ) {
post_fpga_config();
}
 
IOE = select_mask | 0x0f;
OEE = 0xff;
}
 
 
/* *********************************************************************
***** EP0 vendor request 0x30 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
MEM_COPY1(fpga_checksum,EP0BUF+1,6);
OEE = 0xf0;
if ( (IOE & config_mask_l) == config_mask_l ) {
EP0BUF[0] = 0; // FPGA configured
IOE = select_mask | 0x0f;
OEE = 0xff;
}
else {
EP0BUF[0] = 1; // FPGA unconfigured
reset_fpga(); // prepare FPGA for configuration
}
 
EP0BUF[7] = 0; // not used
EP0BUF[8] = 0; // not used
 
EP0BCH = 0;
EP0BCL = 9;
,,));;
 
 
/* *********************************************************************
***** EP0 vendor command 0x31 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA
 
 
/* *********************************************************************
***** EP0 vendor command 0x32 ***************************************
********************************************************************* */
void fpga_send_ep0() { // send FPGA configuration data
BYTE oOEB;
oOEB = OEB;
OEB = 255;
fpga_bytes += ep0_payload_transfer;
__asm
mov dptr,#_EP0BCL
movx a,@dptr
jz 010000$
mov r2,a
mov _AUTOPTRL1,#(_EP0BUF)
mov _AUTOPTRH1,#(_EP0BUF >> 8)
mov _AUTOPTRSETUP,#0x07
mov dptr,#_fpga_checksum
movx a,@dptr
mov r1,a
mov dptr,#_XAUTODAT1
010001$:
movx a,@dptr // 2
mov _IOB,a // 2
setb _IOA1 // 2
add a,r1 // 1
mov r1,a // 1
clr _IOA1 // 2
djnz r2, 010001$ // 4
 
mov dptr,#_fpga_checksum
mov a,r1
movx @dptr,a
010000$:
__endasm;
OEB = oOEB;
if ( EP0BCL<64 ) {
finish_fpga_configuration();
}
}
 
ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
,,
fpga_send_ep0();
));;
 
 
#ifdef[HS_FPGA_CONF_EP]
 
#ifeq[HS_FPGA_CONF_EP][2]
#elifeq[HS_FPGA_CONF_EP][4]
#elifeq[HS_FPGA_CONF_EP][6]
#elifneq[HS_FPGA_CONF_EP][8]
#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
#endif
 
#define[@CAPABILITY_HS_FPGA;]
 
/* *********************************************************************
***** EP0 vendor request 0x33 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
EP0BCH = 0;
EP0BCL = 2;
,,));;
 
 
/* *********************************************************************
***** EP0 vendor command 0x34 ***************************************
********************************************************************* */
// FIFO write wave form
const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
{
/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
};
 
const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
{
/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
};
 
 
void init_cpld_fpga_configuration() {
IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
// IFCONFIG = bmBIT7 | 2; // Internal source, 30MHz, GPIF
 
GPIFREADYCFG = 0x0;
GPIFCTLCFG = 0;
GPIFIDLECS = 0;
GPIFIDLECTL = 0x20;
GPIFWFSELECT = 0x4E;
GPIFREADYSTAT = 0;
 
MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
 
FLOWSTATE = 0;
FLOWLOGIC = 0x10;
FLOWEQ0CTL = 0;
FLOWEQ1CTL = 0;
FLOWHOLDOFF = 0;
FLOWSTB = 0;
FLOWSTBEDGE = 0;
FLOWSTBHPERIOD = 0;
 
REVCTL = 0x1; // reset fifo
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = HS_FPGA_CONF_EP;
SYNCDELAY;
FIFORESET = 0x0;
SYNCDELAY;
 
EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
SYNCDELAY;
EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4;
SYNCDELAY;
EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
SYNCDELAY;
 
GPIFTCB3 = 1; // abort after at least 14*65536 transactions
SYNCDELAY;
GPIFTCB2 = 0;
SYNCDELAY;
GPIFTCB1 = 0;
SYNCDELAY;
GPIFTCB0 = 0;
SYNCDELAY;
EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
SYNCDELAY;
IOA3 = 0;
}
 
 
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
init_fpga_configuration();
 
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
 
GPIFABORT = 0xFF; // abort pendig
init_cpld_fpga_configuration();
,,));;
 
/* *********************************************************************
***** select_fpga ***************************************************
********************************************************************* */
void select_fpga ( BYTE fn )
{
prev_select_num = select_num;
select_num = fn & 3;
select_mask = 0x10 << fn;
config_mask_h = select_mask;
 
IOE = 0x0f;
{
PRE_FPGA_SELECT
}
IOE = select_mask | 0x0f;
}
 
 
/* *********************************************************************
***** EP0 vendor command 0x35 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
IOA3 = 1; // disable GPIF mode of CPLD
 
GPIFABORT = 0xFF;
SYNCDELAY;
IFCONFIG &= 0xf0;
SYNCDELAY;
 
finish_fpga_configuration();
,,));;
 
#endif // HS_FPGA_CONF_EP
 
 
/* *********************************************************************
***** EP0 vendor request 0x50 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x50,, // Return multi-FPGA information
EP0BUF[0] = 3; // 1 FPGA's
EP0BUF[1] = select_num; // select methods: any combination
EP0BUF[2] = 0; // no parallel configuration support
EP0BCH = 0;
EP0BCL = 3;
,,));;
 
/* *********************************************************************
***** EP0 vendor command 0x51 ***************************************
********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x51,, // select command
if ( SETUPDAT[4] == 1 ) {
config_mask_h = 0xf0;
}
else {
select_fpga( SETUPDAT[2] );
}
config_mask_l = config_mask_h >> 4;
,,
NOP;
));;
 
#endif /*ZTEX_FPGA_H*/
/ztex.h
25,6 → 25,14
 
#define[INIT_CMDS;][]
 
#ifneq[PRODUCT_IS][UFM-1_15]
#define[UFM_1_15X_DETECTION_ENABLED][0]
#endif
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
__xdata BYTE is_ufm_1_15x;
#endif
 
/* *********************************************************************
***** include the basic functions ***********************************
********************************************************************* */
39,6 → 47,9
#ifeq[PRODUCT_IS][UFM-1_15]
#define[MAC_EEPROM_ENABLED]
#endif // PRODUCT_IS=UFM-1_15
#ifeq[PRODUCT_IS][UFM-1_15Y]
#define[MAC_EEPROM_ENABLED]
#endif // PRODUCT_IS=UFM-1_15Y
#endif // EEPROM_MAC_DISABLED
 
#include[ztex-eeprom.h]
138,6 → 149,8
#include[ztex-fpga3.h]
#elifeq[PRODUCT_IS][UFM-1_15]
#include[ztex-fpga4.h]
#elifeq[PRODUCT_IS][UFM-1_15Y]
#include[ztex-fpga5.h]
#endif
 
 
191,11 → 204,11
********************************************************************* */
void mac_eeprom_init ( ) {
BYTE b,c,d;
xdata BYTE buf[5];
__xdata BYTE buf[5];
__code char hexdigits[] = "0123456789ABCDEF";
for (b=0; b<10; b++) { // abort if SN != "0000000000"
if ( SN_STRING[b] != '0' )
if ( SN_STRING[b] != 48 )
return;
}
 
255,9 → 268,10
SYNCDELAY;
]
 
 
void init_USB ()
{
USBCS |= 0x08;
USBCS |= bmBIT3;
CPUCS = bmBIT4 | bmBIT1;
wait(2);
281,6 → 295,8
#elifeq[PRODUCT_IS][UFM-1_15]
IOA1 = 1;
OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_15Y]
init_fpga();
#endif
 
INIT_CMDS;
322,6 → 338,16
EPXCFG(4);
EPXCFG(6);
EPXCFG(8);
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
OEA &= ~bmBIT3;
if ( IOA3 ) {
is_ufm_1_15x = 0;
} else {
is_ufm_1_15x = 1;
// INTERFACE_CAPABILITIES[0] &= ~32;
}
#endif
#ifeq[FLASH_ENABLED][1]
flash_init();
339,11 → 365,10
mac_eeprom_init();
#endif
 
 
USBCS |= bmBIT7 | bmBIT1;
wait(10);
// wait(250);
USBCS &= ~0x08;
USBCS &= ~bmBIT3;
}
 
 
/ztex-fpga-flash.h
75,7 → 75,7
return 3;
 
// read the bitstream
if ( flash_read_init( 1 ) ) // prepare reading sector k
if ( flash_read_init( 1 ) ) // prepare reading sector 1
return 2;
for ( k=1; k<i; k++ ) {
fpga_send_bitstream_from_flash( flash_sector_size );
126,6 → 126,11
********************************************************************* */
// this function is colled by init_USB;
void fpga_configure_from_flash_init() {
if ( ! flash_enabled ) {
fpga_flash_result = 2;
return;
}
 
fpga_flash_result = fpga_configure_from_flash(0);
if ( fpga_flash_result == 1 ) {
post_fpga_config();
/ztex-flash1.h
825,7 → 825,7
mmc_clocks(0); // 256 clocks = 32 dummy bytes
n-=32;
}
mmc_clocks(n << 3);
if ( n>0) mmc_clocks(n << 3);
mmc_clocks(16); // 16 CRC clocks
mmc_send_cmd(12, 0.0.0.0, 0); // stop transmission command, errors are ignored
// mmc_wait_busy(); // not required here
890,7 → 890,7
Between flash_write_finish / flash_write_next and flash_write_finish_sector some code
may be executed because flash_write_finish / flash_write_next start with
mmc_wauit_busy().
mmc_wait_busy().
 
Returns an error code (FLASH_EC_*). 0 means no error.
*/
900,7 → 900,7
mmc_clocks(0); // 256 clocks = 32 dummy bytes
n-=32;
}
mmc_clocks(n << 3);
if ( n>0) mmc_clocks(n << 3);
 
MMC_IO |= MMC_bmDI;
mmc_clocks(16); // 16 CRC clocks
946,6 → 946,14
void flash_init() {
BYTE i, j, k;
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
if ( is_ufm_1_15x ) {
flash_enabled = 0;
flash_ec = FLASH_EC_NOTSUPPORTED;
return;
}
#endif
 
flash_enabled = 1;
flash_sector_size = 512;
mmc_version = 0;
/ztex-conf.h
75,6 → 75,14
*/
#define[POST_FPGA_CONFIG][]
 
/*
On multi FPGA boards this macro is called betwen deselection and
selection of a FPGA. This can be used to store / resore I/O contents.
To append something to this macro use the following definition:
#define[PRE_FPGA_SELECT][PRE_FPGA_SELECT
...]
*/
#define[PRE_FPGA_SELECT][]
 
 
/*
387,9 → 395,23
#define[PRODUCT_ID_3][$3]
#define[FWVER][$4]
#define[PRODUCT_IS][UFM-1_15]
#define[PRODUCT_STRING]["USB-FPGA Module 1.15"]]
#define[PRODUCT_STRING]["USB-FPGA Module 1.15"]
#define[NUMBER_OF_FPGAS][1]]
 
/*
Identify as ZTEX USB FPGA Module 1.15y
Usage: IDENTITY_UFM_1_10(<PRODUCT_ID_0>.<PRODUCT_ID_1><PRODUCT_ID_2>.<PRODUCT_ID_3>,<FW_VERSION>);
*/
#define[IDENTITY_UFM_1_15Y(][.$1.$2.$3,$4);][#define[PRODUCT_ID_0][$0]
#define[PRODUCT_ID_1][$1]
#define[PRODUCT_ID_2][$2]
#define[PRODUCT_ID_3][$3]
#define[FWVER][$4]
#define[PRODUCT_IS][UFM-1_15Y]
#define[PRODUCT_STRING]["USB-FPGA Module 1.15y"]
#define[NUMBER_OF_FPGAS][4]]
 
 
/*
Identify as ZTEX USB Module 1.0
Usage: IDENTITY_UM_1_0(<PRODUCT_ID_0>.<PRODUCT_ID_1><PRODUCT_ID_2>.<PRODUCT_ID_3>,<FW_VERSION>);
427,17 → 449,10
*/
#define[PRODUCT_STRING]["USB-FPGA Module"]
 
 
/*
This macro defines the Configuration string. Limited to 31 characters.
*/
#define[CONFIGURATION_STRING]["(unknown)"]
 
 
/*
This macro enables defines the Configuration string. Limited to 31 characters.
*/
#define[CONFIGURATION_STRING]["(unknown)"]
#define[CONFIGURATION_STRING]["default"]
 
 
/*
483,7 → 498,7
#define[EXTENSION_EXP_1_10;][#define[EXP_1_10_ENABLED][1]]
 
/*
Enables high speed FPGA configuration for ZTEX USB-FPGA Module 1.15 and 1GbE-USB-FPGA Module 1.20
Enables high speed FPGA configuration for ZTEX USB-FPGA Module 1.15 and 1.15y
Usage: ENABLE_HS_FPGA_CONF(<ENDPOINT>);
<endpoint> endpoint which shall be used (any bulk output can be used)
*/
502,4 → 517,10
*/
#define[DISABLE_MAC_EEPROM;][#define[EEPROM_MAC_DISABLED][1]]
 
/*
Enables detection of USB-FPGA Modules 1.15x. This avoids some warnings and makes the variable is_ufm_1_15x available.
Usage: ENABLE_UFM_1_15X_DETECTION;
*/
#define[ENABLE_UFM_1_15X_DETECTION;][#define[UFM_1_15X_DETECTION_ENABLED][1]]
 
#endif
/ztex-isr.h
361,7 → 361,8
void HSGRANT_ISR() __interrupt
{
EXIF &= ~bmBIT4;
USBIRQ = bmBIT5;
// while ( USBIRQ & bmBIT5 )
USBIRQ = bmBIT5;
}
 
/* *********************************************************************
/ztex-fpga3.h
85,7 → 85,7
***** finish_fpga_configuration *************************************
********************************************************************* */
static void finish_fpga_configuration () {
WORD w;
BYTE w;
fpga_init_b += IOA0 ? 20 : 10;
 
for ( w=0; w<64; w++ ) {

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