URL
https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk
Subversion Repositories usb_fpga_1_2
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb_fpga_1_2/trunk/examples/usb-fpga-1.15
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/nvmtest/Makefile
7,11 → 7,11
JARTARGET=NVMTest.jar |
CLASSTARGETS=NVMTest.class |
CLASSEXTRADEPS= |
CLASSEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/java/ztex/*.java) |
CLASSEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/java/ztex/*.java) |
|
IHXTARGETS=nvmtest.ihx |
IHXEXTRADEPS= |
IHXEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/include/*.h) |
IHXEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/include/*.h) |
EXTRAJARFILES=nvmtest.ihx |
|
################################ |
/1.15a/mmio/ucecho.sh
0,0 → 1,4
#make -C ../../../java distclean all || exit |
#make distclean all || exit |
#make || exit |
java -cp UCEcho.jar UCEcho $@ |
1.15a/mmio/ucecho.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/mmio/UCEcho.java
===================================================================
--- 1.15a/mmio/UCEcho.java (nonexistent)
+++ 1.15a/mmio/UCEcho.java (revision 9)
@@ -0,0 +1,169 @@
+/*!
+ mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+import java.io.*;
+import java.util.*;
+
+import ch.ntb.usb.*;
+
+import ztex.*;
+
+// *****************************************************************************
+// ******* ParameterException **************************************************
+// *****************************************************************************
+// Exception the prints a help message
+class ParameterException extends Exception {
+ public final static String helpMsg = new String (
+ "Parameters:\n"+
+ " -d Device Number (default: 0)\n" +
+ " -f Force uploads\n" +
+ " -p Print bus info\n" +
+ " -w Enable certain workarounds\n"+
+ " -h This help" );
+
+ public ParameterException (String msg) {
+ super( msg + "\n" + helpMsg );
+ }
+}
+
+// *****************************************************************************
+// ******* Test0 ***************************************************************
+// *****************************************************************************
+class UCEcho extends Ztex1v1 {
+
+// ******* UCEcho **************************************************************
+// constructor
+ public UCEcho ( ZtexDevice1 pDev ) throws UsbException {
+ super ( pDev );
+ }
+
+// ******* echo ****************************************************************
+// writes a string to Endpoint 4, reads it back from Endpoint 2 and writes the output to System.out
+ public void echo ( String input ) throws UsbException {
+ byte buf[] = input.getBytes();
+ int i = LibusbJava.usb_bulk_write(handle(), 0x04, buf, buf.length, 1000);
+ if ( i<0 )
+ throw new UsbException("Error sending data: " + LibusbJava.usb_strerror());
+ System.out.println("Send "+i+" bytes: `"+input+"'" );
+
+ try {
+ Thread.sleep( 10 );
+ }
+ catch ( InterruptedException e ) {
+ }
+
+ buf = new byte[1024];
+ i = LibusbJava.usb_bulk_read(handle(), 0x82, buf, 1024, 1000);
+ if ( i<0 )
+ throw new UsbException("Error receiving data: " + LibusbJava.usb_strerror());
+ System.out.println("Read "+i+" bytes: `"+new String(buf,0,i)+"'" );
+ }
+
+// ******* main ****************************************************************
+ public static void main (String args[]) {
+
+ int devNum = 0;
+ boolean force = false;
+ boolean workarounds = false;
+
+ try {
+// init USB stuff
+ LibusbJava.usb_init();
+
+// scan the USB bus
+ ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1);
+ if ( bus.numberOfDevices() <= 0) {
+ System.err.println("No devices found");
+ System.exit(0);
+ }
+
+// scan the command line arguments
+ for (int i=0; i=args.length) throw new Exception();
+ devNum = Integer.parseInt( args[i] );
+ }
+ catch (Exception e) {
+ throw new ParameterException("Device number expected after -d");
+ }
+ }
+ else if ( args[i].equals("-f") ) {
+ force = true;
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-w") ) {
+ workarounds = true;
+ }
+ else if ( args[i].equals("-h") ) {
+ System.err.println(ParameterException.helpMsg);
+ System.exit(0);
+ }
+ else throw new ParameterException("Invalid Parameter: "+args[i]);
+ }
+
+
+// create the main class
+ UCEcho ztex = new UCEcho ( bus.device(devNum) );
+ ztex.certainWorkarounds = workarounds;
+
+// upload the firmware if necessary
+ if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 1.15") ) {
+ System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms");
+ force = true;
+ }
+
+// upload the bitstream if necessary
+ if ( force || ! ztex.getFpgaConfiguration() ) {
+ System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/ucecho.bit" , force ) + " ms");
+ }
+
+
+// claim interface 0
+ ztex.trySetConfiguration ( 1 );
+ ztex.claimInterface ( 0 );
+
+// read string from stdin and write it to USB device
+ String str = "";
+ BufferedReader reader = new BufferedReader( new InputStreamReader( System.in ) );
+ while ( ! str.equals("quit") ) {
+ System.out.print("Enter a string or `quit' to exit the program: ");
+ str = reader.readLine();
+ if ( ! str.equals("") )
+ ztex.echo(str);
+ System.out.println("");
+ }
+
+// release interface 0
+ ztex.releaseInterface( 0 );
+
+ }
+ catch (Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ }
+ }
+
+}
Index: 1.15a/mmio/ucecho.c
===================================================================
--- 1.15a/mmio/ucecho.c (nonexistent)
+++ 1.15a/mmio/ucecho.c (revision 9)
@@ -0,0 +1,103 @@
+/*!
+ mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
+#include[ztex-utils.h] // include basic functions
+
+// configure endpoints 2 and 4, both belong to interface 0 (in/out are from the point of view of the host)
+EP_CONFIG(2,0,BULK,IN,512,2);
+EP_CONFIG(4,0,BULK,OUT,512,2);
+
+// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
+IDENTITY_UFM_1_15(10.13.0.0,0);
+
+// enables high speed FPGA configuration, (re)use EP 4
+ENABLE_HS_FPGA_CONF(4);
+
+// this product string is also used for identification by the host software
+#define[PRODUCT_STRING]["memeory mapping example for UFM 1.15"]
+
+__xdata BYTE run;
+
+#define[PRE_FPGA_RESET][PRE_FPGA_RESET
+ run = 0;
+]
+
+#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
+ IFCONFIG = bmBIT7; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
+ SYNCDELAY;
+ EP2FIFOCFG = 0;
+ SYNCDELAY;
+ EP4FIFOCFG = 0;
+ SYNCDELAY;
+
+ REVCTL = 0x0; // reset
+ SYNCDELAY;
+ EP2CS &= ~bmBIT0; // stall = 0
+ SYNCDELAY;
+ EP4CS &= ~bmBIT0; // stall = 0
+
+ SYNCDELAY; // first two packages are waste
+ EP4BCL = 0x80; // skip package, (re)arm EP4
+ SYNCDELAY;
+ EP4BCL = 0x80; // skip package, (re)arm EP4
+
+ FIFORESET = 0x80; // reset FIFO
+ SYNCDELAY;
+ FIFORESET = 0x82;
+ SYNCDELAY;
+ FIFORESET = 0x00;
+ SYNCDELAY;
+
+ run = 1;
+]
+
+// include the main part of the firmware kit, define the descriptors, ...
+#include[ztex.h]
+
+
+__xdata __at 0x5001 volatile BYTE OUT_REG; // FPGA register where the data is written to
+__xdata __at 0x5002 volatile BYTE IN_REG; // FPGA register where the result is read from
+
+
+void main(void)
+{
+ WORD i,size;
+
+// init everything
+ init_USB();
+
+ while (1) {
+ if ( run & !(EP4CS & bmBIT2) ) { // EP4 is not empty
+ size = (EP4BCH << 8) | EP4BCL;
+ if ( size>0 && size<=512 && !(EP2CS & bmBIT3)) { // EP2 is not full
+ for ( i=0; i> 8;
+ SYNCDELAY;
+ EP2BCL = size & 255; // arm EP2
+ SYNCDELAY;
+ INPKTEND = 0x2;
+ }
+ SYNCDELAY;
+ EP4BCL = 0x80; // (re)arm EP4
+ }
+ }
+}
Index: 1.15a/mmio/ucecho.bat
===================================================================
--- 1.15a/mmio/ucecho.bat (nonexistent)
+++ 1.15a/mmio/ucecho.bat (revision 9)
@@ -0,0 +1,2 @@
+java -cp UCEcho.jar UCEcho
+pause
Index: 1.15a/mmio/fpga/ucecho.ucf
===================================================================
--- 1.15a/mmio/fpga/ucecho.ucf (nonexistent)
+++ 1.15a/mmio/fpga/ucecho.ucf (revision 9)
@@ -0,0 +1,33 @@
+NET "FXCLK" TNM_NET = "FXCLK";
+TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 48 MHz HIGH 50 %;
+NET "FXCLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ;
+
+NET "MM_A<0>" LOC = "M20" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<1>" LOC = "M19" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<2>" LOC = "M18" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<3>" LOC = "N19" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<4>" LOC = "T19" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<5>" LOC = "T21" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<6>" LOC = "T22" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<7>" LOC = "R19" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<8>" LOC = "P20" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<9>" LOC = "P21" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<10>" LOC = "P22" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<11>" LOC = "J22" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<12>" LOC = "H21" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<13>" LOC = "H22" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<14>" LOC = "G22" | IOSTANDARD = LVCMOS33 ;
+NET "MM_A<15>" LOC = "F21" | IOSTANDARD = LVCMOS33 ;
+
+NET "MM_D<0>" LOC = "D20" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<1>" LOC = "C20" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<2>" LOC = "C19" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<3>" LOC = "B21" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<4>" LOC = "B20" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<5>" LOC = "J19" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<6>" LOC = "K19" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+NET "MM_D<7>" LOC = "L19" | IOSTANDARD = LVCMOS33 | DRIVE = 2;
+
+NET "MM_WRN" LOC = "C22" | IOSTANDARD = LVCMOS33 ;
+NET "MM_RDN" LOC = "D21" | IOSTANDARD = LVCMOS33 ;
+NET "MM_PSENN" LOC = "D22" | IOSTANDARD = LVCMOS33 ;
Index: 1.15a/mmio/fpga/ucecho.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: 1.15a/mmio/fpga/ucecho.ise
===================================================================
--- 1.15a/mmio/fpga/ucecho.ise (nonexistent)
+++ 1.15a/mmio/fpga/ucecho.ise (revision 9)
1.15a/mmio/fpga/ucecho.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: 1.15a/mmio/fpga/ucecho.vhd
===================================================================
--- 1.15a/mmio/fpga/ucecho.vhd (nonexistent)
+++ 1.15a/mmio/fpga/ucecho.vhd (revision 9)
@@ -0,0 +1,63 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+--#use IEEE.numeric_std.all;
+
+
+entity ucecho is
+ port(
+ FXCLK : in std_logic;
+ MM_A : in std_logic_vector(15 downto 0);
+ MM_D : inout std_logic_vector(7 downto 0);
+ MM_WRN : in std_logic;
+ MM_RDN : in std_logic;
+ MM_PSENN : in std_logic
+ );
+end ucecho;
+
+architecture RTL of ucecho is
+
+--signal declaration
+signal rd : std_logic := '1';
+signal rd_prev : std_logic := '1';
+signal wr : std_logic := '1';
+signal wr_prev : std_logic := '1';
+
+signal datain : std_logic_vector(7 downto 0);
+signal dataout : std_logic_vector(7 downto 0);
+
+begin
+ rd <= MM_RDN and MM_PSENN;
+ wr <= MM_WRN;
+
+ MM_D <= dataout when ((rd_prev or rd) = '0') else ( others => 'Z' ); -- enable output
+
+ dpUCECHO: process(FXCLK)
+ begin
+ if FXCLK' event and FXCLK = '1' then
+ if (wr_prev = '1') and (wr = '0') -- EZ-USB write strobe
+ then
+ if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
+ then
+ datain <= MM_D;
+ end if;
+ elsif (rd_prev = '1') and (rd = '0') -- EZ-USB read strobe
+ then
+ if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
+ then
+ if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
+ then
+ dataout <= datain - conv_std_logic_vector(32,8);
+ else
+ dataout <= datain ;
+ end if;
+ end if;
+ end if;
+
+ rd_prev <= rd;
+ wr_prev <= wr;
+ end if;
+ end process dpUCECHO;
+
+end RTL;
Index: 1.15a/mmio/fpga/clean.sh
===================================================================
--- 1.15a/mmio/fpga/clean.sh (nonexistent)
+++ 1.15a/mmio/fpga/clean.sh (revision 9)
@@ -0,0 +1,80 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.vhd *.ucf *.sh *.ise *.bit *.bin *.xise"
+subdirs="ipcore_dir"
+
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/mmio/fpga/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/mmio/fpga/ucecho.xise
===================================================================
--- 1.15a/mmio/fpga/ucecho.xise (nonexistent)
+++ 1.15a/mmio/fpga/ucecho.xise (revision 9)
@@ -0,0 +1,56 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: 1.15a/mmio/Readme
===================================================================
--- 1.15a/mmio/Readme (nonexistent)
+++ 1.15a/mmio/Readme (revision 9)
@@ -0,0 +1,24 @@
+mmio
+----
+
+This example is intended for ZTEX USB-FPGA Modules 1.15. It demonstrates
+memory mapped I/O between the EZ-USB FX2 and the FPGA.
+
+The firmware (defined in ucecho.c) declares Endpoint 2 and Endpoint 4
+(both 512 bytes, double buffered, bulk transfer, belong to interface 0).
+All data that is written to Endpoint 4 is converted to uppercase by
+the FPGA and can be read back from Endpoint 2.
+
+This example does the same as the example in directory ../../all/ucecho
+except that the uppercase - lowercase conversion is made by the FPGA
+through memory mapped I/O: The EZ-USB FX2 writes the data to address
+0x5001 and reads the converted data back from 0x5002.
+
+The driver (defined in UCEcho.java) uploads the the Firmware (ucecho.ihx)
+to the EZ-USB Microcontroller and the Bitstream (fpga/ucecho.bit) to the
+FPGA if necessary, sends user string to the device and reads them back.
+
+Uploading the Firmware to EEPROM is also supported by the firmware (e.g.
+using the FWLoader utility).
+
+This example may serve a good starting point for own projects.
Index: 1.15a/mmio/Makefile
===================================================================
--- 1.15a/mmio/Makefile (nonexistent)
+++ 1.15a/mmio/Makefile (revision 9)
@@ -0,0 +1,27 @@
+#########################
+# configuration section #
+#########################
+
+# Defines the location of the EZ-USB SDK
+ZTEXPREFIX=../../../..
+
+# The name of the jar archive
+JARTARGET=UCEcho.jar
+# Java Classes that have to be build
+CLASSTARGETS=UCEcho.class
+# Extra dependencies for Java Classes
+CLASSEXTRADEPS=
+
+# ihx files (firmware ROM files) that have to be build
+IHXTARGETS=ucecho.ihx
+# Extra Dependencies for ihx files
+IHXEXTRADEPS=
+
+# Extra files that should be included into th jar archive
+EXTRAJARFILES=ucecho.ihx fpga/ucecho.bit
+
+################################
+# DO NOT CHANAGE THE FOLLOWING #
+################################
+# includes the main Makefile
+include $(ZTEXPREFIX)/Makefile.mk
Index: 1.15a/intraffic/InTraffic.java
===================================================================
--- 1.15a/intraffic/InTraffic.java (nonexistent)
+++ 1.15a/intraffic/InTraffic.java (revision 9)
@@ -0,0 +1,317 @@
+/*!
+ intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+import java.io.*;
+import java.util.*;
+
+import ch.ntb.usb.*;
+
+import ztex.*;
+
+// *****************************************************************************
+// ******* ParameterException **************************************************
+// *****************************************************************************
+// Exception the prints a help message
+class ParameterException extends Exception {
+ public final static String helpMsg = new String (
+ "Parameters:\n"+
+ " -d Device Number (default: 0)\n" +
+ " -f Force uploads\n" +
+ " -p Print bus info\n" +
+ " -w Enable certain workarounds\n"+
+ " -h This help" );
+
+ public ParameterException (String msg) {
+ super( msg + "\n" + helpMsg );
+ }
+}
+
+// *****************************************************************************
+// ******* USBReader ***********************************************************
+// *****************************************************************************
+class UsbReader extends Thread {
+ private final int bufNum = 8;
+ public final int bufSize = 512*1024;
+ public byte[][] buf = new byte[bufNum][];
+ public int[] bufBytes = new int[bufNum];
+ private int readCount = -1;
+ private int getCount = -1;
+ public boolean terminate = false;
+ private Ztex1v1 ztex;
+
+ public UsbReader ( Ztex1v1 p_ztex ) {
+ super ();
+ ztex = p_ztex;
+ for (int i=0; i= readCount) {
+ try {
+ sleep(1);
+ }
+ catch ( InterruptedException e) {
+ }
+ }
+ return getCount % bufNum;
+ }
+
+ public void reset () {
+ getCount = readCount + 1;
+ }
+
+ public void run() {
+ setPriority(MAX_PRIORITY);
+
+// claim interface 0
+ try {
+ ztex.trySetConfiguration ( 1 );
+ ztex.claimInterface ( 0 );
+ }
+ catch ( Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ System.exit(2);
+ }
+
+
+// reader loop
+ while ( !terminate ) {
+ readCount += 1;
+
+ while ( readCount - bufNum >= getCount ) {
+ try {
+ sleep(1);
+ }
+ catch ( InterruptedException e) {
+ }
+ }
+
+ int i = readCount % bufNum;
+ bufBytes[i] = LibusbJava.usb_bulk_read(ztex.handle(), 0x82, buf[i], bufSize, 1000);
+// System.out.println("Buffer " + i +": read " + bufBytes[i] + " bytes");
+ }
+
+// release interface 0
+ ztex.releaseInterface( 0 );
+
+ }
+}
+
+
+// *****************************************************************************
+// ******* Test0 ***************************************************************
+// *****************************************************************************
+class InTraffic extends Ztex1v1 {
+
+// ******* InTraffic **************************************************************
+// constructor
+ public InTraffic ( ZtexDevice1 pDev ) throws UsbException {
+ super ( pDev );
+ }
+
+// ******* main ****************************************************************
+ public static void main (String args[]) {
+
+ int devNum = 0;
+ boolean force = false;
+ boolean workarounds = false;
+
+ try {
+// init USB stuff
+ LibusbJava.usb_init();
+
+// scan the USB bus
+ ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1);
+ if ( bus.numberOfDevices() <= 0) {
+ System.err.println("No devices found");
+ System.exit(0);
+ }
+
+// scan the command line arguments
+ for (int i=0; i=args.length) throw new Exception();
+ devNum = Integer.parseInt( args[i] );
+ }
+ catch (Exception e) {
+ throw new ParameterException("Device number expected after -d");
+ }
+ }
+ else if ( args[i].equals("-f") ) {
+ force = true;
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-w") ) {
+ workarounds = true;
+ }
+ else if ( args[i].equals("-h") ) {
+ System.err.println(ParameterException.helpMsg);
+ System.exit(0);
+ }
+ else throw new ParameterException("Invalid Parameter: "+args[i]);
+ }
+
+
+// create the main class
+ InTraffic ztex = new InTraffic ( bus.device(devNum) );
+ ztex.certainWorkarounds = workarounds;
+
+// upload the firmware if necessary
+ if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("intraffic example for UFM 1.15") ) {
+ System.out.println("Firmware upload time: " + ztex.uploadFirmware( "intraffic.ihx", force ) + " ms");
+ force = true;
+ }
+
+// upload the bitstream if necessary
+ if ( force || ! ztex.getFpgaConfiguration() ) {
+ System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/intraffic.bit" , force ) + " ms");
+ }
+
+// read the traffic
+ UsbReader reader = new UsbReader( ztex );
+ reader.start();
+
+// EZ-USB FIFO test (controlled mode)
+ ztex.vendorCommand (0x60, "Set test mode", 0, 0);
+ reader.reset();
+
+ int vcurrent = -1;
+ for (int i=0; i<1000; i++) {
+ int j = reader.getBuffer();
+ int bb = reader.bufBytes[j];
+ byte[] b = reader.buf[j];
+ int current = vcurrent+1;
+ int lastwi = -1;
+ int aerrors = 0;
+ int ferrors = 0;
+ int errors = 0;
+ int prevErrors = 0;
+
+ for (int k=1; k 0 ) System.out.println(" 0b" + Integer.toBinaryString(current) );
+ if ( prevErrors == 1 )
+ ferrors +=1;
+ prevErrors = 0;
+ }
+
+ lastwi = 1;
+// System.out.println(current);
+ }
+// System.out.println(b[k]+" " +b[k+1]);
+ }
+ System.out.print("Buffer " + i + ": " + (errors-ferrors) + " errors, " + ferrors + " FIFO errors, " + aerrors + " alignment errors \r");
+ }
+ System.out.println();
+
+// performance test (continous mode)
+ ztex.vendorCommand (0x60, "Set test mode", 1, 0);
+ reader.reset();
+
+ int words = 0;
+ int intSum = 0;
+ int intMax = 0;
+ int intAdj = 0;
+ int lastwi = -1;
+ for (int i=0; i<1000; i++) {
+ int j = reader.getBuffer();
+ int bb = reader.bufBytes[j];
+ byte[] b = reader.buf[j];
+ int current = vcurrent+1;
+
+ for (int k=1; k 0 && words > 0) {
+ intSum += it;
+ if ( it > intMax )
+ intMax = it;
+ }
+ words += 2;
+ vcurrent = current;
+ intAdj = 0;
+ }
+ lastwi = 1;
+// System.out.println(current);
+ }
+// System.out.println(b[k]+" " +b[k+1]);
+ }
+ System.out.print("Buffer " + i + ": " + Math.round(words*6000.0/(words+intSum))/100.0 + "MB/s, max. interrupt: " + Math.round(intMax/150.0)/100 + "ms \r");
+ }
+ System.out.println();
+
+
+ reader.terminate=true;
+
+ }
+ catch (Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ }
+ }
+
+}
Index: 1.15a/intraffic/intraffic.c
===================================================================
--- 1.15a/intraffic/intraffic.c (nonexistent)
+++ 1.15a/intraffic/intraffic.c (revision 9)
@@ -0,0 +1,99 @@
+/*!
+ intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
+#include[ztex-utils.h] // include basic functions
+
+// configure endpoint 2, in, quad buffered, 512 bytes, interface 0
+EP_CONFIG(2,0,BULK,IN,512,4);
+
+// configure endpoint 6, out, doublebuffered, 512 bytes, interface 0
+EP_CONFIG(6,0,BULK,OUT,512,2);
+
+// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
+IDENTITY_UFM_1_15(10.13.0.0,0);
+
+// this product string is also used for identification by the host software
+#define[PRODUCT_STRING]["intraffic example for UFM 1.15"]
+
+// enables high speed FPGA configuration via EP6
+ENABLE_HS_FPGA_CONF(6);
+
+// this is called automatically after FPGA configuration
+#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
+ IOA7 = 1; // reset on
+ OEA |= bmBIT7;
+ IOC0 = 0; // controlled mode
+ OEC = 1;
+
+ EP2CS &= ~bmBIT0; // clear stall bit
+
+ REVCTL = 0x3;
+ SYNCDELAY;
+
+ IFCONFIG = bmBIT7 | bmBIT5 | 3; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
+ SYNCDELAY;
+ EP2FIFOCFG = bmBIT3 | bmBIT0; // AOTUOIN, WORDWIDE
+ SYNCDELAY;
+
+#ifdef[fastmode]
+ EP2AUTOINLENH = 4; // 1024 bytes
+#else
+ EP2AUTOINLENH = 2; // 512 bytes
+#endif
+ SYNCDELAY;
+ EP2AUTOINLENL = 0;
+ SYNCDELAY;
+
+ FIFORESET = 0x80; // reset FIFO
+ SYNCDELAY;
+ FIFORESET = 2;
+ SYNCDELAY;
+ FIFORESET = 0x00;
+ SYNCDELAY;
+
+ FIFOPINPOLAR = 0;
+ SYNCDELAY;
+ PINFLAGSAB = 0;
+ SYNCDELAY;
+ PINFLAGSCD = 0;
+ SYNCDELAY;
+
+ IOA7 = 0; // reset off
+]
+
+// set mode
+ADD_EP0_VENDOR_COMMAND((0x60,,
+ IOA7 = 1; // reset on
+ IOC0 = SETUPDAT[2] ? 1 : 0;
+ IOA7 = 0; // reset off
+,,
+ NOP;
+));;
+
+// include the main part of the firmware kit, define the descriptors, ...
+#include[ztex.h]
+
+void main(void)
+{
+ init_USB();
+
+ while (1) {
+ }
+}
+
Index: 1.15a/intraffic/fpga/intraffic.ucf
===================================================================
--- 1.15a/intraffic/fpga/intraffic.ucf (nonexistent)
+++ 1.15a/intraffic/fpga/intraffic.ucf (revision 9)
@@ -0,0 +1,41 @@
+# NET "CLK" TNM_NET = "FXCLK";
+# TIMESPEC "TS_CLK" = PERIOD "FXCLK" 20.83333 ns HIGH 50 %;
+# NET "CLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ;
+
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
+NET "IFCLK" LOC = "K20" | IOSTANDARD = LVCMOS33 ;
+
+# TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
+# TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;
+
+NET "SLOE" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2
+NET "FIFOADR0" LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4
+NET "FIFOADR1" LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5
+NET "PKTEND" LOC = "AB5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6
+NET "RESET" LOC = "AB17" | IOSTANDARD = LVCMOS33 ; # PA7
+
+NET "CONT" LOC = "G20" | IOSTANDARD = LVCMOS33 ; # PA3
+
+NET "fd<0>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
+NET "fd<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
+NET "fd<2>" LOC = "W13" | IOSTANDARD = LVCMOS33 ;
+NET "fd<3>" LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
+NET "fd<4>" LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
+NET "fd<5>" LOC = "W6" | IOSTANDARD = LVCMOS33 ;
+NET "fd<6>" LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
+NET "fd<7>" LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
+NET "fd<8>" LOC = "V21" | IOSTANDARD = LVCMOS33 ;
+NET "fd<9>" LOC = "V22" | IOSTANDARD = LVCMOS33 ;
+NET "fd<10>" LOC = "U20" | IOSTANDARD = LVCMOS33 ;
+NET "fd<11>" LOC = "U22" | IOSTANDARD = LVCMOS33 ;
+NET "fd<12>" LOC = "R20" | IOSTANDARD = LVCMOS33 ;
+NET "fd<13>" LOC = "R22" | IOSTANDARD = LVCMOS33 ;
+NET "fd<14>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
+NET "fd<15>" LOC = "P19" | IOSTANDARD = LVCMOS33 ;
+
+NET "FLAGB" LOC = "F19" | IOSTANDARD = LVCMOS33 ;
+
+NET "SLRD" LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
+NET "SLWR" LOC = "M22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
+
Index: 1.15a/intraffic/fpga/intraffic.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: 1.15a/intraffic/fpga/intraffic.ise
===================================================================
--- 1.15a/intraffic/fpga/intraffic.ise (nonexistent)
+++ 1.15a/intraffic/fpga/intraffic.ise (revision 9)
1.15a/intraffic/fpga/intraffic.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: 1.15a/intraffic/fpga/intraffic.vhd
===================================================================
--- 1.15a/intraffic/fpga/intraffic.vhd (nonexistent)
+++ 1.15a/intraffic/fpga/intraffic.vhd (revision 9)
@@ -0,0 +1,91 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+
+entity intraffic is
+ port(
+ RESET : in std_logic;
+ CONT : in std_logic;
+ IFCLK : in std_logic;
+
+ FD : out std_logic_vector(15 downto 0);
+
+ SLOE : out std_logic;
+ SLRD : out std_logic;
+ SLWR : out std_logic;
+ FIFOADR0 : out std_logic;
+ FIFOADR1 : out std_logic;
+ PKTEND : out std_logic;
+
+ FLAGB : in std_logic
+ );
+end intraffic;
+
+architecture RTL of intraffic is
+
+----------------------------
+-- test pattern generator --
+----------------------------
+-- 30 bit counter
+signal GEN_CNT : std_logic_vector(29 downto 0);
+signal INT_CNT : std_logic_vector(6 downto 0);
+
+signal FIFO_WORD : std_logic;
+
+begin
+
+ SLOE <= '1';
+ SLRD <= '1';
+ FIFOADR0 <= '0';
+ FIFOADR1 <= '0';
+ PKTEND <= '1'; -- no data alignment
+
+ dpIFCLK: process (IFCLK, RESET)
+ begin
+-- reset
+ if RESET = '1'
+ then
+ GEN_CNT <= ( others => '0' );
+ INT_CNT <= ( others => '0' );
+ FIFO_WORD <= '0';
+ SLWR <= '1';
+-- IFCLK
+ elsif IFCLK'event and IFCLK = '1'
+ then
+
+ if CONT = '1' or FLAGB = '1'
+ then
+ if FIFO_WORD = '0'
+ then
+ FD(14 downto 0) <= GEN_CNT(14 downto 0);
+ else
+ FD(14 downto 0) <= GEN_CNT(29 downto 15);
+ end if;
+ FD(15) <= FIFO_WORD;
+
+ if FIFO_WORD = '1'
+ then
+ GEN_CNT <= GEN_CNT + '1';
+ if INT_CNT = conv_std_logic_vector(99,7)
+ then
+ INT_CNT <= ( others => '0' );
+ else
+ INT_CNT <= INT_CNT + '1';
+ end if;
+ end if;
+ FIFO_WORD <= not FIFO_WORD;
+ end if;
+
+ if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
+ then
+ SLWR <= '1';
+ else
+ SLWR <= '0';
+ end if;
+
+ end if;
+ end process dpIFCLK;
+
+end RTL;
Index: 1.15a/intraffic/fpga/clean.sh
===================================================================
--- 1.15a/intraffic/fpga/clean.sh (nonexistent)
+++ 1.15a/intraffic/fpga/clean.sh (revision 9)
@@ -0,0 +1,79 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.vhd *.ucf *.sh *.ise *.bit *.bin *.xise"
+subdirs="ipcore_dir"
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/intraffic/fpga/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/intraffic/fpga/intraffic.xise
===================================================================
--- 1.15a/intraffic/fpga/intraffic.xise (nonexistent)
+++ 1.15a/intraffic/fpga/intraffic.xise (revision 9)
@@ -0,0 +1,442 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: 1.15a/intraffic/Readme
===================================================================
--- 1.15a/intraffic/Readme (nonexistent)
+++ 1.15a/intraffic/Readme (revision 9)
@@ -0,0 +1,18 @@
+intraffic
+---------
+
+This example shows how the EZ-USB input FIFO interface is used.
+
+A traffic generator sends test data to the EZ-USB. The hosts PC reads
+out this data and verifies it.
+
+The traffic generator is implemented in the FPGA and supports two modes:
+
+1. (IOA3=0) This mode supports data flow control using FIFO full flag
+ (FLAGB) and SLWR control pin. Use this mode as starting point for
+ data acquisition applications.
+
+2. (IOA=3) In this mode and uninterrupted test pattern is generated,
+ i.e. flow control is disabled. This mode is used for performance
+ measurements (speed rate and interrupt measurements)
+
Index: 1.15a/intraffic/Makefile
===================================================================
--- 1.15a/intraffic/Makefile (nonexistent)
+++ 1.15a/intraffic/Makefile (revision 9)
@@ -0,0 +1,27 @@
+#########################
+# configuration section #
+#########################
+
+# Defines the location of the EZ-USB SDK
+ZTEXPREFIX=../../../..
+
+# The name of the jar archive
+JARTARGET=InTraffic.jar
+# Java Classes that have to be build
+CLASSTARGETS=InTraffic.class
+# Extra dependencies for Java Classes
+CLASSEXTRADEPS=
+
+# ihx files (firmware ROM files) that have to be build
+IHXTARGETS=intraffic.ihx
+# Extra Dependencies for ihx files
+IHXEXTRADEPS=
+
+# Extra files that should be included into th jar archive
+EXTRAJARFILES=intraffic.ihx fpga/intraffic.bit
+
+################################
+# DO NOT CHANAGE THE FOLLOWING #
+################################
+# includes the main Makefile
+include $(ZTEXPREFIX)/Makefile.mk
Index: 1.15a/intraffic/intraffic.sh
===================================================================
--- 1.15a/intraffic/intraffic.sh (nonexistent)
+++ 1.15a/intraffic/intraffic.sh (revision 9)
@@ -0,0 +1,4 @@
+#make -C ../../../java distclean all || exit
+#make distclean all || exit
+#make || exit
+java -cp InTraffic.jar InTraffic $@
1.15a/intraffic/intraffic.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/ucecho/ucecho.sh
===================================================================
--- 1.15a/ucecho/ucecho.sh (nonexistent)
+++ 1.15a/ucecho/ucecho.sh (revision 9)
@@ -0,0 +1,4 @@
+#make -C ../../../java distclean all || exit
+#make distclean all || exit
+#make || exit
+java -cp UCEcho.jar UCEcho $@
1.15a/ucecho/ucecho.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/ucecho/UCEcho.java
===================================================================
--- 1.15a/ucecho/UCEcho.java (nonexistent)
+++ 1.15a/ucecho/UCEcho.java (revision 9)
@@ -0,0 +1,169 @@
+/*!
+ ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+import java.io.*;
+import java.util.*;
+
+import ch.ntb.usb.*;
+
+import ztex.*;
+
+// *****************************************************************************
+// ******* ParameterException **************************************************
+// *****************************************************************************
+// Exception the prints a help message
+class ParameterException extends Exception {
+ public final static String helpMsg = new String (
+ "Parameters:\n"+
+ " -d Device Number (default: 0)\n" +
+ " -f Force uploads\n" +
+ " -p Print bus info\n" +
+ " -w Enable certain workarounds\n"+
+ " -h This help" );
+
+ public ParameterException (String msg) {
+ super( msg + "\n" + helpMsg );
+ }
+}
+
+// *****************************************************************************
+// ******* Test0 ***************************************************************
+// *****************************************************************************
+class UCEcho extends Ztex1v1 {
+
+// ******* UCEcho **************************************************************
+// constructor
+ public UCEcho ( ZtexDevice1 pDev ) throws UsbException {
+ super ( pDev );
+ }
+
+// ******* echo ****************************************************************
+// writes a string to Endpoint 4, reads it back from Endpoint 2 and writes the output to System.out
+ public void echo ( String input ) throws UsbException {
+ byte buf[] = input.getBytes();
+ int i = LibusbJava.usb_bulk_write(handle(), 0x04, buf, buf.length, 1000);
+ if ( i<0 )
+ throw new UsbException("Error sending data: " + LibusbJava.usb_strerror());
+ System.out.println("Send "+i+" bytes: `"+input+"'" );
+
+ try {
+ Thread.sleep( 10 );
+ }
+ catch ( InterruptedException e ) {
+ }
+
+ buf = new byte[1024];
+ i = LibusbJava.usb_bulk_read(handle(), 0x82, buf, 1024, 1000);
+ if ( i<0 )
+ throw new UsbException("Error receiving data: " + LibusbJava.usb_strerror());
+ System.out.println("Read "+i+" bytes: `"+new String(buf,0,i)+"'" );
+ }
+
+// ******* main ****************************************************************
+ public static void main (String args[]) {
+
+ int devNum = 0;
+ boolean force = false;
+ boolean workarounds = false;
+
+ try {
+// init USB stuff
+ LibusbJava.usb_init();
+
+// scan the USB bus
+ ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1);
+ if ( bus.numberOfDevices() <= 0) {
+ System.err.println("No devices found");
+ System.exit(0);
+ }
+
+// scan the command line arguments
+ for (int i=0; i=args.length) throw new Exception();
+ devNum = Integer.parseInt( args[i] );
+ }
+ catch (Exception e) {
+ throw new ParameterException("Device number expected after -d");
+ }
+ }
+ else if ( args[i].equals("-f") ) {
+ force = true;
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-w") ) {
+ workarounds = true;
+ }
+ else if ( args[i].equals("-h") ) {
+ System.err.println(ParameterException.helpMsg);
+ System.exit(0);
+ }
+ else throw new ParameterException("Invalid Parameter: "+args[i]);
+ }
+
+
+// create the main class
+ UCEcho ztex = new UCEcho ( bus.device(devNum) );
+ ztex.certainWorkarounds = workarounds;
+
+// upload the firmware if necessary
+ if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 1.15") ) {
+ System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms");
+ force = true;
+ }
+
+// upload the bitstream if necessary
+ if ( force || ! ztex.getFpgaConfiguration() ) {
+ System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/ucecho.bit" , force ) + " ms");
+ }
+
+
+// claim interface 0
+ ztex.trySetConfiguration ( 1 );
+ ztex.claimInterface ( 0 );
+
+// read string from stdin and write it to USB device
+ String str = "";
+ BufferedReader reader = new BufferedReader( new InputStreamReader( System.in ) );
+ while ( ! str.equals("quit") ) {
+ System.out.print("Enter a string or `quit' to exit the program: ");
+ str = reader.readLine();
+ if ( ! str.equals("") )
+ ztex.echo(str);
+ System.out.println("");
+ }
+
+// release interface 0
+ ztex.releaseInterface( 0 );
+
+ }
+ catch (Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ }
+ }
+
+}
Index: 1.15a/ucecho/ucecho.c
===================================================================
--- 1.15a/ucecho/ucecho.c (nonexistent)
+++ 1.15a/ucecho/ucecho.c (revision 9)
@@ -0,0 +1,97 @@
+/*!
+ ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
+#include[ztex-utils.h] // include basic functions
+
+// configure endpoints 2 and 4, both belong to interface 0 (in/out are from the point of view of the host)
+EP_CONFIG(2,0,BULK,IN,512,2);
+EP_CONFIG(4,0,BULK,OUT,512,2);
+
+// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
+IDENTITY_UFM_1_15(10.13.0.0,0);
+
+// this product string is also used for identification by the host software
+#define[PRODUCT_STRING]["ucecho example for UFM 1.15"]
+
+// enables high speed FPGA configuration via EP4
+ENABLE_HS_FPGA_CONF(4);
+
+__xdata BYTE run;
+
+#define[PRE_FPGA_RESET][PRE_FPGA_RESET
+ run = 0;
+]
+// this is called automatically after FPGA configuration
+#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
+ IFCONFIG = bmBIT7; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
+ SYNCDELAY;
+ EP2FIFOCFG = 0;
+ SYNCDELAY;
+ EP4FIFOCFG = 0;
+ SYNCDELAY;
+
+ REVCTL = 0x0; // reset
+ SYNCDELAY;
+ EP2CS &= ~bmBIT0; // stall = 0
+ SYNCDELAY;
+ EP4CS &= ~bmBIT0; // stall = 0
+
+ SYNCDELAY; // first two packages are waste
+ EP4BCL = 0x80; // skip package, (re)arm EP4
+ SYNCDELAY;
+ EP4BCL = 0x80; // skip package, (re)arm EP4
+
+ FIFORESET = 0x80; // reset FIFO
+ SYNCDELAY;
+ FIFORESET = 0x82;
+ SYNCDELAY;
+ FIFORESET = 0x00;
+ SYNCDELAY;
+
+ OEC = 255;
+ run = 1;
+]
+
+// include the main part of the firmware kit, define the descriptors, ...
+#include[ztex.h]
+
+void main(void)
+{
+ WORD i,size;
+
+// init everything
+ init_USB();
+
+ while (1) {
+ if ( run && !(EP4CS & bmBIT2) ) { // EP4 is not empty
+ size = (EP4BCH << 8) | EP4BCL;
+ if ( size>0 && size<=512 && !(EP2CS & bmBIT3)) { // EP2 is not full
+ for ( i=0; i> 8;
+ SYNCDELAY;
+ EP2BCL = size & 255; // arm EP2
+ }
+ SYNCDELAY;
+ EP4BCL = 0x80; // (re)arm EP4
+ }
+ }
+}
Index: 1.15a/ucecho/ucecho.bat
===================================================================
--- 1.15a/ucecho/ucecho.bat (nonexistent)
+++ 1.15a/ucecho/ucecho.bat (revision 9)
@@ -0,0 +1,2 @@
+java -cp UCEcho.jar UCEcho
+pause
Index: 1.15a/ucecho/fpga/ucecho.ucf
===================================================================
--- 1.15a/ucecho/fpga/ucecho.ucf (nonexistent)
+++ 1.15a/ucecho/fpga/ucecho.ucf (revision 9)
@@ -0,0 +1,21 @@
+NET "CLK" TNM_NET = "CLK";
+TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
+NET "CLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ;
+
+NET "pb<0>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
+NET "pb<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
+NET "pb<2>" LOC = "W13" | IOSTANDARD = LVCMOS33 ;
+NET "pb<3>" LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
+NET "pb<4>" LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
+NET "pb<5>" LOC = "W6" | IOSTANDARD = LVCMOS33 ;
+NET "pb<6>" LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
+NET "pb<7>" LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
+
+NET "pc<0>" LOC = "G20" | IOSTANDARD = LVCMOS33 ;
+NET "pc<1>" LOC = "T20" | IOSTANDARD = LVCMOS33 ;
+NET "pc<2>" LOC = "Y5" | IOSTANDARD = LVCMOS33 ;
+NET "pc<3>" LOC = "AB9" | IOSTANDARD = LVCMOS33 ;
+NET "pc<4>" LOC = "G19" | IOSTANDARD = LVCMOS33 ;
+NET "pc<5>" LOC = "H20" | IOSTANDARD = LVCMOS33 ;
+NET "pc<6>" LOC = "H19" | IOSTANDARD = LVCMOS33 ;
+NET "pc<7>" LOC = "H18" | IOSTANDARD = LVCMOS33 ;
Index: 1.15a/ucecho/fpga/ucecho.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: 1.15a/ucecho/fpga/ucecho.ise
===================================================================
--- 1.15a/ucecho/fpga/ucecho.ise (nonexistent)
+++ 1.15a/ucecho/fpga/ucecho.ise (revision 9)
1.15a/ucecho/fpga/ucecho.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: 1.15a/ucecho/fpga/ucecho.vhd
===================================================================
--- 1.15a/ucecho/fpga/ucecho.vhd (nonexistent)
+++ 1.15a/ucecho/fpga/ucecho.vhd (revision 9)
@@ -0,0 +1,33 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ucecho is
+ port(
+ pc : in unsigned(7 downto 0);
+ pb : out unsigned(7 downto 0);
+ CLK : in std_logic
+ );
+end ucecho;
+
+
+architecture RTL of ucecho is
+
+--signal declaration
+signal pb_buf : unsigned(7 downto 0);
+
+begin
+ dpUCECHO: process(CLK)
+ begin
+ if CLK' event and CLK = '1' then
+ if ( pc >= 97 ) and ( pc <= 122)
+ then
+ pb_buf <= pc - 32;
+ else
+ pb_buf <= pc;
+ end if;
+ pb <= pb_buf;
+ end if;
+ end process dpUCECHO;
+
+end RTL;
Index: 1.15a/ucecho/fpga/clean.sh
===================================================================
--- 1.15a/ucecho/fpga/clean.sh (nonexistent)
+++ 1.15a/ucecho/fpga/clean.sh (revision 9)
@@ -0,0 +1,80 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.vhd *.ucf *.sh *.ise *.bit *.bin *.xise"
+subdirs="ipcore_dir"
+
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/ucecho/fpga/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/ucecho/fpga/ucecho.xise
===================================================================
--- 1.15a/ucecho/fpga/ucecho.xise (nonexistent)
+++ 1.15a/ucecho/fpga/ucecho.xise (revision 9)
@@ -0,0 +1,56 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: 1.15a/ucecho/Makefile
===================================================================
--- 1.15a/ucecho/Makefile (nonexistent)
+++ 1.15a/ucecho/Makefile (revision 9)
@@ -0,0 +1,27 @@
+#########################
+# configuration section #
+#########################
+
+# Defines the location of the EZ-USB SDK
+ZTEXPREFIX=../../../..
+
+# The name of the jar archive
+JARTARGET=UCEcho.jar
+# Java Classes that have to be build
+CLASSTARGETS=UCEcho.class
+# Extra dependencies for Java Classes
+CLASSEXTRADEPS=
+
+# ihx files (firmware ROM files) that have to be build
+IHXTARGETS=ucecho.ihx
+# Extra Dependencies for ihx files
+IHXEXTRADEPS=
+
+# Extra files that should be included into th jar archive
+EXTRAJARFILES=ucecho.ihx fpga/ucecho.bit
+
+################################
+# DO NOT CHANAGE THE FOLLOWING #
+################################
+# includes the main Makefile
+include $(ZTEXPREFIX)/Makefile.mk
Index: 1.15a/ucecho/Readme
===================================================================
--- 1.15a/ucecho/Readme (nonexistent)
+++ 1.15a/ucecho/Readme (revision 9)
@@ -0,0 +1,21 @@
+ucecho
+------
+
+This example is intended for ZTEX USB-FPGA-Modules.
+
+The firmware (defined in ucecho.c) declares Endpoint 2 and Endpoint 4
+(both 512 bytes, double buffered, bulk transfer, belong to interface 0).
+All data that is written to Endpoint 4 is converted to uppercase by
+the FPGA and can be read back from Endpoint 2.
+
+This example does the same as the example in directory ../../all/ucecho
+except that the uppercase - lowercase conversion is made by the FPGA.
+
+The driver (defined in UCEcho.java) uploads the the Firmware (ucecho.ihx)
+to the EZ-USB Microcontroller and the Bitstream (fpga/ucecho.bit) to the
+FPGA if necessary, sends user string to the device and reads them back.
+
+Uploading the Firmware to EEPROM is also supported by the firmware (e.g.
+using the FWLoader utility).
+
+This example may serve a good starting point for own projects.
Index: 1.15a/lightshow/lightshow.sh
===================================================================
--- 1.15a/lightshow/lightshow.sh (nonexistent)
+++ 1.15a/lightshow/lightshow.sh (revision 9)
@@ -0,0 +1,4 @@
+#make -C ../../../java distclean all || exit
+#make distclean all || exit
+#make || exit
+java -cp Lightshow.jar Lightshow $@
1.15a/lightshow/lightshow.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/lightshow/lightshow-prog.sh
===================================================================
--- 1.15a/lightshow/lightshow-prog.sh (nonexistent)
+++ 1.15a/lightshow/lightshow-prog.sh (revision 9)
@@ -0,0 +1,7 @@
+# programms the EEPROM and the FPGA for standalone usage
+#make -C ../../../../java distclean all || exit
+#make distclean all || exit
+
+java -cp Lightshow.jar Lightshow $@
+../../../../java/FWLoader -ue lightshow.ihx -um fpga/lightshow.bit
+
1.15a/lightshow/lightshow-prog.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/lightshow/avr/lightshow.ihx
===================================================================
--- 1.15a/lightshow/avr/lightshow.ihx (nonexistent)
+++ 1.15a/lightshow/avr/lightshow.ihx (revision 9)
@@ -0,0 +1,44 @@
+:100000000C94FA000C9418010C9418010C9418012B
+:100010000C9418010C9418010C9418010C941801FC
+:100020000C9418010C9418010C9418010C941801EC
+:100030000C9418010C9418010C9418010C941801DC
+:100040000C9418010C9418010C9418010C941801CC
+:100050000C9418010C9418010C9418010C941801BC
+:100060000C9418010C9418010C9418010C941801AC
+:100070000C9418010C9418010C9418010C9418019C
+:100080000C9418010C9418010C9418010C9418018C
+:100090000C9418010C9418010C9418010C9418017C
+:1000A0000C9418010C9418010C9418010C9418016C
+:1000B0000C9418010C9418010C9418010C9418015C
+:1000C0000C9418010C9418010C9418010C9418014C
+:1000D0000C9418010C9418010C9418010C9418013C
+:1000E0000C9418010C9418010C9418010C9418012C
+:1000F0000C9418010C9418010C9418010C9418011C
+:100100000C9418010C9418010C9418010C9418010B
+:100110000C9418010C9418010C9418010C941801FB
+:100120000C9418010C9418010C9418010C941801EB
+:100130000C9418010C9418010C9418010C941801DB
+:100140000C9418010C9418010C9418010C941801CB
+:100150000C9418010C9418010C9418010C941801BB
+:100160000C9418010C9418010C9418010C941801AB
+:100170000C9418010C9418010C9418010C9418019B
+:100180000C9418010C9418010C9418010C9418018B
+:100190000C9418010C9418010C9418010C9418017B
+:1001A0000C9418010C9418010C9418010C9418016B
+:1001B0000C9418010C9418010C9418010C9418015B
+:1001C0000C9418010C9418010C9418010C9418014B
+:1001D0000C9418010C9418010C9418010C9418013B
+:1001E0000C9418010C9418010C9418010C9418012B
+:1001F0000C94180111241FBECFEFDFE3DEBFCDBF8B
+:1002000000E00CBF18BE19BE1ABE1BBE10E2A0E073
+:10021000B0E2ECEAF2E000E00BBF02C007900D9202
+:10022000A030B107D9F71BBE0E941A010C945401EB
+:100230000C94000088ED77E084BF709350008091AB
+:10024000510087708730D9F788ED71E084BF7093D3
+:10025000600084BF7093680084BF7093400088ED95
+:1002600071E084BF7093960082E0E0EBF0E084835D
+:1002700080E880936006109200071092E00680915B
+:1002800060068F60809360068FEF8093A006A0E6E3
+:10029000B6E0E0EAF6E08091080714968C93149794
+:0C02A0008091E8068483F7CFF894FFCF2C
+:00000001FF
Index: 1.15a/lightshow/avr/avrdude.sh
===================================================================
--- 1.15a/lightshow/avr/avrdude.sh (nonexistent)
+++ 1.15a/lightshow/avr/avrdude.sh (revision 9)
@@ -0,0 +1,2 @@
+make || exit
+avrdude -p x128a1 -c avrispmkii -P usb -e -U flash:w:test.ihx:i
1.15a/lightshow/avr/avrdude.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/lightshow/avr/lightshow.c
===================================================================
--- 1.15a/lightshow/avr/lightshow.c (nonexistent)
+++ 1.15a/lightshow/avr/lightshow.c (revision 9)
@@ -0,0 +1,76 @@
+/*!
+ lightshow -- lightshow on Experimental Board 1.10
+ Copyright (C) 2009-2010 ZTEX e.K.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+#include
+
+#define F_CPU 32000000UL
+#include
+
+typedef uint8_t byte;
+
+int main(void)
+{
+ // enable 32.768 kHz, 32 MHz, 2 Mhz clocks
+ asm volatile (
+ "ldi r24,0xd8" "\n\t"
+ "ldi r23,7" "\n\t"
+ "out 0x34,r24" "\n\t"
+ "sts 0x50,r23"
+ ::: "r24", "r23"
+ );
+
+ // wait until clocks are ready
+ while ( (OSC.STATUS & 7) != 7 ) { }
+
+ // enable run time configuration of 32 MHz and 2 MHz clocks; select 32 MHz clock as system clock
+ asm volatile (
+ "ldi r24,0xd8" "\n\t"
+ "ldi r23,1" "\n\t"
+ "out 0x34,r24" "\n\t"
+ "sts 0x60,r23" "\n\t"
+ "out 0x34,r24" "\n\t"
+ "sts 0x68,r23" "\n\t"
+ "out 0x34,r24" "\n\t"
+ "sts 0x40,r23"
+ ::: "r24", "r23"
+ );
+
+ // disable JTAG at portb
+ asm volatile (
+ "ldi r24,0xd8" "\n\t"
+ "ldi r23,1" "\n\t"
+ "out 0x34,r24" "\n\t"
+ "sts 0x96,r23" "\n\t"
+ ::: "r24", "r23"
+ );
+
+ // clock output to PD7
+ PORTCFG.CLKEVOUT = 2;
+ PORTD.DIR = 128;
+
+ PORTJ.DIR = 0; // input: 4 LED's
+ PORTH.DIR = 0; // input: 8 LED's
+ PORTD.DIR |= 15; // output: 4 LED's
+ PORTF.DIR = 255; // output: 8 LED's
+
+ while (1) {
+ PORTD.OUT = PORTJ.IN;
+ PORTF.OUT = PORTH.IN;
+ }
+}
+
Index: 1.15a/lightshow/avr/Makefile
===================================================================
--- 1.15a/lightshow/avr/Makefile (nonexistent)
+++ 1.15a/lightshow/avr/Makefile (revision 9)
@@ -0,0 +1,16 @@
+AVRGCC=avr-gcc -std=gnu99 -save-temps -mmcu=atxmega128a1 -O2
+OBJ2HEX=avr-objcopy
+
+all: lightshow.ihx
+
+%.obj : %.c
+ $(AVRGCC) $< -o $@
+
+%.ihx : %.obj
+ $(OBJ2HEX) -R .eeprom -O ihex $< $@
+
+clean:
+ rm -f *.o *.i *.s *.obj *.old *.bak *~
+
+distclean:
+ rm -f *.ihx
Index: 1.15a/lightshow/Lightshow.java
===================================================================
--- 1.15a/lightshow/Lightshow.java (nonexistent)
+++ 1.15a/lightshow/Lightshow.java (revision 9)
@@ -0,0 +1,130 @@
+/*!
+ lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+import java.io.*;
+import java.util.*;
+
+import ch.ntb.usb.*;
+
+import ztex.*;
+
+// *****************************************************************************
+// ******* ParameterException **************************************************
+// *****************************************************************************
+// Exception the prints a help message
+class ParameterException extends Exception {
+ public final static String helpMsg = new String (
+ "Parameters:\n"+
+ " -d Device Number (default: 0)\n" +
+ " -f Force uploads\n" +
+ " -p Print bus info\n" +
+ " -h This help" );
+
+ public ParameterException (String msg) {
+ super( msg + "\n" + helpMsg );
+ }
+}
+
+// *****************************************************************************
+// ******* Test0 ***************************************************************
+// *****************************************************************************
+class Lightshow extends Ztex1v1 {
+
+// ******* Lightshow ***********************************************************
+// constructor
+ public Lightshow ( ZtexDevice1 pDev ) throws UsbException {
+ super ( pDev );
+ }
+
+// ******* main ****************************************************************
+ public static void main (String args[]) {
+
+ int devNum = 0;
+ boolean force = false;
+ boolean workarounds = false;
+
+ try {
+// init USB stuff
+ LibusbJava.usb_init();
+
+// scan the USB bus
+ ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1);
+ if ( bus.numberOfDevices() <= 0) {
+ System.err.println("No devices found");
+ System.exit(0);
+ }
+
+// scan the command line arguments
+ for (int i=0; i=args.length) throw new Exception();
+ devNum = Integer.parseInt( args[i] );
+ }
+ catch (Exception e) {
+ throw new ParameterException("Device number expected after -d");
+ }
+ }
+ else if ( args[i].equals("-f") ) {
+ force = true;
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-h") ) {
+ System.err.println(ParameterException.helpMsg);
+ System.exit(0);
+ }
+ else throw new ParameterException("Invalid Parameter: "+args[i]);
+ }
+
+
+// create the main class
+ Lightshow ztex = new Lightshow ( bus.device(devNum) );
+
+// upload the firmware if necessary
+ if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("lightshow for EXP-1.10") ) {
+ System.out.println("Firmware upload time: " + ztex.uploadFirmware( "lightshow.ihx", force ) + " ms");
+ }
+
+// check for Experimental Bord 1.10
+ if ( ! ztex.xmegaEnabled() )
+ throw new Exception("Experimental Board 1.10 required");
+
+// upload the bitstream if necessary
+ System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/lightshow.bit" , true ) + " ms");
+
+// bitstream if necessary
+ System.out.println("AVR Firmware upload time: " + ztex.xmegaWriteFirmware( new IhxFile("avr/lightshow.ihx" ) ) + " ms");
+
+// program the ATxmega
+ System.out.println( ztex );
+
+ }
+ catch (Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ }
+ }
+
+}
Index: 1.15a/lightshow/lightshow.c
===================================================================
--- 1.15a/lightshow/lightshow.c (nonexistent)
+++ 1.15a/lightshow/lightshow.c (revision 9)
@@ -0,0 +1,50 @@
+/*!
+ lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
+#include[ztex-utils.h] // include basic functions
+
+// Endpoint 2 is used to high speed FPGA configuration
+EP_CONFIG(2,0,BULK,OUT,512,4);
+
+// select ZTEX USB FPGA Module 1.15 + Experimental Board 1.10 as target
+IDENTITY_UFM_1_15(10.13.0.0,0);
+EXTENSION_EXP_1_10;
+
+// enables high speed FPGA configuration, use EP 2
+ENABLE_HS_FPGA_CONF(2);
+
+// this product string is also used for identification by the host software
+#define[PRODUCT_STRING]["lightshow for EXP-1.10"]
+
+// enable Flash support
+ENABLE_FLASH;
+ENABLE_FLASH_BITSTREAM;
+
+// include the main part of the firmware kit, define the descriptors, ...
+#include[ztex.h]
+
+void main(void)
+{
+// init everything
+ init_USB();
+
+ while ( 1 ) {
+ }
+}
+
Index: 1.15a/lightshow/fpga/lightshow.xise
===================================================================
--- 1.15a/lightshow/fpga/lightshow.xise (nonexistent)
+++ 1.15a/lightshow/fpga/lightshow.xise (revision 9)
@@ -0,0 +1,327 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: 1.15a/lightshow/fpga/lightshow.ucf
===================================================================
--- 1.15a/lightshow/fpga/lightshow.ucf (nonexistent)
+++ 1.15a/lightshow/fpga/lightshow.ucf (revision 9)
@@ -0,0 +1,17 @@
+NET "CLK" TNM_NET = "CLK";
+TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
+# NET "CLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ; # EZ-USB clock
+NET "CLK" LOC = "AB12" | IOSTANDARD = LVCMOS33 ; # xmega clock
+
+NET "led<0>" LOC = "D11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<0>
+NET "led<1>" LOC = "F10" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<1>
+NET "led<2>" LOC = "D10" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<2>
+NET "led<3>" LOC = "D9" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<3>
+NET "led<4>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<4>
+NET "led<5>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<5>
+NET "led<6>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<6>
+NET "led<7>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # ph<7>
+NET "led<8>" LOC = "W12" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # pj<0>
+NET "led<9>" LOC = "W9" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # pj<1>
+NET "led<10>" LOC = "T14" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # pj<2>
+NET "led<11>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # pj<3>
Index: 1.15a/lightshow/fpga/lightshow.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: 1.15a/lightshow/fpga/lightshow.ise
===================================================================
--- 1.15a/lightshow/fpga/lightshow.ise (nonexistent)
+++ 1.15a/lightshow/fpga/lightshow.ise (revision 9)
1.15a/lightshow/fpga/lightshow.ise
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: 1.15a/lightshow/fpga/lightshow.vhd
===================================================================
--- 1.15a/lightshow/fpga/lightshow.vhd (nonexistent)
+++ 1.15a/lightshow/fpga/lightshow.vhd (revision 9)
@@ -0,0 +1,84 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity lightshow is
+ port(
+ led : out std_logic_vector(11 downto 0);
+ CLK : in std_logic -- 32 MHz
+ );
+end lightshow;
+
+--signal declaration
+architecture RTL of lightshow is
+
+type tPattern is array(11 downto 0) of integer range 0 to 15;
+
+signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
+signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
+signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
+
+type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
+constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
+type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
+--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
+constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
+
+signal cp1 : std_logic_vector(22 downto 0);
+signal cp2 : std_logic_vector(22 downto 0);
+signal cp3 : std_logic_vector(22 downto 0);
+signal d : std_logic_vector(16 downto 0);
+
+begin
+ dpCLK: process(CLK)
+ begin
+ if CLK' event and CLK = '1' then
+
+ if ( cp1 = conv_std_logic_vector(3000000,23) )
+ then
+ pattern1(10 downto 0) <= pattern1(11 downto 1);
+ pattern1(11) <= pattern1(0);
+ cp1 <= (others => '0');
+ else
+ cp1 <= cp1 + 1;
+ end if;
+
+ if ( cp2 = conv_std_logic_vector(2200000,23) )
+ then
+ pattern2(10 downto 0) <= pattern2(11 downto 1);
+ pattern2(11) <= pattern2(0);
+ cp2 <= (others => '0');
+ else
+ cp2 <= cp2 + 1;
+ end if;
+
+ if ( cp3 = conv_std_logic_vector(1500000,23) )
+ then
+ pattern3(11 downto 1) <= pattern3(10 downto 0);
+ pattern3(0) <= pattern3(11);
+ cp3 <= (others => '0');
+ else
+ cp3 <= cp3 + 1;
+ end if;
+
+ if ( d = conv_std_logic_vector(1278*64-1,17) )
+ then
+ d <= (others => '0');
+ else
+ d <= d + 1;
+ end if;
+
+ for i in 0 to 11 loop
+ if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
+ then
+ led(i) <= '1';
+ else
+ led(i) <= '0';
+ end if;
+ end loop;
+
+ end if;
+ end process dpCLK;
+
+end RTL;
Index: 1.15a/lightshow/fpga/clean.sh
===================================================================
--- 1.15a/lightshow/fpga/clean.sh (nonexistent)
+++ 1.15a/lightshow/fpga/clean.sh (revision 9)
@@ -0,0 +1,80 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.vhd *.ucf *.sh *.ise *.bit *.bin *.xise"
+subdirs="ipcore_dir"
+
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/lightshow/fpga/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/lightshow/Makefile
===================================================================
--- 1.15a/lightshow/Makefile (nonexistent)
+++ 1.15a/lightshow/Makefile (revision 9)
@@ -0,0 +1,21 @@
+#########################
+# configuration section #
+#########################
+
+ZTEXPREFIX=../../../..
+
+JARTARGET=Lightshow.jar
+CLASSTARGETS=Lightshow.class
+CLASSEXTRADEPS=
+#CLASSEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/java/ztex/*.java)
+
+IHXTARGETS=lightshow.ihx
+IHXEXTRADEPS=
+#IHXEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/include/*.h)
+EXTRAJARFILES=lightshow.ihx avr/lightshow.ihx fpga/lightshow.bit
+
+################################
+# DO NOT CHANAGE THE FOLLOWING #
+################################
+
+include $(ZTEXPREFIX)/Makefile.mk
Index: 1.15a/lightshow/Readme
===================================================================
--- 1.15a/lightshow/Readme (nonexistent)
+++ 1.15a/lightshow/Readme (revision 9)
@@ -0,0 +1,6 @@
+lightshow
+---------
+
+This example requires the Experimental Board 1.10.
+
+It implements a light show using the LED's on the board.
Index: 1.15a/lightshow/lightshow.bat
===================================================================
--- 1.15a/lightshow/lightshow.bat (nonexistent)
+++ 1.15a/lightshow/lightshow.bat (revision 9)
@@ -0,0 +1,2 @@
+java -cp Lightshow.jar Lightshow
+pause
Index: 1.15a/Makefile
===================================================================
--- 1.15a/Makefile (nonexistent)
+++ 1.15a/Makefile (revision 9)
@@ -0,0 +1,26 @@
+DIRS=ucecho intraffic memtest lightshow mmio
+
+.PHONY: default all clean distclean avr avrclean avrdistclean
+
+default:
+ @echo "This makefile is intended to clean up the project or to build all examples in this subdirectory"
+ @echo "Usage: make all | clean | distclean"
+
+all:
+ set -e; for i in $(DIRS); do make -C $$i all; done
+
+clean:
+ set -e; for i in $(DIRS); do make -C $$i clean; done
+
+distclean:
+ set -e; for i in $(DIRS); do make -C $$i distclean; done
+
+avr:
+ set -e; for i in $(DIRS); do make -C $$i avr; done
+
+avrclean:
+ set -e; for i in $(DIRS); do make -C $$i avrclean; done
+
+avrdistclean:
+ set -e; for i in $(DIRS); do make -C $$i avrdistclean; done
+
Index: 1.15a/memtest/memtest.c
===================================================================
--- 1.15a/memtest/memtest.c (nonexistent)
+++ 1.15a/memtest/memtest.c (revision 9)
@@ -0,0 +1,96 @@
+/*!
+ memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
+#include[ztex-utils.h] // include basic functions
+
+// configure endpoint 2, in, quad buffered, 512 bytes, interface 0
+EP_CONFIG(2,0,BULK,IN,512,4);
+
+// configure endpoint 6, out, doublebuffered, 512 bytes, interface 0
+EP_CONFIG(6,0,BULK,OUT,512,2);
+
+// select ZTEX USB FPGA Module 1.11 as target (required for FPGA configuration)
+IDENTITY_UFM_1_15(10.13.0.0,0);
+
+// enables high speed FPGA configuration via EP6
+ENABLE_HS_FPGA_CONF(6);
+
+// this product string is also used for identification by the host software
+#define[PRODUCT_STRING]["memtest example for UFM 1.15"]
+
+// 0 : counter mode; 1: shift pattern mode
+__xdata BYTE mode = 0;
+
+// this is called automatically after FPGA configuration
+#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
+ IOA7 = 1; // reset on
+ OEA |= bmBIT7;
+ IOC0 = mode ? 1 : 0;
+ OEC = bmBIT0;
+
+ EP2CS &= ~bmBIT0; // clear stall bit
+
+ REVCTL = 0x3;
+ SYNCDELAY;
+
+ IFCONFIG = bmBIT7 | bmBIT5 | 3; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
+ SYNCDELAY;
+ EP2FIFOCFG = bmBIT3 | bmBIT0; // AOTUOIN, WORDWIDE
+ SYNCDELAY;
+
+ EP2AUTOINLENH = 2; // 512 bytes
+ SYNCDELAY;
+ EP2AUTOINLENL = 0;
+ SYNCDELAY;
+
+ FIFORESET = 0x80; // reset FIFO
+ SYNCDELAY;
+ FIFORESET = 2;
+ SYNCDELAY;
+ FIFORESET = 0x00;
+ SYNCDELAY;
+
+ FIFOPINPOLAR = 0;
+ SYNCDELAY;
+ PINFLAGSAB = 0;
+ SYNCDELAY;
+ PINFLAGSCD = 0;
+ SYNCDELAY;
+
+ IOA7 = 0; // reset off
+]
+
+// set the test pattern
+ADD_EP0_VENDOR_COMMAND((0x60,,
+ mode = SETUPDAT[2];
+,,
+ NOP;
+));;
+
+// include the main part of the firmware kit, define the descriptors, ...
+#include[ztex.h]
+
+void main(void)
+{
+ init_USB();
+
+ while (1) {
+ }
+}
+
Index: 1.15a/memtest/memtest.bat
===================================================================
--- 1.15a/memtest/memtest.bat (nonexistent)
+++ 1.15a/memtest/memtest.bat (revision 9)
@@ -0,0 +1,3 @@
+java -cp MemTest.jar MemTest
+pause
+
Index: 1.15a/memtest/memtest.sh
===================================================================
--- 1.15a/memtest/memtest.sh (nonexistent)
+++ 1.15a/memtest/memtest.sh (revision 9)
@@ -0,0 +1,6 @@
+#make -C ../../../java distclean all || exit
+#cd fpga
+#./promgen.sh
+#cd ..
+#make distclean all || exit
+java -cp MemTest.jar MemTest $@
1.15a/memtest/memtest.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0.xise
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0.xise (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0.xise (revision 9)
@@ -0,0 +1,122 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: 1.15a/memtest/fpga/ipcore_dir/mem0.xco
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0.xco (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0.xco (revision 9)
@@ -0,0 +1,42 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Wed Jul 20 10:38:33 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT MIG family Xilinx,_Inc. 3.5
+# END Select
+# BEGIN Parameters
+CSET component_name=mem0
+CSET xml_input_file=./mem0/user_design/mig.prj
+# END Parameters
+GENERATE
+# CRC: b055767e
Index: 1.15a/memtest/fpga/ipcore_dir/clean.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/clean.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/clean.sh (revision 9)
@@ -0,0 +1,85 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.vhd *.sh *.ise *.xco *.xise *.tcl"
+subdirs="mem0 custom_part"
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $binfiles; do # binfiles is set by distclean.sh
+ if [ "$i" == "$f" ]; then
+ keep=false
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/memtest/fpga/ipcore_dir/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 9)
@@ -0,0 +1,61 @@
+--- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200
++++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200
+@@ -122,7 +122,6 @@
+ signal mcb_drp_clk_bufg_in : std_logic;
+ signal clkfbout_clkfbin : std_logic;
+ signal rst_tmp : std_logic;
+- signal sys_clk_ibufg : std_logic;
+ signal sys_rst : std_logic;
+ signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
+ signal powerup_pll_locked : std_logic;
+@@ -135,7 +134,6 @@
+ attribute KEEP : string;
+ attribute max_fanout of rst0_sync_r : signal is "10";
+ attribute syn_maxfan of rst0_sync_r : signal is 10;
+- attribute KEEP of sys_clk_ibufg : signal is "TRUE";
+
+ begin
+
+@@ -144,33 +142,6 @@
+ pll_lock <= bufpll_mcb_locked;
+ mcb_drp_clk <= mcb_drp_clk_sig;
+
+- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
+- --***********************************************************************
+- -- Differential input clock input buffers
+- --***********************************************************************
+- u_ibufg_sys_clk : IBUFGDS
+- generic map (
+- DIFF_TERM => TRUE
+- )
+- port map (
+- I => sys_clk_p,
+- IB => sys_clk_n,
+- O => sys_clk_ibufg
+- );
+- end generate;
+-
+-
+- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
+- --***********************************************************************
+- -- SINGLE_ENDED input clock input buffers
+- --***********************************************************************
+- u_ibufg_sys_clk : IBUFG
+- port map (
+- I => sys_clk,
+- O => sys_clk_ibufg
+- );
+- end generate;
+-
+ --***************************************************************************
+ -- Global clock generation and distribution
+ --***************************************************************************
+@@ -209,7 +180,7 @@
+ (
+ CLKFBIN => clkfbout_clkfbin,
+ CLKINSEL => '1',
+- CLKIN1 => sys_clk_ibufg,
++ CLKIN1 => sys_clk,
+ CLKIN2 => '0',
+ DADDR => (others => '0'),
+ DCLK => '0',
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 9)
@@ -0,0 +1,131 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.1
+# Date: Wed Mar 11 06:55:40 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=256
+CSET data_same_as_trigger=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=true
+CSET exclude_from_data_storage_10=true
+CSET exclude_from_data_storage_11=true
+CSET exclude_from_data_storage_12=true
+CSET exclude_from_data_storage_13=true
+CSET exclude_from_data_storage_14=true
+CSET exclude_from_data_storage_15=true
+CSET exclude_from_data_storage_16=true
+CSET exclude_from_data_storage_2=true
+CSET exclude_from_data_storage_3=true
+CSET exclude_from_data_storage_4=true
+CSET exclude_from_data_storage_5=true
+CSET exclude_from_data_storage_6=true
+CSET exclude_from_data_storage_7=true
+CSET exclude_from_data_storage_8=true
+CSET exclude_from_data_storage_9=true
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=1024
+CSET sample_on=Rising
+CSET trigger_port_width_1=2
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE
+# CRC: eff89f81
+
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 9)
@@ -0,0 +1,86 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+# ____ ____
+# / /\/ /
+# /___/ \ / Vendor : Xilinx
+# \ \ \/ Version : 3.5
+# \ \ Application : MIG
+# / / Filename : ise_flow.bat
+# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $
+# \ \ / \ Date Created : Fri Feb 06 2009
+# \___\/\___\
+#
+# Device : Spartan-6
+# Design Name : DDR/DDR2/DDR3/LPDDR
+# Purpose : Batch file to run PAR through ISE batch mode
+# Reference :
+# Revision History :
+# ****************************************************************************
+
+./rem_files.sh
+
+
+
+
+echo Synthesis Tool: XST
+
+mkdir "../synth/__projnav" > ise_flow_results.txt
+mkdir "../synth/xst" >> ise_flow_results.txt
+mkdir "../synth/xst/work" >> ise_flow_results.txt
+
+xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
+ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx45csg484-2 mem0.ngc mem0.ngd >> ise_flow_results.txt
+
+map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt
+par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt
+trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt
+bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt
+
+echo done!
1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 9)
@@ -0,0 +1,2 @@
+NEWPROJECT .
+SETPROJECT .
1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 9)
@@ -0,0 +1,48 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.1
+# Date: Wed Mar 11 07:09:11 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET enable_jtag_bufg=true
+CSET number_control_ports=2
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE
+# CRC: 7da1f376
+
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 9)
@@ -0,0 +1,51 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.2
+# Date: Fri Jun 12 05:42:56 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET asynchronous_input_port_width=8
+CSET asynchronous_output_port_width=7
+CSET component_name=vio
+CSET enable_asynchronous_input_port=false
+CSET enable_asynchronous_output_port=true
+CSET enable_synchronous_input_port=false
+CSET enable_synchronous_output_port=false
+CSET invert_clock_input=false
+CSET synchronous_input_port_width=8
+CSET synchronous_output_port_width=8
+# END Parameters
+GENERATE
+# CRC: 66fe39ed
+
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 9)
@@ -0,0 +1,72 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+# ____ ____
+# / /\/ /
+# /___/ \ / Vendor : Xilinx
+# \ \ \/ Version : 3.5
+# \ \ Application : MIG
+# / / Filename : create_ise.bat
+# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:12 $
+# \ \ / \ Date Created : Fri Feb 06 2009
+# \___\/\___\
+#
+# Device : Spartan-6
+# Design Name : DDR/DDR2/DDR3/LPDDR
+# Purpose : Batch file to run PAR through ISE
+# Reference :
+# Revision History :
+# ****************************************************************************
+
+./rem_files.sh
+
+
+
+
+xtclsh set_ise_prop.tcl
1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 9)
@@ -0,0 +1,169 @@
+##!/bin/csh -f
+##****************************************************************************
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+##****************************************************************************
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor : Xilinx
+## \ \ \/ Version : 3.5
+## \ \ Application : MIG
+## / / Filename : rem_files.bat
+## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $
+## \ \ / \ Date Created : Fri Feb 06 2009
+## \___\/\___\
+##
+## Device : Spartan-6
+## Design Name : DDR/DDR2/DDR3/LPDDR
+## Purpose : Batch file to remove files generated from ISE
+## Reference :
+## Revision History :
+##****************************************************************************
+
+rm -rf "../synth/__projnav"
+rm -rf "../synth/xst"
+rm -rf "../synth/_ngo"
+
+rm -rf tmp
+rm -rf _xmsgs
+rm -rf ila_xdb
+rm -rf icon_xdb
+rm -rf vio_xdb
+
+rm -rf xlnx_auto_0_xdb
+
+rm -rf vio_xmdf.tcl
+rm -rf vio_readme.txt
+rm -rf vio_flist.txt
+rm -rf vio.xise del
+rm -rf vio.xco del
+rm -rf vio.ngc del
+rm -rf vio.ise del
+rm -rf vio.gise del
+rm -rf vio.cdc del
+
+rm -rf coregen.cgp
+rm -rf coregen.cgc
+rm -rf coregen.log
+rm -rf ila.cdc
+rm -rf ila.gise
+rm -rf ila.ise
+rm -rf ila.ngc
+rm -rf ila.xco
+rm -rf ila.xise
+rm -rf ila_flist.txt
+rm -rf ila_readme.txt
+rm -rf ila_xmdf.tcl
+
+rm -rf icon.asy
+rm -rf icon.gise
+rm -rf icon.ise
+rm -rf icon.ncf
+rm -rf icon.ngc
+rm -rf icon.xco
+rm -rf icon.xise
+rm -rf icon_flist.txt
+rm -rf icon_readme.txt
+rm -rf icon_xmdf.tcl
+
+rm -rf ise_flow_results.txt
+rm -rf mem0_vhdl.prj
+rm -rf mem_interface_top.syr
+rm -rf mem0.ngc
+rm -rf mem0.ngr
+rm -rf mem0_xst.xrpt
+rm -rf mem0.bld
+rm -rf mem0.ngd
+rm -rf mem0_ngdbuild.xrpt
+rm -rf mem0_map.map
+rm -rf mem0_map.mrp
+rm -rf mem0_map.ngm
+rm -rf mem0.pcf
+rm -rf mem0_map.ncd
+rm -rf mem0_map.xrpt
+rm -rf mem0_summary.xml
+rm -rf mem0_usage.xml
+rm -rf mem0.ncd
+rm -rf mem0.par
+rm -rf mem0.xpi
+rm -rf mem0.ptwx
+rm -rf mem0.pad
+rm -rf mem0.unroutes
+rm -rf mem0_pad.csv
+rm -rf mem0_pad.txt
+rm -rf mem0_par.xrpt
+rm -rf mem0.twx
+rm -rf mem0.bgn
+rm -rf mem0.twr
+rm -rf mem0.drc
+rm -rf mem0_bitgen.xwbt
+rm -rf mem0.bit
+
+# Files and folders generated by create ise
+rm -rf test_xdb
+rm -rf _xmsgs
+rm -rf test.gise
+rm -rf test.xise
+rm -rf test.xise
+
+# Files and folders generated by ISE through GUI mode
+rm -rf _ngo
+rm -rf xst
+rm -rf mem0.lso
+rm -rf mem0.prj
+rm -rf mem0.xst
+rm -rf mem0.stx
+rm -rf mem0_prev_built.ngd
+rm -rf test.ntrc_log
+rm -rf mem0_guide.ncd
+rm -rf mem0.cmd_log
+rm -rf mem0_summary.html
+rm -rf mem0.ut
+rm -rf par_usage_statistics.html
+rm -rf usage_statistics_webtalk.html
+rm -rf webtalk.log
+rm -rf device_usage_statistics.html
1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (revision 9)
@@ -0,0 +1,8 @@
+vhdl work ../rtl/iodrp_controller.vhd
+vhdl work ../rtl/iodrp_mcb_controller.vhd
+vhdl work ../rtl/mcb_raw_wrapper.vhd
+vhdl work ../rtl/mcb_soft_calibration.vhd
+vhdl work ../rtl/mcb_soft_calibration_top.vhd
+vhdl work ../rtl/mem0.vhd
+vhdl work ../rtl/memc3_infrastructure.vhd
+vhdl work ../rtl/memc3_wrapper.vhd
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (revision 9)
@@ -0,0 +1,60 @@
+
+
+ mem0
+ xc6slx45-csg484/-2
+ 3.5
+
+ DDR2_SDRAM/Components/MT47H64M16XX-25E
+ 2500
+ 1
+ 1
+ FALSE
+ 13
+ 10
+ 3
+
+
+ 4(010)
+ 5
+ Enable-Normal
+ Fullstrength
+ RTT Disabled
+ 0
+ OCD Exit
+ Enable
+ Disable
+ Enable
+ Disable
+ Class II
+ Class II
+ CALIB_TERM
+ 25 Ohms
+ 1
+ Disable
+ Single-Ended
+ Two 32-bit bi-directional and four 32-bit unidirectional ports
+ AA2
+ Y2
+ Port0,Port1,Port2,Port3,Port4,Port5
+ Bi-directional,Bi-directional,Write,Read,Write,Read
+ ROW_BANK_COLUMN
+ Round Robin
+ 012345
+ 123450
+ 234501
+ 345012
+ 450123
+ 501234
+ 012345
+ 123450
+ 234501
+ 345012
+ 450123
+ 501234
+
+
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (revision 9)
@@ -0,0 +1,85 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.sh *.prj"
+subdirs="par rtl synth"
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $binfiles; do # binfiles is set by distclean.sh
+ if [ "$i" == "$f" ]; then
+ keep=false
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh
===================================================================
--- 1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent)
+++ 1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 9)
@@ -0,0 +1,86 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.sh"
+subdirs="user_design"
+
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $binfiles; do # binfiles is set by distclean.sh
+ if [ "$i" == "$f" ]; then
+ keep=false
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/memtest.xise
===================================================================
--- 1.15a/memtest/fpga/memtest.xise (nonexistent)
+++ 1.15a/memtest/fpga/memtest.xise (revision 9)
@@ -0,0 +1,481 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: 1.15a/memtest/fpga/memtest.ucf
===================================================================
--- 1.15a/memtest/fpga/memtest.ucf (nonexistent)
+++ 1.15a/memtest/fpga/memtest.ucf (revision 9)
@@ -0,0 +1,159 @@
+NET "FXCLK" TNM_NET = "FXCLK";
+TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 20.83333 ns HIGH 50 %;
+NET "FXCLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ;
+
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
+NET "IFCLK" LOC = "K20" | IOSTANDARD = LVCMOS33 ;
+
+NET "CLK" TNM_NET = "CLK";
+TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
+TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;
+
+NET "SLOE" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2
+NET "FIFOADR0" LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4
+NET "FIFOADR1" LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5
+NET "PKTEND" LOC = "AB5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6
+NET "RESET_IN" LOC = "AB17" | IOSTANDARD = LVCMOS33 ; # PA7
+
+NET "PC0" LOC = "G20" | IOSTANDARD = LVCMOS33 ;
+
+NET "fd<0>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
+NET "fd<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
+NET "fd<2>" LOC = "W13" | IOSTANDARD = LVCMOS33 ;
+NET "fd<3>" LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
+NET "fd<4>" LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
+NET "fd<5>" LOC = "W6" | IOSTANDARD = LVCMOS33 ;
+NET "fd<6>" LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
+NET "fd<7>" LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
+NET "fd<8>" LOC = "V21" | IOSTANDARD = LVCMOS33 ;
+NET "fd<9>" LOC = "V22" | IOSTANDARD = LVCMOS33 ;
+NET "fd<10>" LOC = "U20" | IOSTANDARD = LVCMOS33 ;
+NET "fd<11>" LOC = "U22" | IOSTANDARD = LVCMOS33 ;
+NET "fd<12>" LOC = "R20" | IOSTANDARD = LVCMOS33 ;
+NET "fd<13>" LOC = "R22" | IOSTANDARD = LVCMOS33 ;
+NET "fd<14>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
+NET "fd<15>" LOC = "P19" | IOSTANDARD = LVCMOS33 ;
+
+NET "FLAGB" LOC = "F19" | IOSTANDARD = LVCMOS33 ;
+
+NET "SLRD" LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
+NET "SLWR" LOC = "M22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
+
+
+############################################################################
+# VCC AUX VOLTAGE
+############################################################################
+CONFIG VCCAUX=2.5;
+
+############################################################################
+## Memory Controller 3
+## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT
+## Frequency: 200 MHz
+## Time Period: 5000 ps
+## Supported Part Numbers: MT46V32M16BN-5B-IT
+############################################################################
+CONFIG MCB_PERFORMANCE= EXTENDED;
+
+############################################################################
+## I/O TERMINATION
+############################################################################
+#NET "mcb3_dram_dq[*]" IN_TERM = UNTUNED_SPLIT_50;
+#NET "mcb3_dram_dqs" IN_TERM = UNTUNED_SPLIT_50;
+#NET "mcb3_dram_dqs_n" IN_TERM = UNTUNED_SPLIT_50;
+#NET "mcb3_dram_udqs" IN_TERM = UNTUNED_SPLIT_50;
+#NET "mcb3_dram_udqs_n" IN_TERM = UNTUNED_SPLIT_50;
+NET "mcb3_dram_dq[*]" IN_TERM = NONE;
+NET "mcb3_dram_dqs" IN_TERM = NONE;
+NET "mcb3_dram_dqs_n" IN_TERM = NONE;
+NET "mcb3_dram_udqs" IN_TERM = NONE;
+NET "mcb3_dram_udqs_n" IN_TERM = NONE;
+
+#NET "mcb3_dram_dq[*]" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_a[*]" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_ba[*]" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_ck" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_ck_n" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_cke" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_ras_n" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_cas_n" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_we_n" OUT_TERM = UNTUNED_50;
+#NET "mcb3_dram_odt" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_dm" OUT_TERM = UNTUNED_50;
+NET "mcb3_dram_udm" OUT_TERM = UNTUNED_50;
+
+############################################################################
+# I/O STANDARDS
+############################################################################
+NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II;
+NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II;
+NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II;
+NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II;
+NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II;
+NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II;
+NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II;
+#NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II;
+NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II;
+NET "mcb3_rzq" IOSTANDARD = SSTL18_II;
+NET "mcb3_zio" IOSTANDARD = SSTL18_II;
+
+############################################################################
+# MCB 3
+# Pin Location Constraints for Clock, Masks, Address, and Controls
+############################################################################
+NET "mcb3_dram_a[0]" LOC = "M5" ;
+NET "mcb3_dram_a[10]" LOC = "K6" ;
+NET "mcb3_dram_a[11]" LOC = "B1" ;
+NET "mcb3_dram_a[12]" LOC = "J4" ;
+NET "mcb3_dram_a[1]" LOC = "L4" ;
+NET "mcb3_dram_a[2]" LOC = "K3" ;
+NET "mcb3_dram_a[3]" LOC = "M4" ;
+NET "mcb3_dram_a[4]" LOC = "K5" ;
+NET "mcb3_dram_a[5]" LOC = "G3" ;
+NET "mcb3_dram_a[6]" LOC = "G1" ;
+NET "mcb3_dram_a[7]" LOC = "K4" ;
+NET "mcb3_dram_a[8]" LOC = "C3" ;
+NET "mcb3_dram_a[9]" LOC = "C1" ;
+NET "mcb3_dram_ba[0]" LOC = "E3" ;
+NET "mcb3_dram_ba[1]" LOC = "E1" ;
+NET "mcb3_dram_ba[2]" LOC = "D1" ;
+NET "mcb3_dram_cas_n" LOC = "P3" ;
+NET "mcb3_dram_ck" LOC = "F2" ;
+NET "mcb3_dram_ck_n" LOC = "F1" ;
+NET "mcb3_dram_cke" LOC = "J6" ;
+NET "mcb3_dram_dm" LOC = "H1" ;
+NET "mcb3_dram_dq[0]" LOC = "N3" ;
+NET "mcb3_dram_dq[10]" LOC = "R3" ;
+NET "mcb3_dram_dq[11]" LOC = "R1" ;
+NET "mcb3_dram_dq[12]" LOC = "U3" ;
+NET "mcb3_dram_dq[13]" LOC = "U1" ;
+NET "mcb3_dram_dq[14]" LOC = "V2" ;
+NET "mcb3_dram_dq[15]" LOC = "V1" ;
+NET "mcb3_dram_dq[1]" LOC = "N1" ;
+NET "mcb3_dram_dq[2]" LOC = "M2" ;
+NET "mcb3_dram_dq[3]" LOC = "M1" ;
+NET "mcb3_dram_dq[4]" LOC = "J3" ;
+NET "mcb3_dram_dq[5]" LOC = "J1" ;
+NET "mcb3_dram_dq[6]" LOC = "K2" ;
+NET "mcb3_dram_dq[7]" LOC = "K1" ;
+NET "mcb3_dram_dq[8]" LOC = "P2" ;
+NET "mcb3_dram_dq[9]" LOC = "P1" ;
+NET "mcb3_dram_dqs" LOC = "L3" ;
+NET "mcb3_dram_dqs_n" LOC = "L1" ;
+#NET "mcb3_dram_odt" LOC = "M3" ;
+NET "mcb3_dram_ras_n" LOC = "N4" ;
+NET "mcb3_dram_udm" LOC = "H2" ;
+NET "mcb3_dram_udqs" LOC = "T2" ;
+NET "mcb3_dram_udqs_n" LOC = "T1" ;
+NET "mcb3_dram_we_n" LOC = "D2" ;
+
+# The following pins are available for used as RZQ or ZIO pins#
+NET "mcb3_rzq" LOC = "AA2" ;
+NET "mcb3_zio" LOC = "Y2" ;
Index: 1.15a/memtest/fpga/clean.sh
===================================================================
--- 1.15a/memtest/fpga/clean.sh (nonexistent)
+++ 1.15a/memtest/fpga/clean.sh (revision 9)
@@ -0,0 +1,80 @@
+#!/bin/bash
+
+# This files / directories from this directory will not be removed
+# Filenames with spaces or other spuid characters will be ignored
+sourcefiles="*.vhd *.ucf *.sh *.ise *.bit *.bin *.xise"
+subdirs="ipcore_dir"
+
+
+# This sould not be edited.
+list_files() {
+ if [ "$2" != "" ]; then
+ echo "$1"
+ for i in $2; do
+ echo " $i"
+ done
+ fi
+}
+
+rmfiles=""
+rmdirs=""
+keepfiles=""
+keepdirs=""
+allfiles=`ls -A`
+for f in $allfiles; do
+ keep=false
+ for i in $sourcefiles; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ for i in $subdirs; do
+ if [ "$i" == "$f" ]; then
+ keep=true
+ fi
+ done
+ if [ -d "$f" ]; then
+ if $keep; then
+ keepdirs+=" $f"
+ else
+ rmdirs+=" $f"
+ fi
+ fi
+ if [ -f "$f" ]; then
+ if $keep; then
+ keepfiles+=" $f"
+ else
+ rmfiles+=" $f"
+ fi
+ fi
+done
+
+echo
+echo "Directory $PWD:"
+list_files "This directories will NOT be removed:" "$keepdirs"
+list_files "This files will NOT be removed:" "$keepfiles"
+list_files "This directories will be removed:" "$rmdirs"
+list_files "This files will be removed:" "$rmfiles"
+
+if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then
+ c="yes"
+else
+ echo -n 'Confirm this by entering "yes": '
+ read c
+fi
+
+if [ "$c" == "yes" ]; then
+ [ "$rmfiles" != "" ] && rm $rmfiles
+ [ "$rmdirs" != "" ] && rm -r $rmdirs
+
+ for d in $subdirs; do
+ if [ -x "$d/clean.sh" ]; then
+ cd $d
+ ./clean.sh || exit 1
+ cd ..
+ fi
+ done
+
+ exit 0
+fi
+exit 1
1.15a/memtest/fpga/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15a/memtest/fpga/memtest.vhd
===================================================================
--- 1.15a/memtest/fpga/memtest.vhd (nonexistent)
+++ 1.15a/memtest/fpga/memtest.vhd (revision 9)
@@ -0,0 +1,634 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity memtest is
+ port(
+ FXCLK : in std_logic;
+ RESET_IN : in std_logic;
+ IFCLK : in std_logic;
+ PC0 : in std_logic;
+
+ -- FX2 FIFO
+ FD : out std_logic_vector(15 downto 0);
+
+ SLOE : out std_logic;
+ SLRD : out std_logic;
+ SLWR : out std_logic;
+ FIFOADR0 : out std_logic;
+ FIFOADR1 : out std_logic;
+ PKTEND : out std_logic;
+
+ FLAGB : in std_logic;
+
+ -- DDR-SDRAM
+ mcb3_dram_dq : inout std_logic_vector(15 downto 0);
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udqs : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_dram_dqs : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_a : out std_logic_vector(12 downto 0);
+ mcb3_dram_ba : out std_logic_vector(2 downto 0);
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+-- mcb3_dram_odt : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udm : out std_logic;
+ mcb3_dram_ck : out std_logic;
+ mcb3_dram_ck_n : out std_logic
+ );
+end memtest;
+
+
+architecture RTL of memtest is
+
+component mem0
+ generic (
+ C3_P0_MASK_SIZE : integer := 4;
+ C3_P0_DATA_PORT_SIZE : integer := 32;
+ C3_P1_MASK_SIZE : integer := 4;
+ C3_P1_DATA_PORT_SIZE : integer := 32;
+ C3_MEMCLK_PERIOD : integer := 2500;
+ C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
+ C3_RST_ACT_LOW : integer := 0;
+ C3_CALIB_SOFT_IP : string := "FALSE";
+ C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
+ C3_NUM_DQ_PINS : integer := 16;
+ C3_MEM_ADDR_WIDTH : integer := 13;
+ C3_MEM_BANKADDR_WIDTH : integer := 3
+ );
+
+ port (
+ mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+ mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+ mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+ mcb3_dram_cke : out std_logic;
+ mcb3_dram_ras_n : out std_logic;
+ mcb3_dram_cas_n : out std_logic;
+ mcb3_dram_we_n : out std_logic;
+ mcb3_dram_dm : out std_logic;
+ mcb3_dram_udqs : inout std_logic;
+ mcb3_dram_udqs_n : inout std_logic;
+ mcb3_rzq : inout std_logic;
+ mcb3_zio : inout std_logic;
+ mcb3_dram_udm : out std_logic;
+ mcb3_dram_dqs : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+ mcb3_dram_ck : out std_logic;
+ mcb3_dram_ck_n : out std_logic;
+-- mcb3_dram_odt : out std_logic;
+
+ c3_sys_clk : in std_logic;
+ c3_sys_rst_n : in std_logic;
+
+ c3_calib_done : out std_logic;
+ c3_clk0 : out std_logic;
+ c3_rst0 : out std_logic;
+
+ c3_p0_cmd_clk : in std_logic;
+ c3_p0_cmd_en : in std_logic;
+ c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p0_cmd_empty : out std_logic;
+ c3_p0_cmd_full : out std_logic;
+ c3_p0_wr_clk : in std_logic;
+ c3_p0_wr_en : in std_logic;
+ c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+ c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+ c3_p0_wr_full : out std_logic;
+ c3_p0_wr_empty : out std_logic;
+ c3_p0_wr_count : out std_logic_vector(6 downto 0);
+ c3_p0_wr_underrun : out std_logic;
+ c3_p0_wr_error : out std_logic;
+ c3_p0_rd_clk : in std_logic;
+ c3_p0_rd_en : in std_logic;
+ c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+ c3_p0_rd_full : out std_logic;
+ c3_p0_rd_empty : out std_logic;
+ c3_p0_rd_count : out std_logic_vector(6 downto 0);
+ c3_p0_rd_overflow : out std_logic;
+ c3_p0_rd_error : out std_logic;
+
+ c3_p1_cmd_clk : in std_logic;
+ c3_p1_cmd_en : in std_logic;
+ c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p1_cmd_empty : out std_logic;
+ c3_p1_cmd_full : out std_logic;
+ c3_p1_wr_clk : in std_logic;
+ c3_p1_wr_en : in std_logic;
+ c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
+ c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+ c3_p1_wr_full : out std_logic;
+ c3_p1_wr_empty : out std_logic;
+ c3_p1_wr_count : out std_logic_vector(6 downto 0);
+ c3_p1_wr_underrun : out std_logic;
+ c3_p1_wr_error : out std_logic;
+ c3_p1_rd_clk : in std_logic;
+ c3_p1_rd_en : in std_logic;
+ c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+ c3_p1_rd_full : out std_logic;
+ c3_p1_rd_empty : out std_logic;
+ c3_p1_rd_count : out std_logic_vector(6 downto 0);
+ c3_p1_rd_overflow : out std_logic;
+ c3_p1_rd_error : out std_logic;
+
+ c3_p2_cmd_clk : in std_logic;
+ c3_p2_cmd_en : in std_logic;
+ c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p2_cmd_empty : out std_logic;
+ c3_p2_cmd_full : out std_logic;
+ c3_p2_wr_clk : in std_logic;
+ c3_p2_wr_en : in std_logic;
+ c3_p2_wr_mask : in std_logic_vector(3 downto 0);
+ c3_p2_wr_data : in std_logic_vector(31 downto 0);
+ c3_p2_wr_full : out std_logic;
+ c3_p2_wr_empty : out std_logic;
+ c3_p2_wr_count : out std_logic_vector(6 downto 0);
+ c3_p2_wr_underrun : out std_logic;
+ c3_p2_wr_error : out std_logic;
+
+ c3_p3_cmd_clk : in std_logic;
+ c3_p3_cmd_en : in std_logic;
+ c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p3_cmd_empty : out std_logic;
+ c3_p3_cmd_full : out std_logic;
+ c3_p3_rd_clk : in std_logic;
+ c3_p3_rd_en : in std_logic;
+ c3_p3_rd_data : out std_logic_vector(31 downto 0);
+ c3_p3_rd_full : out std_logic;
+ c3_p3_rd_empty : out std_logic;
+ c3_p3_rd_count : out std_logic_vector(6 downto 0);
+ c3_p3_rd_overflow : out std_logic;
+ c3_p3_rd_error : out std_logic;
+
+ c3_p4_cmd_clk : in std_logic;
+ c3_p4_cmd_en : in std_logic;
+ c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p4_cmd_empty : out std_logic;
+ c3_p4_cmd_full : out std_logic;
+ c3_p4_wr_clk : in std_logic;
+ c3_p4_wr_en : in std_logic;
+ c3_p4_wr_mask : in std_logic_vector(3 downto 0);
+ c3_p4_wr_data : in std_logic_vector(31 downto 0);
+ c3_p4_wr_full : out std_logic;
+ c3_p4_wr_empty : out std_logic;
+ c3_p4_wr_count : out std_logic_vector(6 downto 0);
+ c3_p4_wr_underrun : out std_logic;
+ c3_p4_wr_error : out std_logic;
+
+ c3_p5_cmd_clk : in std_logic;
+ c3_p5_cmd_en : in std_logic;
+ c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
+ c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
+ c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
+ c3_p5_cmd_empty : out std_logic;
+ c3_p5_cmd_full : out std_logic;
+ c3_p5_rd_clk : in std_logic;
+ c3_p5_rd_en : in std_logic;
+ c3_p5_rd_data : out std_logic_vector(31 downto 0);
+ c3_p5_rd_full : out std_logic;
+ c3_p5_rd_empty : out std_logic;
+ c3_p5_rd_count : out std_logic_vector(6 downto 0);
+ c3_p5_rd_overflow : out std_logic;
+ c3_p5_rd_error : out std_logic
+);
+end component;
+
+--attribute optimize : string;
+--attribute optimize of counters:entity is "off";
+
+signal fxclk_buf : std_logic;
+signal CLK : std_logic;
+signal RESET0 : std_logic; -- released after dcm0 is ready
+signal RESET : std_logic; -- released after MCB is ready
+
+signal DCM0_LOCKED : std_logic;
+--signal DCM0_CLK_VALID : std_logic;
+
+----------------------------
+-- test pattern generator --
+----------------------------
+signal GEN_CNT : std_logic_vector(29 downto 0);
+signal GEN_PATTERN : std_logic_vector(29 downto 0);
+
+signal FIFO_WORD : std_logic;
+
+-----------------------
+-- memory controller --
+-----------------------
+signal MEM_CLK : std_logic;
+signal C3_CALIB_DONE : std_logic;
+signal C3_RST0 : std_logic;
+
+---------------
+-- DRAM FIFO --
+---------------
+signal WR_CLK : std_logic;
+signal WR_CMD_EN : std_logic_vector(2 downto 0);
+type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
+signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
+signal WR_ADDR : std_logic_vector(18 downto 0); -- in 256 bytes burst blocks
+signal WR_EN : std_logic_vector(2 downto 0);
+signal WR_EN_TMP : std_logic_vector(2 downto 0);
+signal WR_DATA : std_logic_vector(31 downto 0);
+signal WR_EMPTY : std_logic_vector(2 downto 0);
+signal WR_UNDERRUN : std_logic_vector(2 downto 0);
+signal WR_ERROR : std_logic_vector(2 downto 0);
+type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
+signal WR_COUNT : WR_COUNT_ARRAY;
+signal WR_PORT : std_logic_vector(1 downto 0);
+
+signal RD_CLK : std_logic;
+signal RD_CMD_EN : std_logic_vector(2 downto 0);
+type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
+signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
+signal RD_ADDR : std_logic_vector(18 downto 0); -- in 256 bytes burst blocks
+signal RD_EN : std_logic_vector(2 downto 0);
+type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
+signal RD_DATA : RD_DATA_ARRAY;
+signal RD_EMPTY : std_logic_vector(2 downto 0);
+signal RD_OVERFLOW : std_logic_vector(2 downto 0);
+signal RD_ERROR : std_logic_vector(2 downto 0);
+signal RD_PORT : std_logic_vector(1 downto 0);
+type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
+signal RD_COUNT : RD_COUNT_ARRAY;
+
+signal FD_TMP : std_logic_vector(15 downto 0);
+
+signal RD_ADDR2 : std_logic_vector(18 downto 0); -- 256 bytes burst block currently beeing read
+signal RD_ADDR2_BAK1 : std_logic_vector(18 downto 0); -- backup for synchronization
+signal RD_ADDR2_BAK2 : std_logic_vector(18 downto 0); -- backup for synchronization
+signal WR_ADDR2 : std_logic_vector(18 downto 0); -- 256 bytes burst block currently beeing written
+signal WR_ADDR2_BAK1 : std_logic_vector(18 downto 0); -- backup for synchronization
+signal WR_ADDR2_BAK2 : std_logic_vector(18 downto 0); -- backup for synchronization
+
+signal RD_STOP : std_logic;
+
+begin
+
+ clkin_buf : IBUFG
+ port map (
+ O => FXCLK_BUF,
+ I => FXCLK
+ );
+
+ dcm0 : DCM_CLKGEN
+ generic map (
+ CLKFX_DIVIDE => 3,
+-- CLKFX_MULTIPLY => 33,
+ CLKFX_MULTIPLY => 21,
+ CLKFXDV_DIVIDE => 8,
+ SPREAD_SPECTRUM => "NONE",
+ STARTUP_WAIT => FALSE,
+ CLKIN_PERIOD => 20.83333,
+ CLKFX_MD_MAX => 0.000
+ )
+ port map (
+ CLKIN => FXCLK_BUF,
+ CLKFX => MEM_CLK,
+ CLKFX180 => open,
+ CLKFXDV => CLK,
+ LOCKED => DCM0_LOCKED,
+ PROGDONE => open,
+ STATUS => open,
+ FREEZEDCM => '0',
+ PROGCLK => '0',
+ PROGDATA => '0',
+ PROGEN => '0',
+ RST => '0'
+ );
+
+ inst_mem0 : mem0 port map (
+ mcb3_dram_dq => mcb3_dram_dq,
+ mcb3_dram_a => mcb3_dram_a,
+ mcb3_dram_ba => mcb3_dram_ba,
+ mcb3_dram_ras_n => mcb3_dram_ras_n,
+ mcb3_dram_cas_n => mcb3_dram_cas_n,
+ mcb3_dram_we_n => mcb3_dram_we_n,
+-- mcb3_dram_odt => mcb3_dram_odt,
+ mcb3_dram_cke => mcb3_dram_cke,
+ mcb3_dram_ck => mcb3_dram_ck,
+ mcb3_dram_ck_n => mcb3_dram_ck_n,
+ mcb3_dram_dqs => mcb3_dram_dqs,
+ mcb3_dram_dqs_n => mcb3_dram_dqs_n,
+ mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
+ mcb3_dram_udqs_n=> mcb3_dram_udqs_n, -- for X16 parts
+ mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
+ mcb3_dram_dm => mcb3_dram_dm,
+ mcb3_rzq => mcb3_rzq,
+ mcb3_zio => mcb3_zio,
+
+ c3_sys_clk => MEM_CLK,
+ c3_sys_rst_n => RESET0,
+
+ c3_clk0 => open,
+ c3_rst0 => C3_RST0,
+ c3_calib_done => C3_CALIB_DONE,
+
+ c3_p0_cmd_clk => WR_CLK,
+ c3_p0_cmd_en => WR_CMD_EN(0),
+ c3_p0_cmd_instr => "000",
+ c3_p0_cmd_bl => ( others => '1' ),
+ c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
+ c3_p0_cmd_empty => open,
+ c3_p0_cmd_full => open,
+ c3_p0_wr_clk => WR_CLK,
+ c3_p0_wr_en => WR_EN(0),
+ c3_p0_wr_mask => ( others => '0' ),
+ c3_p0_wr_data => WR_DATA,
+ c3_p0_wr_full => open,
+ c3_p0_wr_empty => WR_EMPTY(0),
+ c3_p0_wr_count => open,
+ c3_p0_wr_underrun => WR_UNDERRUN(0),
+ c3_p0_wr_error => WR_ERROR(0),
+ c3_p0_rd_clk => WR_CLK,
+ c3_p0_rd_en => '0',
+ c3_p0_rd_data => open,
+ c3_p0_rd_full => open,
+ c3_p0_rd_empty => open,
+ c3_p0_rd_count => open,
+ c3_p0_rd_overflow => open,
+ c3_p0_rd_error => open,
+
+ c3_p2_cmd_clk => WR_CLK,
+ c3_p2_cmd_en => WR_CMD_EN(1),
+ c3_p2_cmd_instr => "000",
+ c3_p2_cmd_bl => ( others => '1' ),
+ c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
+ c3_p2_cmd_empty => open,
+ c3_p2_cmd_full => open,
+ c3_p2_wr_clk => WR_CLK,
+ c3_p2_wr_en => WR_EN(1),
+ c3_p2_wr_mask => ( others => '0' ),
+ c3_p2_wr_data => WR_DATA,
+ c3_p2_wr_full => open,
+ c3_p2_wr_empty => WR_EMPTY(1),
+ c3_p2_wr_count => open,
+ c3_p2_wr_underrun => WR_UNDERRUN(1),
+ c3_p2_wr_error => WR_ERROR(1),
+
+ c3_p4_cmd_clk => WR_CLK,
+ c3_p4_cmd_en => WR_CMD_EN(2),
+ c3_p4_cmd_instr => "000",
+ c3_p4_cmd_bl => ( others => '1' ),
+ c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
+ c3_p4_cmd_empty => open,
+ c3_p4_cmd_full => open,
+ c3_p4_wr_clk => WR_CLK,
+ c3_p4_wr_en => WR_EN(2),
+ c3_p4_wr_mask => ( others => '0' ),
+ c3_p4_wr_data => WR_DATA,
+ c3_p4_wr_full => open,
+ c3_p4_wr_empty => WR_EMPTY(2),
+ c3_p4_wr_count => open,
+ c3_p4_wr_underrun => WR_UNDERRUN(2),
+ c3_p4_wr_error => WR_ERROR(2),
+
+ c3_p1_cmd_clk => RD_CLK,
+ c3_p1_cmd_en => RD_CMD_EN(0),
+ c3_p1_cmd_instr => "001",
+ c3_p1_cmd_bl => ( others => '1' ),
+ c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
+ c3_p1_cmd_empty => open,
+ c3_p1_cmd_full => open,
+ c3_p1_wr_clk => RD_CLK,
+ c3_p1_wr_en => '0',
+ c3_p1_wr_mask => ( others => '0' ),
+ c3_p1_wr_data => ( others => '0' ),
+ c3_p1_wr_full => open,
+ c3_p1_wr_empty => open,
+ c3_p1_wr_count => open,
+ c3_p1_wr_underrun => open,
+ c3_p1_wr_error => open,
+ c3_p1_rd_clk => RD_CLK,
+ c3_p1_rd_en => RD_EN(0),
+ c3_p1_rd_data => RD_DATA(0),
+ c3_p1_rd_full => open,
+ c3_p1_rd_empty => RD_EMPTY(0),
+ c3_p1_rd_count => open,
+ c3_p1_rd_overflow => RD_OVERFLOW(0),
+ c3_p1_rd_error => RD_ERROR(0),
+
+ c3_p3_cmd_clk => RD_CLK,
+ c3_p3_cmd_en => RD_CMD_EN(1),
+ c3_p3_cmd_instr => "001",
+ c3_p3_cmd_bl => ( others => '1' ),
+ c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
+ c3_p3_cmd_empty => open,
+ c3_p3_cmd_full => open,
+ c3_p3_rd_clk => RD_CLK,
+ c3_p3_rd_en => RD_EN(1),
+ c3_p3_rd_data => RD_DATA(1),
+ c3_p3_rd_full => open,
+ c3_p3_rd_empty => RD_EMPTY(1),
+ c3_p3_rd_count => open,
+ c3_p3_rd_overflow => RD_OVERFLOW(1),
+ c3_p3_rd_error => RD_ERROR(1),
+
+ c3_p5_cmd_clk => RD_CLK,
+ c3_p5_cmd_en => RD_CMD_EN(2),
+ c3_p5_cmd_instr => "001",
+ c3_p5_cmd_bl => ( others => '1' ),
+ c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
+ c3_p5_cmd_empty => open,
+ c3_p5_cmd_full => open,
+ c3_p5_rd_clk => RD_CLK,
+ c3_p5_rd_en => RD_EN(2),
+ c3_p5_rd_data => RD_DATA(2),
+ c3_p5_rd_full => open,
+ c3_p5_rd_empty => RD_EMPTY(2),
+ c3_p5_rd_count => open,
+ c3_p5_rd_overflow => RD_OVERFLOW(2),
+ c3_p5_rd_error => RD_ERROR(2)
+);
+
+ SLOE <= '1';
+ SLRD <= '1';
+ FIFOADR0 <= '0';
+ FIFOADR1 <= '0';
+ PKTEND <= '1';
+
+ WR_CLK <= CLK;
+ RD_CLK <= IFCLK;
+
+
+-- DCM0_CLK_VALID <= ( DCM0_LOCKED and ( not status_internal(2) ) );
+-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
+ RESET0 <= RESET_IN or (not DCM0_LOCKED);
+ RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
+
+
+ dpCLK: process (CLK, RESET)
+ begin
+-- reset
+ if RESET = '1'
+ then
+ GEN_CNT <= ( others => '0' );
+ GEN_PATTERN <= "100101010101010101010101010101";
+
+ WR_CMD_EN <= ( others => '0' );
+ WR_CMD_ADDR(0) <= ( others => '0' );
+ WR_CMD_ADDR(1) <= ( others => '0' );
+ WR_CMD_ADDR(2) <= ( others => '0' );
+ WR_ADDR <= conv_std_logic_vector(3,19);
+ WR_EN <= ( others => '0' );
+ WR_COUNT(0) <= ( others => '0' );
+ WR_COUNT(1) <= ( others => '0' );
+ WR_COUNT(2) <= ( others => '0' );
+ WR_PORT <= ( others => '0' );
+
+ WR_ADDR2 <= ( others => '0' );
+ RD_ADDR2_BAK1 <= ( others => '0' );
+ RD_ADDR2_BAK2 <= ( others => '0' );
+
+-- CLK
+ elsif CLK'event and CLK = '1'
+ then
+ WR_CMD_EN <= ( others => '0' );
+ WR_EN <= ( others => '0' );
+ WR_CMD_ADDR(conv_integer(WR_PORT))(26 downto 8) <= WR_ADDR;
+
+ if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
+ then
+ -- FF flag = 1
+ if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
+ then
+ WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
+ WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
+ if WR_PORT = "10"
+ then
+ WR_PORT <= "00";
+ else
+ WR_PORT <= WR_PORT + 1;
+ end if;
+ WR_ADDR <= WR_ADDR + 1;
+ WR_ADDR2 <= WR_ADDR2 + 1;
+ end if;
+ elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
+ then
+ -- FF flag = 1
+ else
+ WR_EN(conv_integer(WR_PORT)) <= '1';
+ WR_DATA(31) <= '1';
+ WR_DATA(15) <= '0';
+ if PC0 = '1'
+ then
+ WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
+ WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
+ else
+ WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
+ WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
+ end if;
+ GEN_CNT <= GEN_CNT + 1;
+ GEN_PATTERN(29) <= GEN_PATTERN(0);
+ GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
+-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
+-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
+-- then
+-- else
+ WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
+-- end if;
+ end if;
+
+ RD_ADDR2_BAK1 <= RD_ADDR2;
+ RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
+
+ end if;
+ end process dpCLK;
+
+
+ dpIFCLK: process (IFCLK, RESET)
+ begin
+-- reset
+ if RESET = '1'
+ then
+ FIFO_WORD <= '0';
+ SLWR <= '1';
+
+ RD_CMD_EN <= ( others => '0' );
+ RD_CMD_ADDR(0) <= ( others => '0' );
+ RD_CMD_ADDR(1) <= ( others => '0' );
+ RD_CMD_ADDR(2) <= ( others => '0' );
+ RD_ADDR <= conv_std_logic_vector(3,19);
+ RD_EN <= ( others => '0' );
+ RD_COUNT(0) <= conv_std_logic_vector(64,7);
+ RD_COUNT(1) <= conv_std_logic_vector(64,7);
+ RD_COUNT(2) <= conv_std_logic_vector(64,7);
+ RD_PORT <= ( others => '0' );
+
+ RD_ADDR2 <= ( others => '0' );
+ WR_ADDR2_BAK1 <= ( others => '0' );
+ WR_ADDR2_BAK2 <= ( others => '0' );
+
+ RD_STOP <= '1';
+
+-- IFCLK
+ elsif IFCLK'event and IFCLK = '1'
+ then
+
+ RD_CMD_EN <= ( others => '0' );
+ RD_CMD_ADDR(conv_integer(RD_PORT))(26 downto 8) <= RD_ADDR;
+ RD_EN(conv_integer(RD_PORT)) <= '0';
+
+ if FLAGB = '1'
+ then
+ if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
+ then
+ SLWR <= '1';
+ if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
+ then
+ RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
+ RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
+ if RD_PORT = "10"
+ then
+ RD_PORT <= "00";
+ else
+ RD_PORT <= RD_PORT + 1;
+ end if;
+ RD_ADDR <= RD_ADDR + 1;
+ RD_ADDR2 <= RD_ADDR2 + 1;
+ end if;
+ else
+ SLWR <= '0';
+ if FIFO_WORD = '0'
+ then
+ FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
+ FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
+ RD_EN(conv_integer(RD_PORT)) <= '1';
+ else
+ FD(15 downto 0) <= FD_TMP;
+ RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
+ end if;
+ FIFO_WORD <= not FIFO_WORD;
+ end if;
+ end if;
+
+ WR_ADDR2_BAK1 <= WR_ADDR2;
+ WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
+
+ if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
+ then
+ RD_STOP <= '0';
+ end if;
+
+ end if;
+ end process dpIFCLK;
+
+end RTL;
+
Index: 1.15a/memtest/Makefile
===================================================================
--- 1.15a/memtest/Makefile (nonexistent)
+++ 1.15a/memtest/Makefile (revision 9)
@@ -0,0 +1,27 @@
+#########################
+# configuration section #
+#########################
+
+# Defines the location of the EZ-USB SDK
+ZTEXPREFIX=../../../..
+
+# The name of the jar archive
+JARTARGET=MemTest.jar
+# Java Classes that have to be build
+CLASSTARGETS=MemTest.class
+# Extra dependencies for Java Classes
+CLASSEXTRADEPS=
+
+# ihx files (firmware ROM files) that have to be build
+IHXTARGETS=memtest.ihx
+# Extra Dependencies for ihx files
+IHXEXTRADEPS=
+
+# Extra files that should be included into th jar archive
+EXTRAJARFILES=memtest.ihx fpga/memtest.bit
+
+################################
+# DO NOT CHANAGE THE FOLLOWING #
+################################
+# includes the main Makefile
+include $(ZTEXPREFIX)/Makefile.mk
Index: 1.15a/memtest/Readme
===================================================================
--- 1.15a/memtest/Readme (nonexistent)
+++ 1.15a/memtest/Readme (revision 9)
@@ -0,0 +1,12 @@
+memtest
+-------
+
+This example implements a FIFO using DDR2 SDRAM.
+
+The input data is generated by a test pattern generator and is written
+continuously to the SDRAM FIFO. This FIFO is read out continuously and
+the data is written to the EZ-USB using the slave FIFO interface of the
+EZ-USB. The host PC's reads out this data via USB and verifies it.
+
+Use this example as starting point for high speed (uninterrupted)
+data acquisition applications.
Index: 1.15a/memtest/MemTest.java
===================================================================
--- 1.15a/memtest/MemTest.java (nonexistent)
+++ 1.15a/memtest/MemTest.java (revision 9)
@@ -0,0 +1,283 @@
+/*!
+ memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b
+ Copyright (C) 2009-2011 ZTEX GmbH.
+ http://www.ztex.de
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License version 3 as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see http://www.gnu.org/licenses/.
+!*/
+
+import java.io.*;
+import java.util.*;
+
+import ch.ntb.usb.*;
+
+import ztex.*;
+
+// *****************************************************************************
+// ******* ParameterException **************************************************
+// *****************************************************************************
+// Exception the prints a help message
+class ParameterException extends Exception {
+ public final static String helpMsg = new String (
+ "Parameters:\n"+
+ " -d Device Number (default: 0)\n" +
+ " -c Counter test patttern\n" +
+ " -f Force uploads\n" +
+ " -p Print bus info\n" +
+ " -w Enable certain workarounds\n"+
+ " -h This help" );
+
+ public ParameterException (String msg) {
+ super( msg + "\n" + helpMsg );
+ }
+}
+
+// *****************************************************************************
+// ******* USBReader ***********************************************************
+// *****************************************************************************
+class UsbReader extends Thread {
+ private final int bufNum = 8;
+ public final int bufSize = 512*1024;
+ public byte[][] buf = new byte[bufNum][];
+ public int[] bufBytes = new int[bufNum];
+ private int readCount = -1;
+ private int getCount = -1;
+ public boolean terminate = false;
+ private Ztex1v1 ztex;
+
+ public UsbReader ( Ztex1v1 p_ztex ) {
+ super ();
+ ztex = p_ztex;
+ for (int i=0; i= readCount) {
+ try {
+ sleep(1);
+ }
+ catch ( InterruptedException e) {
+ }
+ }
+ return getCount % bufNum;
+ }
+
+
+ public void run() {
+ setPriority(MAX_PRIORITY);
+
+// claim interface 0
+ try {
+ ztex.trySetConfiguration ( 1 );
+ ztex.claimInterface ( 0 );
+ }
+ catch ( Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ System.exit(2);
+ }
+
+
+// reader loop
+ while ( !terminate ) {
+ readCount += 1;
+
+ while ( readCount - bufNum >= getCount ) {
+ try {
+ sleep(1);
+ }
+ catch ( InterruptedException e) {
+ }
+ }
+
+ int i = readCount % bufNum;
+ bufBytes[i] = LibusbJava.usb_bulk_read(ztex.handle(), 0x82, buf[i], bufSize, 1000);
+// System.out.println("Buffer " + i +": read " + bufBytes[i] + " bytes");
+ }
+
+// release interface 0
+ ztex.releaseInterface( 0 );
+
+ }
+}
+
+// *****************************************************************************
+// ******* Test0 ***************************************************************
+// *****************************************************************************
+class MemTest extends Ztex1v1 {
+
+// ******* MemTest **************************************************************
+// constructor
+ public MemTest ( ZtexDevice1 pDev ) throws UsbException {
+ super ( pDev );
+ }
+
+// ******* main ****************************************************************
+ public static void main (String args[]) {
+
+ int devNum = 0;
+ boolean force = false;
+ boolean workarounds = false;
+ boolean genMode = true;
+
+ try {
+// init USB stuff
+ LibusbJava.usb_init();
+
+// scan the USB bus
+ ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1);
+ if ( bus.numberOfDevices() <= 0) {
+ System.err.println("No devices found");
+ System.exit(0);
+ }
+
+// scan the command line arguments
+ for (int i=0; i=args.length) throw new Exception();
+ devNum = Integer.parseInt( args[i] );
+ }
+ catch (Exception e) {
+ throw new ParameterException("Device number expected after -d");
+ }
+ }
+ else if ( args[i].equals("-f") ) {
+ force = true;
+ }
+ else if ( args[i].equals("-c") ) {
+ genMode = false;
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-p") ) {
+ bus.printBus(System.out);
+ System.exit(0);
+ }
+ else if ( args[i].equals("-w") ) {
+ workarounds = true;
+ }
+ else if ( args[i].equals("-h") ) {
+ System.err.println(ParameterException.helpMsg);
+ System.exit(0);
+ }
+ else throw new ParameterException("Invalid Parameter: "+args[i]);
+ }
+
+
+// create the main class
+ MemTest ztex = new MemTest ( bus.device(devNum) );
+ ztex.certainWorkarounds = workarounds;
+
+// upload the firmware if necessary
+ if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("memtest example for UFM 1.15") ) {
+ System.out.println("Firmware upload time: " + ztex.uploadFirmware( "memtest.ihx", force ) + " ms");
+ force = true;
+ }
+
+ ztex.vendorCommand (0x60, "Set test pattern", (genMode ? 1 : 0), 0);
+
+// upload the bitstream if necessary
+ if ( force || ! ztex.getFpgaConfiguration() ) {
+ System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/memtest.bit" , force ) + " ms");
+ }
+
+// read the traffic
+ UsbReader reader = new UsbReader( ztex );
+ reader.start();
+
+// test
+ int vcurrent = -1;
+ int prevErrors = 0;
+
+ for (int i=0; i<1921; i++) {
+ int j = reader.getBuffer();
+ int bb = reader.bufBytes[j];
+ byte[] b = reader.buf[j];
+ int current = vcurrent+1;
+ int lastwi = 1;
+ int aerrors = 0;
+ int ferrors = 0;
+ int errors = 0;
+
+ if ( bb != reader.bufSize ) {
+ System.out.println("Unable to read data");
+ }
+
+ for (int k=1; k> 1) | (1 << 29);
+ else
+ vcurrent = (vcurrent >> 1);
+ }
+ else {
+ vcurrent += 1;
+ }
+
+ if ( lastwi == 1 ) {
+ aerrors+=1;
+ System.out.println("Alignment error: 1 at " + i + ":" + (k-1) );
+ }
+ else if ( vcurrent != current ) {
+ if ( (i != 0) && ( k != 3) ) {
+ System.out.println("Error: 0b" + Integer.toBinaryString(vcurrent) + " expected at " + i + ":" + (k-3) + " but " );
+ System.out.println(" 0b" + Integer.toBinaryString(current) + " found");
+ errors+=1;
+ prevErrors+=1;
+ }
+ vcurrent = current;
+ }
+ else {
+// if ( prevErrors > 0 ) System.out.println(" 0b" + Integer.toBinaryString(current) );
+ if ( prevErrors == 1 )
+ ferrors +=1;
+ prevErrors = 0;
+ }
+
+ lastwi = 1;
+// System.out.println(current);
+ }
+// System.out.println( (((b[k] & 0x7f) << 8) | (b[k-1] & 0xff)) + " " + Integer.toBinaryString(b[k] & 255) + " " + Integer.toBinaryString(b[k-1] & 255));
+ }
+ System.out.print("Buffer " + i + ": " + (errors-ferrors) + " errors, " + ferrors + " FIFO errors, " + aerrors + " alignment errors \r");
+ if ( errors != 0 | aerrors != 0 ) System.out.println();
+ }
+ System.out.println();
+
+// stop the reader
+ reader.terminate=true;
+
+ }
+ catch (Exception e) {
+ System.out.println("Error: "+e.getLocalizedMessage() );
+ }
+ }
+
+}
Index: 1.15b/mmio/UCEcho.java
===================================================================
--- 1.15b/mmio/UCEcho.java (revision 8)
+++ 1.15b/mmio/UCEcho.java (revision 9)
@@ -133,6 +133,7 @@
// upload the firmware if necessary
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 1.15") ) {
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms");
+ force = true;
}
// upload the bitstream if necessary
/1.15b/mmio/ucecho.c
32,7 → 32,7
// this product string is also used for identification by the host software |
#define[PRODUCT_STRING]["memeory mapping example for UFM 1.15"] |
|
xdata BYTE run; |
__xdata BYTE run; |
|
#define[PRE_FPGA_RESET][PRE_FPGA_RESET |
run = 0; |
/1.15b/intraffic/InTraffic.java
186,6 → 186,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("intraffic example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "intraffic.ihx", force ) + " ms"); |
force = true; |
} |
|
// upload the bitstream if necessary |
/1.15b/ucecho/UCEcho.java
133,6 → 133,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms"); |
force = true; |
} |
|
// upload the bitstream if necessary |
/1.15b/ucecho/ucecho.c
32,7 → 32,7
// enables high speed FPGA configuration via EP4 |
ENABLE_HS_FPGA_CONF(4); |
|
xdata BYTE run; |
__xdata BYTE run; |
|
#define[PRE_FPGA_RESET][PRE_FPGA_RESET |
run = 0; |
/1.15b/lightshow/avr/lightshow.ihx
1,45 → 1,44
:100000000C94FA000C941B010C941B010C941B0122 |
:100010000C941B010C941B010C941B010C941B01F0 |
:100020000C941B010C941B010C941B010C941B01E0 |
:100030000C941B010C941B010C941B010C941B01D0 |
:100040000C941B010C941B010C941B010C941B01C0 |
:100050000C941B010C941B010C941B010C941B01B0 |
:100060000C941B010C941B010C941B010C941B01A0 |
:100070000C941B010C941B010C941B010C941B0190 |
:100080000C941B010C941B010C941B010C941B0180 |
:100090000C941B010C941B010C941B010C941B0170 |
:1000A0000C941B010C941B010C941B010C941B0160 |
:1000B0000C941B010C941B010C941B010C941B0150 |
:1000C0000C941B010C941B010C941B010C941B0140 |
:1000D0000C941B010C941B010C941B010C941B0130 |
:1000E0000C941B010C941B010C941B010C941B0120 |
:1000F0000C941B010C941B010C941B010C941B0110 |
:100100000C941B010C941B010C941B010C941B01FF |
:100110000C941B010C941B010C941B010C941B01EF |
:100120000C941B010C941B010C941B010C941B01DF |
:100130000C941B010C941B010C941B010C941B01CF |
:100140000C941B010C941B010C941B010C941B01BF |
:100150000C941B010C941B010C941B010C941B01AF |
:100160000C941B010C941B010C941B010C941B019F |
:100170000C941B010C941B010C941B010C941B018F |
:100180000C941B010C941B010C941B010C941B017F |
:100190000C941B010C941B010C941B010C941B016F |
:1001A0000C941B010C941B010C941B010C941B015F |
:1001B0000C941B010C941B010C941B010C941B014F |
:1001C0000C941B010C941B010C941B010C941B013F |
:1001D0000C941B010C941B010C941B010C941B012F |
:1001E0000C941B010C941B010C941B010C941B011F |
:1001F0000C941B0111241FBECFEFDFE3DEBFCDBF88 |
:1002000000E00CBF10E2A0E0B0E2E2EBF2E000E0C0 |
:100210000BBF02C007900D92A030B107D9F710E2D2 |
:10022000A0E0B0E201C01D92A030B107E1F70E944A |
:100230001D010C9457010C94000088ED77E084BFF9 |
:10024000709350008091510087708730D9F788ED06 |
:1002500071E084BF7093600084BF7093680084BFB6 |
:100260007093400088ED71E084BF7093960082E047 |
:10027000E0EBF0E0848380E8809360061092000752 |
:100280001092E006809160068F60809360068FEF89 |
:100290008093A006A0E6B6E0E0EAF6E080910807C9 |
:1002A00014968C9314978091E8068483F7CFF89482 |
:0202B000FFCF7E |
:100000000C94FA000C9418010C9418010C9418012B |
:100010000C9418010C9418010C9418010C941801FC |
:100020000C9418010C9418010C9418010C941801EC |
:100030000C9418010C9418010C9418010C941801DC |
:100040000C9418010C9418010C9418010C941801CC |
:100050000C9418010C9418010C9418010C941801BC |
:100060000C9418010C9418010C9418010C941801AC |
:100070000C9418010C9418010C9418010C9418019C |
:100080000C9418010C9418010C9418010C9418018C |
:100090000C9418010C9418010C9418010C9418017C |
:1000A0000C9418010C9418010C9418010C9418016C |
:1000B0000C9418010C9418010C9418010C9418015C |
:1000C0000C9418010C9418010C9418010C9418014C |
:1000D0000C9418010C9418010C9418010C9418013C |
:1000E0000C9418010C9418010C9418010C9418012C |
:1000F0000C9418010C9418010C9418010C9418011C |
:100100000C9418010C9418010C9418010C9418010B |
:100110000C9418010C9418010C9418010C941801FB |
:100120000C9418010C9418010C9418010C941801EB |
:100130000C9418010C9418010C9418010C941801DB |
:100140000C9418010C9418010C9418010C941801CB |
:100150000C9418010C9418010C9418010C941801BB |
:100160000C9418010C9418010C9418010C941801AB |
:100170000C9418010C9418010C9418010C9418019B |
:100180000C9418010C9418010C9418010C9418018B |
:100190000C9418010C9418010C9418010C9418017B |
:1001A0000C9418010C9418010C9418010C9418016B |
:1001B0000C9418010C9418010C9418010C9418015B |
:1001C0000C9418010C9418010C9418010C9418014B |
:1001D0000C9418010C9418010C9418010C9418013B |
:1001E0000C9418010C9418010C9418010C9418012B |
:1001F0000C94180111241FBECFEFDFE3DEBFCDBF8B |
:1002000000E00CBF18BE19BE1ABE1BBE10E2A0E073 |
:10021000B0E2ECEAF2E000E00BBF02C007900D9202 |
:10022000A030B107D9F71BBE0E941A010C945401EB |
:100230000C94000088ED77E084BF709350008091AB |
:10024000510087708730D9F788ED71E084BF7093D3 |
:10025000600084BF7093680084BF7093400088ED95 |
:1002600071E084BF7093960082E0E0EBF0E084835D |
:1002700080E880936006109200071092E00680915B |
:1002800060068F60809360068FEF8093A006A0E6E3 |
:10029000B6E0E0EAF6E08091080714968C93149794 |
:0C02A0008091E8068483F7CFF894FFCF2C |
:00000001FF |
/1.15b/lightshow/lightshow.c
19,7 → 19,7
#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros |
#include[ztex-utils.h] // include basic functions |
|
// Endpoint 2 is used to high spee FPGA configuration |
// Endpoint 2 is used to high speed FPGA configuration |
EP_CONFIG(2,0,BULK,OUT,512,4); |
|
// select ZTEX USB FPGA Module 1.15 + Experimental Board 1.10 as target |
/1.15b/lightshow/Makefile
7,11 → 7,11
JARTARGET=Lightshow.jar |
CLASSTARGETS=Lightshow.class |
CLASSEXTRADEPS= |
#CLASSEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/java/ztex/*.java) |
#CLASSEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/java/ztex/*.java) |
|
IHXTARGETS=lightshow.ihx |
IHXEXTRADEPS= |
#IHXEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/include/*.h) |
#IHXEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/include/*.h) |
EXTRAJARFILES=lightshow.ihx avr/lightshow.ihx fpga/lightshow.bit |
|
################################ |
/1.15b/Makefile
1,6 → 1,6
DIRS=ucecho intraffic memtest lightshow mmio |
|
.PHONY: default all clean distclean |
.PHONY: default all clean distclean avr avrclean avrdistclean |
|
default: |
@echo "This makefile is intended to clean up the project or to build all examples in this subdirectory" |
7,10 → 7,20
@echo "Usage: make all | clean | distclean" |
|
all: |
for i in $(DIRS); do make -C $$i all; done |
set -e; for i in $(DIRS); do make -C $$i all; done |
|
clean: |
for i in $(DIRS); do make -C $$i clean; done |
set -e; for i in $(DIRS); do make -C $$i clean; done |
|
distclean: clean |
for i in $(DIRS); do make -C $$i distclean; done |
distclean: |
set -e; for i in $(DIRS); do make -C $$i distclean; done |
|
avr: |
set -e; for i in $(DIRS); do make -C $$i avr; done |
|
avrclean: |
set -e; for i in $(DIRS); do make -C $$i avrclean; done |
|
avrdistclean: |
set -e; for i in $(DIRS); do make -C $$i avrdistclean; done |
|
/1.15b/memtest/MemTest.java
187,6 → 187,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("memtest example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "memtest.ihx", force ) + " ms"); |
force = true; |
} |
|
ztex.vendorCommand (0x60, "Set test pattern", (genMode ? 1 : 0), 0); |
/1.15d/mmio/UCEcho.java
133,6 → 133,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms"); |
force = true; |
} |
|
// upload the bitstream if necessary |
/1.15d/mmio/ucecho.c
25,6 → 25,7
|
// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration) |
IDENTITY_UFM_1_15(10.13.0.0,0); |
ENABLE_UFM_1_15X_DETECTION; // avoids some warnings |
|
// enables high speed FPGA configuration, (re)use EP 4 |
ENABLE_HS_FPGA_CONF(4); |
32,7 → 33,7
// this product string is also used for identification by the host software |
#define[PRODUCT_STRING]["memeory mapping example for UFM 1.15"] |
|
xdata BYTE run; |
__xdata BYTE run; |
|
#define[PRE_FPGA_RESET][PRE_FPGA_RESET |
run = 0; |
/1.15d/intraffic/InTraffic.java
186,6 → 186,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("intraffic example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "intraffic.ihx", force ) + " ms"); |
force = true; |
} |
|
// upload the bitstream if necessary |
/1.15d/intraffic/intraffic.c
27,6 → 27,7
|
// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration) |
IDENTITY_UFM_1_15(10.13.0.0,0); |
ENABLE_UFM_1_15X_DETECTION; // avoids some warnings |
|
// this product string is also used for identification by the host software |
#define[PRODUCT_STRING]["intraffic example for UFM 1.15"] |
/1.15d/intraffic/intraffic.sh
1,4 → 1,4
#make -C ../../../java distclean all || exit |
#make distclean all || exit |
make distclean all || exit |
#make || exit |
java -cp InTraffic.jar InTraffic $@ |
/1.15d/ucecho/UCEcho.java
133,6 → 133,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms"); |
force = true; |
} |
|
// upload the bitstream if necessary |
/1.15d/ucecho/ucecho.c
25,6 → 25,7
|
// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration) |
IDENTITY_UFM_1_15(10.13.0.0,0); |
ENABLE_UFM_1_15X_DETECTION; // avoids some warnings |
|
// this product string is also used for identification by the host software |
#define[PRODUCT_STRING]["ucecho example for UFM 1.15"] |
32,7 → 33,7
// enables high speed FPGA configuration via EP4 |
ENABLE_HS_FPGA_CONF(4); |
|
xdata BYTE run; |
__xdata BYTE run; |
|
#define[PRE_FPGA_RESET][PRE_FPGA_RESET |
run = 0; |
/1.15d/lightshow/avr/lightshow.ihx
1,45 → 1,44
:100000000C94FA000C941B010C941B010C941B0122 |
:100010000C941B010C941B010C941B010C941B01F0 |
:100020000C941B010C941B010C941B010C941B01E0 |
:100030000C941B010C941B010C941B010C941B01D0 |
:100040000C941B010C941B010C941B010C941B01C0 |
:100050000C941B010C941B010C941B010C941B01B0 |
:100060000C941B010C941B010C941B010C941B01A0 |
:100070000C941B010C941B010C941B010C941B0190 |
:100080000C941B010C941B010C941B010C941B0180 |
:100090000C941B010C941B010C941B010C941B0170 |
:1000A0000C941B010C941B010C941B010C941B0160 |
:1000B0000C941B010C941B010C941B010C941B0150 |
:1000C0000C941B010C941B010C941B010C941B0140 |
:1000D0000C941B010C941B010C941B010C941B0130 |
:1000E0000C941B010C941B010C941B010C941B0120 |
:1000F0000C941B010C941B010C941B010C941B0110 |
:100100000C941B010C941B010C941B010C941B01FF |
:100110000C941B010C941B010C941B010C941B01EF |
:100120000C941B010C941B010C941B010C941B01DF |
:100130000C941B010C941B010C941B010C941B01CF |
:100140000C941B010C941B010C941B010C941B01BF |
:100150000C941B010C941B010C941B010C941B01AF |
:100160000C941B010C941B010C941B010C941B019F |
:100170000C941B010C941B010C941B010C941B018F |
:100180000C941B010C941B010C941B010C941B017F |
:100190000C941B010C941B010C941B010C941B016F |
:1001A0000C941B010C941B010C941B010C941B015F |
:1001B0000C941B010C941B010C941B010C941B014F |
:1001C0000C941B010C941B010C941B010C941B013F |
:1001D0000C941B010C941B010C941B010C941B012F |
:1001E0000C941B010C941B010C941B010C941B011F |
:1001F0000C941B0111241FBECFEFDFE3DEBFCDBF88 |
:1002000000E00CBF10E2A0E0B0E2E2EBF2E000E0C0 |
:100210000BBF02C007900D92A030B107D9F710E2D2 |
:10022000A0E0B0E201C01D92A030B107E1F70E944A |
:100230001D010C9457010C94000088ED77E084BFF9 |
:10024000709350008091510087708730D9F788ED06 |
:1002500071E084BF7093600084BF7093680084BFB6 |
:100260007093400088ED71E084BF7093960082E047 |
:10027000E0EBF0E0848380E8809360061092000752 |
:100280001092E006809160068F60809360068FEF89 |
:100290008093A006A0E6B6E0E0EAF6E080910807C9 |
:1002A00014968C9314978091E8068483F7CFF89482 |
:0202B000FFCF7E |
:100000000C94FA000C9418010C9418010C9418012B |
:100010000C9418010C9418010C9418010C941801FC |
:100020000C9418010C9418010C9418010C941801EC |
:100030000C9418010C9418010C9418010C941801DC |
:100040000C9418010C9418010C9418010C941801CC |
:100050000C9418010C9418010C9418010C941801BC |
:100060000C9418010C9418010C9418010C941801AC |
:100070000C9418010C9418010C9418010C9418019C |
:100080000C9418010C9418010C9418010C9418018C |
:100090000C9418010C9418010C9418010C9418017C |
:1000A0000C9418010C9418010C9418010C9418016C |
:1000B0000C9418010C9418010C9418010C9418015C |
:1000C0000C9418010C9418010C9418010C9418014C |
:1000D0000C9418010C9418010C9418010C9418013C |
:1000E0000C9418010C9418010C9418010C9418012C |
:1000F0000C9418010C9418010C9418010C9418011C |
:100100000C9418010C9418010C9418010C9418010B |
:100110000C9418010C9418010C9418010C941801FB |
:100120000C9418010C9418010C9418010C941801EB |
:100130000C9418010C9418010C9418010C941801DB |
:100140000C9418010C9418010C9418010C941801CB |
:100150000C9418010C9418010C9418010C941801BB |
:100160000C9418010C9418010C9418010C941801AB |
:100170000C9418010C9418010C9418010C9418019B |
:100180000C9418010C9418010C9418010C9418018B |
:100190000C9418010C9418010C9418010C9418017B |
:1001A0000C9418010C9418010C9418010C9418016B |
:1001B0000C9418010C9418010C9418010C9418015B |
:1001C0000C9418010C9418010C9418010C9418014B |
:1001D0000C9418010C9418010C9418010C9418013B |
:1001E0000C9418010C9418010C9418010C9418012B |
:1001F0000C94180111241FBECFEFDFE3DEBFCDBF8B |
:1002000000E00CBF18BE19BE1ABE1BBE10E2A0E073 |
:10021000B0E2ECEAF2E000E00BBF02C007900D9202 |
:10022000A030B107D9F71BBE0E941A010C945401EB |
:100230000C94000088ED77E084BF709350008091AB |
:10024000510087708730D9F788ED71E084BF7093D3 |
:10025000600084BF7093680084BF7093400088ED95 |
:1002600071E084BF7093960082E0E0EBF0E084835D |
:1002700080E880936006109200071092E00680915B |
:1002800060068F60809360068FEF8093A006A0E6E3 |
:10029000B6E0E0EAF6E08091080714968C93149794 |
:0C02A0008091E8068483F7CFF894FFCF2C |
:00000001FF |
/1.15d/lightshow/Makefile
7,11 → 7,11
JARTARGET=Lightshow.jar |
CLASSTARGETS=Lightshow.class |
CLASSEXTRADEPS= |
#CLASSEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/java/ztex/*.java) |
#CLASSEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/java/ztex/*.java) |
|
IHXTARGETS=lightshow.ihx |
IHXEXTRADEPS= |
#IHXEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/include/*.h) |
#IHXEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/include/*.h) |
EXTRAJARFILES=lightshow.ihx avr/lightshow.ihx fpga/lightshow.bit |
|
################################ |
/1.15d/Makefile
1,6 → 1,6
DIRS=ucecho intraffic memtest lightshow mmio |
|
.PHONY: default all clean distclean |
.PHONY: default all clean distclean avr avrclean avrdistclean |
|
default: |
@echo "This makefile is intended to clean up the project or to build all examples in this subdirectory" |
7,10 → 7,19
@echo "Usage: make all | clean | distclean" |
|
all: |
for i in $(DIRS); do make -C $$i all; done |
set -e; for i in $(DIRS); do make -C $$i all; done |
|
clean: |
for i in $(DIRS); do make -C $$i clean; done |
set -e; for i in $(DIRS); do make -C $$i clean; done |
|
distclean: clean |
for i in $(DIRS); do make -C $$i distclean; done |
distclean: |
set -e; for i in $(DIRS); do make -C $$i distclean; done |
|
avr: |
set -e; for i in $(DIRS); do make -C $$i avr; done |
|
avrclean: |
set -e; for i in $(DIRS); do make -C $$i avrclean; done |
|
avrdistclean: |
set -e; for i in $(DIRS); do make -C $$i avrdistclean; done |
/1.15d/memtest/MemTest.java
187,6 → 187,7
// upload the firmware if necessary |
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("memtest example for UFM 1.15") ) { |
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "memtest.ihx", force ) + " ms"); |
force = true; |
} |
|
ztex.vendorCommand (0x60, "Set test pattern", (genMode ? 1 : 0), 0); |
/1.15x/default/default.c
0,0 → 1,44
/*! |
default -- Default Firmware for ZTEX USB-FPGA Modules 1.15x |
Copyright (C) 2009-2011 ZTEX GmbH. |
http://www.ztex.de |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License version 3 as |
published by the Free Software Foundation. |
|
This program is distributed in the hope that it will be useful, but |
WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, see http://www.gnu.org/licenses/. |
!*/ |
|
#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros |
#include[ztex-utils.h] // include basic functions and variables |
|
// Endpoint 2 is used to high speed FPGA configuration |
EP_CONFIG(2,0,BULK,OUT,512,4); |
|
// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration) |
IDENTITY_UFM_1_15(10.13.0.0,0); |
ENABLE_UFM_1_15X_DETECTION; // avoids some warnings |
|
// enables high speed FPGA configuration, use EP 2 |
ENABLE_HS_FPGA_CONF(2); |
|
// this product string can also used for identification by the host software |
#define[PRODUCT_STRING]["USB-FPGA Module 1.15x (default)"] |
|
#include[ztex.h] |
|
void main(void) |
{ |
init_USB(); // init everything |
|
while (1) { } // twiddle thumbs |
} |
|
|
/1.15x/default/Makefile
0,0 → 1,23
######################### |
# configuration section # |
######################### |
|
ZTEXPREFIX=../../../.. |
|
JARTARGET= |
CLASSTARGETS= |
CLASSEXTRADEPS= |
|
IHXTARGETS=default.ihx |
IHXEXTRADEPS= |
EXTRAJARFILES= |
EXTRADISTCLEANFILES= |
|
default: all |
|
################################ |
# DO NOT CHANAGE THE FOLLOWING # |
################################ |
|
include $(ZTEXPREFIX)/Makefile.mk |
|
/1.15x/default/default.sh
0,0 → 1,2
../../../../java/FWLoader -c -uu default.ihx -ue default.ihx |
|
1.15x/default/default.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: 1.15x/default/Readme
===================================================================
--- 1.15x/default/Readme (nonexistent)
+++ 1.15x/default/Readme (revision 9)
@@ -0,0 +1 @@
+Default Firmware for USB-FPGA Modules 1.15x.
Index: 1.15x/Makefile
===================================================================
--- 1.15x/Makefile (nonexistent)
+++ 1.15x/Makefile (revision 9)
@@ -0,0 +1,25 @@
+DIRS=default
+
+.PHONY: default all clean distclean avr avrclean avrdistclean
+
+default:
+ @echo "This makefile is intended to clean up the project or to build all examples in this subdirectory"
+ @echo "Usage: make all | clean | distclean"
+
+all:
+ set -e; for i in $(DIRS); do make -C $$i all; done
+
+clean:
+ set -e; for i in $(DIRS); do make -C $$i clean; done
+
+distclean:
+ set -e; for i in $(DIRS); do make -C $$i distclean; done
+
+avr:
+ set -e; for i in $(DIRS); do make -C $$i avr; done
+
+avrclean:
+ set -e; for i in $(DIRS); do make -C $$i avrclean; done
+
+avrdistclean:
+ set -e; for i in $(DIRS); do make -C $$i avrdistclean; done
Index: 1.15x/Readme
===================================================================
--- 1.15x/Readme (nonexistent)
+++ 1.15x/Readme (revision 9)
@@ -0,0 +1,12 @@
+USB-FPGA Modules 1.15x and 1.15d can use the same Firmware and
+Bitstreams. Nevertheless, 1.15x detection can be added by calling the
+macro `ENABLE_UFM_1_15X_DETECTION;', see the description in
+include/ztex.conf and the examples below.
+
+The following examples are supported by USB-FPGA Modules 1.15x:
+../1.15d/intraffic
+../1.15d/mmio
+../1.15d/ucecho
+
+
+
Index: Makefile
===================================================================
--- Makefile (revision 8)
+++ Makefile (revision 9)
@@ -1,6 +1,6 @@
-DIRS=flashdemo flashbench standalone nvmtest 1.15b 1.15d
+DIRS=flashdemo flashbench standalone nvmtest 1.15a 1.15b 1.15d 1.15x
-.PHONY: default all clean distclean
+.PHONY: default all clean distclean avr avrclean avrdistclean
default:
@echo "This makefile is intended to clean up the project or to build all examples in this subdirectory"
@@ -7,10 +7,19 @@
@echo "Usage: make all | clean | distclean"
all:
- for i in $(DIRS); do make -C $$i all; done
+ set -e; for i in $(DIRS); do make -C $$i all; done
clean:
- for i in $(DIRS); do make -C $$i clean; done
+ set -e; for i in $(DIRS); do make -C $$i clean; done
-distclean: clean
- for i in $(DIRS); do make -C $$i distclean; done
+distclean:
+ set -e; for i in $(DIRS); do make -C $$i distclean; done
+
+avr:
+ set -e; for i in $(DIRS); do make -C $$i avr; done
+
+avrclean:
+ set -e; for i in $(DIRS); do make -C $$i avrclean; done
+
+avrdistclean:
+ set -e; for i in $(DIRS); do make -C $$i avrdistclean; done
/flashbench/Makefile
7,11 → 7,11
JARTARGET=FlashBench.jar |
CLASSTARGETS=FlashBench.class |
CLASSEXTRADEPS= |
#CLASSEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/java/ztex/*.java) |
#CLASSEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/java/ztex/*.java) |
|
IHXTARGETS=flashbench.ihx |
IHXEXTRADEPS= |
#IHXEXTRADEPS:=$(shell echo $(ZTEXPREFIX)/include/*.h) |
#IHXEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/include/*.h) |
EXTRAJARFILES=flashbench.ihx |
|
################################ |