OpenCores
URL https://opencores.org/ocsvn/usb_fpga_2_16/usb_fpga_2_16/trunk

Subversion Repositories usb_fpga_2_16

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    /usb_fpga_2_16/trunk/examples
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Rev 2 → Rev 3

/usb-fpga-1.15y/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15y and 1.15y2
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15y/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15y and 1.15y2
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15y/ucecho/UCEcho.java
1,6 → 1,6
/*!2
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b and 1.15y2
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15y/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b and 1.15y2
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/nvmtest/NVMTest.java
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Module 1.11 plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Modules 1.11 plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/nvmtest/nvmtest.c
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Module 1.11 plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Modules 1.11 plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11a
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11a
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.11a
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.11a
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.11a plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.11a plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11a/memtest/memtest.c
1,6 → 1,6
/*!
memtest -- DDR SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.11a
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent) @@ -1,61 +0,0 @@ ---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 -+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 -@@ -122,7 +122,6 @@ - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; -- signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; -@@ -135,7 +134,6 @@ - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; -- attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - - begin - -@@ -144,33 +142,6 @@ - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - -- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate -- --*********************************************************************** -- -- Differential input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFGDS -- generic map ( -- DIFF_TERM => TRUE -- ) -- port map ( -- I => sys_clk_p, -- IB => sys_clk_n, -- O => sys_clk_ibufg -- ); -- end generate; -- -- -- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate -- --*********************************************************************** -- -- SINGLE_ENDED input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFG -- port map ( -- I => sys_clk, -- O => sys_clk_ibufg -- ); -- end generate; -- - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** -@@ -209,7 +180,7 @@ - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', -- CLKIN1 => sys_clk_ibufg, -+ CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent) @@ -1,169 +0,0 @@ -##!/bin/csh -f -##**************************************************************************** -## (c) Copyright 2009 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. -## -##**************************************************************************** -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.5 -## \ \ Application : MIG -## / / Filename : rem_files.bat -## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $ -## \ \ / \ Date Created : Fri Feb 06 2009 -## \___\/\___\ -## -## Device : Spartan-6 -## Design Name : DDR/DDR2/DDR3/LPDDR -## Purpose : Batch file to remove files generated from ISE -## Reference : -## Revision History : -##**************************************************************************** - -rm -rf "../synth/__projnav" -rm -rf "../synth/xst" -rm -rf "../synth/_ngo" - -rm -rf tmp -rm -rf _xmsgs -rm -rf ila_xdb -rm -rf icon_xdb -rm -rf vio_xdb - -rm -rf xlnx_auto_0_xdb - -rm -rf vio_xmdf.tcl -rm -rf vio_readme.txt -rm -rf vio_flist.txt -rm -rf vio.xise del -rm -rf vio.xco del -rm -rf vio.ngc del -rm -rf vio.ise del -rm -rf vio.gise del -rm -rf vio.cdc del - -rm -rf coregen.cgp -rm -rf coregen.cgc -rm -rf coregen.log -rm -rf ila.cdc -rm -rf ila.gise -rm -rf ila.ise -rm -rf ila.ngc -rm -rf ila.xco -rm -rf ila.xise -rm -rf ila_flist.txt -rm -rf ila_readme.txt -rm -rf ila_xmdf.tcl - -rm -rf icon.asy -rm -rf icon.gise -rm -rf icon.ise -rm -rf icon.ncf -rm -rf icon.ngc -rm -rf icon.xco -rm -rf icon.xise -rm -rf icon_flist.txt -rm -rf icon_readme.txt -rm -rf icon_xmdf.tcl - -rm -rf ise_flow_results.txt -rm -rf mem0_vhdl.prj -rm -rf mem_interface_top.syr -rm -rf mem0.ngc -rm -rf mem0.ngr -rm -rf mem0_xst.xrpt -rm -rf mem0.bld -rm -rf mem0.ngd -rm -rf mem0_ngdbuild.xrpt -rm -rf mem0_map.map -rm -rf mem0_map.mrp -rm -rf mem0_map.ngm -rm -rf mem0.pcf -rm -rf mem0_map.ncd -rm -rf mem0_map.xrpt -rm -rf mem0_summary.xml -rm -rf mem0_usage.xml -rm -rf mem0.ncd -rm -rf mem0.par -rm -rf mem0.xpi -rm -rf mem0.ptwx -rm -rf mem0.pad -rm -rf mem0.unroutes -rm -rf mem0_pad.csv -rm -rf mem0_pad.txt -rm -rf mem0_par.xrpt -rm -rf mem0.twx -rm -rf mem0.bgn -rm -rf mem0.twr -rm -rf mem0.drc -rm -rf mem0_bitgen.xwbt -rm -rf mem0.bit - -# Files and folders generated by create ise -rm -rf test_xdb -rm -rf _xmsgs -rm -rf test.gise -rm -rf test.xise -rm -rf test.xise - -# Files and folders generated by ISE through GUI mode -rm -rf _ngo -rm -rf xst -rm -rf mem0.lso -rm -rf mem0.prj -rm -rf mem0.xst -rm -rf mem0.stx -rm -rf mem0_prev_built.ngd -rm -rf test.ntrc_log -rm -rf mem0_guide.ncd -rm -rf mem0.cmd_log -rm -rf mem0_summary.html -rm -rf mem0.ut -rm -rf par_usage_statistics.html -rm -rf usage_statistics_webtalk.html -rm -rf webtalk.log -rm -rf device_usage_statistics.html
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 06:55:40 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=2 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: eff89f81 - Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : ise_flow.bat -# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE batch mode -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -echo Synthesis Tool: XST - -mkdir "../synth/__projnav" > ise_flow_results.txt -mkdir "../synth/xst" >> ise_flow_results.txt -mkdir "../synth/xst/work" >> ise_flow_results.txt - -xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt -ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx16ftg256-2 mem0.ngc mem0.ngd >> ise_flow_results.txt - -map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt -par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt -trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt -bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt - -echo done!
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent) @@ -1,2 +0,0 @@ -NEWPROJECT . -SETPROJECT .
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent) @@ -1,48 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 07:09:11 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7da1f376 - Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent) @@ -1,51 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.2 -# Date: Fri Jun 12 05:42:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET asynchronous_input_port_width=8 -CSET asynchronous_output_port_width=7 -CSET component_name=vio -CSET enable_asynchronous_input_port=false -CSET enable_asynchronous_output_port=true -CSET enable_synchronous_input_port=false -CSET enable_synchronous_output_port=false -CSET invert_clock_input=false -CSET synchronous_input_port_width=8 -CSET synchronous_output_port_width=8 -# END Parameters -GENERATE -# CRC: 66fe39ed - Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : create_ise.bat -# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:15 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -xtclsh set_ise_prop.tcl
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent) @@ -1,8 +0,0 @@ -vhdl work ../rtl/iodrp_controller.vhd -vhdl work ../rtl/iodrp_mcb_controller.vhd -vhdl work ../rtl/mcb_raw_wrapper.vhd -vhdl work ../rtl/mcb_soft_calibration.vhd -vhdl work ../rtl/mcb_soft_calibration_top.vhd -vhdl work ../rtl/mem0.vhd -vhdl work ../rtl/memc3_infrastructure.vhd -vhdl work ../rtl/memc3_wrapper.vhd Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (nonexistent) @@ -1,53 +0,0 @@ - - - mem0 - xc6slx16-ftg256/-2 - 3.5 - - DDR_SDRAM/Components/MT46V32M16XX-5B-IT - 5000 - 0 - 1 - FALSE - - 13 - 10 - 2 - - - - 4(010) - 3 - Enable-Normal - Normal - Class II - Class II - UNCALIB_TERM - 50 Ohms - - - - 1 - Disable - Single-Ended - Two 32-bit bi-directional and four 32-bit unidirectional ports - M4 - M5 - Port0,Port1,Port2,Port3,Port4,Port5 - Bi-directional,Bi-directional,Write,Read,Write,Read - ROW_BANK_COLUMN - Round Robin - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - - Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh *.prj" -subdirs="par rtl synth" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/clean.sh =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh" -subdirs="user_design" - - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/mem0/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/dcm0.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/dcm0.ise =================================================================== --- usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/dcm0.ise (revision 2) +++ usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/dcm0.ise (nonexistent)
usb-fpga-1.11/1.11a/memtest/fpga/ipcore_dir/dcm0.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: usb-fpga-1.11/1.11a/memtest/MemTest.java =================================================================== --- usb-fpga-1.11/1.11a/memtest/MemTest.java (revision 2) +++ usb-fpga-1.11/1.11a/memtest/MemTest.java (revision 3) @@ -1,6 +1,6 @@ /*! memtest -- DDR SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.11a - Copyright (C) 2009-2011 ZTEX GmbH. + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.11b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.11b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.11b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.11b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/memtest/memtest.c
1,6 → 1,6
/*!
memtest -- DDR SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.11b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0.xise =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0.xise (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0.xise (nonexistent) @@ -1,122 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0.xco =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0.xco (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0.xco (nonexistent) @@ -1,42 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Fri Aug 20 09:42:54 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT MIG family Xilinx,_Inc. 3.5 -# END Select -# BEGIN Parameters -CSET component_name=mem0 -CSET xml_input_file=./mem0/user_design/mig.prj -# END Parameters -GENERATE -# CRC: 1734ed6e Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.xise =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.xise (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.xise (nonexistent) @@ -1,395 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.xco =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.xco (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/dcm0.xco (nonexistent) @@ -1,211 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Tue Oct 5 20:56:26 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = true -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT Clocking_Wizard family Xilinx,_Inc. 1.4 -# END Select -# BEGIN Parameters -CSET clkfb_in_signaling=SINGLE -CSET clkin1_jitter_ps=100.0 -CSET clkin2_jitter_ps=100.0 -CSET clkout1_drives=BUFG -CSET clkout1_requested_duty_cycle=50.0 -CSET clkout1_requested_out_freq=200.000 -CSET clkout1_requested_phase=0.000 -CSET clkout2_drives=BUFG -CSET clkout2_requested_duty_cycle=50.0 -CSET clkout2_requested_out_freq=50.000 -CSET clkout2_requested_phase=0 -CSET clkout2_used=true -CSET clkout3_drives=BUFG -CSET clkout3_requested_duty_cycle=50.0 -CSET clkout3_requested_out_freq=48 -CSET clkout3_requested_phase=0.000 -CSET clkout3_used=false -CSET clkout4_drives=BUFG -CSET clkout4_requested_duty_cycle=50.0 -CSET clkout4_requested_out_freq=100.000 -CSET clkout4_requested_phase=0.000 -CSET clkout4_used=false -CSET clkout5_drives=BUFG -CSET clkout5_requested_duty_cycle=50.0 -CSET clkout5_requested_out_freq=100.000 -CSET clkout5_requested_phase=0.000 -CSET clkout5_used=false -CSET clkout6_drives=BUFG -CSET clkout6_requested_duty_cycle=50.0 -CSET clkout6_requested_out_freq=100.000 -CSET clkout6_requested_phase=0.000 -CSET clkout6_used=false -CSET clkout7_drives=BUFG -CSET clkout7_requested_duty_cycle=50.0 -CSET clkout7_requested_out_freq=100.000 -CSET clkout7_requested_phase=0.000 -CSET clkout7_used=false -CSET clock_mgr_type=MANUAL -CSET component_name=dcm0 -CSET dcm_clk_feedback=1X -CSET dcm_clk_out1_port=CLKFX -CSET dcm_clk_out2_port=CLK0 -CSET dcm_clk_out3_port=CLK0 -CSET dcm_clk_out4_port=CLK0 -CSET dcm_clk_out5_port=CLK0 -CSET dcm_clk_out6_port=CLK0 -CSET dcm_clkdv_divide=12.0 -CSET dcm_clkfx_divide=1 -CSET dcm_clkfx_multiply=4 -CSET dcm_clkgen_clk_out1_port=CLKFX -CSET dcm_clkgen_clk_out2_port=CLKFXDV -CSET dcm_clkgen_clk_out3_port=CLKFX -CSET dcm_clkgen_clkfx_divide=6 -CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=25 -CSET dcm_clkgen_clkfxdv_divide=4 -CSET dcm_clkgen_clkin_period=20.83333 -CSET dcm_clkgen_notes=None -CSET dcm_clkgen_spread_spectrum=NONE -CSET dcm_clkgen_startup_wait=false -CSET dcm_clkin_divide_by_2=false -CSET dcm_clkin_period=20.833 -CSET dcm_clkout_phase_shift=NONE -CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS -CSET dcm_notes=None -CSET dcm_phase_shift=0 -CSET dcm_startup_wait=false -CSET feedback_source=FDBK_AUTO -CSET in_freq_units=Units_MHz -CSET in_jitter_units=Units_UI -CSET jitter_sel=No_Jitter -CSET mmcm_bandwidth=OPTIMIZED -CSET mmcm_clkfbout_mult_f=4.000 -CSET mmcm_clkfbout_phase=0.000 -CSET mmcm_clkfbout_use_fine_ps=false -CSET mmcm_clkin1_period=10.000 -CSET mmcm_clkin2_period=10.000 -CSET mmcm_clkout0_divide_f=4.000 -CSET mmcm_clkout0_duty_cycle=0.500 -CSET mmcm_clkout0_phase=0.000 -CSET mmcm_clkout0_use_fine_ps=false -CSET mmcm_clkout1_divide=1 -CSET mmcm_clkout1_duty_cycle=0.500 -CSET mmcm_clkout1_phase=0.000 -CSET mmcm_clkout1_use_fine_ps=false -CSET mmcm_clkout2_divide=1 -CSET mmcm_clkout2_duty_cycle=0.500 -CSET mmcm_clkout2_phase=0.000 -CSET mmcm_clkout2_use_fine_ps=false -CSET mmcm_clkout3_divide=1 -CSET mmcm_clkout3_duty_cycle=0.500 -CSET mmcm_clkout3_phase=0.000 -CSET mmcm_clkout3_use_fine_ps=false -CSET mmcm_clkout4_cascade=false -CSET mmcm_clkout4_divide=1 -CSET mmcm_clkout4_duty_cycle=0.500 -CSET mmcm_clkout4_phase=0.000 -CSET mmcm_clkout4_use_fine_ps=false -CSET mmcm_clkout5_divide=1 -CSET mmcm_clkout5_duty_cycle=0.500 -CSET mmcm_clkout5_phase=0.000 -CSET mmcm_clkout5_use_fine_ps=false -CSET mmcm_clkout6_divide=1 -CSET mmcm_clkout6_duty_cycle=0.500 -CSET mmcm_clkout6_phase=0.000 -CSET mmcm_clkout6_use_fine_ps=false -CSET mmcm_clock_hold=false -CSET mmcm_compensation=ZHOLD -CSET mmcm_divclk_divide=1 -CSET mmcm_notes=None -CSET mmcm_ref_jitter1=0.010 -CSET mmcm_ref_jitter2=0.010 -CSET mmcm_startup_wait=false -CSET num_out_clks=2 -CSET override_dcm=false -CSET override_dcm_clkgen=true -CSET override_mmcm=false -CSET override_pll=false -CSET platform=lin -CSET pll_bandwidth=OPTIMIZED -CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=12 -CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=20.833 -CSET pll_clkout0_divide=3 -CSET pll_clkout0_duty_cycle=0.500 -CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=12 -CSET pll_clkout1_duty_cycle=0.500 -CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=6 -CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=0.000 -CSET pll_clkout3_divide=1 -CSET pll_clkout3_duty_cycle=0.500 -CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=1 -CSET pll_clkout4_duty_cycle=0.500 -CSET pll_clkout4_phase=0.000 -CSET pll_clkout5_divide=1 -CSET pll_clkout5_duty_cycle=0.500 -CSET pll_clkout5_phase=0.000 -CSET pll_compensation=INTERNAL -CSET pll_divclk_divide=1 -CSET pll_notes=None -CSET pll_ref_jitter=0.010 -CSET prim_in_freq=48.000 -CSET prim_in_jitter=0.010 -CSET prim_source=Single_ended_clock_capable_pin -CSET primtype_sel=DCM_CLKGEN -CSET relative_inclk=REL_PRIMARY -CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.010 -CSET secondary_source=Single_ended_clock_capable_pin -CSET summary_strings=empty -CSET use_clk_valid=true -CSET use_dyn_phase_shift=false -CSET use_dyn_reconfig=false -CSET use_freeze=false -CSET use_freq_synth=true -CSET use_inclk_stopped=false -CSET use_inclk_switchover=false -CSET use_locked=true -CSET use_max_i_jitter=false -CSET use_min_o_jitter=false -CSET use_min_power=false -CSET use_phase_alignment=false -CSET use_power_down=false -CSET use_reset=true -CSET use_spread_spectrum=false -CSET use_status=false -# END Parameters -GENERATE -# CRC: 585c5e74 Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/clean.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/clean.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.vhd *.sh *.ise *.xco *.xise *.tcl" -subdirs="mem0" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent) @@ -1,61 +0,0 @@ ---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 -+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 -@@ -122,7 +122,6 @@ - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; -- signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; -@@ -135,7 +134,6 @@ - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; -- attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - - begin - -@@ -144,33 +142,6 @@ - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - -- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate -- --*********************************************************************** -- -- Differential input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFGDS -- generic map ( -- DIFF_TERM => TRUE -- ) -- port map ( -- I => sys_clk_p, -- IB => sys_clk_n, -- O => sys_clk_ibufg -- ); -- end generate; -- -- -- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate -- --*********************************************************************** -- -- SINGLE_ENDED input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFG -- port map ( -- I => sys_clk, -- O => sys_clk_ibufg -- ); -- end generate; -- - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** -@@ -209,7 +180,7 @@ - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', -- CLKIN1 => sys_clk_ibufg, -+ CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent) @@ -1,51 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.2 -# Date: Fri Jun 12 05:42:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET asynchronous_input_port_width=8 -CSET asynchronous_output_port_width=7 -CSET component_name=vio -CSET enable_asynchronous_input_port=false -CSET enable_asynchronous_output_port=true -CSET enable_synchronous_input_port=false -CSET enable_synchronous_output_port=false -CSET invert_clock_input=false -CSET synchronous_input_port_width=8 -CSET synchronous_output_port_width=8 -# END Parameters -GENERATE -# CRC: 66fe39ed - Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : create_ise.bat -# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:15 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -xtclsh set_ise_prop.tcl
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent) @@ -1,169 +0,0 @@ -##!/bin/csh -f -##**************************************************************************** -## (c) Copyright 2009 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. -## -##**************************************************************************** -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.5 -## \ \ Application : MIG -## / / Filename : rem_files.bat -## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $ -## \ \ / \ Date Created : Fri Feb 06 2009 -## \___\/\___\ -## -## Device : Spartan-6 -## Design Name : DDR/DDR2/DDR3/LPDDR -## Purpose : Batch file to remove files generated from ISE -## Reference : -## Revision History : -##**************************************************************************** - -rm -rf "../synth/__projnav" -rm -rf "../synth/xst" -rm -rf "../synth/_ngo" - -rm -rf tmp -rm -rf _xmsgs -rm -rf ila_xdb -rm -rf icon_xdb -rm -rf vio_xdb - -rm -rf xlnx_auto_0_xdb - -rm -rf vio_xmdf.tcl -rm -rf vio_readme.txt -rm -rf vio_flist.txt -rm -rf vio.xise del -rm -rf vio.xco del -rm -rf vio.ngc del -rm -rf vio.ise del -rm -rf vio.gise del -rm -rf vio.cdc del - -rm -rf coregen.cgp -rm -rf coregen.cgc -rm -rf coregen.log -rm -rf ila.cdc -rm -rf ila.gise -rm -rf ila.ise -rm -rf ila.ngc -rm -rf ila.xco -rm -rf ila.xise -rm -rf ila_flist.txt -rm -rf ila_readme.txt -rm -rf ila_xmdf.tcl - -rm -rf icon.asy -rm -rf icon.gise -rm -rf icon.ise -rm -rf icon.ncf -rm -rf icon.ngc -rm -rf icon.xco -rm -rf icon.xise -rm -rf icon_flist.txt -rm -rf icon_readme.txt -rm -rf icon_xmdf.tcl - -rm -rf ise_flow_results.txt -rm -rf mem0_vhdl.prj -rm -rf mem_interface_top.syr -rm -rf mem0.ngc -rm -rf mem0.ngr -rm -rf mem0_xst.xrpt -rm -rf mem0.bld -rm -rf mem0.ngd -rm -rf mem0_ngdbuild.xrpt -rm -rf mem0_map.map -rm -rf mem0_map.mrp -rm -rf mem0_map.ngm -rm -rf mem0.pcf -rm -rf mem0_map.ncd -rm -rf mem0_map.xrpt -rm -rf mem0_summary.xml -rm -rf mem0_usage.xml -rm -rf mem0.ncd -rm -rf mem0.par -rm -rf mem0.xpi -rm -rf mem0.ptwx -rm -rf mem0.pad -rm -rf mem0.unroutes -rm -rf mem0_pad.csv -rm -rf mem0_pad.txt -rm -rf mem0_par.xrpt -rm -rf mem0.twx -rm -rf mem0.bgn -rm -rf mem0.twr -rm -rf mem0.drc -rm -rf mem0_bitgen.xwbt -rm -rf mem0.bit - -# Files and folders generated by create ise -rm -rf test_xdb -rm -rf _xmsgs -rm -rf test.gise -rm -rf test.xise -rm -rf test.xise - -# Files and folders generated by ISE through GUI mode -rm -rf _ngo -rm -rf xst -rm -rf mem0.lso -rm -rf mem0.prj -rm -rf mem0.xst -rm -rf mem0.stx -rm -rf mem0_prev_built.ngd -rm -rf test.ntrc_log -rm -rf mem0_guide.ncd -rm -rf mem0.cmd_log -rm -rf mem0_summary.html -rm -rf mem0.ut -rm -rf par_usage_statistics.html -rm -rf usage_statistics_webtalk.html -rm -rf webtalk.log -rm -rf device_usage_statistics.html
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 06:55:40 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=2 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: eff89f81 - Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : ise_flow.bat -# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE batch mode -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -echo Synthesis Tool: XST - -mkdir "../synth/__projnav" > ise_flow_results.txt -mkdir "../synth/xst" >> ise_flow_results.txt -mkdir "../synth/xst/work" >> ise_flow_results.txt - -xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt -ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx16ftg256-2 mem0.ngc mem0.ngd >> ise_flow_results.txt - -map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt -par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt -trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt -bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt - -echo done!
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent) @@ -1,2 +0,0 @@ -NEWPROJECT . -SETPROJECT .
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent) @@ -1,48 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 07:09:11 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx16 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7da1f376 - Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent) @@ -1,8 +0,0 @@ -vhdl work ../rtl/iodrp_controller.vhd -vhdl work ../rtl/iodrp_mcb_controller.vhd -vhdl work ../rtl/mcb_raw_wrapper.vhd -vhdl work ../rtl/mcb_soft_calibration.vhd -vhdl work ../rtl/mcb_soft_calibration_top.vhd -vhdl work ../rtl/mem0.vhd -vhdl work ../rtl/memc3_infrastructure.vhd -vhdl work ../rtl/memc3_wrapper.vhd Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (nonexistent) @@ -1,53 +0,0 @@ - - - mem0 - xc6slx16-ftg256/-2 - 3.5 - - DDR_SDRAM/Components/MT46V32M16XX-5B-IT - 5000 - 0 - 1 - FALSE - - 13 - 10 - 2 - - - - 4(010) - 3 - Enable-Normal - Normal - Class II - Class II - UNCALIB_TERM - 50 Ohms - - - - 1 - Disable - Single-Ended - Two 32-bit bi-directional and four 32-bit unidirectional ports - M4 - M5 - Port0,Port1,Port2,Port3,Port4,Port5 - Bi-directional,Bi-directional,Write,Read,Write,Read - ROW_BANK_COLUMN - Round Robin - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - - Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh *.prj" -subdirs="par rtl synth" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/clean.sh =================================================================== --- usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 2) +++ usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh" -subdirs="user_design" - - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11b/memtest/fpga/ipcore_dir/mem0/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11b/memtest/MemTest.java =================================================================== --- usb-fpga-1.11/1.11b/memtest/MemTest.java (revision 2) +++ usb-fpga-1.11/1.11b/memtest/MemTest.java (revision 3) @@ -1,6 +1,6 @@ /*! memtest -- DDR SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.11b - Copyright (C) 2009-2011 ZTEX GmbH. + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/flashdemo/FlashDemo.java
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.11
Copyright (C) 2009-2011 ZTEX GmbH.
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 1.11
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/flashdemo/flashdemo.c
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.11
Copyright (C) 2009-2011 ZTEX GmbH.
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 1.11
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11c
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.11c
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.11c
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.11c
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.11c plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.11c plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/1.11c/memtest/memtest.c
1,6 → 1,6
/*!
memtest -- DDR SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.11c
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent) @@ -1,61 +0,0 @@ ---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 -+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 -@@ -122,7 +122,6 @@ - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; -- signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; -@@ -135,7 +134,6 @@ - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; -- attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - - begin - -@@ -144,33 +142,6 @@ - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - -- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate -- --*********************************************************************** -- -- Differential input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFGDS -- generic map ( -- DIFF_TERM => TRUE -- ) -- port map ( -- I => sys_clk_p, -- IB => sys_clk_n, -- O => sys_clk_ibufg -- ); -- end generate; -- -- -- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate -- --*********************************************************************** -- -- SINGLE_ENDED input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFG -- port map ( -- I => sys_clk, -- O => sys_clk_ibufg -- ); -- end generate; -- - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** -@@ -209,7 +180,7 @@ - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', -- CLKIN1 => sys_clk_ibufg, -+ CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 06:55:40 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx25 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=2 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: eff89f81 - Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : ise_flow.bat -# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE batch mode -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -echo Synthesis Tool: XST - -mkdir "../synth/__projnav" > ise_flow_results.txt -mkdir "../synth/xst" >> ise_flow_results.txt -mkdir "../synth/xst/work" >> ise_flow_results.txt - -xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt -ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx25ftg256-3 mem0.ngc mem0.ngd >> ise_flow_results.txt - -map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt -par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt -trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt -bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt - -echo done!
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent) @@ -1,2 +0,0 @@ -NEWPROJECT . -SETPROJECT .
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent) @@ -1,48 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 07:09:11 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx25 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7da1f376 - Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent) @@ -1,51 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.2 -# Date: Fri Jun 12 05:42:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx25 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET asynchronous_input_port_width=8 -CSET asynchronous_output_port_width=7 -CSET component_name=vio -CSET enable_asynchronous_input_port=false -CSET enable_asynchronous_output_port=true -CSET enable_synchronous_input_port=false -CSET enable_synchronous_output_port=false -CSET invert_clock_input=false -CSET synchronous_input_port_width=8 -CSET synchronous_output_port_width=8 -# END Parameters -GENERATE -# CRC: 66fe39ed - Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : create_ise.bat -# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:15 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -xtclsh set_ise_prop.tcl
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent) @@ -1,169 +0,0 @@ -##!/bin/csh -f -##**************************************************************************** -## (c) Copyright 2009 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. -## -##**************************************************************************** -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.5 -## \ \ Application : MIG -## / / Filename : rem_files.bat -## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $ -## \ \ / \ Date Created : Fri Feb 06 2009 -## \___\/\___\ -## -## Device : Spartan-6 -## Design Name : DDR/DDR2/DDR3/LPDDR -## Purpose : Batch file to remove files generated from ISE -## Reference : -## Revision History : -##**************************************************************************** - -rm -rf "../synth/__projnav" -rm -rf "../synth/xst" -rm -rf "../synth/_ngo" - -rm -rf tmp -rm -rf _xmsgs -rm -rf ila_xdb -rm -rf icon_xdb -rm -rf vio_xdb - -rm -rf xlnx_auto_0_xdb - -rm -rf vio_xmdf.tcl -rm -rf vio_readme.txt -rm -rf vio_flist.txt -rm -rf vio.xise del -rm -rf vio.xco del -rm -rf vio.ngc del -rm -rf vio.ise del -rm -rf vio.gise del -rm -rf vio.cdc del - -rm -rf coregen.cgp -rm -rf coregen.cgc -rm -rf coregen.log -rm -rf ila.cdc -rm -rf ila.gise -rm -rf ila.ise -rm -rf ila.ngc -rm -rf ila.xco -rm -rf ila.xise -rm -rf ila_flist.txt -rm -rf ila_readme.txt -rm -rf ila_xmdf.tcl - -rm -rf icon.asy -rm -rf icon.gise -rm -rf icon.ise -rm -rf icon.ncf -rm -rf icon.ngc -rm -rf icon.xco -rm -rf icon.xise -rm -rf icon_flist.txt -rm -rf icon_readme.txt -rm -rf icon_xmdf.tcl - -rm -rf ise_flow_results.txt -rm -rf mem0_vhdl.prj -rm -rf mem_interface_top.syr -rm -rf mem0.ngc -rm -rf mem0.ngr -rm -rf mem0_xst.xrpt -rm -rf mem0.bld -rm -rf mem0.ngd -rm -rf mem0_ngdbuild.xrpt -rm -rf mem0_map.map -rm -rf mem0_map.mrp -rm -rf mem0_map.ngm -rm -rf mem0.pcf -rm -rf mem0_map.ncd -rm -rf mem0_map.xrpt -rm -rf mem0_summary.xml -rm -rf mem0_usage.xml -rm -rf mem0.ncd -rm -rf mem0.par -rm -rf mem0.xpi -rm -rf mem0.ptwx -rm -rf mem0.pad -rm -rf mem0.unroutes -rm -rf mem0_pad.csv -rm -rf mem0_pad.txt -rm -rf mem0_par.xrpt -rm -rf mem0.twx -rm -rf mem0.bgn -rm -rf mem0.twr -rm -rf mem0.drc -rm -rf mem0_bitgen.xwbt -rm -rf mem0.bit - -# Files and folders generated by create ise -rm -rf test_xdb -rm -rf _xmsgs -rm -rf test.gise -rm -rf test.xise -rm -rf test.xise - -# Files and folders generated by ISE through GUI mode -rm -rf _ngo -rm -rf xst -rm -rf mem0.lso -rm -rf mem0.prj -rm -rf mem0.xst -rm -rf mem0.stx -rm -rf mem0_prev_built.ngd -rm -rf test.ntrc_log -rm -rf mem0_guide.ncd -rm -rf mem0.cmd_log -rm -rf mem0_summary.html -rm -rf mem0.ut -rm -rf par_usage_statistics.html -rm -rf usage_statistics_webtalk.html -rm -rf webtalk.log -rm -rf device_usage_statistics.html
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/clean.sh =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh" -subdirs="user_design" - - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.ise =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.ise (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.ise (nonexistent)
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.ise Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0.xise =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0.xise (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0.xise (nonexistent) @@ -1,122 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0.xco =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0.xco (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/mem0.xco (nonexistent) @@ -1,42 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Tue Oct 5 21:28:57 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx25 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT MIG family Xilinx,_Inc. 3.5 -# END Select -# BEGIN Parameters -CSET component_name=mem0 -CSET xml_input_file=./mem0/user_design/mig.prj -# END Parameters -GENERATE -# CRC: 43347ccc Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.xise =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.xise (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.xise (nonexistent) @@ -1,395 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.xco =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.xco (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/dcm0.xco (nonexistent) @@ -1,211 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Tue Oct 5 21:15:02 2010 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx25 -SET devicefamily = spartan6 -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ftg256 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT Clocking_Wizard family Xilinx,_Inc. 1.4 -# END Select -# BEGIN Parameters -CSET clkfb_in_signaling=SINGLE -CSET clkin1_jitter_ps=100.0 -CSET clkin2_jitter_ps=100.0 -CSET clkout1_drives=BUFG -CSET clkout1_requested_duty_cycle=50.0 -CSET clkout1_requested_out_freq=200.000 -CSET clkout1_requested_phase=0.000 -CSET clkout2_drives=BUFG -CSET clkout2_requested_duty_cycle=50.0 -CSET clkout2_requested_out_freq=50.000 -CSET clkout2_requested_phase=0 -CSET clkout2_used=true -CSET clkout3_drives=BUFG -CSET clkout3_requested_duty_cycle=50.0 -CSET clkout3_requested_out_freq=48 -CSET clkout3_requested_phase=0.000 -CSET clkout3_used=false -CSET clkout4_drives=BUFG -CSET clkout4_requested_duty_cycle=50.0 -CSET clkout4_requested_out_freq=100.000 -CSET clkout4_requested_phase=0.000 -CSET clkout4_used=false -CSET clkout5_drives=BUFG -CSET clkout5_requested_duty_cycle=50.0 -CSET clkout5_requested_out_freq=100.000 -CSET clkout5_requested_phase=0.000 -CSET clkout5_used=false -CSET clkout6_drives=BUFG -CSET clkout6_requested_duty_cycle=50.0 -CSET clkout6_requested_out_freq=100.000 -CSET clkout6_requested_phase=0.000 -CSET clkout6_used=false -CSET clkout7_drives=BUFG -CSET clkout7_requested_duty_cycle=50.0 -CSET clkout7_requested_out_freq=100.000 -CSET clkout7_requested_phase=0.000 -CSET clkout7_used=false -CSET clock_mgr_type=MANUAL -CSET component_name=dcm0 -CSET dcm_clk_feedback=1X -CSET dcm_clk_out1_port=CLKFX -CSET dcm_clk_out2_port=CLK0 -CSET dcm_clk_out3_port=CLK0 -CSET dcm_clk_out4_port=CLK0 -CSET dcm_clk_out5_port=CLK0 -CSET dcm_clk_out6_port=CLK0 -CSET dcm_clkdv_divide=12.0 -CSET dcm_clkfx_divide=1 -CSET dcm_clkfx_multiply=4 -CSET dcm_clkgen_clk_out1_port=CLKFX -CSET dcm_clkgen_clk_out2_port=CLKFXDV -CSET dcm_clkgen_clk_out3_port=CLKFX -CSET dcm_clkgen_clkfx_divide=6 -CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=25 -CSET dcm_clkgen_clkfxdv_divide=4 -CSET dcm_clkgen_clkin_period=20.83333 -CSET dcm_clkgen_notes=None -CSET dcm_clkgen_spread_spectrum=NONE -CSET dcm_clkgen_startup_wait=false -CSET dcm_clkin_divide_by_2=false -CSET dcm_clkin_period=20.833 -CSET dcm_clkout_phase_shift=NONE -CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS -CSET dcm_notes=None -CSET dcm_phase_shift=0 -CSET dcm_startup_wait=false -CSET feedback_source=FDBK_AUTO -CSET in_freq_units=Units_MHz -CSET in_jitter_units=Units_UI -CSET jitter_sel=No_Jitter -CSET mmcm_bandwidth=OPTIMIZED -CSET mmcm_clkfbout_mult_f=4.000 -CSET mmcm_clkfbout_phase=0.000 -CSET mmcm_clkfbout_use_fine_ps=false -CSET mmcm_clkin1_period=10.000 -CSET mmcm_clkin2_period=10.000 -CSET mmcm_clkout0_divide_f=4.000 -CSET mmcm_clkout0_duty_cycle=0.500 -CSET mmcm_clkout0_phase=0.000 -CSET mmcm_clkout0_use_fine_ps=false -CSET mmcm_clkout1_divide=1 -CSET mmcm_clkout1_duty_cycle=0.500 -CSET mmcm_clkout1_phase=0.000 -CSET mmcm_clkout1_use_fine_ps=false -CSET mmcm_clkout2_divide=1 -CSET mmcm_clkout2_duty_cycle=0.500 -CSET mmcm_clkout2_phase=0.000 -CSET mmcm_clkout2_use_fine_ps=false -CSET mmcm_clkout3_divide=1 -CSET mmcm_clkout3_duty_cycle=0.500 -CSET mmcm_clkout3_phase=0.000 -CSET mmcm_clkout3_use_fine_ps=false -CSET mmcm_clkout4_cascade=false -CSET mmcm_clkout4_divide=1 -CSET mmcm_clkout4_duty_cycle=0.500 -CSET mmcm_clkout4_phase=0.000 -CSET mmcm_clkout4_use_fine_ps=false -CSET mmcm_clkout5_divide=1 -CSET mmcm_clkout5_duty_cycle=0.500 -CSET mmcm_clkout5_phase=0.000 -CSET mmcm_clkout5_use_fine_ps=false -CSET mmcm_clkout6_divide=1 -CSET mmcm_clkout6_duty_cycle=0.500 -CSET mmcm_clkout6_phase=0.000 -CSET mmcm_clkout6_use_fine_ps=false -CSET mmcm_clock_hold=false -CSET mmcm_compensation=ZHOLD -CSET mmcm_divclk_divide=1 -CSET mmcm_notes=None -CSET mmcm_ref_jitter1=0.010 -CSET mmcm_ref_jitter2=0.010 -CSET mmcm_startup_wait=false -CSET num_out_clks=2 -CSET override_dcm=false -CSET override_dcm_clkgen=true -CSET override_mmcm=false -CSET override_pll=false -CSET platform=lin -CSET pll_bandwidth=OPTIMIZED -CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=12 -CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=20.833 -CSET pll_clkout0_divide=3 -CSET pll_clkout0_duty_cycle=0.500 -CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=12 -CSET pll_clkout1_duty_cycle=0.500 -CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=6 -CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=0.000 -CSET pll_clkout3_divide=1 -CSET pll_clkout3_duty_cycle=0.500 -CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=1 -CSET pll_clkout4_duty_cycle=0.500 -CSET pll_clkout4_phase=0.000 -CSET pll_clkout5_divide=1 -CSET pll_clkout5_duty_cycle=0.500 -CSET pll_clkout5_phase=0.000 -CSET pll_compensation=INTERNAL -CSET pll_divclk_divide=1 -CSET pll_notes=None -CSET pll_ref_jitter=0.010 -CSET prim_in_freq=48.000 -CSET prim_in_jitter=0.010 -CSET prim_source=Single_ended_clock_capable_pin -CSET primtype_sel=DCM_CLKGEN -CSET relative_inclk=REL_PRIMARY -CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.010 -CSET secondary_source=Single_ended_clock_capable_pin -CSET summary_strings=empty -CSET use_clk_valid=true -CSET use_dyn_phase_shift=false -CSET use_dyn_reconfig=false -CSET use_freeze=false -CSET use_freq_synth=true -CSET use_inclk_stopped=false -CSET use_inclk_switchover=false -CSET use_locked=true -CSET use_max_i_jitter=false -CSET use_min_o_jitter=false -CSET use_min_power=false -CSET use_phase_alignment=false -CSET use_power_down=false -CSET use_reset=true -CSET use_spread_spectrum=false -CSET use_status=false -# END Parameters -GENERATE -# CRC: 6bde6d0 Index: usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/clean.sh =================================================================== --- usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/clean.sh (revision 2) +++ usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.vhd *.sh *.ise *.xco *.xise *.tcl" -subdirs="mem0" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.11/1.11c/memtest/fpga/ipcore_dir/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.11/1.11c/memtest/MemTest.java =================================================================== --- usb-fpga-1.11/1.11c/memtest/MemTest.java (revision 2) +++ usb-fpga-1.11/1.11c/memtest/MemTest.java (revision 3) @@ -1,6 +1,6 @@ /*! memtest -- DDR SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.11c - Copyright (C) 2009-2011 ZTEX GmbH. + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/standalone/standalone.c
1,6 → 1,6
/*!
standalone -- standalone firmware that supports FPGA configuration from Flash firmware loading from EEPROM for ZTEX USB-FPGA Module 1.11
Copyright (C) 2009-2011 ZTEX GmbH.
standalone -- standalone firmware that supports FPGA configuration from Flash firmware loading from EEPROM for ZTEX USB-FPGA Modules 1.11
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/flashbench/FlashBench.java
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.11
Copyright (C) 2009-2011 ZTEX GmbH.
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 1.11
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.11/flashbench/flashbench.c
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.11
Copyright (C) 2009-2011 ZTEX GmbH.
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 1.11
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/nvmtest/NVMTest.java
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test
Copyright (C) 2009-2010 ZTEX e.K.
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Modules 1.2 plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/nvmtest/nvmtest.c
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test
Copyright (C) 2009-2010 ZTEX e.K.
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Modules 1.2 plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/flashdemo/FlashDemo.java
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/flashdemo/flashdemo.c
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.2 plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.2 plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/standalone/standalone.c
1,6 → 1,6
/*!
standalone -- standalone firmware that supports FPGA configuration from Flash firmware loading from EEPROM for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/flashbench/FlashBench.java
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.2/flashbench/flashbench.c
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/nvmtest/NVMTest.java
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test on ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/nvmtest/nvmtest.c
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test on ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/flashdemo/FlashDemo.java
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/flashdemo/flashdemo.c
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/ucecho/avr/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for all EZ-USB devices
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/flashbench/FlashBench.java
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-xmega-1.0/flashbench/flashbench.c
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-XMEGA Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-1.0/flashdemo/FlashDemo.java
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-1.0/flashdemo/flashdemo.c
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-1.0/flashbench/FlashBench.java
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-1.0/flashbench/flashbench.c
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB Module 1.0
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.13/flashdemo/FlashDemo.java
0,0 → 1,160
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 2.13
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
 
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
import java.io.*;
import java.util.*;
 
import ch.ntb.usb.*;
 
import ztex.*;
 
// *****************************************************************************
// ******* ParameterException **************************************************
// *****************************************************************************
// Exception the prints a help message
class ParameterException extends Exception {
public final static String helpMsg = new String (
"Parameters:\n"+
" -d <number> Device Number (default: 0)\n" +
" -f Force uploads\n" +
" -p Print bus info\n" +
" -ue Upload Firmware to EEPROM\n" +
" -re Reset EEPROM Firmware\n" +
" -w Enable certain workarounds\n" +
" -h This help" );
public ParameterException (String msg) {
super( msg + "\n" + helpMsg );
}
}
 
// *****************************************************************************
// ******* Test0 ***************************************************************
// *****************************************************************************
class FlashDemo extends Ztex1v1 {
 
// ******* FlashDemo ***********************************************************
// constructor
public FlashDemo ( ZtexDevice1 pDev ) throws UsbException {
super ( pDev );
}
 
// ******* main ****************************************************************
public static void main (String args[]) {
int devNum = 0;
boolean force = false;
boolean workarounds = false;
try {
// init USB stuff
LibusbJava.usb_init();
 
// scan the USB bus
ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1);
if ( bus.numberOfDevices() <= 0) {
System.err.println("No devices found");
System.exit(0);
}
// scan the command line arguments
for (int i=0; i<args.length; i++ ) {
if ( args[i].equals("-d") ) {
i++;
try {
if (i>=args.length) throw new Exception();
devNum = Integer.parseInt( args[i] );
}
catch (Exception e) {
throw new ParameterException("Device number expected after -d");
}
}
else if ( args[i].equals("-f") ) {
force = true;
}
else if ( args[i].equals("-p") ) {
bus.printBus(System.out);
System.exit(0);
}
else if ( args[i].equals("-w") ) {
workarounds = true;
}
else if ( args[i].equals("-h") ) {
System.err.println(ParameterException.helpMsg);
System.exit(0);
}
else if ( !args[i].equals("-re") && !args[i].equals("-ue") )
throw new ParameterException("Invalid Parameter: "+args[i]);
}
 
// create the main class
FlashDemo ztex = new FlashDemo ( bus.device(devNum) );
ztex.certainWorkarounds = workarounds;
// upload the firmware if necessary
if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("Flash demo for UFM 2.13") ) {
System.out.println("Firmware upload time: " + ztex.uploadFirmware( "flashdemo.ihx", force ) + " ms");
}
for (int i=0; i<args.length; i++ ) {
if ( args[i].equals("-re") ) {
ztex.eepromDisable();
}
else if ( args[i].equals("-ue") ) {
System.out.println("Firmware to EEPROM upload time: " + ztex.eepromUpload( "flashdemo.ihx", force ) + " ms");
}
}
// print some information
System.out.println("Capabilities: " + ztex.capabilityInfo(", "));
System.out.println("Enabled: " + ztex.flashEnabled());
System.out.println("Size: " + ztex.flashSize());
if ( ztex.getFlashEC() == ztex.FLASH_EC_PENDING ) {
System.out.print("Another operation is pending. Waiting ..");
int i = 20;
do {
System.out.print(".");
try {
Thread.sleep( 1000 );
}
catch ( InterruptedException e) {
}
i--;
} while ( ztex.getFlashEC()==ztex.FLASH_EC_PENDING && i>0 );
System.out.println();
}
byte[] buf = new byte[ztex.flashSectorSize()];
ztex.flashReadSector(0,buf); // read out the last sector;
int sector = (buf[0] & 255) | ((buf[1] & 255) << 8) | ((buf[1] & 255) << 16) | ((buf[1] & 255) << 24);
System.out.println("Last sector: "+sector);
 
ztex.flashReadSector(sector,buf); // read out the string
int i=0;
while ( buf[i] != '\0'&& i < ztex.flashSectorSize() )
i++;
System.out.println("The string: `" + new String(buf,0,i)+ "'");
}
catch (Exception e) {
System.out.println("Error: "+e.getLocalizedMessage() );
}
}
}
/usb-fpga-2.13/flashdemo/flashdemo.c
0,0 → 1,65
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 2.13
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
 
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
#include[ztex-utils.h] // include basic functions and variables
 
// select ZTEX USB FPGA Module 2.13 as target (required for FPGA configuration)
IDENTITY_UFM_2_13(10.17.0.0,0);
 
// enable Flash support
ENABLE_FLASH;
 
// this product string is also used for identification by the host software
#define[PRODUCT_STRING]["Flash demo for UFM 2.13"]
 
__code char flash_string[] = "Hello World!";
 
// include the main part of the firmware kit, define the descriptors, ...
#include[ztex.h]
 
void main(void)
{
__xdata DWORD sector;
 
init_USB(); // init everything
 
if ( flash_enabled ) {
flash_read_init( 0 ); // prepare reading sector 0
flash_read((__xdata BYTE*) &sector, 4); // read the number of last sector
flash_read_finish(flash_sector_size - 4); // dummy-read the rest of the sector + finish read operation
 
sector++;
if ( sector > flash_sectors || sector == 0 ) {
sector = 1;
}
 
flash_write_init( 0 ); // prepare writing sector 0
flash_write((__xdata BYTE*) &sector, 4); // write the current sector number
flash_write_finish_sector(flash_sector_size - 4); // dummy-write the rest of the sector + CRC
flash_write_finish(); // finish write operation
 
flash_write_init( sector ); // prepare writing sector sector
flash_write((__xdata BYTE*) flash_string, sizeof(flash_string)); // write the string
flash_write_finish_sector(flash_sector_size - sizeof(flash_string)); // dummy-write the rest of the sector + CRC
flash_write_finish(); // finish write operation
}
 
while (1) { } // twiddle thumbs
}
 
/usb-fpga-2.13/flashdemo/flashdemo.bat
0,0 → 1,2
java -cp FlashDemo.jar FlashDemo
pause
/usb-fpga-2.13/flashdemo/flashdemo.sh
0,0 → 1,3
#make -C ../../../java distclean all || exit
#make distclean all || exit
java -cp FlashDemo.jar FlashDemo $@
usb-fpga-2.13/flashdemo/flashdemo.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/flashdemo/Makefile =================================================================== --- usb-fpga-2.13/flashdemo/Makefile (nonexistent) +++ usb-fpga-2.13/flashdemo/Makefile (revision 3) @@ -0,0 +1,23 @@ +######################### +# configuration section # +######################### + +ZTEXPREFIX=../../.. + +JARTARGET=FlashDemo.jar +CLASSTARGETS=FlashDemo.class +CLASSEXTRADEPS= + +IHXTARGETS=flashdemo.ihx +IHXEXTRADEPS= +EXTRAJARFILES=flashdemo.ihx +EXTRADISTCLEANFILES= + +default: all + +################################ +# DO NOT CHANAGE THE FOLLOWING # +################################ + +include $(ZTEXPREFIX)/Makefile.mk + Index: usb-fpga-2.13/flashdemo/Readme =================================================================== --- usb-fpga-2.13/flashdemo/Readme (nonexistent) +++ usb-fpga-2.13/flashdemo/Readme (revision 3) @@ -0,0 +1,16 @@ +flashdemo +--------- + +This example demonstrates how data can be read and written to/from the +Flash memory. + +During the start-up the firmware (defined in flashdemo.c) reads the +number of last sector n from sector 0 (dword at position 0) and +increments it by one. If n is larger than or equal to the total amount +of sectors, or if it is equal to 0, n is set to 1. + +Then n is written back to sector 0 and sector n is filled with the +string "Hello World!". + +The host software (defined in FlashDemo.java) reads out the string from +the last sector of the flash memory. Index: usb-fpga-2.13/2.13d/memfifo/MemFifo.java =================================================================== --- usb-fpga-2.13/2.13d/memfifo/MemFifo.java (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/MemFifo.java (revision 3) @@ -0,0 +1,477 @@ +/*! + memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ + +import java.io.*; +import java.util.*; +import java.text.*; + +import ch.ntb.usb.*; + +import ztex.*; + +// ***************************************************************************** +// ******* ParameterException ************************************************** +// ***************************************************************************** +// Exception the prints a help message +class ParameterException extends Exception { + public final static String helpMsg = new String ( + "Parameters:\n"+ + " -d Device Number (default: 0)\n" + + " -f Force uploads\n" + + " -p Print bus info\n" + + " -h This help" ); + + public ParameterException (String msg) { + super( msg + "\n" + helpMsg ); + } +} + +// ***************************************************************************** +// ******* USBReader *********************************************************** +// ***************************************************************************** +class UsbReader extends Thread { + private final int bufNum = 8; + public final int bufSize = 512*1024; + public byte[][] buf = new byte[bufNum][]; + public int[] bufBytes = new int[bufNum]; + private int readCount = -1; + private int getCount = -1; + public boolean terminate = false; + private Ztex1v1 ztex; + + public UsbReader ( Ztex1v1 p_ztex ) { + super (); + ztex = p_ztex; + for (int i=0; i= readCount) { + try { + sleep(1); + } + catch ( InterruptedException e) { + } + } + return getCount % bufNum; + } + + public void reset () { + getCount = readCount + 1; + } + + public void run() { + setPriority(MAX_PRIORITY); + +// reader loop + while ( !terminate ) { + readCount += 1; + + while ( readCount - bufNum >= getCount ) { + try { + sleep(1); + } + catch ( InterruptedException e) { + } + } + + int i = readCount % bufNum; + bufBytes[i] = LibusbJava.usb_bulk_read(ztex.handle(), 0x82, buf[i], bufSize, 1000); +// System.out.println("Buffer " + i +": read " + bufBytes[i] + " bytes"); + } + + } +} + +// ***************************************************************************** +// ******* UsbWriter *********************************************************** +// ***************************************************************************** +class UsbWriter extends Thread { + private final int bufNum = 8; + public final int bufSize = 512*1024; + public byte[][] buf = new byte[bufNum][]; + private int writeCount = -1; + private int getCount = -1; + public boolean terminate = false; + private Ztex1v1 ztex; + public int errorBuffferCount = -1; // buffer count if an error occurred; otherwise -1 + public int errorResult = 0; // error code or number of bytes if an error occurred + + public UsbWriter ( Ztex1v1 p_ztex ) { + super (); + ztex = p_ztex; + for (int i=0; i= writeCount) { + try { + sleep(1); + } + catch ( InterruptedException e) { + } + } + return getCount % bufNum; + } + + public void reset () { + getCount = writeCount + 1; + errorBuffferCount = -1; + } + + public void run() { + setPriority(MAX_PRIORITY); + +// writer loop + while ( !terminate ) { + writeCount += 1; + + while ( writeCount >= getCount ) { + try { + sleep(1); + } + catch ( InterruptedException e) { + } + } + + int i = writeCount % bufNum; + int j = LibusbJava.usb_bulk_write(ztex.handle(), 0x06, buf[i], bufSize, 1000); + if ( j != bufSize ) { + errorBuffferCount = writeCount; + errorResult = j; + } +// System.out.println("Buffer " + i +": wrote " + j + " bytes"); + } + + } +} + +// ***************************************************************************** +// ******* UsbTestWriter ******************************************************* +// ***************************************************************************** +class UsbTestWriter extends Thread { + public boolean terminate = false; + private UsbWriter writer; + + public UsbTestWriter ( Ztex1v1 p_ztex ) { + super (); + writer = new UsbWriter( p_ztex ); + } + + public boolean error () { + return writer.errorBuffferCount >= 0; + } + + public void run() { + writer.start(); + + int k = 0; + int cs = 47; + int sync; + Random random = new Random(); + while ( !terminate ) { + byte[] b = writer.buf[writer.getBuffer()]; + for ( int i=0; i>7))); + cs = 47; + } + else { +// b[i] = (byte) ( (j==0 ? (k>>4) & 127 : random.nextInt(128)) | sync ); + b[i] = (byte) ( (((k>>4)+j) & 127) | sync ); + cs += (b[i] & 255); + } + k=(k+1) & 65535; + } + } + + writer.terminate=true; + } +} + + +// ***************************************************************************** +// ******* MemFifo ************************************************************* +// ***************************************************************************** +class MemFifo extends Ztex1v1 { + + // constructor + public MemFifo ( ZtexDevice1 pDev ) throws UsbException { + super ( pDev ); + } + + // set mode + public void setMode( int i ) throws UsbException { + i = i & 3; + vendorCommand (0x80, "Set test mode", i, 0); + } + + // reset + public void reset( ) throws UsbException { + vendorCommand (0x81, "Reset:", 0, 0); + try { + Thread.sleep(300); + } + catch ( InterruptedException e) { + } + byte[] buf = new byte[4096]; + while ( LibusbJava.usb_bulk_read(handle(), 0x82, buf, buf.length, 100) == buf.length ) { }; // empties buffers + } + + // reads data and verifies them. + // returns true if errors occurred + // rate is data rate in kBytes; <=0 means unlimited + public boolean verify ( UsbReader reader, int iz, int rate ) { + boolean valid = false; + int byte_cnt = 0, sync_cnt = 0, cs = 47, first = 255, prev_first = 255; + boolean memError = false; + + for (int i=0; i0 && rate>0 ) { + try { + Thread.sleep(reader.bufSize/rate); + } + catch ( InterruptedException e) { + } + } + int j = reader.getBuffer(); + int bb = reader.bufBytes[j]; + byte[] b = reader.buf[j]; + int merrors = 0; + int ferrors = 0; + int serrors = 0; + boolean prev_sync = false; + + if ( bb != reader.bufSize ) { + System.out.println("Data read error"); + memError = true; + break; + } + +/* for ( int l=0; l<512; l+=1) { + System.out.print(" " + (b[l] & 255) ); + if ( (l & 15) == 15 ) System.out.println(); + } */ + + for (int k=0; k>7)) + " " + byte_cnt + " " + sync_cnt +" " + prev_first + " " + first ); + if ( sync_cnt == 3 ) { + boolean serror = byte_cnt != 16; + boolean merror = ( b[k] & 127 ) != ((cs & 127) ^ (cs>>7)); + boolean ferror = prev_sync && ( first != ((prev_first + 1) & 127) ); + prev_sync = byte_cnt == 16; +// valid = valid || ( !serror && !merror && !ferror ); + valid = valid || ( !serror && !merror ); + if ( valid ) { + if ( serror ) serrors += 1; + else if ( merror ) merrors += 1; + else if ( ferror ) ferrors += 1; + if ( serror && (serrors <= 2) && (k>=byte_cnt-1) && (k+1 (i==0 ? 1 : 0 ) ) { // one error in first buffer may occurs ofter changing mode + System.out.println(); + memError = true; + } + } + System.out.println(); + return memError; + } + +// ******* main **************************************************************** + public static void main (String args[]) { + + int devNum = 0; + boolean force = false; + + try { +// init USB stuff + LibusbJava.usb_init(); + +// scan the USB bus + ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1); + if ( bus.numberOfDevices() <= 0) { + System.err.println("No devices found"); + System.exit(0); + } + +// scan the command line arguments + for (int i=0; i=args.length) throw new Exception(); + devNum = Integer.parseInt( args[i] ); + } + catch (Exception e) { + throw new ParameterException("Device number expected after -d"); + } + } + else if ( args[i].equals("-f") ) { + force = true; + } + else if ( args[i].equals("-p") ) { + bus.printBus(System.out); + System.exit(0); + } + else if ( args[i].equals("-p") ) { + bus.printBus(System.out); + System.exit(0); + } + else if ( args[i].equals("-h") ) { + System.err.println(ParameterException.helpMsg); + System.exit(0); + } + else throw new ParameterException("Invalid Parameter: "+args[i]); + } + + String errStr = ""; + +// create the main class + MemFifo ztex = new MemFifo ( bus.device(devNum) ); + +// upload the firmware if necessary + if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("memfifo for UFM 2.13") ) { + System.out.println("Firmware upload time: " + ztex.uploadFirmware( "memfifo.ihx", force ) + " ms"); + force = true; + } + +// upload the bitstream if necessary + if ( force || ! ztex.getFpgaConfiguration() ) { + System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/memfifo.runs/impl_1/memfifo.bit" , force, -1 ) + " ms"); + } + +// claim tnterface + ztex.trySetConfiguration ( 1 ); + ztex.claimInterface ( 0 ); + +// reset FIFO's + if ( !force ) { + System.out.println("Resetting FIFO's"); + ztex.reset(); + } + +// PKTEND test +/* { + byte[] buf = new byte[65536]; + int i = LibusbJava.usb_bulk_write(ztex.handle(), 0x06, buf, buf.length, 1000); +// System.out.println("PKTEND test: wrote "+i+" bytes"); + // number of read bytes is usually less than number written bytes because DRAM FIFO is usually never completely emptied in order to avoid small transactions + i=LibusbJava.usb_bulk_read(ztex.handle(), 0x82, buf, buf.length, 1000); + // + int j = i & 511; + System.out.println("PKTEND test: read "+i+" bytes, last paket: " + (j == 0 ? 512 : j) + " bytes" ); + } */ + +// start traffic reader + UsbReader reader = new UsbReader( ztex ); + reader.start(); + +// Mode 1: 48 MByte/s Test data generator: used for speed test + ztex.setMode(1); + System.out.println("48 MByte/s test data generator: "); + long t0 = new Date().getTime(); + ztex.verify(reader, 2000, 0); + System.out.println("Read data rate: " + Math.round(reader.bufSize*2000.0/((new Date().getTime()-t0)*100.0)*0.1) + " MByte/s"); + + +// Mode 2: 12 MByte/s Test data generator: tests flow control + ztex.setMode(2); + System.out.println("12 MByte/s test data generator: "); + ztex.verify(reader, 2000, 0); + +// PKTEND test + { + byte[] buf = new byte[65536]; + int i; + while ( (i = LibusbJava.usb_bulk_write(ztex.handle(), 0x06, buf, buf.length, 1000)) == buf.length ) { } + int j = i & 511; + System.out.println("PKTEND test: last paket size: " + (j == 0 ? 512 : j) + " bytes" ); + } + +// Mode 0: write+read mode + ztex.reset(); + UsbTestWriter writer = new UsbTestWriter( ztex ); + writer.start(); + reader.reset(); + + System.out.println("USB write + read mode: speed test"); + t0 = new Date().getTime(); + ztex.verify(reader, 1000, 0); + System.out.println("Read data rate: " + Math.round(reader.bufSize*1000.0/((new Date().getTime()-t0)*100.0)*0.1) + " MByte/s"); + + System.out.println("USB write + read mode: 5 MByte/s read rate"); + ztex.verify(reader, 1000, 5000); + + if ( writer.error() ) System.out.println("Write errors occured"); + +// Terminating threads + writer.terminate=true; // stop the writer + reader.terminate=true; // stop the reader +/* for (int i=0; i<10000 && writer.isAlive() && reader.isAlive(); i++ ) { + if ( ( i % 1000 ) == 999 ) System.out.print("."); + try { + Thread.sleep(1); + } + catch ( InterruptedException e) { + } + } + System.out.println(); + +// releases interface + ztex.releaseInterface( 0 ); */ + + } + catch (Exception e) { + System.out.println("Error: "+e.getLocalizedMessage() ); + } + + } + +} Index: usb-fpga-2.13/2.13d/memfifo/memfifo.c =================================================================== --- usb-fpga-2.13/2.13d/memfifo/memfifo.c (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/memfifo.c (revision 3) @@ -0,0 +1,125 @@ +/*! + memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ +#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros +#include[ztex-utils.h] // include basic functions + +// configure endpoint 2, in, quad buffered, 512 bytes, interface 0 +EP_CONFIG(2,0,BULK,IN,512,4); + +// configure endpoint 6, out, double buffered, 512 bytes, interface 0 +EP_CONFIG(6,0,BULK,OUT,512,4); + +// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration) +IDENTITY_UFM_2_13(10.17.0.0,0); + +// this product string is also used for identification by the host software +#define[PRODUCT_STRING]["memfifo for UFM 2.13"] + +// enables high speed FPGA configuration via EP6 +ENABLE_HS_FPGA_CONF(6); + +// enable Flash support +ENABLE_FLASH; + +#define[MT_RESET][IOA7] +#define[MT_MODE0][IOA0] +#define[MT_MODE1][IOA1] + +// this is called automatically after FPGA configuration +#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG + reset (); +] + +// set mode +ADD_EP0_VENDOR_COMMAND((0x80,, + IOA = SETUPDAT[2] & 3; +,, + NOP; +));; + +// reset +ADD_EP0_VENDOR_COMMAND((0x81,, + reset(); +,, + NOP; +));; + +void reset () { + OEA = bmBIT0 | bmBIT1 | bmBIT7; + OEB = 0; + OED = 0; + MT_RESET = 1; + MT_MODE0 = 0; + MT_MODE1 = 0; + + EP2CS &= ~bmBIT0; // clear stall bit + EP6CS &= ~bmBIT0; // clear stall bit + + IFCONFIG = bmBIT7 | bmBIT6 | bmBIT5 | 3; // internal 48MHz clock, drive IFCLK output, slave FIFO interface +// IFCONFIG = bmBIT7 | bmBIT5 | 3; // internal 30MHz clock, drive IFCLK output, slave FIFO interface + SYNCDELAY; + + REVCTL = 0x1; + SYNCDELAY; + + FIFORESET = 0x80; // reset FIFO ... + SYNCDELAY; + FIFORESET = 2; // ... for EP 2 + SYNCDELAY; + FIFORESET = 0x00; + SYNCDELAY; + FIFORESET = 6; // ... for EP 6 + SYNCDELAY; + FIFORESET = 0x00; + SYNCDELAY; + + EP2FIFOCFG = bmBIT0; + SYNCDELAY; + EP2FIFOCFG = bmBIT3 | bmBIT0; // EP2: AUTOIN, WORDWIDE + SYNCDELAY; + EP2AUTOINLENH = 2; // 512 bytes + SYNCDELAY; + EP2AUTOINLENL = 0; + SYNCDELAY; + + EP6FIFOCFG = bmBIT0; + SYNCDELAY; + EP6FIFOCFG = bmBIT4 | bmBIT0; // EP6: 0 -> 1 transition of AUTOOUT bit arms the FIFO, WORDWIDE + SYNCDELAY; + + FIFOPINPOLAR = 0; + SYNCDELAY; + PINFLAGSAB = 0xca; // FLAGA: EP6: EF; FLAGB: EP2 FF + SYNCDELAY; + + MT_RESET = 0; +} + + +// include the main part of the firmware kit, define the descriptors, ... +#include[ztex.h] + +void main(void) +{ + init_USB(); + + while (1) { + } +} + + Index: usb-fpga-2.13/2.13d/memfifo/memfifo.sh =================================================================== --- usb-fpga-2.13/2.13d/memfifo/memfifo.sh (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/memfifo.sh (revision 3) @@ -0,0 +1,4 @@ +#make -C ../../../java distclean all || exit +#make distclean all || exit +#make || exit +java -cp MemFifo.jar MemFifo $@
usb-fpga-2.13/2.13d/memfifo/memfifo.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.xdc =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.xdc (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.xdc (revision 3) @@ -0,0 +1,140 @@ +# fxclk_in +create_clock -period 20.833 -name fxclk_in [get_ports fxclk_in] +set_property PACKAGE_PIN P15 [get_ports fxclk_in] +set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in] + +# IFCLK +create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in] +#create_clock -name ifclk_in -period 33.333 [get_ports ifclk_in] +set_property PACKAGE_PIN P17 [get_ports ifclk_in] +set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in] + +# source mode pins +set_property PACKAGE_PIN R15 [get_ports {mode[0]}] ;# PA0/INT0# +set_property PACKAGE_PIN T15 [get_ports {mode[1]}] ;# PA1/INT1# +set_property IOSTANDARD LVCMOS33 [get_ports {mode[*]}] +set_property PULLUP true [get_ports {mode[*]}] + +# PA7/FLAGD/SLCS# +set_property PACKAGE_PIN T10 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] + +# PB[0..9], PD[0..7] +set_property PACKAGE_PIN M16 [get_ports {fd[0]}] +set_property PACKAGE_PIN L16 [get_ports {fd[1]}] +set_property PACKAGE_PIN L14 [get_ports {fd[2]}] +set_property PACKAGE_PIN M14 [get_ports {fd[3]}] +set_property PACKAGE_PIN L18 [get_ports {fd[4]}] +set_property PACKAGE_PIN M18 [get_ports {fd[5]}] +set_property PACKAGE_PIN R12 [get_ports {fd[6]}] +set_property PACKAGE_PIN R13 [get_ports {fd[7]}] +set_property PACKAGE_PIN T9 [get_ports {fd[8]}] +set_property PACKAGE_PIN V10 [get_ports {fd[9]}] +set_property PACKAGE_PIN U11 [get_ports {fd[10]}] +set_property PACKAGE_PIN V11 [get_ports {fd[11]}] +set_property PACKAGE_PIN V12 [get_ports {fd[12]}] +set_property PACKAGE_PIN U13 [get_ports {fd[13]}] +set_property PACKAGE_PIN U14 [get_ports {fd[14]}] +set_property PACKAGE_PIN V14 [get_ports {fd[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fd[*]}] +set_property DRIVE 4 [get_ports {fd[*]}] + +# CTL0/FLAGA +set_property PACKAGE_PIN N16 [get_ports {FLAGA}] +set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}] + +# CTL1/FLAGB +set_property PACKAGE_PIN N15 [get_ports FLAGB] +set_property IOSTANDARD LVCMOS33 [get_ports FLAGB] + +# PA2/SLOE +set_property PACKAGE_PIN T14 [get_ports SLOE] +set_property IOSTANDARD LVCMOS33 [get_ports SLOE] + +# PA4/FIFOADR0 +set_property PACKAGE_PIN R11 [get_ports FIFOADDR0] +set_property IOSTANDARD LVCMOS33 [get_ports FIFOADDR0] + +# PA5/FIFOADR1 +set_property PACKAGE_PIN T11 [get_ports FIFOADDR1] +set_property IOSTANDARD LVCMOS33 [get_ports FIFOADDR1] + +# PA6/PKTEND +set_property PACKAGE_PIN R10 [get_ports PKTEND] +set_property IOSTANDARD LVCMOS33 [get_ports PKTEND] + +# RDY0/SLRD +set_property PACKAGE_PIN V16 [get_ports SLRD] +set_property IOSTANDARD LVCMOS33 [get_ports SLRD] + +# RDY1/SLWR +set_property PACKAGE_PIN U16 [get_ports SLWR] +set_property IOSTANDARD LVCMOS33 [get_ports SLWR] +#set_property DRIVE 4 [get_ports SLWR] +#set_property SLEW FAST [get_ports SLWR] + +# I/O delays +set_input_delay -clock ifclk_in -min 0 [get_ports {FLAG* fd[*]}] +set_input_delay -clock ifclk_in -max 15 [get_ports {FLAG* fd[*]}] +set_output_delay -clock ifclk_in -min 0 [get_ports {SLRD SLWR}] +set_output_delay -clock ifclk_in -max 15 [get_ports {SLRD SLWR}] + +# LED's +set_property PACKAGE_PIN H15 [get_ports {led1[0]}] ;# A6 / B21~IO_L21P_T3_DQS_16 +set_property PACKAGE_PIN J13 [get_ports {led1[1]}] ;# B6 / A21~IO_L21N_T3_DQS_16 +set_property PACKAGE_PIN J14 [get_ports {led1[2]}] ;# A7 / D20~IO_L19P_T3_16 +set_property PACKAGE_PIN H14 [get_ports {led1[3]}] ;# B7 / C20~IO_L19N_T3_VREF_16 +set_property PACKAGE_PIN H17 [get_ports {led1[4]}] ;# A8 / B20~IO_L16P_T2_16 +set_property PACKAGE_PIN G14 [get_ports {led1[5]}] ;# B8 / A20~IO_L16N_T2_16 +set_property PACKAGE_PIN G17 [get_ports {led1[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16 +set_property PACKAGE_PIN G16 [get_ports {led1[7]}] ;# B9 / A19~IO_L17N_T2_16 +set_property PACKAGE_PIN G18 [get_ports {led1[8]}] ;# A10 / C18~IO_L13P_T2_MRCC_16 +set_property PACKAGE_PIN H16 [get_ports {led1[9]}] ;# B10 / A18~IO_L17P_T2_16 +set_property IOSTANDARD LVCMOS33 [get_ports {led1[*]}] +set_property DRIVE 12 [get_ports {led1[*]}] + +set_property PACKAGE_PIN U9 [get_ports {led2[0]}] ;# C3 / AB17~IO_L2N_T0_13 +set_property PACKAGE_PIN V9 [get_ports {led2[1]}] ;# D3 / AB16~IO_L2P_T0_13 +set_property PACKAGE_PIN U8 [get_ports {led2[2]}] ;# C4 / Y16~IO_L1P_T0_13 +set_property PACKAGE_PIN V7 [get_ports {led2[3]}] ;# D4 / AA16~IO_L1N_T0_13 +set_property PACKAGE_PIN U7 [get_ports {led2[4]}] ;# C5 / AA15~IO_L4P_T0_13 +set_property PACKAGE_PIN V6 [get_ports {led2[5]}] ;# D5 / AB15~IO_L4N_T0_13 +set_property PACKAGE_PIN U6 [get_ports {led2[6]}] ;# C6 / Y13~IO_L5P_T0_13 +set_property PACKAGE_PIN V5 [get_ports {led2[7]}] ;# D6 / AA14~IO_L5N_T0_13 +set_property PACKAGE_PIN T8 [get_ports {led2[8]}] ;# C7 / W14~IO_L6P_T0_13 +set_property PACKAGE_PIN V4 [get_ports {led2[9]}] ;# D7 / Y14~IO_L6N_T0_VREF_13 +set_property PACKAGE_PIN R8 [get_ports {led2[10]}] ;# C8 / AA13~IO_L3P_T0_DQS_13 +set_property PACKAGE_PIN T5 [get_ports {led2[11]}] ;# D8 / AB13~IO_L3N_T0_DQS_13 +set_property PACKAGE_PIN R7 [get_ports {led2[12]}] ;# C9 / AB12~IO_L7N_T1_13 +set_property PACKAGE_PIN T4 [get_ports {led2[13]}] ;# D9 / AB11~IO_L7P_T1_13 +set_property PACKAGE_PIN T6 [get_ports {led2[14]}] ;# C10 / W12~IO_L12N_T1_MRCC_13 +set_property PACKAGE_PIN U4 [get_ports {led2[15]}] ;# D10 / W11~IO_L12P_T1_MRCC_13 +set_property PACKAGE_PIN R6 [get_ports {led2[16]}] ;# C11 / AA11~IO_L9N_T1_DQS_13 +set_property PACKAGE_PIN U3 [get_ports {led2[17]}] ;# D11 / AA10~IO_L9P_T1_DQS_13 +set_property PACKAGE_PIN R5 [get_ports {led2[18]}] ;# C12 / AA9~IO_L8P_T1_13 +set_property PACKAGE_PIN V1 [get_ports {led2[19]}] ;# D12 / AB10~IO_L8N_T1_13 +set_property IOSTANDARD LVCMOS33 [get_ports {led2[*]}] +set_property DRIVE 12 [get_ports {led2[*]}] + +# switches +#set_property PACKAGE_PIN F18 [get_ports SW7] ;# A11 / B18~IO_L11N_T1_SRCC_16 +set_property PACKAGE_PIN F16 [get_ports SW8] ;# B11 / D17~IO_L12P_T1_MRCC_16 +#set_property PACKAGE_PIN E18 [get_ports SW9] ;# A12 / B17~IO_L11P_T1_SRCC_16 +set_property PACKAGE_PIN F15 [get_ports SW10] ;# B12 / C17~IO_L12N_T1_MRCC_16 +set_property IOSTANDARD LVCMOS33 [get_ports {SW*}] +set_property PULLUP true [get_ports {SW*}] + +# location constraints +set_property LOC PLLE2_ADV_X1Y1 [get_cells dram_fifo_inst/dram_fifo_pll_inst] + +# TIG's +set_false_path -from [get_clocks *ifclk_out] -to [get_clocks *clk200] +set_false_path -from [get_clocks *ifclk_out] -to [get_clocks ] +set_false_path -from [get_clocks *clk_pll_i] -to [get_clocks *ifclk_out] + +# bitstream settings +set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] + Index: usb-fpga-2.13/2.13d/memfifo/fpga/ezusb_io.v =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/ezusb_io.v (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/ezusb_io.v (revision 3) @@ -0,0 +1,190 @@ +/*! + memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ +/* + Implements the EZ-USB Slave FIFO interface for both + directions. It also includes an scheduler (required if both + directions are used at the same time) and short packets (PKTEND). +*/ +module ezusb_io #( + parameter OUTEP = 2, // EP for FPGA -> EZ-USB transfers + parameter INEP = 6 // EP for EZ-USB -> FPGA transfers + ) ( + output ifclk, + input reset, // asynchronous reset input + output reset_out, // synchronous reset output + // pins + input ifclk_in, + inout [15:0] fd, + output reg SLWR, PKTEND, + output SLRD, SLOE, + output [1:0] FIFOADDR, + input EMPTY_FLAG, FULL_FLAG, + // signals for FPGA -> EZ-USB transfer + input [15:0] DI, // data written to EZ-USB + input DI_valid, // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0 + output DI_ready, // 1 if new data are accepted + input DI_enable, // setting to 0 disables FPGA -> EZ-USB transfers + input [15:0] pktend_timeout, // timeout in multiples of 65536 clocks before a short packet committed + // setting to 0 disables this feature + // signals for EZ-USB -> FPGA transfer + output reg [15:0] DO, // data read from EZ-USB + output reg DO_valid, // 1 indicated valid data + input DO_ready, // setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0 + // set to 0 to disable data reads + // debug output + output [3:0] status + ); + + + wire ifclk_inbuf, ifclk_fbin, ifclk_fbout, ifclk_out, locked; + + IBUFG ifclkin_buf ( + .I(ifclk_in), + .O(ifclk_inbuf) + ); + + BUFG ifclk_fb_buf ( + .I(ifclk_fbout), + .O(ifclk_fbin) + ); + + BUFG ifclk_out_buf ( + .I(ifclk_out), + .O(ifclk) + ); + + MMCME2_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(20.0), + .CLKFBOUT_PHASE(0.0), + .CLKIN1_PERIOD(0.0), + .CLKOUT0_DIVIDE_F(20.0), + .CLKOUT1_DIVIDE(1), + .CLKOUT2_DIVIDE(1), + .CLKOUT3_DIVIDE(1), + .CLKOUT4_DIVIDE(1), + .CLKOUT5_DIVIDE(1), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0.0), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_PHASE(0.0), + .CLKOUT3_PHASE(0.0), + .CLKOUT4_PHASE(0.0), + .CLKOUT5_PHASE(0.0), + .CLKOUT4_CASCADE("FALSE"), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.0), + .STARTUP_WAIT("FALSE") + ) isclk_mmcm_inst ( + .CLKOUT0(ifclk_out), + .CLKFBOUT(ifclk_fbout), + .CLKIN1(ifclk_inbuf), + .PWRDWN(1'b0), + .RST(reset), + .CLKFBIN(ifclk_fbin), + .LOCKED(locked) + ); + + reg reset_ifclk = 1; + reg if_out, if_in; + reg [4:0] if_out_buf; + reg [15:0] fd_buf; + reg resend; + reg SLRD_buf, pktend_req, pktend_en; + reg [31:0] pktend_cnt; + + // FPGA <-> EZ-USB signals + assign SLOE = if_out; +// assign FIFOADDR[0] = 1'b0; +// assign FIFOADDR[1] = !if_out; + assign FIFOADDR = if_out ? OUTEP/2-1 : INEP/2-1; + assign fd = if_out ? fd_buf : {16{1'bz}}; + assign SLRD = SLRD_buf || !DO_ready; + + assign status = { !SLRD_buf, !SLWR, resend, if_out }; + + assign DI_ready = !reset_ifclk && FULL_FLAG && if_out & if_out_buf[4] && !resend; + assign reset_out = reset || reset_ifclk; + + always @ (posedge ifclk) + begin + reset_ifclk <= reset || !locked; + // FPGA -> EZ-USB + if ( reset_ifclk ) + begin + SLWR <= 1'b1; + if_out <= DI_enable; // direction of EZ-USB interface: 1 means FPGA writes / EZ_USB reads + resend <= 1'b0; + SLRD_buf <= 1'b1; + if_out_buf = {5{!DI_enable}}; + end else if ( FULL_FLAG && if_out && if_out_buf[4] && ( resend || DI_valid) ) // FPGA -> EZ-USB + begin + SLWR <= 1'b0; + SLRD_buf <= 1'b1; + resend <= 1'b0; + if ( !resend ) fd_buf <= DI; + end else if ( EMPTY_FLAG && !if_out && !if_out_buf[4] && DO_ready ) // EZ-USB -> FPGA + begin + SLWR <= 1'b1; + DO <= fd; + SLRD_buf <= 1'b0; + end else if (if_out == if_out_buf[4]) + begin + if ( !SLWR && !FULL_FLAG ) resend <= 1'b1; // FLAGS are received two clocks after data. If FULL_FLAG was asserted last data was ignored and has to be re-sent. + SLRD_buf <= 1'b1; + SLWR <= 1'b1; + if_out <= DI_enable && (!DO_ready || !EMPTY_FLAG); + end + if_out_buf <= { if_out_buf[3:0], if_out }; + if ( DO_ready ) DO_valid <= !if_out && !if_out_buf[4] && EMPTY_FLAG && !SLRD_buf; // assertion of SLRD_buf takes two clocks to take effect + + // PKTEND processing + if ( reset_ifclk || DI_valid ) + begin + pktend_req <= 1'b0; + pktend_en <= !reset_ifclk; + pktend_cnt <= 32'd0; + PKTEND <= 1'b1; + end else + begin + pktend_req <= pktend_req || ( pktend_en && (pktend_timeout != 16'd0) && (pktend_timeout == pktend_cnt[31:16]) ); + pktend_cnt <= pktend_cnt + 1; + if ( pktend_req && if_out && if_out_buf[4] ) + begin + PKTEND <= 1'b0; + pktend_req <= 1'b0; + pktend_en <= 1'b0; + end else + begin + PKTEND <= 1'b1; + pktend_req <= pktend_req || ( pktend_en && (pktend_timeout != 16'd0) && (pktend_timeout == pktend_cnt[31:16]) ); + end + end + + + + end + + +endmodule + Index: usb-fpga-2.13/2.13d/memfifo/fpga/usb_fpga_2_13_mem.ucf =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/usb_fpga_2_13_mem.ucf (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/usb_fpga_2_13_mem.ucf (revision 3) @@ -0,0 +1,62 @@ +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41J128M16XX-125 +## Data Width: 16 +## Time Period: 2500 +## Data Mask: 1 +################################################################################################## + +############## NET - IOSTANDARD ################## + +NET "ddr3_dq[0]" LOC = "H1" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L13P_T2_MRCC_35 +NET "ddr3_dq[1]" LOC = "F1" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L13N_T2_MRCC_35 +NET "ddr3_dq[2]" LOC = "E2" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L14P_T2_SRCC_35 +NET "ddr3_dq[3]" LOC = "E1" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L14N_T2_SRCC_35 +NET "ddr3_dq[4]" LOC = "F4" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L16N_T2_35 +NET "ddr3_dq[5]" LOC = "C1" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L17P_T2_35 +NET "ddr3_dq[6]" LOC = "F3" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L17N_T2_35 +NET "ddr3_dq[7]" LOC = "D2" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L18P_T2_35 +NET "ddr3_dq[8]" LOC = "G4" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L20P_T3_35 +NET "ddr3_dq[9]" LOC = "H5" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L20N_T3_35 +NET "ddr3_dq[10]" LOC = "G3" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L22P_T3_35 +NET "ddr3_dq[11]" LOC = "H6" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L22N_T3_35 +NET "ddr3_dq[12]" LOC = "J2" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L23P_T3_35 +NET "ddr3_dq[13]" LOC = "J3" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L23N_T3_35 +NET "ddr3_dq[14]" LOC = "K1" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L24P_T3_35 +NET "ddr3_dq[15]" LOC = "K2" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L24N_T3_35 + +NET "ddr3_dqs_p[0]" LOC = "H2" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L15P_T2_DQS_35 +NET "ddr3_dqs_n[0]" LOC = "G2" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L15N_T2_DQS_35 +NET "ddr3_dqs_p[1]" LOC = "J4" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L21P_T3_DQS_35 +NET "ddr3_dqs_n[1]" LOC = "H4" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_40 ; # Pad function: IO_L21N_T3_DQS_35 + +NET "ddr3_addr[0]" LOC = "C5" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_AD7P_35 +NET "ddr3_addr[1]" LOC = "B6" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L8N_T1_AD14N_35 +NET "ddr3_addr[2]" LOC = "C7" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L8P_T1_AD14P_35 +NET "ddr3_addr[3]" LOC = "D5" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L7N_T1_AD6N_35 +NET "ddr3_addr[4]" LOC = "A3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L7P_T1_AD6P_35 +NET "ddr3_addr[5]" LOC = "E7" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L6P_T0_35 +NET "ddr3_addr[6]" LOC = "A4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L5N_T0_AD13N_35 +NET "ddr3_addr[7]" LOC = "C6" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L5P_T0_AD13P_35 +NET "ddr3_addr[8]" LOC = "A6" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L4N_T0_35 +NET "ddr3_addr[9]" LOC = "D8" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L4P_T0_35 +NET "ddr3_addr[10]" LOC = "B2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L2N_T0_AD12N_35 +NET "ddr3_addr[11]" LOC = "A5" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L2P_T0_AD12P_35 +NET "ddr3_addr[12]" LOC = "B3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L1N_T0_AD4N_35 +NET "ddr3_addr[13]" LOC = "B7" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L1P_T0_AD4P_35 +NET "ddr3_ba[0]" LOC = "E5" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L10N_T1_AD15N_35 +NET "ddr3_ba[1]" LOC = "A1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L10P_T1_AD15P_35 +NET "ddr3_ba[2]" LOC = "E6" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_AD7N_35 + +NET "ddr3_cas_n" LOC = "D3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_35 +NET "ddr3_cke[0]" LOC = "B1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_35 +NET "ddr3_ras_n" LOC = "E3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_35 +NET "ddr3_we_n" LOC = "D4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_35 +NET "ddr3_reset_n" LOC = "J5" | IOSTANDARD = LVCMOS15 | SLEW = FAST ; # Pad function: IO_L18N_T2_35 +NET "ddr3_odt[0]" LOC = "F5" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_0_35 +NET "ddr3_dm[0]" LOC = "G1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L16P_T2_35 +NET "ddr3_dm[1]" LOC = "G6" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L19P_T3_35 + +NET "ddr3_ck_p[0]" LOC = "C4" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_AD5P_35 +NET "ddr3_ck_n[0]" LOC = "B4" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_AD5N_35 + \ No newline at end of file Index: usb-fpga-2.13/2.13d/memfifo/fpga/usb_fpga_2_13_mem.xdc =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/usb_fpga_2_13_mem.xdc (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/usb_fpga_2_13_mem.xdc (revision 3) @@ -0,0 +1,351 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Sa. Dez 7 15:38:25 2013 +## Generated by MIG Version 2.0 +## +################################################################################################## +## File name : mig_7series_0.xdc +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A100T-CSG324 +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 303.03 MHz +## Time Period: 3300 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41J128M16XX-125 +## Data Width: 16 +## Time Period: 3300 +## Data Mask: 1 +################################################################################################## + +#create_clock -name sys_clk_i -period 3.3 [get_ports sys_clk_i] +#set_propagated_clock sys_clk_i + +#create_clock -name clk_ref_i -period 5 [get_ports clk_ref_i] +#set_propagated_clock clk_ref_i + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L17P_T2_35 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN H1 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L18P_T2_35 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L14P_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L18N_T2_35 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN F4 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L16N_T2_35 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN C1 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L14N_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L20P_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN G4 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L24N_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN H5 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L20N_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L24P_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN H6 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L22N_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN J2 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L22P_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN J3 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L23N_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L23P_T3_35 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_L2P_T0_AD12P_35 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L10P_T1_AD15P_35 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN B3 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L3N_T0_DQS_AD5N_35 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN A5 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L10N_T1_AD15N_35 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L4P_T0_35 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN D8 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L3P_T0_DQS_AD5P_35 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN A6 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L1P_T0_AD4P_35 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN C6 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L8P_T1_AD14P_35 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN A4 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L6P_T0_35 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN E7 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L8N_T1_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN A3 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN D5 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L4N_T0_35 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN C7 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L2N_T0_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN B6 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L1N_T0_AD4N_35 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN C5 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L5P_T0_AD13P_35 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN E6 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L9N_T1_DQS_AD7N_35 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN A1 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L5N_T0_AD13N_35 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN E5 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L12N_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN D3 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN D4 [get_ports {ddr3_we_n}] + +# PadFunction: IO_25_35 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L9P_T1_DQS_AD7P_35 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_0_35 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN F5 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L17N_T2_35 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L19P_T3_35 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN G6 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L15P_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L15N_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN G2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L21P_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L21N_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L7P_T1_AD6P_35 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN C4 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L7N_T1_AD6N_35 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN B4 [get_ports {ddr3_ck_n[0]}] + + + +set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] + +## set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] + + + +set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] + +set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] + +set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + +set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + +set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ *ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] + +set_property LOC PLLE2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ *u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ *u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ *mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ *input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ *mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ *input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +#set_multicycle_path -from [get_cells -hier -filter {NAME =~ *mc0/mc_read_idle_r*}] \ +# -to [get_cells -hier -filter {NAME =~ *input_[?].iserdes_dq_.iserdesdq}] \ +# -setup 6 + +#set_multicycle_path -from [get_cells -hier -filter {NAME =~ *mc0/mc_read_idle_r*}] \ +# -to [get_cells -hier -filter {NAME =~ *input_[?].iserdes_dq_.iserdesdq}] \ +# -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ *DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ *OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ *OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ *RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +#set_max_delay -from [get_cells -hier rstdiv0_sync_r1*] -to [get_pins -filter {NAME =~ *RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 + +set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20 +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*rst_r1*}] 20 + \ No newline at end of file Index: usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.v =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.v (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.v (revision 3) @@ -0,0 +1,292 @@ +/*! + memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ +/* + Top level module: glues everything together. +*/ + +`define IDX(x) (((x)+1)*(8)-1):((x)*(8)) + +module memfifo ( + input fxclk_in, + input ifclk_in, + input reset, + input [1:0] mode, + // debug + output [9:0] led1, + output [19:0] led2, + input SW8, + input SW10, + // ddr3 + inout [15:0] ddr3_dq, + inout [1:0] ddr3_dqs_n, + inout [1:0] ddr3_dqs_p, + output [13:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [0:0] ddr3_ck_p, + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, + output [1:0] ddr3_dm, + output [0:0] ddr3_odt, + // ez-usb + inout [15:0] fd, + output SLWR, SLRD, + output SLOE, FIFOADDR0, FIFOADDR1, PKTEND, + input FLAGA, FLAGB + ); + + wire reset_mem, reset_usb; + wire ifclk; + reg reset_ifclk; + wire [24:0] mem_free; + wire [9:0] status; + wire [3:0] if_status; + reg [1:0] mode_buf; + + // input fifo + reg [127:0] DI; + wire FULL, WRERR, USB_DO_valid; + reg WREN, wrerr_buf; + wire [15:0] USB_DO; + reg [127:0] in_data; + reg [3:0] wr_cnt; + reg [6:0] test_cnt; + reg [13:0] test_cs; + reg in_valid; + wire test_sync; + reg [1:0] clk_div; + + // output fifo + wire [127:0] DO; + wire EMPTY, RDERR, USB_DI_ready; + reg RDEN, rderr_buf, USB_DI_valid; + reg [127:0] rd_buf; + reg [2:0] rd_cnt; + + dram_fifo #( + .FIRST_WORD_FALL_THROUGH("TRUE"), // Sets the FIFO FWFT to FALSE, TRUE + .ALMOST_EMPTY_OFFSET2(13'h0008), + ) dram_fifo_inst ( + .fxclk_in(fxclk_in), // 48 MHz input clock pin + .reset(reset || reset_usb), + .reset_out(reset_mem), // reset output + .clkout2(), // PLL clock outputs not used for memory interface + .clkout3(), + .clkout4(), + .clkout5(), + // Memory interface ports + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + // input fifo interface, see "7 Series Memory Resources" user guide (ug743) + .DI(DI), + .FULL(FULL), // 1-bit output: Full flag + .ALMOSTFULL1(), // 1-bit output: Almost full flag + .ALMOSTFULL2(), // 1-bit output: Almost full flag + .WRERR(WRERR), // 1-bit output: Write error + .WREN(WREN), // 1-bit input: Write enable + .WRCLK(ifclk), // 1-bit input: Rising edge write clock. + // output fifo interface, see "7 Series Memory Resources" user guide (ug743) + .DO(DO), + .EMPTY(EMPTY), // 1-bit output: Empty flag + .ALMOSTEMPTY1(), // 1-bit output: Almost empty flag + .ALMOSTEMPTY2(), // 1-bit output: Almost empty flag + .RDERR(RDERR), // 1-bit output: Read error + .RDCLK(ifclk), // 1-bit input: Read clock + .RDEN(RDEN), // 1-bit input: Read enable + // free memory + .mem_free_out(mem_free), + // for debugging + .status(status) + ); + + ezusb_io #( + .OUTEP(2), // EP for FPGA -> EZ-USB transfers + .INEP(6), // EP for EZ-USB -> FPGA transfers + ) ezusb_io_inst ( + .ifclk(ifclk), + .reset(reset), // asynchronous reset input + .reset_out(reset_usb), // synchronous reset output + // pins + .ifclk_in(ifclk_in), + .fd(fd), + .SLWR(SLWR), + .SLRD(SLRD), + .SLOE(SLOE), + .PKTEND(PKTEND), + .FIFOADDR({FIFOADDR1, FIFOADDR0}), + .EMPTY_FLAG(FLAGA), + .FULL_FLAG(FLAGB), + // signals for FPGA -> EZ-USB transfer + .DI(rd_buf[15:0]), // data written to EZ-USB + .DI_valid(USB_DI_valid), // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0 + .DI_ready(USB_DI_ready), // 1 if new data are accepted + .DI_enable(1'b1), // setting to 0 disables FPGA -> EZ-USB transfers + .pktend_timeout(16'd73), // timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed + // setting to 0 disables this feature + // signals for EZ-USB -> FPGA transfer + .DO(USB_DO), // data read from EZ-USB + .DO_valid(USB_DO_valid), // 1 indicated valid data + .DO_ready((mode_buf==2'd0) && !reset_ifclk && !FULL), // setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0 + // debug output + .status(if_status) + ); + +/* BUFR ifclkin_buf ( + .I(ifclk_in), + .O(ifclk) + ); */ +// assign ifclk = ifclk_in; + + // debug board LEDs + assign led1 = SW10 ? status : { EMPTY, FULL, wrerr_buf, rderr_buf, if_status, FLAGB, FLAGA }; + + assign led2[0] = mem_free != { 1'b1, 24'd0 }; + assign led2[1] = mem_free[23:19] < 5'd30; + assign led2[2] = mem_free[23:19] < 5'd29; + assign led2[3] = mem_free[23:19] < 5'd27; + assign led2[4] = mem_free[23:19] < 5'd25; + assign led2[5] = mem_free[23:19] < 5'd24; + assign led2[6] = mem_free[23:19] < 5'd22; + assign led2[7] = mem_free[23:19] < 5'd20; + assign led2[8] = mem_free[23:19] < 5'd19; + assign led2[9] = mem_free[23:19] < 5'd17; + assign led2[10] = mem_free[23:19] < 5'd15; + assign led2[11] = mem_free[23:19] < 5'd13; + assign led2[12] = mem_free[23:19] < 5'd12; + assign led2[13] = mem_free[23:19] < 5'd10; + assign led2[14] = mem_free[23:19] < 5'd8; + assign led2[15] = mem_free[23:19] < 5'd7; + assign led2[16] = mem_free[23:19] < 5'd5; + assign led2[17] = mem_free[23:19] < 5'd3; + assign led2[18] = mem_free[23:19] < 5'd2; + assign led2[19] = mem_free == 25'd0; + + assign test_sync = wr_cnt[0] || (wr_cnt == 4'd14); + + always @ (posedge ifclk) + begin + reset_ifclk <= reset || reset_usb || reset_mem; + + if ( reset_ifclk ) + begin + rderr_buf <= 1'b0; + wrerr_buf <= 1'b0; + end else + begin + rderr_buf <= rderr_buf || RDERR; + wrerr_buf <= wrerr_buf || WRERR; + end + + // FPGA -> EZ-USB FIFO + if ( reset_ifclk ) + begin + rd_cnt <= 3'd0; + USB_DI_valid <= 1'd0; + end else if ( USB_DI_ready ) + begin + USB_DI_valid <= !EMPTY; + if ( !EMPTY ) + begin + if ( rd_cnt == 3'd0 ) + begin + rd_buf <= DO; + end else + begin + rd_buf[111:0] <= rd_buf[127:16]; + end + rd_cnt <= rd_cnt+1; + end + end + + RDEN <= !reset_ifclk && USB_DI_ready && !EMPTY && (rd_cnt==3'd0); + + if ( reset_ifclk ) + begin + in_data <= 128'd0; + in_valid <= 1'b0; + wr_cnt <= 4'd0; + test_cnt <= 7'd0; + test_cs <= 12'd47; + WREN <= 1'b0; + clk_div <= 2'd3; + end else if ( !FULL ) + begin + if ( in_valid ) DI <= in_data; + + if ( mode_buf == 2'd0 ) // input from USB + begin + if ( USB_DO_valid ) + begin + in_data <= { USB_DO, in_data[127:16] }; + in_valid <= wr_cnt[2:0] == 3'd7; + wr_cnt <= wr_cnt + 1; + end else + begin + in_valid <= 1'b0; + end + end else if ( clk_div == 2'd0 ) // test data generator + begin + if ( wr_cnt == 4'd15 ) + begin + test_cs <= 12'd47; + in_data[126:120] <= test_cs[6:0] ^ test_cs[13:7]; + in_valid <= 1'b1; + end else + begin + test_cnt <= test_cnt + 7'd111; + test_cs <= test_cs + { test_sync, test_cnt }; + in_data[126:120] <= test_cnt; + in_valid <= 1'b0; + end + in_data[127] <= test_sync; + in_data[119:0] <= in_data[127:8]; + wr_cnt <= wr_cnt + 1; + end else + begin + in_valid <= 1'b0; + end + + if ( (mode_buf==2'd1) || ((mode_buf==2'd3) && SW8 ) ) + begin + clk_div <= 2'd0; // data rate: 48 MByte/s + end else + begin + clk_div <= clk_div + 1; // data rate: 12 MByte/s + end + end + WREN <= !reset_ifclk && in_valid && !FULL; + mode_buf<=mode; + end + +endmodule + Index: usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.xpr =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.xpr (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.xpr (revision 3) @@ -0,0 +1,19 @@ + + + + + + + + + + + + + Index: usb-fpga-2.13/2.13d/memfifo/fpga/dram_fifo.v =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/dram_fifo.v (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/dram_fifo.v (revision 3) @@ -0,0 +1,853 @@ +/*! + memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ +/* + Implements a huge FIFO from all SDRAM. +*/ + +module fifo_512x128 #( + parameter ALMOST_EMPTY_OFFSET1 = 13'h0020, // Sets the almost empty threshold + parameter ALMOST_EMPTY_OFFSET2 = 13'h0006, // Sets the almost empty threshold + parameter ALMOST_FULL_OFFSET1 = 13'h0020, // Sets almost full threshold + parameter ALMOST_FULL_OFFSET2 = 13'h0006, // Sets almost full threshold + parameter FIRST_WORD_FALL_THROUGH = "TRUE" // Sets the FIFO FWFT to FALSE, TRUE + ) ( + input RST, // 1-bit input: Reset + // input signals + input [127:0] DI, // 64-bit input: Data input + output FULL, // 1-bit output: Full flag + output ALMOSTFULL1, // 1-bit output: Almost full flag + output ALMOSTFULL2, // 1-bit output: Almost full flag + output WRERR, // 1-bit output: Write error + input WRCLK, // 1-bit input: Rising edge write clock. + input WREN, // 1-bit input: Write enable + // output signals + output [127:0] DO, + output EMPTY, // 1-bit output: Empty flag + output ALMOSTEMPTY1, // 1-bit output: Almost empty flag + output ALMOSTEMPTY2, // 1-bit output: Almost empty flag + output RDERR, // 1-bit output: Read error + input RDCLK, // 1-bit input: Read clock + input RDEN // 1-bit input: Read enable + ); + + FIFO36E1 #( + .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET1), + .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET1), + .DATA_WIDTH(72), + .DO_REG(1), + .EN_ECC_READ("TRUE"), + .EN_ECC_WRITE("TRUE"), + .EN_SYN("FALSE"), + .FIFO_MODE("FIFO36_72"), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH), + .INIT(72'h000000000000000000), + .SIM_DEVICE("7SERIES"), + .SRVAL(72'h000000000000000000) + ) + U ( + .DBITERR(), + .ECCPARITY(), + .SBITERR(), + .DO(DO[127:64]), + .DOP(), + .ALMOSTEMPTY(ALMOSTEMPTY1), + .ALMOSTFULL(ALMOSTFULL1), + .EMPTY(EMPTY_U), + .FULL(FULL_U), + .RDCOUNT(), + .RDERR(RDERR_U), + .WRCOUNT(), + .WRERR(WRERR_U), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDCLK(RDCLK), + .RDEN(RDEN), + .REGCE(1'b0), + .RST(RST), + .RSTREG(1'b0), + .WRCLK(WRCLK), + .WREN(WREN), + .DI(DI[127:64]), + .DIP(4'd0) + ); + + FIFO36E1 #( + .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET2), + .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET2), + .DATA_WIDTH(72), + .DO_REG(1), + .EN_ECC_READ("TRUE"), + .EN_ECC_WRITE("TRUE"), + .EN_SYN("FALSE"), + .FIFO_MODE("FIFO36_72"), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH), + .INIT(72'h000000000000000000), + .SIM_DEVICE("7SERIES"), + .SRVAL(72'h000000000000000000) + ) + L ( + .DBITERR(), + .ECCPARITY(), + .SBITERR(), + .DO(DO[63:0]), + .DOP(), + .ALMOSTEMPTY(ALMOSTEMPTY2), + .ALMOSTFULL(ALMOSTFULL2), + .EMPTY(EMPTY_L), + .FULL(FULL_L), + .RDCOUNT(), + .RDERR(RDERR_L), + .WRCOUNT(), + .WRERR(WRERR_L), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDCLK(RDCLK), + .RDEN(RDEN), + .REGCE(1'b0), + .RST(RST), + .RSTREG(1'b0), + .WRCLK(WRCLK), + .WREN(WREN), + .DI(DI[63:0]), + .DIP(4'd0) + ); + + assign EMPTY = EMPTY_U || EMPTY_L; + assign FULL = FULL_U || FULL_L; + assign RDERR = RDERR_U || RDERR_L; + assign WRERR = WRERR_U || WRERR_L; + +endmodule + + +module dram_fifo # ( + // fifo parameters, see "7 Series Memory Resources" user guide (ug743) + parameter ALMOST_EMPTY_OFFSET1 = 13'h0010, // Sets the almost empty threshold + parameter ALMOST_EMPTY_OFFSET2 = 13'h0001, // Sets the almost empty threshold + parameter ALMOST_FULL_OFFSET1 = 13'h0010, // Sets almost full threshold + parameter ALMOST_FULL_OFFSET2 = 13'h0001, // Sets almost full threshold + parameter FIRST_WORD_FALL_THROUGH = "TRUE", // Sets the FIFO FWFT to FALSE, TRUE + // clock dividers for PLL outputs not used for memory interface, VCO frequency is 1200 MHz + parameter CLKOUT2_DIVIDE = 1, + parameter CLKOUT3_DIVIDE = 1, + parameter CLKOUT4_DIVIDE = 1, + parameter CLKOUT5_DIVIDE = 1, + parameter CLKOUT2_PHASE = 0.0, + parameter CLKOUT3_PHASE = 0.0, + parameter CLKOUT4_PHASE = 0.0, + parameter CLKOUT5_PHASE = 0.0 + ) ( + input fxclk_in, // 48 MHz input clock pin + input reset, + output reset_out, // reset output + output clkout2, clkout3, clkout4, clkout5, // PLL clock outputs not used for memory interface + + // ddr3 pins + inout [15:0] ddr3_dq, + inout [1:0] ddr3_dqs_n, + inout [1:0] ddr3_dqs_p, + output [13:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [0:0] ddr3_ck_p, + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, + output [1:0] ddr3_dm, + output [0:0] ddr3_odt, + + // input fifo interface, see "7 Series Memory Resources" user guide (ug743) + input [127:0] DI, // 64-bit input: Data input + output FULL, // 1-bit output: Full flag + output ALMOSTFULL1, // 1-bit output: Almost full flag + output ALMOSTFULL2, // 1-bit output: Almost full flag + output WRERR, // 1-bit output: Write error + input WRCLK, // 1-bit input: Rising edge write clock. + input WREN, // 1-bit input: Write enable + + // output fifo interface, see "7 Series Memory Resources" user guide (ug743) + output [127:0] DO, + output EMPTY, // 1-bit output: Empty flag + output ALMOSTEMPTY1, // 1-bit output: Almost empty flag + output ALMOSTEMPTY2, // 1-bit output: Almost empty flag + output RDERR, // 1-bit output: Read error + input RDCLK, // 1-bit input: Read clock + input RDEN, // 1-bit input: Read enable + + // free memory + output [APP_ADDR_WIDTH:0] mem_free_out, + + // for debugging + output [9:0] status + ); + + localparam APP_DATA_WIDTH = 128; + localparam APP_MASK_WIDTH = 16; + localparam APP_ADDR_WIDTH = 24; + + wire pll_fb, clk200_in, clk67_in, clk200, clk67, uiclk, fxclk; + + wire mem_reset, ui_clk_sync_rst, init_calib_complete; + reg reset_buf; + +// memory control + reg [7:0] wr_cnt, rd_cnt; + reg [APP_ADDR_WIDTH-1:0] mem_wr_addr, mem_rd_addr; + reg [APP_ADDR_WIDTH:0] mem_free; + reg rd_mode, wr_mode_buf; + wire wr_mode; + +// fifo control + wire infifo_empty, infifo_almost_empty, outfifo_almost_full, infifo_rden; + wire [APP_DATA_WIDTH-1:0] infifo_do; + reg [5:0] outfifo_pending; + reg [9:0] rd_cnt_dbg; + +// debug + wire infifo_err_w, outfifo_err_w; + reg infifo_err, outfifo_err, outfifo_err_uf; + +// memory interface + reg [APP_ADDR_WIDTH-1:0] app_addr; + reg [2:0] app_cmd; + reg app_en, app_wdf_wren; + wire app_rdy, app_wdf_rdy, app_rd_data_valid; + reg [APP_DATA_WIDTH-1:0] app_wdf_data; + wire [APP_DATA_WIDTH-1:0] app_rd_data; + + BUFG fxclk_buf ( + .I(fxclk_in), + .O(fxclk) + ); + + PLLE2_BASE #( + .BANDWIDTH("LOW"), + .CLKFBOUT_MULT(25), // f_VCO = 1200 MHz (valid: 800 .. 1600 MHz) + .CLKFBOUT_PHASE(0.0), + .CLKIN1_PERIOD(0.0), + .CLKOUT0_DIVIDE(18), // 66.666 MHz + .CLKOUT1_DIVIDE(6), // 200 MHz + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0.0), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.0), + .STARTUP_WAIT("FALSE") + ) + dram_fifo_pll_inst ( + .CLKIN1(fxclk), + .CLKOUT0(clk67), + .CLKOUT1(clk200), + .CLKOUT2(clkout2), + .CLKOUT3(clkout3), + .CLKOUT4(clkout4), + .CLKOUT5(clkout5), + .CLKFBOUT(pll_fb), + .CLKFBIN(pll_fb), + .PWRDWN(1'b0), + .RST(1'b0) + ); + + fifo_512x128 #( + .ALMOST_EMPTY_OFFSET1(13'h0026), + .ALMOST_EMPTY_OFFSET2(13'h0006), + .ALMOST_FULL_OFFSET1(ALMOST_FULL_OFFSET1), + .ALMOST_FULL_OFFSET2(ALMOST_FULL_OFFSET2), + .FIRST_WORD_FALL_THROUGH("TRUE") + ) infifo ( + .RST(reset_buf), + // output + .DO(infifo_do), + .EMPTY(infifo_empty), + .ALMOSTEMPTY1(infifo_almost_empty), + .ALMOSTEMPTY2(), + .RDERR(infifo_err_w), + .RDCLK(uiclk), + .RDEN(infifo_rden), + // input + .DI(DI), + .FULL(FULL), + .ALMOSTFULL1(ALMOSTFULL1), + .ALMOSTFULL2(ALMOSTFULL2), + .WRERR(WRERR), + .WRCLK(WRCLK), + .WREN(WREN) + ); + + fifo_512x128 #( + .ALMOST_FULL_OFFSET1(13'h0044), + .ALMOST_FULL_OFFSET2(13'h0004), + .ALMOST_EMPTY_OFFSET1(ALMOST_EMPTY_OFFSET1), + .ALMOST_EMPTY_OFFSET2(ALMOST_EMPTY_OFFSET2), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH) + ) outfifo ( + .RST(reset_buf), + // output + .DO(DO), + .EMPTY(EMPTY), + .ALMOSTEMPTY1(ALMOSTEMPTY1), + .ALMOSTEMPTY2(ALMOSTEMPTY2), + .RDERR(RDERR), + .RDCLK(RDCLK), + .RDEN(RDEN), + // input + .DI(app_rd_data), + .FULL(), + .ALMOSTFULL1(outfifo_almost_full), + .ALMOSTFULL2(), + .WRERR(outfifo_err_w), + .WRCLK(uiclk), + .WREN(app_rd_data_valid) + ); + + mig_7series_0 # ( + //*************************************************************************** + // The following parameters refer to width of various ports + //*************************************************************************** + .BANK_WIDTH (3), + // # of memory Bank Address bits. + .CK_WIDTH (1), + // # of CK/CK# outputs to memory. + .COL_WIDTH (10), + // # of memory Column Address bits. + .CS_WIDTH (1), + // # of unique CS outputs to memory. + .nCS_PER_RANK (1), + // # of unique CS outputs per rank for phy + .CKE_WIDTH (1), + // # of CKE outputs to memory. + .DATA_BUF_ADDR_WIDTH (5), + .DQ_CNT_WIDTH (4), + // = ceil(log2(DQ_WIDTH)) + .DQ_PER_DM (8), + .DM_WIDTH (2), + // # of DM (data mask) + .DQ_WIDTH (16), + // # of DQ (data) + .DQS_WIDTH (2), + .DQS_CNT_WIDTH (1), + // = ceil(log2(DQS_WIDTH)) + .DRAM_WIDTH (8), + // # of DQ per DQS + .ECC ("OFF"), + .DATA_WIDTH (16), + .ECC_TEST ("OFF"), + .PAYLOAD_WIDTH (16), + .nBANK_MACHS (4), + .RANKS (1), + // # of Ranks. + .ODT_WIDTH (1), + // # of ODT outputs to memory. + .ROW_WIDTH (14), + // # of memory Row Address bits. + .ADDR_WIDTH (28), + // # = RANK_WIDTH + BANK_WIDTH + // + ROW_WIDTH + COL_WIDTH; + // Chip Select is always tied to low for + // single rank devices + .USE_CS_PORT (0), + // # = 1, When Chip Select (CS#) output is enabled + // = 0, When Chip Select (CS#) output is disabled + // If CS_N disabled, user must connect + // DRAM CS_N input(s) to ground + .USE_DM_PORT (1), + // # = 1, When Data Mask option is enabled + // = 0, When Data Mask option is disbaled + // When Data Mask option is disabled in + // MIG Controller Options page, the logic + // related to Data Mask should not get + // synthesized + .USE_ODT_PORT (1), + // # = 1, When ODT output is enabled + // = 0, When ODT output is disabled + .PHY_CONTROL_MASTER_BANK (0), + // The bank index where master PHY_CONTROL resides, + // equal to the PLL residing bank + + //*************************************************************************** + // The following parameters are mode register settings + //*************************************************************************** + .AL ("0"), + // DDR3 SDRAM: + // Additive Latency (Mode Register 1). + // # = "0", "CL-1", "CL-2". + // DDR2 SDRAM: + // Additive Latency (Extended Mode Register). + .nAL (0), + // # Additive Latency in number of clock + // cycles. + .BURST_MODE ("8"), + // DDR3 SDRAM: + // Burst Length (Mode Register 0). + // # = "8", "4", "OTF". + // DDR2 SDRAM: + // Burst Length (Mode Register). + // # = "8", "4". + .BURST_TYPE ("SEQ"), + // DDR3 SDRAM: Burst Type (Mode Register 0). + // DDR2 SDRAM: Burst Type (Mode Register). + // # = "SEQ" - (Sequential), + // = "INT" - (Interleaved). + .CL (7), + // in number of clock cycles + // DDR3 SDRAM: CAS Latency (Mode Register 0). + // DDR2 SDRAM: CAS Latency (Mode Register). + .CWL (6), + // in number of clock cycles + // DDR3 SDRAM: CAS Write Latency (Mode Register 2). + // DDR2 SDRAM: Can be ignored + .OUTPUT_DRV ("HIGH"), + // Output Driver Impedance Control (Mode Register 1). + // # = "HIGH" - RZQ/7, + // = "LOW" - RZQ/6. + .RTT_NOM ("40"), + // RTT_NOM (ODT) (Mode Register 1). + // # = "DISABLED" - RTT_NOM disabled, + // = "120" - RZQ/2, + // = "60" - RZQ/4, + // = "40" - RZQ/6. + .RTT_WR ("OFF"), + // RTT_WR (ODT) (Mode Register 2). + // # = "OFF" - Dynamic ODT off, + // = "120" - RZQ/2, + // = "60" - RZQ/4, + .ADDR_CMD_MODE ("1T" ), + // # = "1T", "2T". + .REG_CTRL ("OFF"), + // # = "ON" - RDIMMs, + // = "OFF" - Components, SODIMMs, UDIMMs. + .CA_MIRROR ("OFF"), + // C/A mirror opt for DDR3 dual rank + + //*************************************************************************** + // The following parameters are multiplier and divisor factors for PLLE2. + // Based on the selected design frequency these parameters vary. + //*************************************************************************** + .CLKIN_PERIOD (15000), + // Input Clock Period + .CLKFBOUT_MULT (12), + // write PLL VCO multiplier + .DIVCLK_DIVIDE (1), + // write PLL VCO divisor + .CLKOUT0_DIVIDE (1), + // VCO output divisor for PLL output clock (CLKOUT0) + .CLKOUT1_DIVIDE (2), + // VCO output divisor for PLL output clock (CLKOUT1) + .CLKOUT2_DIVIDE (32), + // VCO output divisor for PLL output clock (CLKOUT2) + .CLKOUT3_DIVIDE (8), + // VCO output divisor for PLL output clock (CLKOUT3) + + //*************************************************************************** + // Memory Timing Parameters. These parameters varies based on the selected + // memory part. + //*************************************************************************** + .tCKE (5000), + // memory tCKE paramter in pS. + .tFAW (40000), + // memory tRAW paramter in pS. + .tPRDI (1_000_000), + // memory tPRDI paramter in pS. + .tRAS (35000), + // memory tRAS paramter in pS. + .tRCD (13750), + // memory tRCD paramter in pS. + .tREFI (7800000), + // memory tREFI paramter in pS. + .tRFC (160000), + // memory tRFC paramter in pS. + .tRP (13750), + // memory tRP paramter in pS. + .tRRD (7500), + // memory tRRD paramter in pS. + .tRTP (7500), + // memory tRTP paramter in pS. + .tWTR (7500), + // memory tWTR paramter in pS. + .tZQI (128_000_000), + // memory tZQI paramter in nS. + .tZQCS (64), + // memory tZQCS paramter in clock cycles. + + //*************************************************************************** + // Simulation parameters + //*************************************************************************** + .SIM_BYPASS_INIT_CAL ("OFF"), + // # = "OFF" - Complete memory init & + // calibration sequence + // # = "SKIP" - Not supported + // # = "FAST" - Complete memory init & use + // abbreviated calib sequence + .SIMULATION ("FALSE"), + // Should be TRUE during design simulations and + // FALSE during implementations + + //*************************************************************************** + // The following parameters varies based on the pin out entered in MIG GUI. + // Do not change any of these parameters directly by editing the RTL. + // Any changes required should be done through GUI and the design regenerated. + //*************************************************************************** + .BYTE_LANES_B0 (4'b1111), + // Byte lanes used in an IO column. + .BYTE_LANES_B1 (4'b0000), + // Byte lanes used in an IO column. + .BYTE_LANES_B2 (4'b0000), + // Byte lanes used in an IO column. + .BYTE_LANES_B3 (4'b0000), + // Byte lanes used in an IO column. + .BYTE_LANES_B4 (4'b0000), + // Byte lanes used in an IO column. + .DATA_CTL_B0 (4'b0011), + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + .DATA_CTL_B1 (4'b0000), + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + .DATA_CTL_B2 (4'b0000), + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + .DATA_CTL_B3 (4'b0000), + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + .DATA_CTL_B4 (4'b0000), + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + + .PHY_0_BITLANES (48'hFFF_CFF_3DF_2FF), + .PHY_1_BITLANES (48'h000_000_000_000), + .PHY_2_BITLANES (48'h000_000_000_000), + .CK_BYTE_MAP (144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02), + .ADDR_MAP (192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038), + .BANK_MAP (36'h033_02A_032), + .CAS_MAP (12'h020), + .CKE_ODT_BYTE_MAP (8'h00), + .CKE_MAP (96'h000_000_000_000_000_000_000_02B), + .ODT_MAP (96'h000_000_000_000_000_000_000_030), + .CS_MAP (120'h000_000_000_000_000_000_000_000_000_000), + .PARITY_MAP (12'h000), + .RAS_MAP (12'h021), + .WE_MAP (12'h022), + .DQS_BYTE_MAP (144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01), + .DATA0_MAP (96'h016_018_014_019_010_017_011_013), + .DATA1_MAP (96'h003_002_005_004_001_006_000_007), + .DATA2_MAP (96'h000_000_000_000_000_000_000_000), + .DATA3_MAP (96'h000_000_000_000_000_000_000_000), + .DATA4_MAP (96'h000_000_000_000_000_000_000_000), + .DATA5_MAP (96'h000_000_000_000_000_000_000_000), + .DATA6_MAP (96'h000_000_000_000_000_000_000_000), + .DATA7_MAP (96'h000_000_000_000_000_000_000_000), + .DATA8_MAP (96'h000_000_000_000_000_000_000_000), + .DATA9_MAP (96'h000_000_000_000_000_000_000_000), + .DATA10_MAP (96'h000_000_000_000_000_000_000_000), + .DATA11_MAP (96'h000_000_000_000_000_000_000_000), + .DATA12_MAP (96'h000_000_000_000_000_000_000_000), + .DATA13_MAP (96'h000_000_000_000_000_000_000_000), + .DATA14_MAP (96'h000_000_000_000_000_000_000_000), + .DATA15_MAP (96'h000_000_000_000_000_000_000_000), + .DATA16_MAP (96'h000_000_000_000_000_000_000_000), + .DATA17_MAP (96'h000_000_000_000_000_000_000_000), + .MASK0_MAP (108'h000_000_000_000_000_000_000_009_012), + .MASK1_MAP (108'h000_000_000_000_000_000_000_000_000), + + .SLOT_0_CONFIG (8'b0000_0001), + // Mapping of Ranks. + .SLOT_1_CONFIG (8'b0000_0000), + // Mapping of Ranks. + .MEM_ADDR_ORDER ("BANK_ROW_COLUMN"), + //*************************************************************************** + // IODELAY and PHY related parameters + //*************************************************************************** + .IBUF_LPWR_MODE ("OFF"), + // to phy_top + .DATA_IO_IDLE_PWRDWN ("ON"), + // # = "ON", "OFF" + .DATA_IO_PRIM_TYPE ("HR_LP"), + // # = "HP_LP", "HR_LP", "DEFAULT" + .CKE_ODT_AUX ("FALSE"), + .USER_REFRESH ("OFF"), + .WRLVL ("ON"), + // # = "ON" - DDR3 SDRAM + // = "OFF" - DDR2 SDRAM. + .ORDERING ("NORM"), + // # = "NORM", "STRICT", "RELAXED". + .CALIB_ROW_ADD (16'h0000), + // Calibration row address will be used for + // calibration read and write operations + .CALIB_COL_ADD (12'h000), + // Calibration column address will be used for + // calibration read and write operations + .CALIB_BA_ADD (3'h0), + // Calibration bank address will be used for + // calibration read and write operations + .TCQ (100), + .IODELAY_GRP ("MIG_7SERIES_0_IODELAY_MIG"), + // It is associated to a set of IODELAYs with + // an IDELAYCTRL that have same IODELAY CONTROLLER + // clock frequency. + .SYSCLK_TYPE ("NO_BUFFER"), + // System clock type DIFFERENTIAL or SINGLE_ENDED + .REFCLK_TYPE ("NO_BUFFER"), + // Reference clock type DIFFERENTIAL or SINGLE_ENDED + .CMD_PIPE_PLUS1 ("ON"), + // add pipeline stage between MC and PHY + .DRAM_TYPE ("DDR3"), + .CAL_WIDTH ("HALF"), + .STARVE_LIMIT (2), + // # = 2,3,4. + //*************************************************************************** + // Referece clock frequency parameters + //*************************************************************************** + .REFCLK_FREQ (200.0), + // IODELAYCTRL reference clock frequency + .DIFF_TERM_REFCLK ("TRUE"), + // Differential Termination for idelay + // reference clock input pins + //*************************************************************************** + // System clock frequency parameters + //*************************************************************************** + .tCK (3000), + // memory tCK paramter. + // # = Clock Period in pS. + .nCK_PER_CLK (4), + // # of memory CKs per fabric CLK + .DIFF_TERM_SYSCLK ("TRUE"), + // Differential Termination for System + // clock input pins + + + //*************************************************************************** + // Debug parameters + //*************************************************************************** + .DEBUG_PORT ("OFF"), + // # = "ON" Enable debug signals/controls. + // = "OFF" Disable debug signals/controls. + + .RST_ACT_LOW (1) + // =1 for active low reset, + // =0 for active high. + ) +//*************************************************************************** +// end of section copied from mig_7series_0.voe +//*************************************************************************** + mem0 ( +// Memory interface ports + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p[0]), + .ddr3_ck_n(ddr3_ck_n[0]), + .ddr3_cke(ddr3_cke[0]), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt[0]), +// Application interface ports + .app_addr( {1'b0, app_addr, 3'b000} ), + .app_cmd(app_cmd), + .app_en(app_en), + .app_rdy(app_rdy), + .app_wdf_rdy(app_wdf_rdy), + .app_wdf_data(app_wdf_data), + .app_wdf_mask({ APP_MASK_WIDTH {1'b0} }), + .app_wdf_end(app_wdf_wren), // always the last word in 4:1 mode + .app_wdf_wren(app_wdf_wren), + .app_rd_data(app_rd_data), + .app_rd_data_end(app_rd_data_end), + .app_rd_data_valid(app_rd_data_valid), + .app_sr_req(1'b0), + .app_sr_active(), + .app_ref_req(1'b0), + .app_ref_ack(), + .app_zq_req(1'b0), + .app_zq_ack(), + .ui_clk(uiclk), + .ui_clk_sync_rst(ui_clk_sync_rst), + .init_calib_complete(init_calib_complete), + .sys_rst(!reset), +// clocks inputs + .sys_clk_i(clk67), + .clk_ref_i(clk200) + ); + + assign mem_reset = reset || ui_clk_sync_rst || !init_calib_complete; + assign reset_out = reset_buf; + assign wr_mode = wr_mode_buf && app_wdf_rdy && !infifo_empty; + assign infifo_rden = app_rdy && wr_mode && !rd_mode; + + assign status[0] = init_calib_complete; + assign status[1] = app_rdy; + assign status[2] = app_wdf_rdy; + assign status[3] = app_rd_data_valid; + assign status[4] = infifo_err; + assign status[5] = outfifo_err; + assign status[6] = outfifo_err_uf; + assign status[7] = wr_mode; + assign status[8] = rd_mode; + assign status[9] = !reset; + + assign mem_free_out = mem_free; + + always @ (posedge uiclk) + begin +// reset + reset_buf <= mem_reset; + + // used for debuggig only + if ( reset_buf ) outfifo_err <= 1'b0; + else if ( outfifo_err_w ) outfifo_err <= 1'b1; + if ( reset_buf ) infifo_err <= 1'b0; + else if ( infifo_err_w ) infifo_err <= 1'b1; + + // memory interface --> outfifo + if ( reset_buf ) + begin + outfifo_err_uf <= 1'b0; + outfifo_pending <= 6'd0; + end else if ( app_rd_data_valid && !(rd_mode && app_rdy) ) + begin + if ( outfifo_pending != 6'd0 ) + begin + outfifo_pending = outfifo_pending - 6'd1; + end else + begin + outfifo_err_uf <= 1'b1; + end + end else if ( (!app_rd_data_valid) && rd_mode && app_rdy ) + begin + outfifo_pending = outfifo_pending + 6'd1; + end + + // wr_mode + if ( reset_buf ) + begin + wr_mode_buf <= 1'b0; + end else if ( infifo_empty || (!app_wdf_rdy) || wr_cnt[7] || ( mem_free[APP_ADDR_WIDTH:1] == {APP_ADDR_WIDTH{1'b0}} ) ) // at maximum 128 words + begin + wr_mode_buf <= 1'b0; + end else if ( (!rd_mode) && !infifo_almost_empty && (mem_free[APP_ADDR_WIDTH:5] != {(APP_ADDR_WIDTH-4){1'b0}}) ) // at least 32 words + begin + wr_mode_buf <= 1'b1; + end + + // rd_mode + if ( reset_buf ) + begin + rd_mode <= 1'b0; + end else if ( rd_mode || outfifo_almost_full || (outfifo_pending == 6'd31) || rd_cnt[7] || ( mem_free[APP_ADDR_WIDTH-1:0] == {(APP_ADDR_WIDTH){1'b1}}) || mem_free[APP_ADDR_WIDTH] ) // at maximum 128 words ) + begin + rd_mode <= 1'b0; + end else if ( (!wr_mode_buf) && (outfifo_pending == 6'd0) && (mem_free[APP_ADDR_WIDTH-1:5] != {(APP_ADDR_WIDTH-5){1'b1}}) ) // at least 32 words + begin + rd_mode <= 1'b1; + end + + if ( reset_buf ) + begin + rd_cnt_dbg <= 10'd0; + end else if ( app_rd_data_valid ) + begin + rd_cnt_dbg <= rd_cnt_dbg + 1; + end; + +// command generator + if ( reset_buf ) + begin + app_en <= 1'b0; + mem_wr_addr <= {APP_ADDR_WIDTH{1'b0}}; + mem_rd_addr <= {APP_ADDR_WIDTH{1'b0}}; + mem_free <= {1'b1, {APP_ADDR_WIDTH{1'b0}}}; + wr_cnt <= 8'd0; + rd_cnt <= 8'd0; + end else if ( app_rdy ) + begin + if ( rd_mode ) + begin + app_cmd <= 3'b001; + app_en <= 1'b1; + app_addr <= mem_rd_addr; + mem_rd_addr <= mem_rd_addr + 1; + rd_cnt <= rd_cnt + 1; + wr_cnt <= 8'd0; + mem_free <= mem_free + 1; + end else if ( wr_mode ) + begin + app_cmd <= 3'b000; + app_en <= 1'b1; + app_addr <= mem_wr_addr; + app_wdf_data <= infifo_do; +// app_wdf_data <= { 8{mem_wr_addr[15:0]} }; +// app_wdf_data <= { {7{mem_wr_addr[15:0]}}, infifo_do[71:64], infifo_do[7:0] }; + mem_wr_addr <= mem_wr_addr + 1; + mem_free <= mem_free - 1; + wr_cnt <= wr_cnt + 1; + rd_cnt <= 8'd0; + end else + begin + app_en <= 1'b0; + wr_cnt <= 8'd0; + rd_cnt <= 8'd0; + end + end + + if ( reset_buf ) + begin + app_wdf_wren <= 1'b0; +// infifo_rden <= 1'b0; + end else if ( app_rdy && (!rd_mode) && wr_mode ) + begin + app_wdf_wren <= 1'b1; +// infifo_rden <= 1'b1; + end else + begin + if ( app_wdf_rdy ) app_wdf_wren <= 1'b0; +// infifo_rden <= 1'b0; + end + + + end + +endmodule Index: usb-fpga-2.13/2.13d/memfifo/fpga/clean.sh =================================================================== --- usb-fpga-2.13/2.13d/memfifo/fpga/clean.sh (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/fpga/clean.sh (revision 3) @@ -0,0 +1,79 @@ +#!/bin/bash + +# This files / directories will be removed +rms="fpga.hw *.cache *.data/wt *.runs/.jobs *.runs/synth_*/* *.runs/impl_*/*" +# This files / directories in *.srcs/sources_*/ip/*/ will be removed +ip_rms="_tmp log.txt */docs */example_design */user_design/log.txt" +# Files with this extensions are not removed +keepext="vhd v xdc ucf bit bin" + +# This sould not be edited. +list_files() { + if [ "$2" != "" ]; then + echo "$1" + for i in $2; do + echo " $i" + done + fi +} + +check_ext() { + f=${1##*.} + for e in $keepext; do + if [ "$e" = "$f" ]; then + return 0 + fi + done + return 1 +} + +rmfiles="" +keepfiles="" +rmdirs="" +for i in $ip_rms; do + for j in *.srcs/sources_*/ip/*/$i; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi + done +done + +for j in $rms; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi +done + +list_files "This files will NOT be removed:" "$keepfiles" +list_files "This directories will be removed:" "$rmdirs" +list_files "This files will be removed:" "$rmfiles" + +if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then + c="yes" +else + echo -n 'Confirm this by entering "yes": ' + read c +fi + +if [ "$c" == "yes" ]; then + rm -fr *.runs/impl_*/.* 2>/dev/null + rm -fr *.runs/synth_*/.* 2>/dev/null + [ "$rmfiles" != "" ] && rm $rmfiles + [ "$rmdirs" != "" ] && rm -r $rmdirs + exit 0 +fi +exit 1
usb-fpga-2.13/2.13d/memfifo/fpga/clean.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/memfifo/Readme =================================================================== --- usb-fpga-2.13/2.13d/memfifo/Readme (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/Readme (revision 3) @@ -0,0 +1,45 @@ +memfifo +------- +This example demonstrates: + +* High speed EZ-USB -> FPGA transfers using the Slave FIFO interface +* High speed FPGA -> EZ-USB transfers using the Slave FIFO interface +* Usage of the DDR3 SDRAM + +All SDRAM is used to build a large FIFO. Input of this FIFO is either +USB Endpoint 6 through the Slave FIFO interface of EZ-USB or a test +pattern generator with variable data rate. Data is written to PC +using Enpdoint 2. + +The host software writes the data (in EP6 input mode), reads it back +and verifies it. Several tests are performed in order to test flow +control, data rates, etc. + +The HDL sources contain 3 modules: +1. ezusb_io.v: Implements the EZ-USB Slave FIFO interface for both + directions. It also includes an scheduler (required if both + directions are used at the same time) and short packets (PKTEND). +2. dram_fifo.v: Implements a huge FIFO from all SDRAM. +3. memfifo.c: The top level module glues everything together. + +ezusb_io and dram_fifo are re-usable for many other projects. + +PIN PA7 is the reset input. + +Data source source is is selected by PA1:PA0: +PA1:PA0 Source +---------------------- +0:0 USB Endpoint 6 (EZ-USB Slave FIFO interface) +0:1 48 MByte/s test pattern generator +1:0 12 MByte/s test pattern generator +1:1 Test pattern generator, speed selected by SW8 of the debug board + +Debug Board (not required) +-------------------------- +LED1: Debug/status output, see SW10 +LED2-3: Fill level of the DRAM FIFO +SW8: Speed of test pattern generator in source mode 11 + on: 12 MByte/s + off: 48 MByte/s +SW10 on: status signals from dram_fifo module + off:status signals from top level module Index: usb-fpga-2.13/2.13d/memfifo/Makefile =================================================================== --- usb-fpga-2.13/2.13d/memfifo/Makefile (nonexistent) +++ usb-fpga-2.13/2.13d/memfifo/Makefile (revision 3) @@ -0,0 +1,27 @@ +######################### +# configuration section # +######################### + +# Defines the location of the EZ-USB SDK +ZTEXPREFIX=../../../.. + +# The name of the jar archive +JARTARGET=MemFifo.jar +# Java Classes that have to be build +CLASSTARGETS=MemFifo.class +# Extra dependencies for Java Classes +CLASSEXTRADEPS= + +# ihx files (firmware ROM files) that have to be build +IHXTARGETS=memfifo.ihx +# Extra Dependencies for ihx files +IHXEXTRADEPS= + +# Extra files that should be included into th jar archive +EXTRAJARFILES=memfifo.ihx fpga/memfifo.runs/impl_1/memfifo.bit + +################################ +# DO NOT CHANAGE THE FOLLOWING # +################################ +# includes the main Makefile +include $(ZTEXPREFIX)/Makefile.mk Index: usb-fpga-2.13/2.13d/ucecho/ucecho.sh =================================================================== --- usb-fpga-2.13/2.13d/ucecho/ucecho.sh (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/ucecho.sh (revision 3) @@ -0,0 +1,4 @@ +#make -C ../../../java distclean all || exit +#make distclean all || exit +#make || exit +java -cp UCEcho.jar UCEcho $@
usb-fpga-2.13/2.13d/ucecho/ucecho.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/ucecho/UCEcho.java =================================================================== --- usb-fpga-2.13/2.13d/ucecho/UCEcho.java (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/UCEcho.java (revision 3) @@ -0,0 +1,171 @@ +/*! + ucecho -- uppercase conversion and bitstream encryption example for ZTEX USB-FPGA Module 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ + +import java.io.*; +import java.util.*; + +import ch.ntb.usb.*; + +import ztex.*; + +// ***************************************************************************** +// ******* ParameterException ************************************************** +// ***************************************************************************** +// Exception the prints a help message +class ParameterException extends Exception { + public final static String helpMsg = new String ( + "Parameters:\n"+ + " -d Device Number (default: 0)\n" + + " -f Force uploads\n" + + " -e Use the encrypted bitstream\n" + + " -p Print bus info\n" + + " -h This help" ); + + public ParameterException (String msg) { + super( msg + "\n" + helpMsg ); + } +} + +// ***************************************************************************** +// ******* Test0 *************************************************************** +// ***************************************************************************** +class UCEcho extends Ztex1v1 { + +// ******* UCEcho ************************************************************** +// constructor + public UCEcho ( ZtexDevice1 pDev ) throws UsbException { + super ( pDev ); + } + +// ******* echo **************************************************************** +// writes a string to Endpoint 4, reads it back from Endpoint 2 and writes the output to System.out + public void echo ( String input ) throws UsbException { + byte buf[] = input.getBytes(); + int i = LibusbJava.usb_bulk_write(handle(), 0x04, buf, buf.length, 1000); + if ( i<0 ) + throw new UsbException("Error sending data: " + LibusbJava.usb_strerror()); + System.out.println("Send "+i+" bytes: `"+input+"'" ); + + try { + Thread.sleep( 10 ); + } + catch ( InterruptedException e ) { + } + + buf = new byte[1024]; + i = LibusbJava.usb_bulk_read(handle(), 0x82, buf, 1024, 1000); + if ( i<0 ) + throw new UsbException("Error receiving data: " + LibusbJava.usb_strerror()); + System.out.println("Read "+i+" bytes: `"+new String(buf,0,i)+"'" ); + } + +// ******* main **************************************************************** + public static void main (String args[]) { + + int devNum = 0; + boolean force = false; + boolean encrypted = false; + + try { +// init USB stuff + LibusbJava.usb_init(); + +// scan the USB bus + ZtexScanBus1 bus = new ZtexScanBus1( ZtexDevice1.ztexVendorId, ZtexDevice1.ztexProductId, true, false, 1); + if ( bus.numberOfDevices() <= 0) { + System.err.println("No devices found"); + System.exit(0); + } + +// scan the command line arguments + for (int i=0; i=args.length) throw new Exception(); + devNum = Integer.parseInt( args[i] ); + } + catch (Exception e) { + throw new ParameterException("Device number expected after -d"); + } + } + else if ( args[i].equals("-f") ) { + force = true; + } + else if ( args[i].equals("-e") ) { + encrypted = true; + } + else if ( args[i].equals("-p") ) { + bus.printBus(System.out); + System.exit(0); + } + else if ( args[i].equals("-p") ) { + bus.printBus(System.out); + System.exit(0); + } + else if ( args[i].equals("-h") ) { + System.err.println(ParameterException.helpMsg); + System.exit(0); + } + else throw new ParameterException("Invalid Parameter: "+args[i]); + } + + +// create the main class + UCEcho ztex = new UCEcho ( bus.device(devNum) ); + +// upload the firmware if necessary + if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("ucecho example for UFM 2.13") ) { + System.out.println("Firmware upload time: " + ztex.uploadFirmware( "ucecho.ihx", force ) + " ms"); + } + +// upload the bitstream if necessary + if ( force || ! ztex.getFpgaConfiguration() ) { + if ( encrypted ) System.out.println("FPGA configuration time: " + ztex.configureFpgaHS( "fpga/ucecho.runs/impl_2/ucecho.bit" , force, -1 ) + " ms"); + else System.out.println("FPGA configuration time: " + ztex.configureFpga( "fpga/ucecho.runs/impl_1/ucecho.bit" , force, -1 ) + " ms"); + } + +// claim interface 0 + ztex.trySetConfiguration ( 1 ); + ztex.claimInterface ( 0 ); + +// read string from stdin and write it to USB device + String str = ""; + BufferedReader reader = new BufferedReader( new InputStreamReader( System.in ) ); + while ( ! str.equals("quit") ) { + System.out.print("Enter a string or `quit' to exit the program: "); + str = reader.readLine(); + if ( ! str.equals("") ) + ztex.echo(str); + System.out.println(""); + } + +// release interface 0 + ztex.releaseInterface( 0 ); + + } + catch ( BitstreamUploadException e ) { + System.out.println("Error: "+e.getLocalizedMessage() ); + if ( encrypted ) System.out.println("Make sure that the encryption key from key file fpga/ucecho.nky is loaded to battery-backed RAM"); + } + catch (Exception e) { + System.out.println("Error: "+e.getLocalizedMessage() ); + } + } + +} Index: usb-fpga-2.13/2.13d/ucecho/ucecho.c =================================================================== --- usb-fpga-2.13/2.13d/ucecho/ucecho.c (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/ucecho.c (revision 3) @@ -0,0 +1,100 @@ +/*! + ucecho -- uppercase conversion and bitstream encryption example for ZTEX USB-FPGA Module 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ + +#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros +#include[ztex-utils.h] // include basic functions + +// configure endpoints 2 and 4, both belong to interface 0 (in/out are from the point of view of the host) +EP_CONFIG(2,0,BULK,IN,512,2); +EP_CONFIG(4,0,BULK,OUT,512,2); + +// select ZTEX USB FPGA Module 1.16 as target (required for FPGA configuration) +IDENTITY_UFM_2_13(10.17.0.0,0); + +// this product string is also used for identification by the host software +#define[PRODUCT_STRING]["ucecho example for UFM 2.13"] + +// enables high speed FPGA configuration via EP4 +ENABLE_HS_FPGA_CONF(4); + +ENABLE_FLASH; +ENABLE_FLASH_BITSTREAM; + +__xdata BYTE run; + +#define[PRE_FPGA_RESET][PRE_FPGA_RESET + run = 0; +] +// this is called automatically after FPGA configuration +#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG + IFCONFIG = bmBIT7; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface + SYNCDELAY; + EP2FIFOCFG = 0; + SYNCDELAY; + EP4FIFOCFG = 0; + SYNCDELAY; + + REVCTL = 0x0; // reset + SYNCDELAY; + EP2CS &= ~bmBIT0; // stall = 0 + SYNCDELAY; + EP4CS &= ~bmBIT0; // stall = 0 + + SYNCDELAY; // first two packages are waste + EP4BCL = 0x80; // skip package, (re)arm EP4 + SYNCDELAY; + EP4BCL = 0x80; // skip package, (re)arm EP4 + + FIFORESET = 0x80; // reset FIFO + SYNCDELAY; + FIFORESET = 0x82; + SYNCDELAY; + FIFORESET = 0x00; + SYNCDELAY; + + OED = 255; + run = 1; +] + +// include the main part of the firmware kit, define the descriptors, ... +#include[ztex.h] + +void main(void) +{ + WORD i,size; + +// init everything + init_USB(); + + while (1) { + if ( run && !(EP4CS & bmBIT2) ) { // EP4 is not empty + size = (EP4BCH << 8) | EP4BCL; + if ( size>0 && size<=512 && !(EP2CS & bmBIT3)) { // EP2 is not full + for ( i=0; i> 8; + SYNCDELAY; + EP2BCL = size & 255; // arm EP2 + } + SYNCDELAY; + EP4BCL = 0x80; // skip package, (re)arm EP4 + } + } +} Index: usb-fpga-2.13/2.13d/ucecho/ucecho-encrypted.sh =================================================================== --- usb-fpga-2.13/2.13d/ucecho/ucecho-encrypted.sh (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/ucecho-encrypted.sh (revision 3) @@ -0,0 +1,4 @@ +#make -C ../../../java distclean all || exit +#make distclean all || exit +#make || exit +java -cp UCEcho.jar UCEcho -e $@
usb-fpga-2.13/2.13d/ucecho/ucecho-encrypted.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.xdc =================================================================== --- usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.xdc (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.xdc (revision 3) @@ -0,0 +1,34 @@ +create_clock -name fxclk_in -period 20.833 [get_ports fxclk] +set_property PACKAGE_PIN P15 [get_ports fxclk] +set_property IOSTANDARD LVCMOS33 [get_ports fxclk] + +# output +set_property PACKAGE_PIN M16 [get_ports {pb[0]}] ;# PB0/FD0 +set_property PACKAGE_PIN L16 [get_ports {pb[1]}] ;# PB1/FD1 +set_property PACKAGE_PIN L14 [get_ports {pb[2]}] ;# PB2/FD2 +set_property PACKAGE_PIN M14 [get_ports {pb[3]}] ;# PB3/FD3 +set_property PACKAGE_PIN L18 [get_ports {pb[4]}] ;# PB4/FD4 +set_property PACKAGE_PIN M18 [get_ports {pb[5]}] ;# PB5/FD5 +set_property PACKAGE_PIN R12 [get_ports {pb[6]}] ;# PB6/FD6 +set_property PACKAGE_PIN R13 [get_ports {pb[7]}] ;# PB7/FD7 +set_property IOSTANDARD LVCMOS33 [get_ports pb[*]] +set_property DRIVE 12 [get_ports pb[*]] + +# input +set_property PACKAGE_PIN T9 [get_ports {pd[0]}] ;# PD0/FD8 +set_property PACKAGE_PIN V10 [get_ports {pd[1]}] ;# PD1/FD9 +set_property PACKAGE_PIN U11 [get_ports {pd[2]}] ;# PD2/FD10 +set_property PACKAGE_PIN V11 [get_ports {pd[3]}] ;# PD3/FD11 +set_property PACKAGE_PIN V12 [get_ports {pd[4]}] ;# PD4/FD12 +set_property PACKAGE_PIN U13 [get_ports {pd[5]}] ;# PD5/FD13 +set_property PACKAGE_PIN U14 [get_ports {pd[6]}] ;# PD6/FD14 +set_property PACKAGE_PIN V14 [get_ports {pd[7]}] ;# PD7/FD15 + +set_property IOSTANDARD LVCMOS33 [get_ports pd[*]] + +# bitstream settings for all ZTEX Series 2 FPGA Boards +set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] + Index: usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.nky =================================================================== --- usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.nky (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.nky (revision 3) @@ -0,0 +1,4 @@ +Device xc7a100tcsg324; +Key 0 47840e495b030edad3388b85f6dc394fecc7eb89471f17292efb14f51324bb80; +Key StartCBC d574ff87606b227da02976144a67f720; +Key HMAC 1a86ec2a13db381e3135e72e8a1d8071dad5d72331fedeb488f37e7d27994078; Index: usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.vhd =================================================================== --- usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.vhd (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.vhd (revision 3) @@ -0,0 +1,36 @@ +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +Library UNISIM; +use UNISIM.vcomponents.all; + +entity ucecho is + port( + pd : in unsigned(7 downto 0); + pb : out unsigned(7 downto 0); + fxclk : in std_logic + ); +end ucecho; + + +architecture RTL of ucecho is + +--signal declaration +signal pb_buf : unsigned(7 downto 0); + +begin + pb <= pb_buf; + + dpUCECHO: process(fxclk) + begin + if fxclk' event and fxclk = '1' then + if ( pd >= 97 ) and ( pd <= 122) + then + pb_buf <= pd - 32; + else + pb_buf <= pd; + end if; + end if; + end process dpUCECHO; + +end RTL; Index: usb-fpga-2.13/2.13d/ucecho/fpga/clean.sh =================================================================== --- usb-fpga-2.13/2.13d/ucecho/fpga/clean.sh (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/fpga/clean.sh (revision 3) @@ -0,0 +1,79 @@ +#!/bin/bash + +# This files / directories will be removed +rms="fpga.hw *.cache *.data/wt *.runs/.jobs *.runs/synth_*/* *.runs/impl_*/*" +# This files / directories in *.srcs/sources_*/ip/*/ will be removed +ip_rms="_tmp log.txt */docs */example_design */user_design/log.txt" +# Files with this extensions are not removed +keepext="vhd v xdc ucf bit bin" + +# This sould not be edited. +list_files() { + if [ "$2" != "" ]; then + echo "$1" + for i in $2; do + echo " $i" + done + fi +} + +check_ext() { + f=${1##*.} + for e in $keepext; do + if [ "$e" = "$f" ]; then + return 0 + fi + done + return 1 +} + +rmfiles="" +keepfiles="" +rmdirs="" +for i in $ip_rms; do + for j in *.srcs/sources_*/ip/*/$i; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi + done +done + +for j in $rms; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi +done + +list_files "This files will NOT be removed:" "$keepfiles" +list_files "This directories will be removed:" "$rmdirs" +list_files "This files will be removed:" "$rmfiles" + +if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then + c="yes" +else + echo -n 'Confirm this by entering "yes": ' + read c +fi + +if [ "$c" == "yes" ]; then + rm -fr *.runs/impl_*/.* 2>/dev/null + rm -fr *.runs/synth_*/.* 2>/dev/null + [ "$rmfiles" != "" ] && rm $rmfiles + [ "$rmdirs" != "" ] && rm -r $rmdirs + exit 0 +fi +exit 1
usb-fpga-2.13/2.13d/ucecho/fpga/clean.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/ucecho/fpga/ucecho_encryption.xdc =================================================================== --- usb-fpga-2.13/2.13d/ucecho/fpga/ucecho_encryption.xdc (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/fpga/ucecho_encryption.xdc (revision 3) @@ -0,0 +1,4 @@ +# encryption settings +set_property BITSTREAM.ENCRYPTION.ENCRYPT Yes [current_design] +set_property BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT bbram [current_design] +set_property BITSTREAM.ENCRYPTION.KEYFILE ../../ucecho.nky [current_design] Index: usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.xpr =================================================================== --- usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.xpr (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.xpr (revision 3) @@ -0,0 +1,19 @@ + + + + + + + + + + + + + Index: usb-fpga-2.13/2.13d/ucecho/Makefile =================================================================== --- usb-fpga-2.13/2.13d/ucecho/Makefile (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/Makefile (revision 3) @@ -0,0 +1,27 @@ +######################### +# configuration section # +######################### + +# Defines the location of the EZ-USB SDK +ZTEXPREFIX=../../../.. + +# The name of the jar archive +JARTARGET=UCEcho.jar +# Java Classes that have to be build +CLASSTARGETS=UCEcho.class +# Extra dependencies for Java Classes +CLASSEXTRADEPS= + +# ihx files (firmware ROM files) that have to be build +IHXTARGETS=ucecho.ihx +# Extra Dependencies for ihx files +IHXEXTRADEPS= + +# Extra files that should be included into th jar archive +EXTRAJARFILES=ucecho.ihx fpga/ucecho.runs/impl_1/ucecho.bit fpga/ucecho.runs/impl_2/ucecho.bit + +################################ +# DO NOT CHANAGE THE FOLLOWING # +################################ +# includes the main Makefile +include $(ZTEXPREFIX)/Makefile.mk Index: usb-fpga-2.13/2.13d/ucecho/Readme =================================================================== --- usb-fpga-2.13/2.13d/ucecho/Readme (nonexistent) +++ usb-fpga-2.13/2.13d/ucecho/Readme (revision 3) @@ -0,0 +1,16 @@ +ucecho +------ + +This example is intended for ZTEX USB-FPGA-Modules. + +The firmware (defined in ucecho.c) declares Endpoint 2 and Endpoint 4 +(both 512 bytes, double buffered, bulk transfer, belong to interface 0). +All data that is written to Endpoint 4 is converted to uppercase by +the FPGA and can be read back from Endpoint 2. + +This example does the same as the example in directory ../../all/ucecho +except that the uppercase - lowercase conversion is made by the FPGA. + +The driver (defined in UCEcho.java) uploads the the Firmware (ucecho.ihx) +to the EZ-USB Microcontroller and the Bitstream (fpga/ucecho.bit) to the +FPGA if necessary, sends user string to the device and reads them back. Index: usb-fpga-2.13/2.13d/lightshow/lightshow.sh =================================================================== --- usb-fpga-2.13/2.13d/lightshow/lightshow.sh (nonexistent) +++ usb-fpga-2.13/2.13d/lightshow/lightshow.sh (revision 3) @@ -0,0 +1,2 @@ +../../../../java/FWLoader/FWLoader -f -uf fpga/lightshow.runs/impl_1/lightshow.bit +
usb-fpga-2.13/2.13d/lightshow/lightshow.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.xpr =================================================================== --- usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.xpr (nonexistent) +++ usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.xpr (revision 3) @@ -0,0 +1,18 @@ + + + + + + + + + + + + Index: usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.xdc =================================================================== --- usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.xdc (nonexistent) +++ usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.xdc (revision 3) @@ -0,0 +1,56 @@ +# CLKOUT/FXCLK +create_clock -name fxclk -period 10 [get_ports fxclk] +set_property PACKAGE_PIN P15 [get_ports fxclk] +set_property IOSTANDARD LVCMOS33 [get_ports fxclk] + +# led1 +set_property PACKAGE_PIN H15 [get_ports {led1[0]}] ;# A6 / B21~IO_L21P_T3_DQS_16 +set_property PACKAGE_PIN J13 [get_ports {led1[1]}] ;# B6 / A21~IO_L21N_T3_DQS_16 +set_property PACKAGE_PIN J14 [get_ports {led1[2]}] ;# A7 / D20~IO_L19P_T3_16 +set_property PACKAGE_PIN H14 [get_ports {led1[3]}] ;# B7 / C20~IO_L19N_T3_VREF_16 +set_property PACKAGE_PIN H17 [get_ports {led1[4]}] ;# A8 / B20~IO_L16P_T2_16 +set_property PACKAGE_PIN G14 [get_ports {led1[5]}] ;# B8 / A20~IO_L16N_T2_16 +set_property PACKAGE_PIN G17 [get_ports {led1[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16 +set_property PACKAGE_PIN G16 [get_ports {led1[7]}] ;# B9 / A19~IO_L17N_T2_16 +set_property PACKAGE_PIN G18 [get_ports {led1[8]}] ;# A10 / C18~IO_L13P_T2_MRCC_16 +set_property PACKAGE_PIN H16 [get_ports {led1[9]}] ;# B10 / A18~IO_L17P_T2_16 +set_property IOSTANDARD LVCMOS33 [get_ports {led1[*]}] +set_property DRIVE 12 [get_ports {led1[*]}] + +# sw +set_property PACKAGE_PIN F18 [get_ports {sw[0]}] ;# A11 / B18~IO_L11N_T1_SRCC_16 +set_property PACKAGE_PIN F16 [get_ports {sw[1]}] ;# B11 / D17~IO_L12P_T1_MRCC_16 +set_property PACKAGE_PIN E18 [get_ports {sw[2]}] ;# A12 / B17~IO_L11P_T1_SRCC_16 +set_property PACKAGE_PIN F15 [get_ports {sw[3]}] ;# B12 / C17~IO_L12N_T1_MRCC_16 +set_property IOSTANDARD LVCMOS33 [get_ports {sw[*]}] +set_property PULLUP true [get_ports {sw[*]}] + +# led2 +set_property PACKAGE_PIN U9 [get_ports {led2[0]}] ;# C3 / AB17~IO_L2N_T0_13 +set_property PACKAGE_PIN V9 [get_ports {led2[1]}] ;# D3 / AB16~IO_L2P_T0_13 +set_property PACKAGE_PIN U8 [get_ports {led2[2]}] ;# C4 / Y16~IO_L1P_T0_13 +set_property PACKAGE_PIN V7 [get_ports {led2[3]}] ;# D4 / AA16~IO_L1N_T0_13 +set_property PACKAGE_PIN U7 [get_ports {led2[4]}] ;# C5 / AA15~IO_L4P_T0_13 +set_property PACKAGE_PIN V6 [get_ports {led2[5]}] ;# D5 / AB15~IO_L4N_T0_13 +set_property PACKAGE_PIN U6 [get_ports {led2[6]}] ;# C6 / Y13~IO_L5P_T0_13 +set_property PACKAGE_PIN V5 [get_ports {led2[7]}] ;# D6 / AA14~IO_L5N_T0_13 +set_property PACKAGE_PIN T8 [get_ports {led2[8]}] ;# C7 / W14~IO_L6P_T0_13 +set_property PACKAGE_PIN V4 [get_ports {led2[9]}] ;# D7 / Y14~IO_L6N_T0_VREF_13 +set_property PACKAGE_PIN R8 [get_ports {led2[10]}] ;# C8 / AA13~IO_L3P_T0_DQS_13 +set_property PACKAGE_PIN T5 [get_ports {led2[11]}] ;# D8 / AB13~IO_L3N_T0_DQS_13 +set_property PACKAGE_PIN R7 [get_ports {led2[12]}] ;# C9 / AB12~IO_L7N_T1_13 +set_property PACKAGE_PIN T4 [get_ports {led2[13]}] ;# D9 / AB11~IO_L7P_T1_13 +set_property PACKAGE_PIN T6 [get_ports {led2[14]}] ;# C10 / W12~IO_L12N_T1_MRCC_13 +set_property PACKAGE_PIN U4 [get_ports {led2[15]}] ;# D10 / W11~IO_L12P_T1_MRCC_13 +set_property PACKAGE_PIN R6 [get_ports {led2[16]}] ;# C11 / AA11~IO_L9N_T1_DQS_13 +set_property PACKAGE_PIN U3 [get_ports {led2[17]}] ;# D11 / AA10~IO_L9P_T1_DQS_13 +set_property PACKAGE_PIN R5 [get_ports {led2[18]}] ;# C12 / AA9~IO_L8P_T1_13 +set_property PACKAGE_PIN V1 [get_ports {led2[19]}] ;# D12 / AB10~IO_L8N_T1_13 +set_property IOSTANDARD LVCMOS33 [get_ports {led2[*]}] +set_property DRIVE 12 [get_ports {led2[*]}] + +# bitstream settings +set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] Index: usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.vhd =================================================================== --- usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.vhd (nonexistent) +++ usb-fpga-2.13/2.13d/lightshow/fpga/lightshow.vhd (revision 3) @@ -0,0 +1,110 @@ +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +entity lightshow is + port( + led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board + led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board + sw : in std_logic_vector(3 downto 0); + fxclk : in std_logic + ); +end lightshow; + +--signal declaration +architecture RTL of lightshow is + +type tPattern1 is array(9 downto 0) of integer range 0 to 255; +type tPattern2 is array(19 downto 0) of integer range 0 to 255; + +signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1 +signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2 +signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2 +signal pattern2 : tPattern2; -- pattern20 + pattern21 + +signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0); +signal pwm_cnt : std_logic_vector(19 downto 0); +signal pwm_cnt8 : std_logic_vector(7 downto 0); + +begin + pwm_cnt8 <= pwm_cnt(19 downto 12); + + dp_fxclk: process(fxclk) + begin + if fxclk' event and fxclk = '1' then + + -- pattern for led 1 + if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz + then + if ( sw(0) = '1' ) + then + pattern1(8 downto 0) <= pattern1(9 downto 1); + pattern1(9) <= pattern1(0); + else + pattern1(9 downto 1) <= pattern1(8 downto 0); + pattern1(0) <= pattern1(9); + end if; + cnt1 <= (others => '0'); + else + cnt1 <= cnt1 + 1; + end if; + + -- pattern for led 2 + if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz + then + pattern20(18 downto 0) <= pattern20(19 downto 1); + pattern20(19) <= pattern20(0); + cnt20 <= (others => '0'); + else + cnt20 <= cnt20 + 1; + end if; + + if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) ) + then + if ( sw(1) = '1' ) + then + pattern21(18 downto 0) <= pattern21(19 downto 1); + pattern21(19) <= pattern21(0); + else + pattern21(19 downto 1) <= pattern21(18 downto 0); + pattern21(0) <= pattern21(19); + end if; + cnt21 <= (others => '0'); + else + cnt21 <= cnt21 + 1; + end if; + + for i in 0 to 19 loop + pattern2(i) <= pattern20(i) + pattern21(i); + end loop; + + -- pwm + if ( pwm_cnt8 = conv_std_logic_vector(255,8) ) + then + pwm_cnt <= ( others => '0' ); + else + pwm_cnt <= pwm_cnt + 1; + end if; + -- led1 + for i in 0 to 9 loop + if ( pwm_cnt8 < pattern1(i) ) + then + led1(i) <= '1'; + else + led1(i) <= '0'; + end if; + end loop; + for i in 0 to 19 loop + if (pwm_cnt8 < pattern2(i) ) + then + led2(i) <= '1'; + else + led2(i) <= '0'; + end if; + end loop; + + end if; + end process dp_fxclk; + +end RTL; Index: usb-fpga-2.13/2.13d/lightshow/fpga/clean.sh =================================================================== --- usb-fpga-2.13/2.13d/lightshow/fpga/clean.sh (nonexistent) +++ usb-fpga-2.13/2.13d/lightshow/fpga/clean.sh (revision 3) @@ -0,0 +1,79 @@ +#!/bin/bash + +# This files / directories will be removed +rms="fpga.hw *.cache *.data/wt *.runs/.jobs *.runs/synth_*/* *.runs/impl_*/*" +# This files / directories in *.srcs/sources_*/ip/*/ will be removed +ip_rms="_tmp log.txt */docs */example_design */user_design/log.txt" +# Files with this extensions are not removed +keepext="vhd v xdc ucf bit bin" + +# This sould not be edited. +list_files() { + if [ "$2" != "" ]; then + echo "$1" + for i in $2; do + echo " $i" + done + fi +} + +check_ext() { + f=${1##*.} + for e in $keepext; do + if [ "$e" = "$f" ]; then + return 0 + fi + done + return 1 +} + +rmfiles="" +keepfiles="" +rmdirs="" +for i in $ip_rms; do + for j in *.srcs/sources_*/ip/*/$i; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi + done +done + +for j in $rms; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi +done + +list_files "This files will NOT be removed:" "$keepfiles" +list_files "This directories will be removed:" "$rmdirs" +list_files "This files will be removed:" "$rmfiles" + +if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then + c="yes" +else + echo -n 'Confirm this by entering "yes": ' + read c +fi + +if [ "$c" == "yes" ]; then + rm -fr *.runs/impl_*/.* 2>/dev/null + rm -fr *.runs/synth_*/.* 2>/dev/null + [ "$rmfiles" != "" ] && rm $rmfiles + [ "$rmdirs" != "" ] && rm -r $rmdirs + exit 0 +fi +exit 1
usb-fpga-2.13/2.13d/lightshow/fpga/clean.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/2.13d/lightshow/Readme =================================================================== --- usb-fpga-2.13/2.13d/lightshow/Readme (nonexistent) +++ usb-fpga-2.13/2.13d/lightshow/Readme (revision 3) @@ -0,0 +1,5 @@ +lightshow +--------- + +This example requires the Debug Board. It implements a light show using +the LED's. Effects are controlled by the switches. Index: usb-fpga-2.13/2.13d/Makefile =================================================================== --- usb-fpga-2.13/2.13d/Makefile (nonexistent) +++ usb-fpga-2.13/2.13d/Makefile (revision 3) @@ -0,0 +1,26 @@ +DIRS=ucecho memfifo + +.PHONY: default all clean distclean avr avrclean avrdistclean + +default: + @echo "This makefile is intended to clean up the project or to build all examples in this subdirectory" + @echo "Usage: make all | clean | distclean" + +all: + set -e; for i in $(DIRS); do make -C $$i all; done + +clean: + set -e; for i in $(DIRS); do make -C $$i clean; done + +distclean: + set -e; for i in $(DIRS); do make -C $$i distclean; done + +avr: + set -e; for i in $(DIRS); do make -C $$i avr; done + +avrclean: + set -e; for i in $(DIRS); do make -C $$i avrclean; done + +avrdistclean: + set -e; for i in $(DIRS); do make -C $$i avrdistclean; done + Index: usb-fpga-2.13/flashbench/flashbench.bat =================================================================== --- usb-fpga-2.13/flashbench/flashbench.bat (nonexistent) +++ usb-fpga-2.13/flashbench/flashbench.bat (revision 3) @@ -0,0 +1,2 @@ +java -cp FlashBench.jar FlashBench +pause Index: usb-fpga-2.13/flashbench/flashbench.sh =================================================================== --- usb-fpga-2.13/flashbench/flashbench.sh (nonexistent) +++ usb-fpga-2.13/flashbench/flashbench.sh (revision 3) @@ -0,0 +1,3 @@ +#make -C ../../ztex/java distclean all || exit +#make distclean all || exit +java -cp FlashBench.jar FlashBench $@
usb-fpga-2.13/flashbench/flashbench.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.13/flashbench/Readme =================================================================== --- usb-fpga-2.13/flashbench/Readme (nonexistent) +++ usb-fpga-2.13/flashbench/Readme (revision 3) @@ -0,0 +1,18 @@ +flashbench +---------- + +A write / read benchmark for Flash memory on ZTEX modules. + +ATTENTION: The tests will destroy the data stored in Flash memory. + +The number of sectors to be tested can be specified using the +-s parameter of the host software. + +Three tests are performed: +1. Read/write test: Pseudo-random test data is written and immediately + read and compared (i.e. write sector 0, read sector 0, write sector + 1, read sector 1, ...) +2. Write test: Pseudo-random test data is written (i.e. write sector 0, + write sector 1, ...) +3. Write test: Pseudo-random test data is read and compared (i.e. read + sector 0, read sector 1, ...) Index: usb-fpga-2.13/flashbench/Makefile =================================================================== --- usb-fpga-2.13/flashbench/Makefile (nonexistent) +++ usb-fpga-2.13/flashbench/Makefile (revision 3) @@ -0,0 +1,21 @@ +######################### +# configuration section # +######################### + +ZTEXPREFIX=../../.. + +JARTARGET=FlashBench.jar +CLASSTARGETS=FlashBench.class +CLASSEXTRADEPS= +#CLASSEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/java/ztex/*.java) + +IHXTARGETS=flashbench.ihx +IHXEXTRADEPS= +#IHXEXTRADEPS:=$(wildcard $(ZTEXPREFIX)/include/*.h) +EXTRAJARFILES=flashbench.ihx + +################################ +# DO NOT CHANAGE THE FOLLOWING # +################################ + +include $(ZTEXPREFIX)/Makefile.mk Index: usb-fpga-2.13/flashbench/FlashBench.java =================================================================== --- usb-fpga-2.13/flashbench/FlashBench.java (nonexistent) +++ usb-fpga-2.13/flashbench/FlashBench.java (revision 3) @@ -0,0 +1,250 @@ +/*! + flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ + +import java.io.*; +import java.util.*; + +import ch.ntb.usb.*; + +import ztex.*; + +// ***************************************************************************** +// ******* ParameterException ************************************************** +// ***************************************************************************** +// Exception the prints a help message +class ParameterException extends Exception { + public final static String helpMsg = new String ( + "Parameters:\n"+ + " -d Device Number (default: 0)\n" + + " -s Number of sectors to be tested, -1 means all (default: 20)\n" + + " -f Force uploads\n" + + " -p Print bus info\n" + + " -w Enable certain workarounds which may be required for vmware + windows\n"+ + " -h This help" ); + + public ParameterException (String msg) { + super( msg + "\n" + helpMsg ); + } +} + +// ***************************************************************************** +// ******* Test0 *************************************************************** +// ***************************************************************************** +class FlashBench extends Ztex1v1 { + +// ******* FlashBench ********************************************************** +// constructor + public FlashBench ( ZtexDevice1 pDev ) throws UsbException { + super ( pDev ); + } + +// ******* testRW ************************************************************** +// measures read + write performance + public double testRW ( int num ) throws UsbException, InvalidFirmwareException, CapabilityException { + int secNum = Math.max(1, 2048 / flashSectorSize()); + byte[] buf1 = new byte[flashSectorSize() * secNum]; + byte[] buf2 = new byte[flashSectorSize() * secNum]; + int errors = 0; + + long t0 = new Date().getTime(); + + for ( int i=0; i=args.length) throw new Exception(); + devNum = Integer.parseInt( args[i] ); + } + catch (Exception e) { + throw new ParameterException("Device number expected after -d"); + } + } + if ( args[i].equals("-s") ) { + i++; + try { + if (i>=args.length) throw new Exception(); + sectors = Integer.parseInt( args[i] ); + } + catch (Exception e) { + throw new ParameterException("Number of sectors expected after -s"); + } + } + else if ( args[i].equals("-f") ) { + force = true; + } + else if ( args[i].equals("-p") ) { + bus.printBus(System.out); + System.exit(0); + } + else if ( args[i].equals("-p") ) { + bus.printBus(System.out); + System.exit(0); + } + else if ( args[i].equals("-w") ) { + workarounds = true; + } + else if ( args[i].equals("-h") ) { + System.err.println(ParameterException.helpMsg); + System.exit(0); + } + else throw new ParameterException("Invalid Parameter: "+args[i]); + } + + +// create the main class + FlashBench ztex = new FlashBench ( bus.device(devNum) ); + ztex.certainWorkarounds = workarounds; + +// upload the firmware if necessary + if ( force || ! ztex.valid() || ! ztex.dev().productString().equals("flashbench for UFM 2.13") ) { + System.out.println("Firmware upload time: " + ztex.uploadFirmware( "flashbench.ihx", force ) + " ms"); + } + +// print some information + System.out.println("Capabilities: " + ztex.capabilityInfo(", ")); + System.out.println("Enabled: " + ztex.flashEnabled()); + System.out.println("SectorSize: " + ztex.flashSectorSize()+" Bytes"); + System.out.println("Size: " + ztex.flashSize()+" Bytes"); + ztex.printSpiState(); + + +/* byte[] buf1 = new byte[ztex.flashSectorSize()]; + byte[] buf2 = new byte[ztex.flashSectorSize()]; + for (int i=0; iztex.flashSectors() ) sectors = ztex.flashSectors(); + + System.out.println("Read + Write Performance: " + ztex.testRW(sectors) + " kb/s \n"); + int seed = (int) Math.round(65535*Math.random()); + System.out.println("Write Performance: " + ztex.testW(sectors, seed) + " kb/s "); + System.out.println("Read Performance: " + ztex.testR(sectors, seed) + " kb/s \n"); + } + catch (Exception e) { + System.out.println("Error: "+e.getLocalizedMessage() ); + } + } + +} Index: usb-fpga-2.13/flashbench/flashbench.c =================================================================== --- usb-fpga-2.13/flashbench/flashbench.c (nonexistent) +++ usb-fpga-2.13/flashbench/flashbench.c (revision 3) @@ -0,0 +1,41 @@ +/*! + flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 2.13 + Copyright (C) 2009-2014 ZTEX GmbH. + http://www.ztex.de + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License version 3 as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see http://www.gnu.org/licenses/. +!*/ + +#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros +#include[ztex-utils.h] // include basic functions and variables + +// select ZTEX USB FPGA Module 2.13 as target +IDENTITY_UFM_2_13(10.17.0.0,0); + +// this product string is also used for identification by the host software +#define[PRODUCT_STRING]["flashbench for UFM 2.13"] +//USE_4KSECTORS; + +// enable Flash support +ENABLE_FLASH; + +// include the main part of the firmware kit, define the descriptors, ... +#include[ztex.h] + +void main(void) +{ + init_USB(); // init everything ... + + while (1) { } // ... and twiddle thumbs +} + Index: usb-fpga-2.13/Makefile =================================================================== --- usb-fpga-2.13/Makefile (nonexistent) +++ usb-fpga-2.13/Makefile (revision 3) @@ -0,0 +1,17 @@ +DIRS=flashdemo flashbench 2.13d + +.PHONY: default all clean distclean + +default: + @echo "This makefile is intended to clean up the project or to build all examples in this subdirectory" + @echo "Usage: make all | clean | distclean" + +all: + set -e; for i in $(DIRS); do make -C $$i all; done + +clean: + set -e; for i in $(DIRS); do make -C $$i clean; done + +distclean: + set -e; for i in $(DIRS); do make -C $$i distclean; done + Index: usb-fpga-1.15/nvmtest/NVMTest.java =================================================================== --- usb-fpga-1.15/nvmtest/NVMTest.java (revision 2) +++ usb-fpga-1.15/nvmtest/NVMTest.java (revision 3) @@ -1,6 +1,6 @@ /*! - nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Module 1.15 plus Experimental Board 1.10 - Copyright (C) 2009-2011 ZTEX GmbH. + nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Modules 1.15 plus Experimental Board 1.10 + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/nvmtest/nvmtest.c
1,6 → 1,6
/*!
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Module 1.15 plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
nvmtest -- ATxmega non volatile memory test on ZTEX USB-FPGA Modules 1.15 plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/flashdemo/FlashDemo.java
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 1.15
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/flashdemo/flashdemo.c
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 1.15
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/mmio/UCEcho.java
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15a
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/mmio/ucecho.c
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15a
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15a
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15a
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15a plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15a plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15a/memtest/memtest.c
1,6 → 1,6
/*!
memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15a
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh *.prj" -subdirs="par rtl synth" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent) @@ -1,61 +0,0 @@ ---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 -+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 -@@ -122,7 +122,6 @@ - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; -- signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; -@@ -135,7 +134,6 @@ - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; -- attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - - begin - -@@ -144,33 +142,6 @@ - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - -- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate -- --*********************************************************************** -- -- Differential input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFGDS -- generic map ( -- DIFF_TERM => TRUE -- ) -- port map ( -- I => sys_clk_p, -- IB => sys_clk_n, -- O => sys_clk_ibufg -- ); -- end generate; -- -- -- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate -- --*********************************************************************** -- -- SINGLE_ENDED input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFG -- port map ( -- I => sys_clk, -- O => sys_clk_ibufg -- ); -- end generate; -- - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** -@@ -209,7 +180,7 @@ - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', -- CLKIN1 => sys_clk_ibufg, -+ CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 06:55:40 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=2 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: eff89f81 - Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : ise_flow.bat -# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE batch mode -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -echo Synthesis Tool: XST - -mkdir "../synth/__projnav" > ise_flow_results.txt -mkdir "../synth/xst" >> ise_flow_results.txt -mkdir "../synth/xst/work" >> ise_flow_results.txt - -xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt -ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx45csg484-2 mem0.ngc mem0.ngd >> ise_flow_results.txt - -map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt -par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt -trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt -bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt - -echo done!
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent) @@ -1,2 +0,0 @@ -NEWPROJECT . -SETPROJECT .
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent) @@ -1,48 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 07:09:11 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7da1f376 - Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent) @@ -1,51 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.2 -# Date: Fri Jun 12 05:42:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -2 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET asynchronous_input_port_width=8 -CSET asynchronous_output_port_width=7 -CSET component_name=vio -CSET enable_asynchronous_input_port=false -CSET enable_asynchronous_output_port=true -CSET enable_synchronous_input_port=false -CSET enable_synchronous_output_port=false -CSET invert_clock_input=false -CSET synchronous_input_port_width=8 -CSET synchronous_output_port_width=8 -# END Parameters -GENERATE -# CRC: 66fe39ed - Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : create_ise.bat -# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:12 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -xtclsh set_ise_prop.tcl
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent) @@ -1,169 +0,0 @@ -##!/bin/csh -f -##**************************************************************************** -## (c) Copyright 2009 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. -## -##**************************************************************************** -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.5 -## \ \ Application : MIG -## / / Filename : rem_files.bat -## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $ -## \ \ / \ Date Created : Fri Feb 06 2009 -## \___\/\___\ -## -## Device : Spartan-6 -## Design Name : DDR/DDR2/DDR3/LPDDR -## Purpose : Batch file to remove files generated from ISE -## Reference : -## Revision History : -##**************************************************************************** - -rm -rf "../synth/__projnav" -rm -rf "../synth/xst" -rm -rf "../synth/_ngo" - -rm -rf tmp -rm -rf _xmsgs -rm -rf ila_xdb -rm -rf icon_xdb -rm -rf vio_xdb - -rm -rf xlnx_auto_0_xdb - -rm -rf vio_xmdf.tcl -rm -rf vio_readme.txt -rm -rf vio_flist.txt -rm -rf vio.xise del -rm -rf vio.xco del -rm -rf vio.ngc del -rm -rf vio.ise del -rm -rf vio.gise del -rm -rf vio.cdc del - -rm -rf coregen.cgp -rm -rf coregen.cgc -rm -rf coregen.log -rm -rf ila.cdc -rm -rf ila.gise -rm -rf ila.ise -rm -rf ila.ngc -rm -rf ila.xco -rm -rf ila.xise -rm -rf ila_flist.txt -rm -rf ila_readme.txt -rm -rf ila_xmdf.tcl - -rm -rf icon.asy -rm -rf icon.gise -rm -rf icon.ise -rm -rf icon.ncf -rm -rf icon.ngc -rm -rf icon.xco -rm -rf icon.xise -rm -rf icon_flist.txt -rm -rf icon_readme.txt -rm -rf icon_xmdf.tcl - -rm -rf ise_flow_results.txt -rm -rf mem0_vhdl.prj -rm -rf mem_interface_top.syr -rm -rf mem0.ngc -rm -rf mem0.ngr -rm -rf mem0_xst.xrpt -rm -rf mem0.bld -rm -rf mem0.ngd -rm -rf mem0_ngdbuild.xrpt -rm -rf mem0_map.map -rm -rf mem0_map.mrp -rm -rf mem0_map.ngm -rm -rf mem0.pcf -rm -rf mem0_map.ncd -rm -rf mem0_map.xrpt -rm -rf mem0_summary.xml -rm -rf mem0_usage.xml -rm -rf mem0.ncd -rm -rf mem0.par -rm -rf mem0.xpi -rm -rf mem0.ptwx -rm -rf mem0.pad -rm -rf mem0.unroutes -rm -rf mem0_pad.csv -rm -rf mem0_pad.txt -rm -rf mem0_par.xrpt -rm -rf mem0.twx -rm -rf mem0.bgn -rm -rf mem0.twr -rm -rf mem0.drc -rm -rf mem0_bitgen.xwbt -rm -rf mem0.bit - -# Files and folders generated by create ise -rm -rf test_xdb -rm -rf _xmsgs -rm -rf test.gise -rm -rf test.xise -rm -rf test.xise - -# Files and folders generated by ISE through GUI mode -rm -rf _ngo -rm -rf xst -rm -rf mem0.lso -rm -rf mem0.prj -rm -rf mem0.xst -rm -rf mem0.stx -rm -rf mem0_prev_built.ngd -rm -rf test.ntrc_log -rm -rf mem0_guide.ncd -rm -rf mem0.cmd_log -rm -rf mem0_summary.html -rm -rf mem0.ut -rm -rf par_usage_statistics.html -rm -rf usage_statistics_webtalk.html -rm -rf webtalk.log -rm -rf device_usage_statistics.html
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent) @@ -1,8 +0,0 @@ -vhdl work ../rtl/iodrp_controller.vhd -vhdl work ../rtl/iodrp_mcb_controller.vhd -vhdl work ../rtl/mcb_raw_wrapper.vhd -vhdl work ../rtl/mcb_soft_calibration.vhd -vhdl work ../rtl/mcb_soft_calibration_top.vhd -vhdl work ../rtl/mem0.vhd -vhdl work ../rtl/memc3_infrastructure.vhd -vhdl work ../rtl/memc3_wrapper.vhd Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (nonexistent) @@ -1,60 +0,0 @@ - - - mem0 - xc6slx45-csg484/-2 - 3.5 - - DDR2_SDRAM/Components/MT47H64M16XX-25E - 2500 - 1 - 1 - FALSE - - 13 - 10 - 3 - - - - 4(010) - 5 - Enable-Normal - Fullstrength - RTT Disabled - 0 - OCD Exit - Enable - Disable - Enable - Disable - Class II - Class II - CALIB_TERM - 25 Ohms - - - - 1 - Disable - Single-Ended - Two 32-bit bi-directional and four 32-bit unidirectional ports - AA2 - Y2 - Port0,Port1,Port2,Port3,Port4,Port5 - Bi-directional,Bi-directional,Write,Read,Write,Read - ROW_BANK_COLUMN - Round Robin - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - - Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh" -subdirs="user_design" - - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0.xise =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0.xise (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0.xise (nonexistent) @@ -1,122 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Index: usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0.xco =================================================================== --- usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0.xco (revision 2) +++ usb-fpga-1.15/1.15a/memtest/fpga/ipcore_dir/mem0.xco (nonexistent) @@ -1,42 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Wed Jul 20 10:38:33 2011 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT MIG family Xilinx,_Inc. 3.5 -# END Select -# BEGIN Parameters -CSET component_name=mem0 -CSET xml_input_file=./mem0/user_design/mig.prj -# END Parameters -GENERATE -# CRC: b055767e Index: usb-fpga-1.15/1.15a/memtest/MemTest.java =================================================================== --- usb-fpga-1.15/1.15a/memtest/MemTest.java (revision 2) +++ usb-fpga-1.15/1.15a/memtest/MemTest.java (revision 3) @@ -1,6 +1,6 @@ /*! - memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b - Copyright (C) 2009-2011 ZTEX GmbH. + memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15a + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/mmio/UCEcho.java
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/mmio/ucecho.c
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15b/memtest/memtest.c
1,6 → 1,6
/*!
memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent) @@ -1,61 +0,0 @@ ---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 -+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 -@@ -122,7 +122,6 @@ - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; -- signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; -@@ -135,7 +134,6 @@ - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; -- attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - - begin - -@@ -144,33 +142,6 @@ - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - -- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate -- --*********************************************************************** -- -- Differential input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFGDS -- generic map ( -- DIFF_TERM => TRUE -- ) -- port map ( -- I => sys_clk_p, -- IB => sys_clk_n, -- O => sys_clk_ibufg -- ); -- end generate; -- -- -- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate -- --*********************************************************************** -- -- SINGLE_ENDED input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFG -- port map ( -- I => sys_clk, -- O => sys_clk_ibufg -- ); -- end generate; -- - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** -@@ -209,7 +180,7 @@ - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', -- CLKIN1 => sys_clk_ibufg, -+ CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent) @@ -1,51 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.2 -# Date: Fri Jun 12 05:42:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET asynchronous_input_port_width=8 -CSET asynchronous_output_port_width=7 -CSET component_name=vio -CSET enable_asynchronous_input_port=false -CSET enable_asynchronous_output_port=true -CSET enable_synchronous_input_port=false -CSET enable_synchronous_output_port=false -CSET invert_clock_input=false -CSET synchronous_input_port_width=8 -CSET synchronous_output_port_width=8 -# END Parameters -GENERATE -# CRC: 66fe39ed - Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : create_ise.bat -# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:12 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -xtclsh set_ise_prop.tcl
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent) @@ -1,169 +0,0 @@ -##!/bin/csh -f -##**************************************************************************** -## (c) Copyright 2009 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. -## -##**************************************************************************** -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.5 -## \ \ Application : MIG -## / / Filename : rem_files.bat -## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $ -## \ \ / \ Date Created : Fri Feb 06 2009 -## \___\/\___\ -## -## Device : Spartan-6 -## Design Name : DDR/DDR2/DDR3/LPDDR -## Purpose : Batch file to remove files generated from ISE -## Reference : -## Revision History : -##**************************************************************************** - -rm -rf "../synth/__projnav" -rm -rf "../synth/xst" -rm -rf "../synth/_ngo" - -rm -rf tmp -rm -rf _xmsgs -rm -rf ila_xdb -rm -rf icon_xdb -rm -rf vio_xdb - -rm -rf xlnx_auto_0_xdb - -rm -rf vio_xmdf.tcl -rm -rf vio_readme.txt -rm -rf vio_flist.txt -rm -rf vio.xise del -rm -rf vio.xco del -rm -rf vio.ngc del -rm -rf vio.ise del -rm -rf vio.gise del -rm -rf vio.cdc del - -rm -rf coregen.cgp -rm -rf coregen.cgc -rm -rf coregen.log -rm -rf ila.cdc -rm -rf ila.gise -rm -rf ila.ise -rm -rf ila.ngc -rm -rf ila.xco -rm -rf ila.xise -rm -rf ila_flist.txt -rm -rf ila_readme.txt -rm -rf ila_xmdf.tcl - -rm -rf icon.asy -rm -rf icon.gise -rm -rf icon.ise -rm -rf icon.ncf -rm -rf icon.ngc -rm -rf icon.xco -rm -rf icon.xise -rm -rf icon_flist.txt -rm -rf icon_readme.txt -rm -rf icon_xmdf.tcl - -rm -rf ise_flow_results.txt -rm -rf mem0_vhdl.prj -rm -rf mem_interface_top.syr -rm -rf mem0.ngc -rm -rf mem0.ngr -rm -rf mem0_xst.xrpt -rm -rf mem0.bld -rm -rf mem0.ngd -rm -rf mem0_ngdbuild.xrpt -rm -rf mem0_map.map -rm -rf mem0_map.mrp -rm -rf mem0_map.ngm -rm -rf mem0.pcf -rm -rf mem0_map.ncd -rm -rf mem0_map.xrpt -rm -rf mem0_summary.xml -rm -rf mem0_usage.xml -rm -rf mem0.ncd -rm -rf mem0.par -rm -rf mem0.xpi -rm -rf mem0.ptwx -rm -rf mem0.pad -rm -rf mem0.unroutes -rm -rf mem0_pad.csv -rm -rf mem0_pad.txt -rm -rf mem0_par.xrpt -rm -rf mem0.twx -rm -rf mem0.bgn -rm -rf mem0.twr -rm -rf mem0.drc -rm -rf mem0_bitgen.xwbt -rm -rf mem0.bit - -# Files and folders generated by create ise -rm -rf test_xdb -rm -rf _xmsgs -rm -rf test.gise -rm -rf test.xise -rm -rf test.xise - -# Files and folders generated by ISE through GUI mode -rm -rf _ngo -rm -rf xst -rm -rf mem0.lso -rm -rf mem0.prj -rm -rf mem0.xst -rm -rf mem0.stx -rm -rf mem0_prev_built.ngd -rm -rf test.ntrc_log -rm -rf mem0_guide.ncd -rm -rf mem0.cmd_log -rm -rf mem0_summary.html -rm -rf mem0.ut -rm -rf par_usage_statistics.html -rm -rf usage_statistics_webtalk.html -rm -rf webtalk.log -rm -rf device_usage_statistics.html
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 06:55:40 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=2 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: eff89f81 - Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : ise_flow.bat -# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE batch mode -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -echo Synthesis Tool: XST - -mkdir "../synth/__projnav" > ise_flow_results.txt -mkdir "../synth/xst" >> ise_flow_results.txt -mkdir "../synth/xst/work" >> ise_flow_results.txt - -xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt -ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx75csg484-3 mem0.ngc mem0.ngd >> ise_flow_results.txt - -map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt -par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt -trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt -bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt - -echo done!
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent) @@ -1,2 +0,0 @@ -NEWPROJECT . -SETPROJECT .
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent) @@ -1,48 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 07:09:11 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7da1f376 - Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent) @@ -1,8 +0,0 @@ -vhdl work ../rtl/iodrp_controller.vhd -vhdl work ../rtl/iodrp_mcb_controller.vhd -vhdl work ../rtl/mcb_raw_wrapper.vhd -vhdl work ../rtl/mcb_soft_calibration.vhd -vhdl work ../rtl/mcb_soft_calibration_top.vhd -vhdl work ../rtl/mem0.vhd -vhdl work ../rtl/memc3_infrastructure.vhd -vhdl work ../rtl/memc3_wrapper.vhd Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/clean.sh =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh" -subdirs="user_design" - - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0.xise =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0.xise (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0.xise (nonexistent) @@ -1,122 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0.xco =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0.xco (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/mem0.xco (nonexistent) @@ -1,42 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 12.2 -# Date: Wed Jul 20 10:38:33 2011 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT MIG family Xilinx,_Inc. 3.5 -# END Select -# BEGIN Parameters -CSET component_name=mem0 -CSET xml_input_file=./mem0/user_design/mig.prj -# END Parameters -GENERATE -# CRC: b055767e Index: usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/clean.sh =================================================================== --- usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/clean.sh (revision 2) +++ usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.vhd *.sh *.ise *.xco *.xise *.tcl" -subdirs="mem0 custom_part" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.15/1.15b/memtest/fpga/ipcore_dir/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15b/memtest/MemTest.java =================================================================== --- usb-fpga-1.15/1.15b/memtest/MemTest.java (revision 2) +++ usb-fpga-1.15/1.15b/memtest/MemTest.java (revision 3) @@ -1,6 +1,6 @@ /*! memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b - Copyright (C) 2009-2011 ZTEX GmbH. + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/mmio/UCEcho.java
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15d and 1.15x
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/mmio/ucecho.c
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15d and 1.15x
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15d and 1.15x
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.15d and 1.15x
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/lightshow/Lightshow.java
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15d plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/lightshow/avr/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on Experimental Board 1.10
Copyright (C) 2009-2010 ZTEX e.K.
Copyright (C) 2009-2014 ZTEX GmbH
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/lightshow/lightshow.c
1,6 → 1,6
/*!
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15b plus Experimental Board 1.10
Copyright (C) 2009-2011 ZTEX GmbH.
lightshow -- lightshow on ZTEX USB-FPGA Module 1.15d plus Experimental Board 1.10
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15d/memtest/memtest.c
1,6 → 1,6
/*!
memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15d and 1.15x
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/mig.prj (nonexistent) @@ -1,60 +0,0 @@ - - - mem0 - xc6slx75-csg484/-3 - 3.5 - - DDR2_SDRAM/Components/MT47H64M16XX-25E - 2500 - 1 - 1 - FALSE - - 13 - 10 - 3 - - - - 4(010) - 5 - Enable-Normal - Fullstrength - RTT Disabled - 0 - OCD Exit - Enable - Disable - Enable - Disable - Class II - Class II - CALIB_TERM - 25 Ohms - - - - 1 - Disable - Single-Ended - Two 32-bit bi-directional and four 32-bit unidirectional ports - AA2 - Y2 - Port0,Port1,Port2,Port3,Port4,Port5 - Bi-directional,Bi-directional,Write,Read,Write,Read - ROW_BANK_COLUMN - Round Robin - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - 012345 - 123450 - 234501 - 345012 - 450123 - 501234 - - Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh (nonexistent) @@ -1,85 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh *.prj" -subdirs="par rtl synth" - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff (nonexistent) @@ -1,61 +0,0 @@ ---- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 -+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 -@@ -122,7 +122,6 @@ - signal mcb_drp_clk_bufg_in : std_logic; - signal clkfbout_clkfbin : std_logic; - signal rst_tmp : std_logic; -- signal sys_clk_ibufg : std_logic; - signal sys_rst : std_logic; - signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0); - signal powerup_pll_locked : std_logic; -@@ -135,7 +134,6 @@ - attribute KEEP : string; - attribute max_fanout of rst0_sync_r : signal is "10"; - attribute syn_maxfan of rst0_sync_r : signal is 10; -- attribute KEEP of sys_clk_ibufg : signal is "TRUE"; - - begin - -@@ -144,33 +142,6 @@ - pll_lock <= bufpll_mcb_locked; - mcb_drp_clk <= mcb_drp_clk_sig; - -- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate -- --*********************************************************************** -- -- Differential input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFGDS -- generic map ( -- DIFF_TERM => TRUE -- ) -- port map ( -- I => sys_clk_p, -- IB => sys_clk_n, -- O => sys_clk_ibufg -- ); -- end generate; -- -- -- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate -- --*********************************************************************** -- -- SINGLE_ENDED input clock input buffers -- --*********************************************************************** -- u_ibufg_sys_clk : IBUFG -- port map ( -- I => sys_clk, -- O => sys_clk_ibufg -- ); -- end generate; -- - --*************************************************************************** - -- Global clock generation and distribution - --*************************************************************************** -@@ -209,7 +180,7 @@ - ( - CLKFBIN => clkfbout_clkfbin, - CLKINSEL => '1', -- CLKIN1 => sys_clk_ibufg, -+ CLKIN1 => sys_clk, - CLKIN2 => '0', - DADDR => (others => '0'), - DCLK => '0', Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/vio_coregen.xco (nonexistent) @@ -1,51 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.2 -# Date: Fri Jun 12 05:42:56 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET asynchronous_input_port_width=8 -CSET asynchronous_output_port_width=7 -CSET component_name=vio -CSET enable_asynchronous_input_port=false -CSET enable_asynchronous_output_port=true -CSET enable_synchronous_input_port=false -CSET enable_synchronous_output_port=false -CSET invert_clock_input=false -CSET synchronous_input_port_width=8 -CSET synchronous_output_port_width=8 -# END Parameters -GENERATE -# CRC: 66fe39ed - Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh (nonexistent) @@ -1,72 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : create_ise.bat -# /___/ /\ Date Last Modified : $Date: 2010/03/21 17:21:12 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -xtclsh set_ise_prop.tcl
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/create_ise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh (nonexistent) @@ -1,169 +0,0 @@ -##!/bin/csh -f -##**************************************************************************** -## (c) Copyright 2009 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. -## -##**************************************************************************** -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.5 -## \ \ Application : MIG -## / / Filename : rem_files.bat -## /___/ /\ Date Last Modified : $Date: 2010/05/21 10:07:50 $ -## \ \ / \ Date Created : Fri Feb 06 2009 -## \___\/\___\ -## -## Device : Spartan-6 -## Design Name : DDR/DDR2/DDR3/LPDDR -## Purpose : Batch file to remove files generated from ISE -## Reference : -## Revision History : -##**************************************************************************** - -rm -rf "../synth/__projnav" -rm -rf "../synth/xst" -rm -rf "../synth/_ngo" - -rm -rf tmp -rm -rf _xmsgs -rm -rf ila_xdb -rm -rf icon_xdb -rm -rf vio_xdb - -rm -rf xlnx_auto_0_xdb - -rm -rf vio_xmdf.tcl -rm -rf vio_readme.txt -rm -rf vio_flist.txt -rm -rf vio.xise del -rm -rf vio.xco del -rm -rf vio.ngc del -rm -rf vio.ise del -rm -rf vio.gise del -rm -rf vio.cdc del - -rm -rf coregen.cgp -rm -rf coregen.cgc -rm -rf coregen.log -rm -rf ila.cdc -rm -rf ila.gise -rm -rf ila.ise -rm -rf ila.ngc -rm -rf ila.xco -rm -rf ila.xise -rm -rf ila_flist.txt -rm -rf ila_readme.txt -rm -rf ila_xmdf.tcl - -rm -rf icon.asy -rm -rf icon.gise -rm -rf icon.ise -rm -rf icon.ncf -rm -rf icon.ngc -rm -rf icon.xco -rm -rf icon.xise -rm -rf icon_flist.txt -rm -rf icon_readme.txt -rm -rf icon_xmdf.tcl - -rm -rf ise_flow_results.txt -rm -rf mem0_vhdl.prj -rm -rf mem_interface_top.syr -rm -rf mem0.ngc -rm -rf mem0.ngr -rm -rf mem0_xst.xrpt -rm -rf mem0.bld -rm -rf mem0.ngd -rm -rf mem0_ngdbuild.xrpt -rm -rf mem0_map.map -rm -rf mem0_map.mrp -rm -rf mem0_map.ngm -rm -rf mem0.pcf -rm -rf mem0_map.ncd -rm -rf mem0_map.xrpt -rm -rf mem0_summary.xml -rm -rf mem0_usage.xml -rm -rf mem0.ncd -rm -rf mem0.par -rm -rf mem0.xpi -rm -rf mem0.ptwx -rm -rf mem0.pad -rm -rf mem0.unroutes -rm -rf mem0_pad.csv -rm -rf mem0_pad.txt -rm -rf mem0_par.xrpt -rm -rf mem0.twx -rm -rf mem0.bgn -rm -rf mem0.twr -rm -rf mem0.drc -rm -rf mem0_bitgen.xwbt -rm -rf mem0.bit - -# Files and folders generated by create ise -rm -rf test_xdb -rm -rf _xmsgs -rm -rf test.gise -rm -rf test.xise -rm -rf test.xise - -# Files and folders generated by ISE through GUI mode -rm -rf _ngo -rm -rf xst -rm -rf mem0.lso -rm -rf mem0.prj -rm -rf mem0.xst -rm -rf mem0.stx -rm -rf mem0_prev_built.ngd -rm -rf test.ntrc_log -rm -rf mem0_guide.ncd -rm -rf mem0.cmd_log -rm -rf mem0_summary.html -rm -rf mem0.ut -rm -rf par_usage_statistics.html -rm -rf usage_statistics_webtalk.html -rm -rf webtalk.log -rm -rf device_usage_statistics.html
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/rem_files.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ila_coregen.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 06:55:40 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = False -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=Disabled -CSET counter_width_10=Disabled -CSET counter_width_11=Disabled -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=Disabled -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=256 -CSET data_same_as_trigger=false -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=true -CSET exclude_from_data_storage_10=true -CSET exclude_from_data_storage_11=true -CSET exclude_from_data_storage_12=true -CSET exclude_from_data_storage_13=true -CSET exclude_from_data_storage_14=true -CSET exclude_from_data_storage_15=true -CSET exclude_from_data_storage_16=true -CSET exclude_from_data_storage_2=true -CSET exclude_from_data_storage_3=true -CSET exclude_from_data_storage_4=true -CSET exclude_from_data_storage_5=true -CSET exclude_from_data_storage_6=true -CSET exclude_from_data_storage_7=true -CSET exclude_from_data_storage_8=true -CSET exclude_from_data_storage_9=true -CSET match_type_1=basic_with_edges -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=basic -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=1 -CSET number_of_trigger_ports=1 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=2 -CSET trigger_port_width_10=8 -CSET trigger_port_width_11=8 -CSET trigger_port_width_12=8 -CSET trigger_port_width_13=8 -CSET trigger_port_width_14=8 -CSET trigger_port_width_15=8 -CSET trigger_port_width_16=8 -CSET trigger_port_width_2=8 -CSET trigger_port_width_3=8 -CSET trigger_port_width_4=8 -CSET trigger_port_width_5=8 -CSET trigger_port_width_6=8 -CSET trigger_port_width_7=8 -CSET trigger_port_width_8=8 -CSET trigger_port_width_9=8 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: eff89f81 - Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/csh -f -#***************************************************************************** -# (c) Copyright 2009 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# **************************************************************************** -# ____ ____ -# / /\/ / -# /___/ \ / Vendor : Xilinx -# \ \ \/ Version : 3.5 -# \ \ Application : MIG -# / / Filename : ise_flow.bat -# /___/ /\ Date Last Modified : $Date: 2010/06/06 09:42:27 $ -# \ \ / \ Date Created : Fri Feb 06 2009 -# \___\/\___\ -# -# Device : Spartan-6 -# Design Name : DDR/DDR2/DDR3/LPDDR -# Purpose : Batch file to run PAR through ISE batch mode -# Reference : -# Revision History : -# **************************************************************************** - -./rem_files.sh - - - - -echo Synthesis Tool: XST - -mkdir "../synth/__projnav" > ise_flow_results.txt -mkdir "../synth/xst" >> ise_flow_results.txt -mkdir "../synth/xst/work" >> ise_flow_results.txt - -xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt -ngdbuild -intstyle ise -dd ../synth/_ngo -uc mem0.ucf -p xc6slx75csg484-3 mem0.ngc mem0.ngd >> ise_flow_results.txt - -map -intstyle ise -detail -w -pr off -c 100 -o mem0_map.ncd mem0.ngd mem0.pcf >> ise_flow_results.txt -par -w -intstyle ise -ol std mem0_map.ncd mem0.ncd mem0.pcf >> ise_flow_results.txt -trce -e 100 mem0.ncd mem0.pcf >> ise_flow_results.txt -bitgen -intstyle ise -f mem_interface_top.ut mem0.ncd >> ise_flow_results.txt - -echo done!
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/ise_flow.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh (nonexistent) @@ -1,2 +0,0 @@ -NEWPROJECT . -SETPROJECT .
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/makeproj.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/par/icon_coregen.xco (nonexistent) @@ -1,48 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 11.1 -# Date: Wed Mar 11 07:09:11 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = vhdl -SET device = xc6slx75 -SET devicefamily = spartan6 -SET flowvendor = ISE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = csg484 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -3 -SET verilogsim = False -SET vhdlsim = False -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7da1f376 - Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/user_design/synth/mem0.prj (nonexistent) @@ -1,8 +0,0 @@ -vhdl work ../rtl/iodrp_controller.vhd -vhdl work ../rtl/iodrp_mcb_controller.vhd -vhdl work ../rtl/mcb_raw_wrapper.vhd -vhdl work ../rtl/mcb_soft_calibration.vhd -vhdl work ../rtl/mcb_soft_calibration_top.vhd -vhdl work ../rtl/mem0.vhd -vhdl work ../rtl/memc3_infrastructure.vhd -vhdl work ../rtl/memc3_wrapper.vhd Index: usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/clean.sh =================================================================== --- usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/clean.sh (revision 2) +++ usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/clean.sh (nonexistent) @@ -1,86 +0,0 @@ -#!/bin/bash - -# This files / directories from this directory will not be removed -# Filenames with spaces or other spuid characters will be ignored -sourcefiles="*.sh" -subdirs="user_design" - - -# This sould not be edited. -list_files() { - if [ "$2" != "" ]; then - echo "$1" - for i in $2; do - echo " $i" - done - fi -} - -rmfiles="" -rmdirs="" -keepfiles="" -keepdirs="" -allfiles=`ls -A` -for f in $allfiles; do - keep=false - for i in $sourcefiles; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $subdirs; do - if [ "$i" == "$f" ]; then - keep=true - fi - done - for i in $binfiles; do # binfiles is set by distclean.sh - if [ "$i" == "$f" ]; then - keep=false - fi - done - if [ -d "$f" ]; then - if $keep; then - keepdirs+=" $f" - else - rmdirs+=" $f" - fi - fi - if [ -f "$f" ]; then - if $keep; then - keepfiles+=" $f" - else - rmfiles+=" $f" - fi - fi -done - - -echo -echo "Directory $PWD:" -list_files "This directories will NOT be removed:" "$keepdirs" -list_files "This files will NOT be removed:" "$keepfiles" -list_files "This directories will be removed:" "$rmdirs" -list_files "This files will be removed:" "$rmfiles" - -if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then - c="yes" -else - echo -n 'Confirm this by entering "yes": ' - read c -fi - -if [ "$c" == "yes" ]; then - [ "$rmfiles" != "" ] && rm $rmfiles - [ "$rmdirs" != "" ] && rm -r $rmdirs - - for d in $subdirs; do - if [ -x "$d/clean.sh" ]; then - cd $d - ./clean.sh || exit 1 - cd .. - fi - done - - exit 0 -fi -exit 1
usb-fpga-1.15/1.15d/memtest/fpga/ipcore_dir/mem0/clean.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb-fpga-1.15/1.15d/memtest/MemTest.java =================================================================== --- usb-fpga-1.15/1.15d/memtest/MemTest.java (revision 2) +++ usb-fpga-1.15/1.15d/memtest/MemTest.java (revision 3) @@ -1,6 +1,6 @@ /*! - memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15b - Copyright (C) 2009-2011 ZTEX GmbH. + memtest -- DDR2 SDRAM FIFO for testing memory on ZTEX USB-FPGA Module 1.15d and 1.15x + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/standalone/standalone.c
1,6 → 1,6
/*!
standalone -- standalone firmware that supports FPGA configuration from Flash firmware loading from EEPROM for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
standalone -- standalone firmware that supports FPGA configuration from Flash firmware loading from EEPROM for ZTEX USB-FPGA Modules 1.15
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/1.15x/default/default.c
1,6 → 1,6
/*!
default -- Default Firmware for ZTEX USB-FPGA Modules 1.15x
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/flashbench/FlashBench.java
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 1.15
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-1.15/flashbench/flashbench.c
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 1.15
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/all/debug/Debug.java
1,6 → 1,6
/*!
debug -- debug helper example
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/all/debug/debug.c
1,6 → 1,6
/*!
debug -- debug helper example
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/all/ucecho/c/UCEcho.c
1,6 → 1,6
/*!
UCEcho -- C host software for ucecho examples
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/all/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for all EZ-USB devices
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/all/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for all EZ-USB devices
Copyright (C) 2009-2011 ZTEX GmbH.
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/flashdemo/FlashDemo.java
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 2.16
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/flashdemo/flashdemo.c
1,6 → 1,6
/*!
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashdemo -- demo for Flash memory access from firmware and host software for ZTEX USB-FPGA Modules 2.16
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/mmio/UCEcho.java
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 2.16b
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/mmio/ucecho.c
1,6 → 1,6
/*!
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 2.16b
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/intraffic/InTraffic.java
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 2.16b
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/intraffic/intraffic.c
1,6 → 1,6
/*!
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
Copyright (C) 2009-2011 ZTEX GmbH.
intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 2.16b
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/ucecho/UCEcho.java
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 1.2
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion and bitstream encryption example for ZTEX USB-FPGA Module 2.16b
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/ucecho/ucecho.c
1,6 → 1,6
/*!
ucecho -- uppercase conversion example for ZTEX USB-FPGA Module 2.16
Copyright (C) 2009-2011 ZTEX GmbH.
ucecho -- uppercase conversion and bitstream encryption example for ZTEX USB-FPGA Module 2.16b
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/2.16b/ucecho/Readme
14,8 → 14,3
The driver (defined in UCEcho.java) uploads the the Firmware (ucecho.ihx)
to the EZ-USB Microcontroller and the Bitstream (fpga/ucecho.bit) to the
FPGA if necessary, sends user string to the device and reads them back.
 
Uploading the Firmware to EEPROM is also supported by the firmware (e.g.
using the FWLoader utility).
 
This example may serve a good starting point for own projects.
/usb-fpga-2.16/2.16b/lightshow/lightshow.sh
0,0 → 1,2
../../../../java/FWLoader/FWLoader -f -uf fpga/lightshow.runs/impl_1/lightshow.bit
 
usb-fpga-2.16/2.16b/lightshow/lightshow.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.xpr =================================================================== --- usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.xpr (nonexistent) +++ usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.xpr (revision 3) @@ -0,0 +1,18 @@ + + + + + + + + + + + + Index: usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.xdc =================================================================== --- usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.xdc (nonexistent) +++ usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.xdc (revision 3) @@ -0,0 +1,56 @@ +# CLKOUT/FXCLK +create_clock -name fxclk -period 10 [get_ports fxclk] +set_property PACKAGE_PIN Y18 [get_ports fxclk] +set_property IOSTANDARD LVCMOS33 [get_ports fxclk] + +# led1 +set_property PACKAGE_PIN B21 [get_ports {led1[0]}] ;# A6 / B21~IO_L21P_T3_DQS_16 +set_property PACKAGE_PIN A21 [get_ports {led1[1]}] ;# B6 / A21~IO_L21N_T3_DQS_16 +set_property PACKAGE_PIN D20 [get_ports {led1[2]}] ;# A7 / D20~IO_L19P_T3_16 +set_property PACKAGE_PIN C20 [get_ports {led1[3]}] ;# B7 / C20~IO_L19N_T3_VREF_16 +set_property PACKAGE_PIN B20 [get_ports {led1[4]}] ;# A8 / B20~IO_L16P_T2_16 +set_property PACKAGE_PIN A20 [get_ports {led1[5]}] ;# B8 / A20~IO_L16N_T2_16 +set_property PACKAGE_PIN C19 [get_ports {led1[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16 +set_property PACKAGE_PIN A19 [get_ports {led1[7]}] ;# B9 / A19~IO_L17N_T2_16 +set_property PACKAGE_PIN C18 [get_ports {led1[8]}] ;# A10 / C18~IO_L13P_T2_MRCC_16 +set_property PACKAGE_PIN A18 [get_ports {led1[9]}] ;# B10 / A18~IO_L17P_T2_16 +set_property IOSTANDARD LVCMOS33 [get_ports {led1[*]}] +set_property DRIVE 12 [get_ports {led1[*]}] + +# sw +set_property PACKAGE_PIN B18 [get_ports {sw[0]}] ;# A11 / B18~IO_L11N_T1_SRCC_16 +set_property PACKAGE_PIN D17 [get_ports {sw[1]}] ;# B11 / D17~IO_L12P_T1_MRCC_16 +set_property PACKAGE_PIN B17 [get_ports {sw[2]}] ;# A12 / B17~IO_L11P_T1_SRCC_16 +set_property PACKAGE_PIN C17 [get_ports {sw[3]}] ;# B12 / C17~IO_L12N_T1_MRCC_16 +set_property IOSTANDARD LVCMOS33 [get_ports {sw[*]}] +set_property PULLUP true [get_ports {sw[*]}] + +# led2 +set_property PACKAGE_PIN AB17 [get_ports {led2[0]}] ;# C3 / AB17~IO_L2N_T0_13 +set_property PACKAGE_PIN AB16 [get_ports {led2[1]}] ;# D3 / AB16~IO_L2P_T0_13 +set_property PACKAGE_PIN Y16 [get_ports {led2[2]}] ;# C4 / Y16~IO_L1P_T0_13 +set_property PACKAGE_PIN AA16 [get_ports {led2[3]}] ;# D4 / AA16~IO_L1N_T0_13 +set_property PACKAGE_PIN AA15 [get_ports {led2[4]}] ;# C5 / AA15~IO_L4P_T0_13 +set_property PACKAGE_PIN AB15 [get_ports {led2[5]}] ;# D5 / AB15~IO_L4N_T0_13 +set_property PACKAGE_PIN Y13 [get_ports {led2[6]}] ;# C6 / Y13~IO_L5P_T0_13 +set_property PACKAGE_PIN AA14 [get_ports {led2[7]}] ;# D6 / AA14~IO_L5N_T0_13 +set_property PACKAGE_PIN W14 [get_ports {led2[8]}] ;# C7 / W14~IO_L6P_T0_13 +set_property PACKAGE_PIN Y14 [get_ports {led2[9]}] ;# D7 / Y14~IO_L6N_T0_VREF_13 +set_property PACKAGE_PIN AA13 [get_ports {led2[10]}] ;# C8 / AA13~IO_L3P_T0_DQS_13 +set_property PACKAGE_PIN AB13 [get_ports {led2[11]}] ;# D8 / AB13~IO_L3N_T0_DQS_13 +set_property PACKAGE_PIN AB12 [get_ports {led2[12]}] ;# C9 / AB12~IO_L7N_T1_13 +set_property PACKAGE_PIN AB11 [get_ports {led2[13]}] ;# D9 / AB11~IO_L7P_T1_13 +set_property PACKAGE_PIN W12 [get_ports {led2[14]}] ;# C10 / W12~IO_L12N_T1_MRCC_13 +set_property PACKAGE_PIN W11 [get_ports {led2[15]}] ;# D10 / W11~IO_L12P_T1_MRCC_13 +set_property PACKAGE_PIN AA11 [get_ports {led2[16]}] ;# C11 / AA11~IO_L9N_T1_DQS_13 +set_property PACKAGE_PIN AA10 [get_ports {led2[17]}] ;# D11 / AA10~IO_L9P_T1_DQS_13 +set_property PACKAGE_PIN AA9 [get_ports {led2[18]}] ;# C12 / AA9~IO_L8P_T1_13 +set_property PACKAGE_PIN AB10 [get_ports {led2[19]}] ;# D12 / AB10~IO_L8N_T1_13 +set_property IOSTANDARD LVCMOS33 [get_ports {led2[*]}] +set_property DRIVE 12 [get_ports {led2[*]}] + +# bitstream settings +set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] Index: usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.vhd =================================================================== --- usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.vhd (nonexistent) +++ usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.vhd (revision 3) @@ -0,0 +1,110 @@ +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +entity lightshow is + port( + led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board + led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board + sw : in std_logic_vector(3 downto 0); + fxclk : in std_logic + ); +end lightshow; + +--signal declaration +architecture RTL of lightshow is + +type tPattern1 is array(9 downto 0) of integer range 0 to 255; +type tPattern2 is array(19 downto 0) of integer range 0 to 255; + +signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1 +signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2 +signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2 +signal pattern2 : tPattern2; -- pattern20 + pattern21 + +signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0); +signal pwm_cnt : std_logic_vector(19 downto 0); +signal pwm_cnt8 : std_logic_vector(7 downto 0); + +begin + pwm_cnt8 <= pwm_cnt(19 downto 12); + + dp_fxclk: process(fxclk) + begin + if fxclk' event and fxclk = '1' then + + -- pattern for led 1 + if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz + then + if ( sw(0) = '1' ) + then + pattern1(8 downto 0) <= pattern1(9 downto 1); + pattern1(9) <= pattern1(0); + else + pattern1(9 downto 1) <= pattern1(8 downto 0); + pattern1(0) <= pattern1(9); + end if; + cnt1 <= (others => '0'); + else + cnt1 <= cnt1 + 1; + end if; + + -- pattern for led 2 + if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz + then + pattern20(18 downto 0) <= pattern20(19 downto 1); + pattern20(19) <= pattern20(0); + cnt20 <= (others => '0'); + else + cnt20 <= cnt20 + 1; + end if; + + if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) ) + then + if ( sw(1) = '1' ) + then + pattern21(18 downto 0) <= pattern21(19 downto 1); + pattern21(19) <= pattern21(0); + else + pattern21(19 downto 1) <= pattern21(18 downto 0); + pattern21(0) <= pattern21(19); + end if; + cnt21 <= (others => '0'); + else + cnt21 <= cnt21 + 1; + end if; + + for i in 0 to 19 loop + pattern2(i) <= pattern20(i) + pattern21(i); + end loop; + + -- pwm + if ( pwm_cnt8 = conv_std_logic_vector(255,8) ) + then + pwm_cnt <= ( others => '0' ); + else + pwm_cnt <= pwm_cnt + 1; + end if; + -- led1 + for i in 0 to 9 loop + if ( pwm_cnt8 < pattern1(i) ) + then + led1(i) <= '1'; + else + led1(i) <= '0'; + end if; + end loop; + for i in 0 to 19 loop + if (pwm_cnt8 < pattern2(i) ) + then + led2(i) <= '1'; + else + led2(i) <= '0'; + end if; + end loop; + + end if; + end process dp_fxclk; + +end RTL; Index: usb-fpga-2.16/2.16b/lightshow/fpga/clean.sh =================================================================== --- usb-fpga-2.16/2.16b/lightshow/fpga/clean.sh (nonexistent) +++ usb-fpga-2.16/2.16b/lightshow/fpga/clean.sh (revision 3) @@ -0,0 +1,79 @@ +#!/bin/bash + +# This files / directories will be removed +rms="fpga.hw *.cache *.data/wt *.runs/.jobs *.runs/synth_*/* *.runs/impl_*/*" +# This files / directories in *.srcs/sources_*/ip/*/ will be removed +ip_rms="_tmp log.txt */docs */example_design */user_design/log.txt" +# Files with this extensions are not removed +keepext="vhd v xdc ucf bit bin" + +# This sould not be edited. +list_files() { + if [ "$2" != "" ]; then + echo "$1" + for i in $2; do + echo " $i" + done + fi +} + +check_ext() { + f=${1##*.} + for e in $keepext; do + if [ "$e" = "$f" ]; then + return 0 + fi + done + return 1 +} + +rmfiles="" +keepfiles="" +rmdirs="" +for i in $ip_rms; do + for j in *.srcs/sources_*/ip/*/$i; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi + done +done + +for j in $rms; do + if [ -d "$j" ]; then + rmdirs+=" $j" + fi + if [ -f "$j" ]; then + if check_ext "$j"; then + keepfiles+=" $j" + else + rmfiles+=" $j" + fi + fi +done + +list_files "This files will NOT be removed:" "$keepfiles" +list_files "This directories will be removed:" "$rmdirs" +list_files "This files will be removed:" "$rmfiles" + +if [ "$rmfiles" == "" -a "$rmdirs" == "" ]; then + c="yes" +else + echo -n 'Confirm this by entering "yes": ' + read c +fi + +if [ "$c" == "yes" ]; then + rm -fr *.runs/impl_*/.* 2>/dev/null + rm -fr *.runs/synth_*/.* 2>/dev/null + [ "$rmfiles" != "" ] && rm $rmfiles + [ "$rmdirs" != "" ] && rm -r $rmdirs + exit 0 +fi +exit 1
usb-fpga-2.16/2.16b/lightshow/fpga/clean.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb-fpga-2.16/2.16b/lightshow/Readme =================================================================== --- usb-fpga-2.16/2.16b/lightshow/Readme (nonexistent) +++ usb-fpga-2.16/2.16b/lightshow/Readme (revision 3) @@ -0,0 +1,5 @@ +lightshow +--------- + +This example requires the Debug Board. It implements a light show using +the LED's. Effects are controlled by the switches. Index: usb-fpga-2.16/flashbench/FlashBench.java =================================================================== --- usb-fpga-2.16/flashbench/FlashBench.java (revision 2) +++ usb-fpga-2.16/flashbench/FlashBench.java (revision 3) @@ -1,6 +1,6 @@ /*! - flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.15 - Copyright (C) 2009-2011 ZTEX GmbH. + flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 2.16 + Copyright (C) 2009-2014 ZTEX GmbH. http://www.ztex.de This program is free software; you can redistribute it and/or modify
/usb-fpga-2.16/flashbench/flashbench.c
1,6 → 1,6
/*!
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Module 1.15
Copyright (C) 2009-2011 ZTEX GmbH.
flashbench -- Flash memory benchmark for ZTEX USB-FPGA Modules 2.16
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
 
This program is free software; you can redistribute it and/or modify
/Makefile
1,4 → 1,4
DIRS=all usb-fpga-1.2 usb-1.0 usb-fpga-1.11 usb-xmega-1.0 usb-fpga-1.15 usb-fpga-1.15y usb-fpga-2.16
DIRS=all usb-fpga-1.2 usb-1.0 usb-fpga-1.11 usb-xmega-1.0 usb-fpga-1.15 usb-fpga-1.15y usb-fpga-2.16 usb-fpga-2.13
 
.PHONY: default all clean distclean avr avrclean avrdistclean
 

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