URL
https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
Compare Revisions
- This comparison shows the changes necessary to convert path
/usbhostslave/tags/rel_00_06_alpha/RTL/buffers
- from Rev 13 to Rev 40
- ↔ Reverse comparison
Rev 13 → Rev 40
/simFifoMem.v
0,0 → 1,82
////////////////////////////////////////////////////////////////////// |
//// //// |
//// simFifoMem.v //// |
//// //// |
//// This file is part of the usbhostslave opencores effort. |
//// <http://www.opencores.org/cores//> //// |
//// //// |
//// Module Description: //// |
//// |
//// //// |
//// To Do: //// |
//// |
//// //// |
//// Author(s): //// |
//// - Steve Fielding, sfielding@base2designs.com //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from <http://www.opencores.org/lgpl.shtml> //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
`timescale 1ns / 1ps |
|
module simFifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut); |
//FIFO_DEPTH = ADDR_WIDTH^2 |
parameter FIFO_WIDTH = 8; |
parameter FIFO_DEPTH = 64; |
parameter ADDR_WIDTH = 6; |
|
input clk; |
input [FIFO_WIDTH-1:0] dataIn; |
output [FIFO_WIDTH-1:0] dataOut; |
input writeEn; |
input readEn; |
input [ADDR_WIDTH-1:0] addrIn; |
input [ADDR_WIDTH-1:0] addrOut; |
|
wire clk; |
wire [FIFO_WIDTH-1:0] dataIn; |
reg [FIFO_WIDTH-1:0] dataOut; |
wire writeEn; |
wire readEn; |
wire [ADDR_WIDTH-1:0] addrIn; |
wire [ADDR_WIDTH-1:0] addrOut; |
|
reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1]; |
|
// synchronous read. Introduces one clock cycle delay |
always @(posedge clk) begin |
dataOut <= buffer[addrOut]; |
end |
|
// synchronous write |
always @(posedge clk) begin |
if (writeEn == 1'b1) |
buffer[addrIn] <= dataIn; |
end |
|
|
endmodule |
simFifoMem.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: RxFifo.v
===================================================================
--- RxFifo.v (nonexistent)
+++ RxFifo.v (revision 40)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+ clk,
+ rst,
+ fifoWEn,
+ fifoFull,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataIn );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk;
+wire rst;
+wire fifoWEn;
+wire fifoFull;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(fifoDataIn),
+ .dataOut(dataFromFifoToBus),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+RxfifoBI u_RxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .fifoDataIn(dataFromFifoToBus),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoREn(fifoREn),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
RxFifo.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: TxFifo.v
===================================================================
--- TxFifo.v (nonexistent)
+++ TxFifo.v (revision 40)
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxFifo.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+ clk,
+ rst,
+ fifoREn,
+ fifoEmpty,
+ busAddress,
+ busWriteEn,
+ busStrobe_i,
+ busFifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoDataOut );
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input fifoREn;
+output fifoEmpty;
+input [2:0] busAddress;
+input busWriteEn;
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk;
+wire rst;
+wire fifoREn;
+wire fifoEmpty;
+wire [2:0] busAddress;
+wire busWriteEn;
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+ .clk(clk),
+ .rst(rst),
+ .dataIn(busDataIn),
+ .dataOut(fifoDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoREn(fifoREn),
+ .fifoFull(fifoFull),
+ .fifoEmpty(fifoEmpty),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo) );
+
+TxfifoBI u_TxfifoBI(
+ .address(busAddress),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .clk(clk),
+ .rst(rst),
+ .fifoSelect(busFifoSelect),
+ .busDataIn(busDataIn),
+ .busDataOut(busDataOut),
+ .fifoWEn(fifoWEn),
+ .fifoFull(fifoFull),
+ .forceEmpty(forceEmpty),
+ .numElementsInFifo(numElementsInFifo)
+ );
+
+endmodule
\ No newline at end of file
TxFifo.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: fifoMem.v
===================================================================
--- fifoMem.v (nonexistent)
+++ fifoMem.v (revision 40)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMem.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMem( addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+ //FIFO_DEPTH = ADDR_WIDTH^2
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+ // Generic synchronous dual-port RAM interface
+ .rclk(clk),
+ .rrst(1'b0),
+ .rce(1'b1),
+ .oe(readEn),
+ .raddr(addrOut),
+ .do(dataOut),
+ .wclk(clk),
+ .wrst(1'b0),
+ .wce(1'b1),
+ .we(writeEn),
+ .waddr(addrIn),
+ .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_simFifoMem (
+ .addrIn(addrIn),
+ .addrOut(addrOut),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(writeEn),
+ .readEn(readEn),
+ .dataOut(dataOut));
+
+endmodule
\ No newline at end of file
fifoMem.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: fifoRTL.v
===================================================================
--- fifoRTL.v (nonexistent)
+++ fifoRTL.v (revision 40)
@@ -0,0 +1,139 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoRTL.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+ parameter FIFO_WIDTH = 8;
+ parameter FIFO_DEPTH = 64;
+ parameter ADDR_WIDTH = 6;
+
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg [15:0]numElementsInFifo;
+
+
+// local registers
+reg [ADDR_WIDTH-1:0]bufferInIndex;
+reg [ADDR_WIDTH-1:0]bufferOutIndex;
+reg [ADDR_WIDTH:0]bufferCnt;
+reg fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1 || forceEmpty == 1'b1)
+ begin
+ bufferCnt <= 0;
+ fifoFull <= 1'b0;
+ fifoEmpty <= 1'b1;
+ bufferInIndex <= 0;
+ bufferOutIndex <= 0;
+ fifoREnDelayed <= 1'b0;
+ end
+ else
+ begin
+ if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ dataOut <= dataFromMem;
+ end
+ fifoREnDelayed <= fifoREn;
+ if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+ bufferCnt <= bufferCnt + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferCnt <= bufferCnt - 1;
+ bufferOutIndex <= bufferOutIndex + 1;
+ end
+ else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+ bufferOutIndex <= bufferOutIndex + 1;
+ bufferInIndex <= bufferInIndex + 1;
+ end
+ if (bufferCnt[ADDR_WIDTH] == 1'b1)
+ fifoFull <= 1'b1;
+ else
+ fifoFull <= 1'b0;
+ if (|bufferCnt == 1'b0)
+ fifoEmpty <= 1'b1;
+ else
+ fifoEmpty <= 1'b0;
+ end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+ numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_fifoMem (
+ .addrIn(bufferInIndex),
+ .addrOut(bufferOutIndex),
+ .clk(clk),
+ .dataIn(dataIn),
+ .writeEn(fifoWEn),
+ .readEn(fifoREn),
+ .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file
fifoRTL.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: RxFifoBI.v
===================================================================
--- RxFifoBI.v (nonexistent)
+++ RxFifoBI.v (revision 40)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// RxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+ address,
+ writeEn,
+ strobe_i,
+ clk,
+ rst,
+ fifoSelect,
+ fifoDataIn,
+ busDataIn,
+ busDataOut,
+ fifoREn,
+ fifoEmpty,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+ case (address)
+ `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoREn <= 1'b1;
+ else
+ fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
RxFifoBI.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: TxFifoBI.v
===================================================================
--- TxFifoBI.v (nonexistent)
+++ TxFifoBI.v (revision 40)
@@ -0,0 +1,116 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// TxfifoBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+ address, writeEn, strobe_i,
+ clk, rst, fifoSelect,
+ busDataIn,
+ busDataOut,
+ fifoWEn,
+ fifoFull,
+ forceEmpty,
+ numElementsInFifo
+ );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn;
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+ if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
+ address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+ forceEmpty <= 1'b1;
+ else
+ forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+ case (address)
+ `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+ `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+ `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+ default: busDataOut <= 8'h00;
+ endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+ if (address == `FIFO_DATA_REG && writeEn == 1'b1 &&
+ strobe_i == 1'b1 && fifoSelect == 1'b1)
+ fifoWEn <= 1'b1;
+ else
+ fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file
TxFifoBI.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property