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/RxFifoBI.v
0,0 → 1,154
//////////////////////////////////////////////////////////////////////
//// ////
//// RxfifoBI.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "wishBoneBus_h.v"
 
module RxfifoBI (
address,
writeEn,
strobe_i,
busClk,
usbClk,
rstSyncToBusClk,
fifoSelect,
fifoDataIn,
busDataIn,
busDataOut,
fifoREn,
forceEmptySyncToUsbClk,
forceEmptySyncToBusClk,
numElementsInFifo
);
input [2:0] address;
input writeEn;
input strobe_i;
input busClk;
input usbClk;
input rstSyncToBusClk;
input [7:0] fifoDataIn;
input [7:0] busDataIn;
output [7:0] busDataOut;
output fifoREn;
output forceEmptySyncToUsbClk;
output forceEmptySyncToBusClk;
input [15:0] numElementsInFifo;
input fifoSelect;
 
 
wire [2:0] address;
wire writeEn;
wire strobe_i;
wire busClk;
wire usbClk;
wire rstSyncToBusClk;
wire [7:0] fifoDataIn;
wire [7:0] busDataIn;
reg [7:0] busDataOut;
reg fifoREn;
wire forceEmptySyncToUsbClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoSelect;
 
reg forceEmptyReg;
reg forceEmpty;
reg forceEmptyToggle;
reg [2:0] forceEmptyToggleSyncToUsbClk;
 
//sync write
always @(posedge busClk)
begin
if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
forceEmpty <= 1'b1;
else
forceEmpty <= 1'b0;
end
 
//detect rising edge of 'forceEmpty', and generate toggle signal
always @(posedge busClk) begin
if (rstSyncToBusClk == 1'b1) begin
forceEmptyReg <= 1'b0;
forceEmptyToggle <= 1'b0;
end
else begin
if (forceEmpty == 1'b1)
forceEmptyReg <= 1'b1;
else
forceEmptyReg <= 1'b0;
if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
forceEmptyToggle <= ~forceEmptyToggle;
end
end
assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
 
 
// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
always @(posedge usbClk) begin
forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
end
assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
 
// async read mux
always @(address or fifoDataIn or numElementsInFifo)
begin
case (address)
`FIFO_DATA_REG : busDataOut <= fifoDataIn;
`FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
`FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
default: busDataOut <= 8'h00;
endcase
end
 
//generate fifo read strobe
always @(address or writeEn or strobe_i or fifoSelect) begin
if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
strobe_i == 1'b1 && fifoSelect == 1'b1)
fifoREn <= 1'b1;
else
fifoREn <= 1'b0;
end
 
 
endmodule
RxFifoBI.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: TxFifoBI.v =================================================================== --- TxFifoBI.v (nonexistent) +++ TxFifoBI.v (revision 40) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TxfifoBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "wishBoneBus_h.v" + +module TxfifoBI ( + address, writeEn, strobe_i, + busClk, + usbClk, + rstSyncToBusClk, + fifoSelect, + busDataIn, + busDataOut, + fifoWEn, + forceEmptySyncToUsbClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input usbClk; +input rstSyncToBusClk; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoWEn; +output forceEmptySyncToUsbClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +reg fifoWEn; +wire forceEmptySyncToUsbClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg forceEmptyReg; +reg forceEmpty; +reg forceEmptyToggle; +reg [2:0] forceEmptyToggleSyncToUsbClk; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//detect rising edge of 'forceEmpty', and generate toggle signal +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + forceEmptyReg <= 1'b0; + forceEmptyToggle <= 1'b0; + end + else begin + if (forceEmpty == 1'b1) + forceEmptyReg <= 1'b1; + else + forceEmptyReg <= 1'b0; + if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) + forceEmptyToggle <= ~forceEmptyToggle; + end +end +assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0; + +// double sync across clock domains to generate 'forceEmptySyncToUsbClk' +always @(posedge usbClk) begin + forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle}; +end +assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1]; + +// async read mux +assign busDataOut = 8'h00; +//always @(address or fifoFull or numElementsInFifo) +//begin +// case (address) +// `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull}; +// `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8]; +// `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0]; +// default: busDataOut <= 8'h00; +// endcase +//end + +//generate fifo write strobe +always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b1 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoWEn <= 1'b1; + else + fifoWEn <= 1'b0; +end + + +endmodule
TxFifoBI.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: RxFifo.v =================================================================== --- RxFifo.v (nonexistent) +++ RxFifo.v (revision 40) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RxFifo.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo read access via bus interface, fifo write access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module RxFifo( + busClk, + usbClk, + rstSyncToBusClk, + rstSyncToUsbClk, + fifoWEn, + fifoFull, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataIn ); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input usbClk; +input rstSyncToBusClk; +input rstSyncToUsbClk; +input fifoWEn; +output fifoFull; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +input [7:0] fifoDataIn; + +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire rstSyncToUsbClk; +wire fifoWEn; +wire fifoFull; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataIn; + +//internal wires and regs +wire [7:0] dataFromFifoToBus; +wire fifoREn; +wire forceEmptySyncToBusClk; +wire forceEmptySyncToUsbClk; +wire [15:0] numElementsInFifo; +wire fifoEmpty; //not used + +fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo( + .wrClk(usbClk), + .rdClk(busClk), + .rstSyncToWrClk(rstSyncToUsbClk), + .rstSyncToRdClk(rstSyncToBusClk), + .dataIn(fifoDataIn), + .dataOut(dataFromFifoToBus), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToUsbClk), + .forceEmptySyncToRdClk(forceEmptySyncToBusClk), + .numElementsInFifo(numElementsInFifo) ); + +RxfifoBI u_RxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .usbClk(usbClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .fifoDataIn(dataFromFifoToBus), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoREn(fifoREn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule
RxFifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: TxFifo.v =================================================================== --- TxFifo.v (nonexistent) +++ TxFifo.v (revision 40) @@ -0,0 +1,132 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TxFifo.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo write access via bus interface, fifo read access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module TxFifo( + busClk, + usbClk, + rstSyncToBusClk, + rstSyncToUsbClk, + fifoREn, + fifoEmpty, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataOut ); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input usbClk; +input rstSyncToBusClk; +input rstSyncToUsbClk; +input fifoREn; +output fifoEmpty; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +output [7:0] fifoDataOut; + +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire rstSyncToUsbClk; +wire fifoREn; +wire fifoEmpty; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataOut; + +//internal wires and regs +wire fifoWEn; +wire forceEmptySyncToUsbClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoFull; + +fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo( + .wrClk(busClk), + .rdClk(usbClk), + .rstSyncToWrClk(rstSyncToBusClk), + .rstSyncToRdClk(rstSyncToUsbClk), + .dataIn(busDataIn), + .dataOut(fifoDataOut), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToBusClk), + .forceEmptySyncToRdClk(forceEmptySyncToUsbClk), + .numElementsInFifo(numElementsInFifo) ); + +TxfifoBI u_TxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .usbClk(usbClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoWEn(fifoWEn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule
TxFifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fifoRTL.v =================================================================== --- fifoRTL.v (nonexistent) +++ fifoRTL.v (revision 40) @@ -0,0 +1,164 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// fifoRTL.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, + dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, + forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo); +//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +// Two clock domains within this module +// These ports are within 'wrClk' domain +input wrClk; +input rstSyncToWrClk; +input [FIFO_WIDTH-1:0] dataIn; +input fifoWEn; +input forceEmptySyncToWrClk; +output fifoFull; + +// These ports are within 'rdClk' domain +input rdClk; +input rstSyncToRdClk; +output [FIFO_WIDTH-1:0] dataOut; +input fifoREn; +input forceEmptySyncToRdClk; +output fifoEmpty; +output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536 + +wire wrClk; +wire rdClk; +wire rstSyncToWrClk; +wire rstSyncToRdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire fifoWEn; +wire fifoREn; +reg fifoFull; +reg fifoEmpty; +wire forceEmpty; +reg [15:0]numElementsInFifo; + + +// local registers +reg [ADDR_WIDTH:0]bufferInIndex; +reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk; +reg [ADDR_WIDTH:0]bufferOutIndex; +reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk; +reg [ADDR_WIDTH-1:0]bufferInIndexToMem; +reg [ADDR_WIDTH-1:0]bufferOutIndexToMem; +reg [ADDR_WIDTH:0]bufferCnt; +reg fifoREnDelayed; +wire [FIFO_WIDTH-1:0] dataFromMem; + +always @(posedge wrClk) +begin + bufferOutIndexSyncToWrClk <= bufferOutIndex; + if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1) + begin + fifoFull <= 1'b0; + bufferInIndex <= 0; + end + else + begin + if (fifoWEn == 1'b1) begin + bufferInIndex <= bufferInIndex + 1'b1; + end + if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) && + (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) ) + fifoFull <= 1'b1; + else + fifoFull <= 1'b0; + end +end + +always @(bufferInIndexSyncToRdClk or bufferOutIndex) + bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex; + +always @(posedge rdClk) +begin + numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes + bufferInIndexSyncToRdClk <= bufferInIndex; + if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1) + begin + fifoEmpty <= 1'b1; + bufferOutIndex <= 0; + fifoREnDelayed <= 1'b0; + end + else + begin + fifoREnDelayed <= fifoREn; + if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin + dataOut <= dataFromMem; + bufferOutIndex <= bufferOutIndex + 1'b1; + end + if (bufferInIndexSyncToRdClk == bufferOutIndex) + fifoEmpty <= 1'b1; + else + fifoEmpty <= 1'b0; + end +end + + +always @(bufferInIndex or bufferOutIndex) begin + bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0]; + bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0]; +end + +dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc ( + .addrIn(bufferInIndexToMem), + .addrOut(bufferOutIndexToMem), + .wrClk(wrClk), + .rdClk(rdClk), + .dataIn(dataIn), + .writeEn(fifoWEn), + .readEn(fifoREn), + .dataOut(dataFromMem)); + +endmodule
fifoRTL.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dpMem_dc.v =================================================================== --- dpMem_dc.v (nonexistent) +++ dpMem_dc.v (revision 40) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dpMem_dc.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Synchronous dual port memory with dual clocks +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input wrClk; +input rdClk; +input [FIFO_WIDTH-1:0] dataIn; +output [FIFO_WIDTH-1:0] dataOut; +input writeEn; +input readEn; +input [ADDR_WIDTH-1:0] addrIn; +input [ADDR_WIDTH-1:0] addrOut; + +wire wrClk; +wire rdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire writeEn; +wire readEn; +wire [ADDR_WIDTH-1:0] addrIn; +wire [ADDR_WIDTH-1:0] addrOut; + +reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1]; + +// synchronous read. Introduces one clock cycle delay +always @(posedge rdClk) begin + dataOut <= buffer[addrOut]; +end + +// synchronous write +always @(posedge wrClk) begin + if (writeEn == 1'b1) + buffer[addrIn] <= dataIn; +end + + +endmodule
dpMem_dc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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