OpenCores

/directcontrol.v

0,0 → 1,196

directcontrol.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hostcontroller.v =================================================================== --- hostcontroller.v (nonexistent) +++ hostcontroller.v (revision 40) @@ -0,0 +1,386 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// hostController +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostControl_h.v" +`include "usbConstants_h.v" + + +module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType); +input [7:0] RXStatus; +input clk; +input getPacketRdy; +input isoEn; +input rst; +input sendPacketArbiterGnt; +input sendPacketRdy; +input transReq; +input [1:0] transType; +output clearTXReq; +output getPacketREn; +output sendPacketArbiterReq; +output [3:0] sendPacketPID; +output sendPacketWEn; +output transDone; + +wire [7:0] RXStatus; +reg clearTXReq, next_clearTXReq; +wire clk; +reg getPacketREn, next_getPacketREn; +wire getPacketRdy; +wire isoEn; +wire rst; +wire sendPacketArbiterGnt; +reg sendPacketArbiterReq, next_sendPacketArbiterReq; +reg [3:0] sendPacketPID, next_sendPacketPID; +wire sendPacketRdy; +reg sendPacketWEn, next_sendPacketWEn; +reg transDone, next_transDone; +wire transReq; +wire [1:0] transType; + +// diagram signals declarations +reg [3:0]delCnt, next_delCnt; + +// BINARY ENCODED state machine: hstCntrl +// State codes definitions: +`define START_HC 6'b000000 +`define TX_REQ 6'b000001 +`define CHK_TYPE 6'b000010 +`define FLAG 6'b000011 +`define IN_WAIT_DATA_RXED 6'b000100 +`define IN_CHK_FOR_ERROR 6'b000101 +`define IN_CLR_SP_WEN2 6'b000110 +`define SETUP_CLR_SP_WEN1 6'b000111 +`define SETUP_CLR_SP_WEN2 6'b001000 +`define FIN 6'b001001 +`define WAIT_GNT 6'b001010 +`define SETUP_WAIT_PKT_RXED 6'b001011 +`define IN_WAIT_IN_SENT 6'b001100 +`define OUT0_WAIT_RX_DATA 6'b001101 +`define OUT0_WAIT_DATA0_SENT 6'b001110 +`define OUT0_WAIT_OUT_SENT 6'b001111 +`define SETUP_HC_WAIT_RDY 6'b010000 +`define IN_WAIT_SP_RDY1 6'b010001 +`define IN_WAIT_SP_RDY2 6'b010010 +`define OUT0_WAIT_SP_RDY1 6'b010011 +`define SETUP_WAIT_SETUP_SENT 6'b010100 +`define SETUP_WAIT_DATA_SENT 6'b010101 +`define IN_CLR_SP_WEN1 6'b010110 +`define IN_WAIT_ACK_SENT 6'b010111 +`define OUT0_CLR_WEN1 6'b011000 +`define OUT0_CLR_WEN2 6'b011001 +`define OUT1_WAIT_RX_DATA 6'b011010 +`define OUT1_WAIT_OUT_SENT 6'b011011 +`define OUT1_WAIT_DATA1_SENT 6'b011100 +`define OUT1_WAIT_SP_RDY1 6'b011101 +`define OUT1_CLR_WEN1 6'b011110 +`define OUT1_CLR_WEN2 6'b011111 +`define OUT0_CHK_ISO 6'b100000 + +reg [5:0] CurrState_hstCntrl; +reg [5:0] NextState_hstCntrl; + + +//-------------------------------------------------------------------- +// Machine: hstCntrl +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (delCnt or transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl) +begin : hstCntrl_NextState + NextState_hstCntrl <= CurrState_hstCntrl; + // Set default values for outputs and signals + next_sendPacketArbiterReq <= sendPacketArbiterReq; + next_transDone <= transDone; + next_clearTXReq <= clearTXReq; + next_delCnt <= delCnt; + next_sendPacketWEn <= sendPacketWEn; + next_getPacketREn <= getPacketREn; + next_sendPacketPID <= sendPacketPID; + case (CurrState_hstCntrl) // synopsys parallel_case full_case + `START_HC: + NextState_hstCntrl <= `TX_REQ; + `TX_REQ: + if (transReq == 1'b1) + begin + NextState_hstCntrl <= `WAIT_GNT; + next_sendPacketArbiterReq <= 1'b1; + end + `CHK_TYPE: + if (transType == `IN_TRANS) + NextState_hstCntrl <= `IN_WAIT_SP_RDY1; + else if (transType == `OUTDATA0_TRANS) + NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1; + else if (transType == `OUTDATA1_TRANS) + NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1; + else if (transType == `SETUP_TRANS) + NextState_hstCntrl <= `SETUP_HC_WAIT_RDY; + `FLAG: + begin + next_transDone <= 1'b1; + next_clearTXReq <= 1'b1; + next_sendPacketArbiterReq <= 1'b0; + next_delCnt <= 4'h0; + NextState_hstCntrl <= `FIN; + end + `FIN: + begin + next_clearTXReq <= 1'b0; + next_transDone <= 1'b0; + next_delCnt <= delCnt + 1'b1; + //now wait for 'transReq' to clear + if (delCnt == 4'hf) + NextState_hstCntrl <= `TX_REQ; + end + `WAIT_GNT: + if (sendPacketArbiterGnt == 1'b1) + NextState_hstCntrl <= `CHK_TYPE; + `SETUP_CLR_SP_WEN1: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT; + end + `SETUP_CLR_SP_WEN2: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT; + end + `SETUP_WAIT_PKT_RXED: + begin + next_getPacketREn <= 1'b0; + if (getPacketRdy == 1'b1) + NextState_hstCntrl <= `FLAG; + end + `SETUP_HC_WAIT_RDY: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `SETUP_CLR_SP_WEN1; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `SETUP; + end + `SETUP_WAIT_SETUP_SENT: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `SETUP_CLR_SP_WEN2; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA0; + end + `SETUP_WAIT_DATA_SENT: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED; + next_getPacketREn <= 1'b1; + end + `IN_WAIT_DATA_RXED: + begin + next_getPacketREn <= 1'b0; + if (getPacketRdy == 1'b1) + NextState_hstCntrl <= `IN_CHK_FOR_ERROR; + end + `IN_CHK_FOR_ERROR: + if (isoEn == 1'b1) + NextState_hstCntrl <= `FLAG; + else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 && + RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 && + RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 && + RXStatus [`HC_NAK_RXED_BIT] == 1'b0 && + RXStatus [`HC_STALL_RXED_BIT] == 1'b0 && + RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0) + NextState_hstCntrl <= `IN_WAIT_SP_RDY2; + else + NextState_hstCntrl <= `FLAG; + `IN_CLR_SP_WEN2: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `IN_WAIT_ACK_SENT; + end + `IN_WAIT_IN_SENT: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `IN_WAIT_DATA_RXED; + next_getPacketREn <= 1'b1; + end + `IN_WAIT_SP_RDY1: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `IN_CLR_SP_WEN1; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `IN; + end + `IN_WAIT_SP_RDY2: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `IN_CLR_SP_WEN2; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `ACK; + end + `IN_CLR_SP_WEN1: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `IN_WAIT_IN_SENT; + end + `IN_WAIT_ACK_SENT: + if (sendPacketRdy == 1'b1) + NextState_hstCntrl <= `FLAG; + `OUT0_WAIT_RX_DATA: + begin + next_getPacketREn <= 1'b0; + if (getPacketRdy == 1'b1) + NextState_hstCntrl <= `FLAG; + end + `OUT0_WAIT_DATA0_SENT: + if (sendPacketRdy == 1'b1) + NextState_hstCntrl <= `OUT0_CHK_ISO; + `OUT0_WAIT_OUT_SENT: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `OUT0_CLR_WEN2; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA0; + end + `OUT0_WAIT_SP_RDY1: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `OUT0_CLR_WEN1; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `OUT; + end + `OUT0_CLR_WEN1: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT; + end + `OUT0_CLR_WEN2: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT; + end + `OUT0_CHK_ISO: + if (isoEn == 1'b0) + begin + NextState_hstCntrl <= `OUT0_WAIT_RX_DATA; + next_getPacketREn <= 1'b1; + end + else + NextState_hstCntrl <= `FLAG; + `OUT1_WAIT_RX_DATA: + begin + next_getPacketREn <= 1'b0; + if (getPacketRdy == 1'b1) + NextState_hstCntrl <= `FLAG; + end + `OUT1_WAIT_OUT_SENT: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `OUT1_CLR_WEN2; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA1; + end + `OUT1_WAIT_DATA1_SENT: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `OUT1_WAIT_RX_DATA; + next_getPacketREn <= 1'b1; + end + `OUT1_WAIT_SP_RDY1: + if (sendPacketRdy == 1'b1) + begin + NextState_hstCntrl <= `OUT1_CLR_WEN1; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `OUT; + end + `OUT1_CLR_WEN1: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT; + end + `OUT1_CLR_WEN2: + begin + next_sendPacketWEn <= 1'b0; + NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : hstCntrl_CurrentState + if (rst) + CurrState_hstCntrl <= `START_HC; + else + CurrState_hstCntrl <= NextState_hstCntrl; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : hstCntrl_RegOutput + if (rst) + begin + delCnt <= 4'h0; + transDone <= 1'b0; + clearTXReq <= 1'b0; + getPacketREn <= 1'b0; + sendPacketArbiterReq <= 1'b0; + sendPacketWEn <= 1'b0; + sendPacketPID <= 4'b0; + end + else + begin + delCnt <= next_delCnt; + transDone <= next_transDone; + clearTXReq <= next_clearTXReq; + getPacketREn <= next_getPacketREn; + sendPacketArbiterReq <= next_sendPacketArbiterReq; + sendPacketWEn <= next_sendPacketWEn; + sendPacketPID <= next_sendPacketPID; + end +end + +endmodule

hostcontroller.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sendpacket.v =================================================================== --- sendpacket.v (nonexistent) +++ sendpacket.v (revision 40) @@ -0,0 +1,345 @@ + +// File : ../RTL/hostController/sendpacket.v +// Generated : 11/10/06 05:37:20 +// From : ../RTL/hostController/sendpacket.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// sendPacket +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + + + +module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, rst, sendPacketRdy, sendPacketWEn); +input HCTxPortGnt; +input HCTxPortRdy; +input [3:0] PID; +input [6:0] TxAddr; +input [3:0] TxEndP; +input clk; +input [7:0] fifoData; +input fifoEmpty; +input fullSpeedPolarity; +input rst; +input sendPacketWEn; +output [7:0] HCTxPortCntl; +output [7:0] HCTxPortData; +output HCTxPortReq; +output HCTxPortWEn; +output fifoReadEn; +output [10:0] frameNum; +output sendPacketRdy; + +reg [7:0] HCTxPortCntl, next_HCTxPortCntl; +reg [7:0] HCTxPortData, next_HCTxPortData; +wire HCTxPortGnt; +wire HCTxPortRdy; +reg HCTxPortReq, next_HCTxPortReq; +reg HCTxPortWEn, next_HCTxPortWEn; +wire [3:0] PID; +wire [6:0] TxAddr; +wire [3:0] TxEndP; +wire clk; +wire [7:0] fifoData; +wire fifoEmpty; +reg fifoReadEn, next_fifoReadEn; +reg [10:0] frameNum, next_frameNum; +wire fullSpeedPolarity; +wire rst; +reg sendPacketRdy, next_sendPacketRdy; +wire sendPacketWEn; + +// diagram signals declarations +reg [7:0]PIDNotPID; + +// BINARY ENCODED state machine: sndPkt +// State codes definitions: +`define START_SP 5'b00000 +`define WAIT_ENABLE 5'b00001 +`define SP_WAIT_GNT 5'b00010 +`define SEND_PID_WAIT_RDY 5'b00011 +`define SEND_PID_FIN 5'b00100 +`define FIN_SP 5'b00101 +`define OUT_IN_SETUP_WAIT_RDY1 5'b00110 +`define OUT_IN_SETUP_WAIT_RDY2 5'b00111 +`define OUT_IN_SETUP_FIN 5'b01000 +`define SEND_SOF_FIN1 5'b01001 +`define SEND_SOF_WAIT_RDY3 5'b01010 +`define SEND_SOF_WAIT_RDY4 5'b01011 +`define DATA0_DATA1_READ_FIFO 5'b01100 +`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101 +`define DATA0_DATA1_FIFO_EMPTY 5'b01110 +`define DATA0_DATA1_FIN 5'b01111 +`define DATA0_DATA1_TERM_BYTE 5'b10000 +`define OUT_IN_SETUP_CLR_WEN1 5'b10001 +`define SEND_SOF_CLR_WEN1 5'b10010 +`define DATA0_DATA1_CLR_WEN 5'b10011 +`define DATA0_DATA1_CLR_REN 5'b10100 +`define LS_EOP_WAIT_RDY 5'b10101 +`define LS_EOP_FIN 5'b10110 + +reg [4:0] CurrState_sndPkt; +reg [4:0] NextState_sndPkt; + +// Diagram actions (continuous assignments allowed only: assign ...) + +always @(PID) +begin + PIDNotPID <= { (PID ^ 4'hf), PID }; +end + +//-------------------------------------------------------------------- +// Machine: sndPkt +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or PID or fullSpeedPolarity or HCTxPortRdy or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt) +begin : sndPkt_NextState + NextState_sndPkt <= CurrState_sndPkt; + // Set default values for outputs and signals + next_sendPacketRdy <= sendPacketRdy; + next_HCTxPortReq <= HCTxPortReq; + next_HCTxPortWEn <= HCTxPortWEn; + next_HCTxPortData <= HCTxPortData; + next_HCTxPortCntl <= HCTxPortCntl; + next_frameNum <= frameNum; + next_fifoReadEn <= fifoReadEn; + case (CurrState_sndPkt) + `START_SP: + NextState_sndPkt <= `WAIT_ENABLE; + `WAIT_ENABLE: + if (sendPacketWEn == 1'b1) + begin + NextState_sndPkt <= `SP_WAIT_GNT; + next_sendPacketRdy <= 1'b0; + next_HCTxPortReq <= 1'b1; + end + `SP_WAIT_GNT: + if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0)) + NextState_sndPkt <= `LS_EOP_WAIT_RDY; + else if (HCTxPortGnt == 1'b1) + NextState_sndPkt <= `SEND_PID_WAIT_RDY; + `FIN_SP: + begin + NextState_sndPkt <= `WAIT_ENABLE; + next_sendPacketRdy <= 1'b1; + next_HCTxPortReq <= 1'b0; + end + `SEND_PID_WAIT_RDY: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `SEND_PID_FIN; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= PIDNotPID; + next_HCTxPortCntl <= `TX_PACKET_START; + end + `SEND_PID_FIN: + begin + next_HCTxPortWEn <= 1'b0; + if (PID == `DATA0 || PID == `DATA1) + NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY; + else if (PID == `SOF) + NextState_sndPkt <= `SEND_SOF_WAIT_RDY3; + else if (PID == `OUT || + PID == `IN || + PID == `SETUP) + NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1; + else + NextState_sndPkt <= `FIN_SP; + end + `OUT_IN_SETUP_WAIT_RDY1: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]}; + next_HCTxPortCntl <= `TX_PACKET_STREAM; + end + `OUT_IN_SETUP_WAIT_RDY2: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `OUT_IN_SETUP_FIN; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= {5'b00000, TxEndP[3:1]}; + next_HCTxPortCntl <= `TX_PACKET_STREAM; + end + `OUT_IN_SETUP_FIN: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sndPkt <= `FIN_SP; + end + `OUT_IN_SETUP_CLR_WEN1: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2; + end + `SEND_SOF_FIN1: + begin + next_HCTxPortWEn <= 1'b0; + next_frameNum <= frameNum + 1'b1; + NextState_sndPkt <= `FIN_SP; + end + `SEND_SOF_WAIT_RDY3: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `SEND_SOF_CLR_WEN1; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= frameNum[7:0]; + next_HCTxPortCntl <= `TX_PACKET_STREAM; + end + `SEND_SOF_WAIT_RDY4: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `SEND_SOF_FIN1; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= {5'b00000, frameNum[10:8]}; + next_HCTxPortCntl <= `TX_PACKET_STREAM; + end + `SEND_SOF_CLR_WEN1: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sndPkt <= `SEND_SOF_WAIT_RDY4; + end + `DATA0_DATA1_READ_FIFO: + begin + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= fifoData; + next_HCTxPortCntl <= `TX_PACKET_STREAM; + NextState_sndPkt <= `DATA0_DATA1_CLR_WEN; + end + `DATA0_DATA1_WAIT_READ_FIFO: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `DATA0_DATA1_CLR_REN; + next_fifoReadEn <= 1'b1; + end + `DATA0_DATA1_FIFO_EMPTY: + if (fifoEmpty == 1'b0) + NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO; + else + NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE; + `DATA0_DATA1_FIN: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sndPkt <= `FIN_SP; + end + `DATA0_DATA1_TERM_BYTE: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `DATA0_DATA1_FIN; + //Last byte is not valid data, + //but the 'TX_PACKET_STOP' flag is required + //by the SIE state machine to detect end of data packet + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= 8'h00; + next_HCTxPortCntl <= `TX_PACKET_STOP; + end + `DATA0_DATA1_CLR_WEN: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY; + end + `DATA0_DATA1_CLR_REN: + begin + next_fifoReadEn <= 1'b0; + NextState_sndPkt <= `DATA0_DATA1_READ_FIFO; + end + `LS_EOP_WAIT_RDY: + if (HCTxPortRdy == 1'b1) + begin + NextState_sndPkt <= `LS_EOP_FIN; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= 8'h00; + next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE; + end + `LS_EOP_FIN: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sndPkt <= `FIN_SP; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : sndPkt_CurrentState + if (rst) + CurrState_sndPkt <= `START_SP; + else + CurrState_sndPkt <= NextState_sndPkt; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : sndPkt_RegOutput + if (rst) + begin + sendPacketRdy <= 1'b1; + HCTxPortReq <= 1'b0; + HCTxPortWEn <= 1'b0; + HCTxPortData <= 8'h00; + HCTxPortCntl <= 8'h00; + frameNum <= 11'h000; + fifoReadEn <= 1'b0; + end + else + begin + sendPacketRdy <= next_sendPacketRdy; + HCTxPortReq <= next_HCTxPortReq; + HCTxPortWEn <= next_HCTxPortWEn; + HCTxPortData <= next_HCTxPortData; + HCTxPortCntl <= next_HCTxPortCntl; + frameNum <= next_frameNum; + fifoReadEn <= next_fifoReadEn; + end +end + +endmodule \ No newline at end of file

sendpacket.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hctxportarbiter.v =================================================================== --- hctxportarbiter.v (nonexistent) +++ hctxportarbiter.v (revision 40) @@ -0,0 +1,239 @@ + +// File : ../RTL/hostController/hctxportarbiter.v +// Generated : 11/10/06 05:37:22 +// From : ../RTL/hostController/hctxportarbiter.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// hctxPortArbiter +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn); +input [7:0] SOFCntlCntl; +input [7:0] SOFCntlData; +input SOFCntlReq; +input SOFCntlWEn; +input clk; +input [7:0] directCntlCntl; +input [7:0] directCntlData; +input directCntlReq; +input directCntlWEn; +input rst; +input [7:0] sendPacketCntl; +input [7:0] sendPacketData; +input sendPacketReq; +input sendPacketWEn; +output [7:0] HCTxPortCntl; +output [7:0] HCTxPortData; +output HCTxPortWEnable; +output SOFCntlGnt; +output directCntlGnt; +output sendPacketGnt; + +reg [7:0] HCTxPortCntl, next_HCTxPortCntl; +reg [7:0] HCTxPortData, next_HCTxPortData; +reg HCTxPortWEnable, next_HCTxPortWEnable; +wire [7:0] SOFCntlCntl; +wire [7:0] SOFCntlData; +reg SOFCntlGnt, next_SOFCntlGnt; +wire SOFCntlReq; +wire SOFCntlWEn; +wire clk; +wire [7:0] directCntlCntl; +wire [7:0] directCntlData; +reg directCntlGnt, next_directCntlGnt; +wire directCntlReq; +wire directCntlWEn; +wire rst; +wire [7:0] sendPacketCntl; +wire [7:0] sendPacketData; +reg sendPacketGnt, next_sendPacketGnt; +wire sendPacketReq; +wire sendPacketWEn; + + +// Constants +`define DIRECT_CTRL_MUX 2'b10 +`define SEND_PACKET_MUX 2'b00 +`define SOF_CTRL_MUX 2'b01 +// diagram signals declarations +reg [1:0]muxCntl, next_muxCntl; + +// BINARY ENCODED state machine: HCTxArb +// State codes definitions: +`define START_HARB 3'b000 +`define WAIT_REQ 3'b001 +`define SEND_SOF 3'b010 +`define SEND_PACKET 3'b011 +`define DIRECT_CONTROL 3'b100 + +reg [2:0] CurrState_HCTxArb; +reg [2:0] NextState_HCTxArb; + +// Diagram actions (continuous assignments allowed only: assign ...) + +// SOFController/directContol/sendPacket mux +always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or + directCntlWEn or directCntlData or directCntlCntl or + directCntlWEn or directCntlData or directCntlCntl or + sendPacketWEn or sendPacketData or sendPacketCntl) +begin +case (muxCntl) + `SOF_CTRL_MUX : + begin + HCTxPortWEnable <= SOFCntlWEn; + HCTxPortData <= SOFCntlData; + HCTxPortCntl <= SOFCntlCntl; + end + `DIRECT_CTRL_MUX : + begin + HCTxPortWEnable <= directCntlWEn; + HCTxPortData <= directCntlData; + HCTxPortCntl <= directCntlCntl; + end + `SEND_PACKET_MUX : + begin + HCTxPortWEnable <= sendPacketWEn; + HCTxPortData <= sendPacketData; + HCTxPortCntl <= sendPacketCntl; + end + default : + begin + HCTxPortWEnable <= 1'b0; + HCTxPortData <= 8'h00; + HCTxPortCntl <= 8'h00; + end +endcase +end + +//-------------------------------------------------------------------- +// Machine: HCTxArb +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb) +begin : HCTxArb_NextState + NextState_HCTxArb <= CurrState_HCTxArb; + // Set default values for outputs and signals + next_SOFCntlGnt <= SOFCntlGnt; + next_muxCntl <= muxCntl; + next_sendPacketGnt <= sendPacketGnt; + next_directCntlGnt <= directCntlGnt; + case (CurrState_HCTxArb) + `START_HARB: + NextState_HCTxArb <= `WAIT_REQ; + `WAIT_REQ: + if (SOFCntlReq == 1'b1) + begin + NextState_HCTxArb <= `SEND_SOF; + next_SOFCntlGnt <= 1'b1; + next_muxCntl <= `SOF_CTRL_MUX; + end + else if (sendPacketReq == 1'b1) + begin + NextState_HCTxArb <= `SEND_PACKET; + next_sendPacketGnt <= 1'b1; + next_muxCntl <= `SEND_PACKET_MUX; + end + else if (directCntlReq == 1'b1) + begin + NextState_HCTxArb <= `DIRECT_CONTROL; + next_directCntlGnt <= 1'b1; + next_muxCntl <= `DIRECT_CTRL_MUX; + end + `SEND_SOF: + if (SOFCntlReq == 1'b0) + begin + NextState_HCTxArb <= `WAIT_REQ; + next_SOFCntlGnt <= 1'b0; + end + `SEND_PACKET: + if (sendPacketReq == 1'b0) + begin + NextState_HCTxArb <= `WAIT_REQ; + next_sendPacketGnt <= 1'b0; + end + `DIRECT_CONTROL: + if (directCntlReq == 1'b0) + begin + NextState_HCTxArb <= `WAIT_REQ; + next_directCntlGnt <= 1'b0; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : HCTxArb_CurrentState + if (rst) + CurrState_HCTxArb <= `START_HARB; + else + CurrState_HCTxArb <= NextState_HCTxArb; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : HCTxArb_RegOutput + if (rst) + begin + muxCntl <= 2'b00; + SOFCntlGnt <= 1'b0; + sendPacketGnt <= 1'b0; + directCntlGnt <= 1'b0; + end + else + begin + muxCntl <= next_muxCntl; + SOFCntlGnt <= next_SOFCntlGnt; + sendPacketGnt <= next_sendPacketGnt; + directCntlGnt <= next_directCntlGnt; + end +end + +endmodule \ No newline at end of file

hctxportarbiter.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hostcontroller.asf =================================================================== --- hostcontroller.asf (nonexistent) +++ hostcontroller.asf (revision 40) @@ -0,0 +1,301 @@ +VERSION=1.21 +HEADER +FILE="hostcontroller.asf" +FID=403fbdc7 +LANGUAGE=VERILOG +ENTITY="hostcontroller" +FREEOID=459 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n" +MULTIPLEARCHSTATUS=FALSE +SYNTHESISATTRIBUTES=TRUE +HEADER_PARAM="AUTHOR," +HEADER_PARAM="COMPANY," +HEADER_PARAM="CREATIONDATE," +HEADER_PARAM="TITLE,No Title" +BLOCKTABLE_FILE="" +BLOCKTABLE_TEMPL="0" +BLOCKTABLE_VISIBLE="1" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 0 "Arial" 0 +B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3125 0 0110 0 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 0 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 0 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 0 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3125 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0 +B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 0,0 215900,279400 +MARGINS 25400,0 0,0 +END +INSTHEADER 45 +PAGE 0,0 215900,279400 +MARGINS 25400,0 0,0 +END +INSTHEADER 47 +PAGE 0,0 215900,279400 +MARGINS 25400,0 0,0 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1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\ndelCnt <= 4'h0;" +S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500 +L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/" +A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;" +W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642 +A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;" +S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500 +L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/" +C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1" +W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\ + 170250,145750 137550,145450 128737,144962 119925,144475\ + 117963,142662 116688,141837 +S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500 +L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/" +S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500 +L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/" +S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500 +L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP" +S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500 +L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN" +S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500 +A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;" +W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767 +H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709 +I 56 52 0 Builtin Exit | 155694,46048 +I 55 52 0 Builtin Entry | 88756,239499 +H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826 +S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500 +L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1" +L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0" +S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500 +W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384 +L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/" +S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500 +W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385 +C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1" +H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397 +A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;" +C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1" +A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;" +W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048 +C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1" +A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;" +W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\ + 110726,37400 115182,37514 117348,37514 +C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1" +W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446 +A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;" +C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1" +S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500 +L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/" +W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725 +W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460 +W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683 +W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100 +W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395 +W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376 +W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006 +W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706 +W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430 +W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995 +W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040 +S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500 +L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/" +W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\ + 129080,35838 133536,35952 135702,35952 +C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1" +S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500 +A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;" +W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258 +S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500 +L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/" +I 365 73 0 Builtin Exit | 138662,35952 +I 366 73 0 Builtin Entry | 66816,246531 +L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/" +W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\ + 40160,89849 37728,77233 37462,69633 37196,62033\ + 38564,44249 44378,36953 50192,29657 72080,18257\ + 79528,15331 86976,12405 94012,13028 97964,12876 +S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500 +L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/" +S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500 +L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/" +C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS" +C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS" +C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS" +C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS" +C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1" +W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472 +I 96 6 0 Builtin Reset | 67359,192312 +A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;" +C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1" +L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/" +S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500 +W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239 +C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1" +A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;" +C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1" +L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/" +S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500 +W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123 +A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;" +C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1" +W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933 +W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077 +L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/" +S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500 +W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408 +C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1" +A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;" +L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/" +S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500 +W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005 +C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1" +A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;" +L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/" +S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500 +W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582 +A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;" +C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1" +L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/" +C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1" +W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876 +A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;" +I 411 59 0 Builtin Exit | 100924,12876 +S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500 +L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/" +W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732 +S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500 +L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/" +W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646 +S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500 +L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/" +W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573 +S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500 +L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/" +A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;" +A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;" +W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637 +S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500 +L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/" +W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\ + 134254,207065 123583,209376 117848,210301 +A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;" +S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500 +L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/" +W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934 +A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;" +S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500 +L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/" +W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186 +A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;" +S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500 +I 147 59 0 Builtin Entry | 48274,244510 +S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500 +L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/" +W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640 +W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024 +L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/" +S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500 +C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1" +C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1" +W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\ + 58620,51804 60468,38868 64038,33660 67608,28452\ + 80040,20556 84492,18330 88944,16104 95212,13380\ + 97900,12876 +W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\ + 41567,48930 50502,39578 58559,36864 66617,34151\ + 89914,32647 97658,32793 105403,32939 113545,36471\ + 117386,37514 +C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0" +A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;" +W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452 +S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500 +L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/" +I 433 0 2 Builtin InPort | 150555,227440 "" "" +L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn" +C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1" +A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;" +L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/" +S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500 +W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909 +W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179 +C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0" +W 455 6 0 294 41 BEZIER "Transitions" | 113108,29526 99069,31142 72011,34324 62012,39273\ + 52013,44222 40095,60786 37368,72855 34641,84925\ + 35651,116639 37115,130223 38580,143808 43428,166432\ + 52518,171128 61608,175825 90617,170916 106373,168997 +L 456 457 0 TEXT "Labels" | 190656,222568 1 0 0 "delCnt[3:0]" +I 457 0 130 Builtin Signal | 187656,222568 "" "" +C 458 455 0 TEXT "Conditions" | 77768,36546 1 0 0 "delCnt == 4'hf" +A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;" +S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500 +L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/" +I 215 66 0 Builtin Entry | 50996,240683 +I 216 66 0 Builtin Exit | 120308,37514 +S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500 +L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/" +W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209 +C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1" +A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;" +L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]" +I 271 0 2 Builtin OutPort | 150487,213642 "" "" +I 270 0 130 Builtin OutPort | 29066,227064 "" "" +L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]" +I 268 0 2 Builtin OutPort | 29318,212721 "" "" +L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq" +I 266 0 2 Builtin OutPort | 85109,222528 "" "" +L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone" +I 264 0 2 Builtin OutPort | 85109,212721 "" "" +L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq" +I 261 0 130 Builtin InPort | 31358,207795 "" "" +L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt" +L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]" +I 259 0 130 Builtin InPort | 86798,217875 "" "" +L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq" +I 257 0 130 Builtin InPort | 87557,207994 "" "" +I 256 0 130 Builtin InPort | 152950,208697 "" "" +END

hostcontroller.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sendpacketcheckpreamble.v =================================================================== --- sendpacketcheckpreamble.v (nonexistent) +++ sendpacketcheckpreamble.v (revision 40) @@ -0,0 +1,205 @@ + +// File : ../RTL/hostController/sendpacketcheckpreamble.v +// Generated : 11/10/06 05:37:21 +// From : ../RTL/hostController/sendpacketcheckpreamble.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// sendpacketcheckpreamble +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbConstants_h.v" + +module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn); +input clk; +input preAmbleEnable; +input rst; +input [3:0] sendPacketCPPID; +input sendPacketCPWEn; +input sendPacketRdy; +output sendPacketCPReady; +output [3:0] sendPacketPID; +output sendPacketWEn; + +wire clk; +wire preAmbleEnable; +wire rst; +wire [3:0] sendPacketCPPID; +reg sendPacketCPReady, next_sendPacketCPReady; +wire sendPacketCPWEn; +reg [3:0] sendPacketPID, next_sendPacketPID; +wire sendPacketRdy; +reg sendPacketWEn, next_sendPacketWEn; + +// BINARY ENCODED state machine: sendPktCP +// State codes definitions: +`define SPC_WAIT_EN 4'b0000 +`define START_SPC 4'b0001 +`define CHK_PREAM 4'b0010 +`define PREAM_PKT_SND_PREAM 4'b0011 +`define PREAM_PKT_WAIT_RDY1 4'b0100 +`define PREAM_PKT_PREAM_SENT 4'b0101 +`define PREAM_PKT_SND_PID 4'b0110 +`define PREAM_PKT_PID_SENT 4'b0111 +`define REG_PKT_SEND_PID 4'b1000 +`define REG_PKT_WAIT_RDY1 4'b1001 +`define REG_PKT_WAIT_RDY 4'b1010 +`define READY 4'b1011 +`define PREAM_PKT_WAIT_RDY2 4'b1100 +`define PREAM_PKT_WAIT_RDY3 4'b1101 + +reg [3:0] CurrState_sendPktCP; +reg [3:0] NextState_sendPktCP; + + +//-------------------------------------------------------------------- +// Machine: sendPktCP +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP) +begin : sendPktCP_NextState + NextState_sendPktCP <= CurrState_sendPktCP; + // Set default values for outputs and signals + next_sendPacketCPReady <= sendPacketCPReady; + next_sendPacketWEn <= sendPacketWEn; + next_sendPacketPID <= sendPacketPID; + case (CurrState_sendPktCP) + `SPC_WAIT_EN: + if (sendPacketCPWEn == 1'b1) + begin + NextState_sendPktCP <= `CHK_PREAM; + next_sendPacketCPReady <= 1'b0; + end + `START_SPC: + NextState_sendPktCP <= `SPC_WAIT_EN; + `CHK_PREAM: + if (preAmbleEnable == 1'b1) + NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1; + else + NextState_sendPktCP <= `REG_PKT_WAIT_RDY1; + `READY: + begin + next_sendPacketCPReady <= 1'b1; + NextState_sendPktCP <= `SPC_WAIT_EN; + end + `PREAM_PKT_SND_PREAM: + begin + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `PREAMBLE; + NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT; + end + `PREAM_PKT_WAIT_RDY1: + if (sendPacketRdy == 1'b1) + NextState_sendPktCP <= `PREAM_PKT_SND_PREAM; + `PREAM_PKT_PREAM_SENT: + begin + next_sendPacketWEn <= 1'b0; + NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2; + end + `PREAM_PKT_SND_PID: + begin + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= sendPacketCPPID; + NextState_sendPktCP <= `PREAM_PKT_PID_SENT; + end + `PREAM_PKT_PID_SENT: + begin + next_sendPacketWEn <= 1'b0; + NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3; + end + `PREAM_PKT_WAIT_RDY2: + if (sendPacketRdy == 1'b1) + NextState_sendPktCP <= `PREAM_PKT_SND_PID; + `PREAM_PKT_WAIT_RDY3: + if (sendPacketRdy == 1'b1) + NextState_sendPktCP <= `READY; + `REG_PKT_SEND_PID: + begin + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= sendPacketCPPID; + NextState_sendPktCP <= `REG_PKT_WAIT_RDY; + end + `REG_PKT_WAIT_RDY1: + if (sendPacketRdy == 1'b1) + NextState_sendPktCP <= `REG_PKT_SEND_PID; + `REG_PKT_WAIT_RDY: + begin + next_sendPacketWEn <= 1'b0; + NextState_sendPktCP <= `READY; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : sendPktCP_CurrentState + if (rst) + CurrState_sendPktCP <= `START_SPC; + else + CurrState_sendPktCP <= NextState_sendPktCP; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : sendPktCP_RegOutput + if (rst) + begin + sendPacketWEn <= 1'b0; + sendPacketPID <= 4'b0; + sendPacketCPReady <= 1'b1; + end + else + begin + sendPacketWEn <= next_sendPacketWEn; + sendPacketPID <= next_sendPacketPID; + sendPacketCPReady <= next_sendPacketCPReady; + end +end + +endmodule \ No newline at end of file

sendpacketcheckpreamble.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sendpacketarbiter.v =================================================================== --- sendpacketarbiter.v (nonexistent) +++ sendpacketarbiter.v (revision 40) @@ -0,0 +1,182 @@ + +// File : ../RTL/hostController/sendpacketarbiter.v +// Generated : 11/10/06 05:37:20 +// From : ../RTL/hostController/sendpacketarbiter.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// sendpacketarbiter +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbConstants_h.v" + +module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable); +input HCTxReq; +input [3:0] HC_PID; +input HC_SP_WEn; +input SOFTxReq; +input SOF_SP_WEn; +input clk; +input rst; +output HCTxGnt; +output SOFTxGnt; +output [3:0] sendPacketPID; +output sendPacketWEnable; + +reg HCTxGnt, next_HCTxGnt; +wire HCTxReq; +wire [3:0] HC_PID; +wire HC_SP_WEn; +reg SOFTxGnt, next_SOFTxGnt; +wire SOFTxReq; +wire SOF_SP_WEn; +wire clk; +wire rst; +reg [3:0] sendPacketPID, next_sendPacketPID; +reg sendPacketWEnable, next_sendPacketWEnable; + +// diagram signals declarations +reg muxSOFNotHC, next_muxSOFNotHC; + +// BINARY ENCODED state machine: sendPktArb +// State codes definitions: +`define HC_ACT 2'b00 +`define SOF_ACT 2'b01 +`define SARB_WAIT_REQ 2'b10 +`define START_SARB 2'b11 + +reg [1:0] CurrState_sendPktArb; +reg [1:0] NextState_sendPktArb; + +// Diagram actions (continuous assignments allowed only: assign ...) + +// hostController/SOFTransmit mux +always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID) +begin + if (muxSOFNotHC == 1'b1) + begin + sendPacketWEnable <= SOF_SP_WEn; + sendPacketPID <= `SOF; + end + else + begin + sendPacketWEnable <= HC_SP_WEn; + sendPacketPID <= HC_PID; + end +end + +//-------------------------------------------------------------------- +// Machine: sendPktArb +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb) +begin : sendPktArb_NextState + NextState_sendPktArb <= CurrState_sendPktArb; + // Set default values for outputs and signals + next_HCTxGnt <= HCTxGnt; + next_SOFTxGnt <= SOFTxGnt; + next_muxSOFNotHC <= muxSOFNotHC; + case (CurrState_sendPktArb) + `HC_ACT: + if (HCTxReq == 1'b0) + begin + NextState_sendPktArb <= `SARB_WAIT_REQ; + next_HCTxGnt <= 1'b0; + end + `SOF_ACT: + if (SOFTxReq == 1'b0) + begin + NextState_sendPktArb <= `SARB_WAIT_REQ; + next_SOFTxGnt <= 1'b0; + end + `SARB_WAIT_REQ: + if (SOFTxReq == 1'b1) + begin + NextState_sendPktArb <= `SOF_ACT; + next_SOFTxGnt <= 1'b1; + next_muxSOFNotHC <= 1'b1; + end + else if (HCTxReq == 1'b1) + begin + NextState_sendPktArb <= `HC_ACT; + next_HCTxGnt <= 1'b1; + next_muxSOFNotHC <= 1'b0; + end + `START_SARB: + NextState_sendPktArb <= `SARB_WAIT_REQ; + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : sendPktArb_CurrentState + if (rst) + CurrState_sendPktArb <= `START_SARB; + else + CurrState_sendPktArb <= NextState_sendPktArb; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : sendPktArb_RegOutput + if (rst) + begin + muxSOFNotHC <= 1'b0; + SOFTxGnt <= 1'b0; + HCTxGnt <= 1'b0; + end + else + begin + muxSOFNotHC <= next_muxSOFNotHC; + SOFTxGnt <= next_SOFTxGnt; + HCTxGnt <= next_HCTxGnt; + end +end + +endmodule \ No newline at end of file

sendpacketarbiter.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sofcontroller.v =================================================================== --- sofcontroller.v (nonexistent) +++ sofcontroller.v (revision 40) @@ -0,0 +1,181 @@ + +// File : ../RTL/hostController/sofcontroller.v +// Generated : 11/10/06 05:37:21 +// From : ../RTL/hostController/sofcontroller.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// sofcontroller +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + +module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst); +input HCTxPortGnt; +input HCTxPortRdy; +input SOFEnable; +input SOFTimerClr; +input clk; +input rst; +output [7:0] HCTxPortCntl; +output [7:0] HCTxPortData; +output HCTxPortReq; +output HCTxPortWEn; +output [15:0] SOFTimer; + +reg [7:0] HCTxPortCntl, next_HCTxPortCntl; +reg [7:0] HCTxPortData, next_HCTxPortData; +wire HCTxPortGnt; +wire HCTxPortRdy; +reg HCTxPortReq, next_HCTxPortReq; +reg HCTxPortWEn, next_HCTxPortWEn; +wire SOFEnable; +wire SOFTimerClr; +reg [15:0] SOFTimer, next_SOFTimer; +wire clk; +wire rst; + +// BINARY ENCODED state machine: sofCntl +// State codes definitions: +`define START_SC 3'b000 +`define WAIT_SOF_EN 3'b001 +`define WAIT_SEND_RESUME 3'b010 +`define INC_TIMER 3'b011 +`define SC_WAIT_GNT 3'b100 +`define CLR_WEN 3'b101 + +reg [2:0] CurrState_sofCntl; +reg [2:0] NextState_sofCntl; + + +//-------------------------------------------------------------------- +// Machine: sofCntl +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl) +begin : sofCntl_NextState + NextState_sofCntl <= CurrState_sofCntl; + // Set default values for outputs and signals + next_HCTxPortReq <= HCTxPortReq; + next_HCTxPortWEn <= HCTxPortWEn; + next_HCTxPortData <= HCTxPortData; + next_HCTxPortCntl <= HCTxPortCntl; + next_SOFTimer <= SOFTimer; + case (CurrState_sofCntl) + `START_SC: + NextState_sofCntl <= `WAIT_SOF_EN; + `WAIT_SOF_EN: + if (SOFEnable == 1'b1) + begin + NextState_sofCntl <= `SC_WAIT_GNT; + next_HCTxPortReq <= 1'b1; + end + `WAIT_SEND_RESUME: + if (HCTxPortRdy == 1'b1) + begin + NextState_sofCntl <= `CLR_WEN; + next_HCTxPortWEn <= 1'b1; + next_HCTxPortData <= 8'h00; + next_HCTxPortCntl <= `TX_RESUME_START; + end + `INC_TIMER: + begin + next_HCTxPortReq <= 1'b0; + if (SOFTimerClr == 1'b1) + next_SOFTimer <= 16'h0000; + else + next_SOFTimer <= SOFTimer + 1'b1; + if (SOFEnable == 1'b0) + begin + NextState_sofCntl <= `WAIT_SOF_EN; + next_SOFTimer <= 16'h0000; + end + end + `SC_WAIT_GNT: + if (HCTxPortGnt == 1'b1) + NextState_sofCntl <= `WAIT_SEND_RESUME; + `CLR_WEN: + begin + next_HCTxPortWEn <= 1'b0; + NextState_sofCntl <= `INC_TIMER; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : sofCntl_CurrentState + if (rst) + CurrState_sofCntl <= `START_SC; + else + CurrState_sofCntl <= NextState_sofCntl; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : sofCntl_RegOutput + if (rst) + begin + SOFTimer <= 16'h0000; + HCTxPortCntl <= 8'h00; + HCTxPortData <= 8'h00; + HCTxPortWEn <= 1'b0; + HCTxPortReq <= 1'b0; + end + else + begin + SOFTimer <= next_SOFTimer; + HCTxPortCntl <= next_HCTxPortCntl; + HCTxPortData <= next_HCTxPortData; + HCTxPortWEn <= next_HCTxPortWEn; + HCTxPortReq <= next_HCTxPortReq; + end +end + +endmodule \ No newline at end of file

sofcontroller.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: USBHostControlBI.v =================================================================== --- USBHostControlBI.v (nonexistent) +++ USBHostControlBI.v (revision 40) @@ -0,0 +1,479 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// USBHostControlBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostControl_h.v" + +module USBHostControlBI (address, dataIn, dataOut, writeEn, + strobe_i, + busClk, + rstSyncToBusClk, + usbClk, + rstSyncToUsbClk, + SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut, + TxTransTypeReg, TxSOFEnableReg, + TxAddrReg, TxEndPReg, frameNumIn, + RxPktStatusIn, RxPIDIn, + connectStateIn, + SOFSentIn, connEventIn, resumeIntIn, transDoneIn, + hostControlSelect, + clrTransReq, + preambleEn, + SOFSync, + TxLineState, + LineDirectControlEn, + fullSpeedPol, + fullSpeedRate, + transReq, + isoEn, + SOFTimer + ); +input [3:0] address; +input [7:0] dataIn; +input writeEn; +input strobe_i; +input busClk; +input rstSyncToBusClk; +input usbClk; +input rstSyncToUsbClk; +output [7:0] dataOut; +output SOFSentIntOut; +output connEventIntOut; +output resumeIntOut; +output transDoneIntOut; + +output [1:0] TxTransTypeReg; +output TxSOFEnableReg; +output [6:0] TxAddrReg; +output [3:0] TxEndPReg; +input [10:0] frameNumIn; +input [7:0] RxPktStatusIn; +input [3:0] RxPIDIn; +input [1:0] connectStateIn; +input SOFSentIn; +input connEventIn; +input resumeIntIn; +input transDoneIn; +input hostControlSelect; +input clrTransReq; +output preambleEn; +output SOFSync; +output [1:0] TxLineState; +output LineDirectControlEn; +output fullSpeedPol; +output fullSpeedRate; +output transReq; +output isoEn; //enable isochronous mode +input [15:0] SOFTimer; + +wire [3:0] address; +wire [7:0] dataIn; +wire writeEn; +wire strobe_i; +wire busClk; +wire rstSyncToBusClk; +wire usbClk; +wire rstSyncToUsbClk; +reg [7:0] dataOut; + +reg SOFSentIntOut; +reg connEventIntOut; +reg resumeIntOut; +reg transDoneIntOut; + +reg [1:0] TxTransTypeReg; +reg [1:0] TxTransTypeReg_reg1; +reg TxSOFEnableReg; +reg TxSOFEnableReg_reg1; +reg [6:0] TxAddrReg; +reg [6:0] TxAddrReg_reg1; +reg [3:0] TxEndPReg; +reg [3:0] TxEndPReg_reg1; +wire [10:0] frameNumIn; +wire [7:0] RxPktStatusIn; +wire [3:0] RxPIDIn; +wire [1:0] connectStateIn; + +wire SOFSentIn; +wire connEventIn; +wire resumeIntIn; +wire transDoneIn; +wire hostControlSelect; +wire clrTransReq; +reg preambleEn; +reg preambleEn_reg1; +reg SOFSync; +reg SOFSync_reg1; +reg [1:0] TxLineState; +reg [1:0] TxLineState_reg1; +reg LineDirectControlEn; +reg LineDirectControlEn_reg1; +reg fullSpeedPol; +reg fullSpeedPol_reg1; +reg fullSpeedRate; +reg fullSpeedRate_reg1; +reg transReq; +reg transReq_reg1; +reg isoEn; +reg isoEn_reg1; +wire [15:0] SOFTimer; + +//internal wire and regs +reg [1:0] TxControlReg; +reg [4:0] TxLineControlReg; +reg clrSOFReq; +reg clrConnEvtReq; +reg clrResInReq; +reg clrTransDoneReq; +reg SOFSentInt; +reg connEventInt; +reg resumeInt; +reg transDoneInt; +reg [3:0] interruptMaskReg; +reg setTransReq; +reg [2:0] resumeIntInExtend; +reg [2:0] transDoneInExtend; +reg [2:0] connEventInExtend; +reg [2:0] SOFSentInExtend; +reg [2:0] clrTransReqExtend; + +//clock domain crossing sync registers +//STB = Sync To Busclk +reg [1:0] TxTransTypeRegSTB; +reg TxSOFEnableRegSTB; +reg [6:0] TxAddrRegSTB; +reg [3:0] TxEndPRegSTB; +reg preambleEnSTB; +reg SOFSyncSTB; +reg [1:0] TxLineStateSTB; +reg LineDirectControlEnSTB; +reg fullSpeedPolSTB; +reg fullSpeedRateSTB; +reg transReqSTB; +reg isoEnSTB; +reg [10:0] frameNumInSTB; +reg [10:0] frameNumInSTB_reg1; +reg [7:0] RxPktStatusInSTB; +reg [7:0] RxPktStatusInSTB_reg1; +reg [3:0] RxPIDInSTB; +reg [3:0] RxPIDInSTB_reg1; +reg [1:0] connectStateInSTB; +reg [1:0] connectStateInSTB_reg1; +reg [2:0] SOFSentInSTB; +reg [2:0] connEventInSTB; +reg [2:0] resumeIntInSTB; +reg [2:0] transDoneInSTB; +reg [2:0] clrTransReqSTB; +reg [15:0] SOFTimerSTB; +reg [15:0] SOFTimerSTB_reg1; + + +//sync write demux +always @(posedge busClk) +begin + if (rstSyncToBusClk == 1'b1) begin + isoEnSTB <= 1'b0; + preambleEnSTB <= 1'b0; + SOFSyncSTB <= 1'b0; + TxTransTypeRegSTB <= 2'b00; + TxLineControlReg <= 5'h00; + TxSOFEnableRegSTB <= 1'b0; + TxAddrRegSTB <= 7'h00; + TxEndPRegSTB <= 4'h0; + interruptMaskReg <= 4'h0; + end + else begin + clrSOFReq <= 1'b0; + clrConnEvtReq <= 1'b0; + clrResInReq <= 1'b0; + clrTransDoneReq <= 1'b0; + setTransReq <= 1'b0; + if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1) + begin + case (address) + `TX_CONTROL_REG : begin + isoEnSTB <= dataIn[`ISO_ENABLE_BIT]; + preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT]; + SOFSyncSTB <= dataIn[`SOF_SYNC_BIT]; + setTransReq <= dataIn[`TRANS_REQ_BIT]; + end + `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0]; + `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0]; + `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT]; + `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0]; + `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0]; + `INTERRUPT_STATUS_REG : begin + clrSOFReq <= dataIn[`SOF_SENT_BIT]; + clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT]; + clrResInReq <= dataIn[`RESUME_INT_BIT]; + clrTransDoneReq <= dataIn[`TRANS_DONE_BIT]; + end + `INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0]; + endcase + end + end +end + +//interrupt control +always @(posedge busClk) +begin + if (rstSyncToBusClk == 1'b1) begin + SOFSentInt <= 1'b0; + connEventInt <= 1'b0; + resumeInt <= 1'b0; + transDoneInt <= 1'b0; + end + else begin + if (SOFSentInSTB[1] == 1'b1 && SOFSentInSTB[0] == 1'b0) + SOFSentInt <= 1'b1; + else if (clrSOFReq == 1'b1) + SOFSentInt <= 1'b0; + + if (connEventInSTB[1] == 1'b1 && connEventInSTB[0] == 1'b0) + connEventInt <= 1'b1; + else if (clrConnEvtReq == 1'b1) + connEventInt <= 1'b0; + + if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0) + resumeInt <= 1'b1; + else if (clrResInReq == 1'b1) + resumeInt <= 1'b0; + + if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0) + transDoneInt <= 1'b1; + else if (clrTransDoneReq == 1'b1) + transDoneInt <= 1'b0; + end +end + +//mask interrupts +always @(*) begin + transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT]; + resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT]; + connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT]; + SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT]; +end + +//transaction request set/clear +//Since 'busClk' can be a higher freq than 'usbClk', +//'setTransReq' must be delayed with respect to other control signals, thus +//ensuring that control signals have been clocked through to 'usbClk' clock +//domain before the transaction request is asserted. +//Not sure this is required because there is at least two 'usbClk' ticks between +//detection of 'transReq' and sampling of related control signals. +always @(posedge busClk) +begin + if (rstSyncToBusClk == 1'b1) begin + transReqSTB <= 1'b0; + end + else begin + if (setTransReq == 1'b1) + transReqSTB <= 1'b1; + else if (clrTransReqSTB[1] == 1'b1 && clrTransReqSTB[0] == 1'b0) + transReqSTB <= 1'b0; + end +end + +//break out control signals +always @(*) begin + TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT]; + LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT]; + fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; + fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT]; +end + +// async read mux +always @(*) +begin + case (address) + `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ; + `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB}; + `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg}; + `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB}; + `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB}; + `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB}; + `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]}; + `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0]; + `INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt}; + `INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg}; + `RX_STATUS_REG : dataOut <= RxPktStatusInSTB; + `RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB}; + `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB}; + `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8]; + default: dataOut <= 8'h00; + endcase +end + +//re-sync from busClk to usbClk. +always @(posedge usbClk) begin + if (rstSyncToUsbClk == 1'b1) begin + isoEn <= 1'b0; + isoEn_reg1 <= 1'b0; + preambleEn <= 1'b0; + preambleEn_reg1 <= 1'b0; + SOFSync <= 1'b0; + SOFSync_reg1 <= 1'b0; + TxTransTypeReg <= 2'b00; + TxTransTypeReg_reg1 <= 2'b00; + TxSOFEnableReg <= 1'b0; + TxSOFEnableReg_reg1 <= 1'b0; + TxAddrReg <= {7{1'b0}}; + TxAddrReg_reg1 <= {7{1'b0}}; + TxEndPReg <= 4'h0; + TxEndPReg_reg1 <= 4'h0; + TxLineState <= 2'b00; + TxLineState_reg1 <= 2'b00; + LineDirectControlEn <= 1'b0; + LineDirectControlEn_reg1 <= 1'b0; + fullSpeedPol <= 1'b0; + fullSpeedPol_reg1 <= 1'b0; + fullSpeedRate <= 1'b0; + fullSpeedRate_reg1 <= 1'b0; + transReq <= 1'b0; + transReq_reg1 <= 1'b0; + end + else begin + isoEn_reg1 <= isoEnSTB; + isoEn <= isoEn_reg1; + preambleEn_reg1 <= preambleEnSTB; + preambleEn <= preambleEn_reg1; + SOFSync_reg1 <= SOFSyncSTB; + SOFSync <= SOFSync_reg1; + TxTransTypeReg_reg1 <= TxTransTypeRegSTB; + TxTransTypeReg <= TxTransTypeReg_reg1; + TxSOFEnableReg_reg1 <= TxSOFEnableRegSTB; + TxSOFEnableReg <= TxSOFEnableReg_reg1; + TxAddrReg_reg1 <= TxAddrRegSTB; + TxAddrReg <= TxAddrReg_reg1; + TxEndPReg_reg1 <= TxEndPRegSTB; + TxEndPReg <= TxEndPReg_reg1; + TxLineState_reg1 <= TxLineStateSTB; + TxLineState <= TxLineState_reg1; + LineDirectControlEn_reg1 <= LineDirectControlEnSTB; + LineDirectControlEn <= LineDirectControlEn_reg1; + fullSpeedPol_reg1 <= fullSpeedPolSTB; + fullSpeedPol <= fullSpeedPol_reg1; + fullSpeedRate_reg1 <= fullSpeedRateSTB; + fullSpeedRate <= fullSpeedRate_reg1; + transReq_reg1 <= transReqSTB; + transReq <= transReq_reg1; + end +end + +//Extend resumeIntIn etc from 1 tick to 3 ticks +always @(posedge usbClk) begin + if (rstSyncToUsbClk == 1'b1) begin + resumeIntInExtend <= 3'b000; + transDoneInExtend <= 3'b000; + connEventInExtend <= 3'b000; + SOFSentInExtend <= 3'b000; + clrTransReqExtend <= 3'b000; + end + else begin + if (resumeIntIn == 1'b1) + resumeIntInExtend <= 3'b111; + else + resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]}; + if (transDoneIn == 1'b1) + transDoneInExtend <= 3'b111; + else + transDoneInExtend <= {1'b0, transDoneInExtend[2:1]}; + if (connEventIn == 1'b1) + connEventInExtend <= 3'b111; + else + connEventInExtend <= {1'b0, connEventInExtend[2:1]}; + if (SOFSentIn == 1'b1) + SOFSentInExtend <= 3'b111; + else + SOFSentInExtend <= {1'b0, SOFSentInExtend[2:1]}; + if (clrTransReq == 1'b1) + clrTransReqExtend <= 3'b111; + else + clrTransReqExtend <= {1'b0, clrTransReqExtend[2:1]}; + end +end + +//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted +//for 3 'usbClk' ticks, busClk freq must be greater than or equal to usbClk/3 freq +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + SOFSentInSTB <= 3'b000; + connEventInSTB <= 3'b000; + resumeIntInSTB <= 3'b000; + transDoneInSTB <= 3'b000; + clrTransReqSTB <= 3'b000; + frameNumInSTB <= {11{1'b0}}; + frameNumInSTB_reg1 <= {11{1'b0}}; + RxPktStatusInSTB <= 8'h00; + RxPktStatusInSTB_reg1 <= 8'h00; + RxPIDInSTB <= 4'h0; + RxPIDInSTB_reg1 <= 4'h0; + connectStateInSTB <= 2'b00; + connectStateInSTB_reg1 <= 2'b00; + SOFTimerSTB <= 16'h0000; + SOFTimerSTB_reg1 <= 16'h0000; + end + else begin + frameNumInSTB_reg1 <= frameNumIn; + frameNumInSTB <= frameNumInSTB_reg1; + RxPktStatusInSTB_reg1 <= RxPktStatusIn; + RxPktStatusInSTB <= RxPktStatusInSTB_reg1; + RxPIDInSTB_reg1 <= RxPIDIn; + RxPIDInSTB <= RxPIDInSTB_reg1; + connectStateInSTB_reg1 <= connectStateIn; + connectStateInSTB <= connectStateInSTB_reg1; + SOFSentInSTB <= {SOFSentInExtend[0], SOFSentInSTB[2:1]}; + connEventInSTB <= {connEventInExtend[0], connEventInSTB[2:1]}; + resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]}; + transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]}; + clrTransReqSTB <= {clrTransReqExtend[0], clrTransReqSTB[2:1]}; + //FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way + //All the other multi-bit signals will be static at the time that they are + //read, but 'SOFTimer' will not be static. + SOFTimerSTB_reg1 <= SOFTimer; + SOFTimerSTB <= SOFTimerSTB_reg1; + end +end + + +endmodule

USBHostControlBI.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: getpacket.v =================================================================== --- getpacket.v (nonexistent) +++ getpacket.v (revision 40) @@ -0,0 +1,375 @@ + +// File : ../RTL/hostController/getpacket.v +// Generated : 11/10/06 05:37:20 +// From : ../RTL/hostController/getpacket.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// getpacket +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + +module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, SIERxTimeOutEn, clk, getPacketEn, rst); +input [7:0] RXDataIn; +input RXDataValid; +input RXFifoFull; +input [7:0] RXStreamStatusIn; +input SIERxTimeOut; // Single cycle pulse +input clk; +input getPacketEn; +input rst; +output [7:0] RXFifoData; +output RXFifoWEn; +output RXPacketRdy; +output [7:0] RXPktStatus; +output [3:0] RxPID; +output SIERxTimeOutEn; + +wire [7:0] RXDataIn; +wire RXDataValid; +reg [7:0] RXFifoData, next_RXFifoData; +wire RXFifoFull; +reg RXFifoWEn, next_RXFifoWEn; +reg RXPacketRdy, next_RXPacketRdy; +reg [7:0] RXPktStatus; +wire [7:0] RXStreamStatusIn; +reg [3:0] RxPID, next_RxPID; +wire SIERxTimeOut; +reg SIERxTimeOutEn, next_SIERxTimeOutEn; +wire clk; +wire getPacketEn; +wire rst; + +// diagram signals declarations +reg ACKRxed, next_ACKRxed; +reg CRCError, next_CRCError; +reg NAKRxed, next_NAKRxed; +reg [7:0]RXByteOld, next_RXByteOld; +reg [7:0]RXByteOldest, next_RXByteOldest; +reg [7:0]RXByte, next_RXByte; +reg RXOverflow, next_RXOverflow; +reg [7:0]RXStreamStatus, next_RXStreamStatus; +reg RXTimeOut, next_RXTimeOut; +reg bitStuffError, next_bitStuffError; +reg dataSequence, next_dataSequence; +reg stallRxed, next_stallRxed; + +// BINARY ENCODED state machine: getPkt +// State codes definitions: +`define PROC_PKT_CHK_PID 5'b00000 +`define PROC_PKT_HS 5'b00001 +`define PROC_PKT_DATA_W_D1 5'b00010 +`define PROC_PKT_DATA_CHK_D1 5'b00011 +`define PROC_PKT_DATA_W_D2 5'b00100 +`define PROC_PKT_DATA_FIN 5'b00101 +`define PROC_PKT_DATA_CHK_D2 5'b00110 +`define PROC_PKT_DATA_W_D3 5'b00111 +`define PROC_PKT_DATA_CHK_D3 5'b01000 +`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001 +`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010 +`define PROC_PKT_DATA_LOOP_W_D 5'b01011 +`define START_GP 5'b01100 +`define WAIT_PKT 5'b01101 +`define CHK_PKT_START 5'b01110 +`define WAIT_EN 5'b01111 +`define PKT_RDY 5'b10000 +`define PROC_PKT_DATA_LOOP_DELAY 5'b10001 + +reg [4:0] CurrState_getPkt; +reg [4:0] NextState_getPkt; + +// Diagram actions (continuous assignments allowed only: assign ...) + +always @ +(CRCError or bitStuffError or + RXOverflow or RXTimeOut or + NAKRxed or stallRxed or + ACKRxed or dataSequence) +begin + RXPktStatus <= { + dataSequence, ACKRxed, + stallRxed, NAKRxed, + RXTimeOut, RXOverflow, + bitStuffError, CRCError}; +end + +//-------------------------------------------------------------------- +// Machine: getPkt +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt) +begin : getPkt_NextState + NextState_getPkt <= CurrState_getPkt; + // Set default values for outputs and signals + next_CRCError <= CRCError; + next_bitStuffError <= bitStuffError; + next_RXOverflow <= RXOverflow; + next_RXTimeOut <= RXTimeOut; + next_NAKRxed <= NAKRxed; + next_stallRxed <= stallRxed; + next_ACKRxed <= ACKRxed; + next_dataSequence <= dataSequence; + next_SIERxTimeOutEn <= SIERxTimeOutEn; + next_RXByte <= RXByte; + next_RXStreamStatus <= RXStreamStatus; + next_RxPID <= RxPID; + next_RXPacketRdy <= RXPacketRdy; + next_RXByteOldest <= RXByteOldest; + next_RXByteOld <= RXByteOld; + next_RXFifoWEn <= RXFifoWEn; + next_RXFifoData <= RXFifoData; + case (CurrState_getPkt) + `START_GP: + NextState_getPkt <= `WAIT_EN; + `WAIT_PKT: + begin + next_CRCError <= 1'b0; + next_bitStuffError <= 1'b0; + next_RXOverflow <= 1'b0; + next_RXTimeOut <= 1'b0; + next_NAKRxed <= 1'b0; + next_stallRxed <= 1'b0; + next_ACKRxed <= 1'b0; + next_dataSequence <= 1'b0; + next_SIERxTimeOutEn <= 1'b1; + if (SIERxTimeOut == 1'b1) + begin + NextState_getPkt <= `PKT_RDY; + next_RXTimeOut <= 1'b1; + end + else if (RXDataValid == 1'b1) + begin + NextState_getPkt <= `CHK_PKT_START; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + end + `CHK_PKT_START: + if (RXStreamStatus == `RX_PACKET_START) + begin + NextState_getPkt <= `PROC_PKT_CHK_PID; + next_RxPID <= RXByte[3:0]; + end + else + begin + NextState_getPkt <= `PKT_RDY; + next_RXTimeOut <= 1'b1; + end + `WAIT_EN: + begin + next_RXPacketRdy <= 1'b0; + next_SIERxTimeOutEn <= 1'b0; + if (getPacketEn == 1'b1) + NextState_getPkt <= `WAIT_PKT; + end + `PKT_RDY: + begin + next_RXPacketRdy <= 1'b1; + NextState_getPkt <= `WAIT_EN; + end + `PROC_PKT_CHK_PID: + if (RXByte[1:0] == `HANDSHAKE) + NextState_getPkt <= `PROC_PKT_HS; + else if (RXByte[1:0] == `DATA) + NextState_getPkt <= `PROC_PKT_DATA_W_D1; + else + NextState_getPkt <= `PKT_RDY; + `PROC_PKT_HS: + if (RXDataValid == 1'b1) + begin + NextState_getPkt <= `PKT_RDY; + next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT]; + next_NAKRxed <= RXDataIn[`NAK_RXED_BIT]; + next_stallRxed <= RXDataIn[`STALL_RXED_BIT]; + next_ACKRxed <= RXDataIn[`ACK_RXED_BIT]; + end + `PROC_PKT_DATA_W_D1: + if (RXDataValid == 1'b1) + begin + NextState_getPkt <= `PROC_PKT_DATA_CHK_D1; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + `PROC_PKT_DATA_CHK_D1: + if (RXStreamStatus == `RX_PACKET_STREAM) + begin + NextState_getPkt <= `PROC_PKT_DATA_W_D2; + next_RXByteOldest <= RXByte; + end + else + NextState_getPkt <= `PROC_PKT_DATA_FIN; + `PROC_PKT_DATA_W_D2: + if (RXDataValid == 1'b1) + begin + NextState_getPkt <= `PROC_PKT_DATA_CHK_D2; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + `PROC_PKT_DATA_FIN: + begin + next_CRCError <= RXByte[`CRC_ERROR_BIT]; + next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT]; + next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT]; + NextState_getPkt <= `PKT_RDY; + end + `PROC_PKT_DATA_CHK_D2: + if (RXStreamStatus == `RX_PACKET_STREAM) + begin + NextState_getPkt <= `PROC_PKT_DATA_W_D3; + next_RXByteOld <= RXByte; + end + else + NextState_getPkt <= `PROC_PKT_DATA_FIN; + `PROC_PKT_DATA_W_D3: + if (RXDataValid == 1'b1) + begin + NextState_getPkt <= `PROC_PKT_DATA_CHK_D3; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + `PROC_PKT_DATA_CHK_D3: + if (RXStreamStatus == `RX_PACKET_STREAM) + NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO; + else + NextState_getPkt <= `PROC_PKT_DATA_FIN; + `PROC_PKT_DATA_LOOP_CHK_FIFO: + if (RXFifoFull == 1'b1) + begin + NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL; + next_RXOverflow <= 1'b1; + end + else + begin + NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D; + next_RXFifoWEn <= 1'b1; + next_RXFifoData <= RXByteOldest; + next_RXByteOldest <= RXByteOld; + next_RXByteOld <= RXByte; + end + `PROC_PKT_DATA_LOOP_FIFO_FULL: + NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D; + `PROC_PKT_DATA_LOOP_W_D: + begin + next_RXFifoWEn <= 1'b0; + if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM)) + begin + NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + else if (RXDataValid == 1'b1) + begin + NextState_getPkt <= `PROC_PKT_DATA_FIN; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + end + `PROC_PKT_DATA_LOOP_DELAY: + NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO; + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : getPkt_CurrentState + if (rst) + CurrState_getPkt <= `START_GP; + else + CurrState_getPkt <= NextState_getPkt; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : getPkt_RegOutput + if (rst) + begin + RXByteOld <= 8'h00; + RXByteOldest <= 8'h00; + CRCError <= 1'b0; + bitStuffError <= 1'b0; + RXOverflow <= 1'b0; + RXTimeOut <= 1'b0; + NAKRxed <= 1'b0; + stallRxed <= 1'b0; + ACKRxed <= 1'b0; + dataSequence <= 1'b0; + RXByte <= 8'h00; + RXStreamStatus <= 8'h00; + RXPacketRdy <= 1'b0; + RXFifoWEn <= 1'b0; + RXFifoData <= 8'h00; + RxPID <= 4'h0; + SIERxTimeOutEn <= 1'b0; + end + else + begin + RXByteOld <= next_RXByteOld; + RXByteOldest <= next_RXByteOldest; + CRCError <= next_CRCError; + bitStuffError <= next_bitStuffError; + RXOverflow <= next_RXOverflow; + RXTimeOut <= next_RXTimeOut; + NAKRxed <= next_NAKRxed; + stallRxed <= next_stallRxed; + ACKRxed <= next_ACKRxed; + dataSequence <= next_dataSequence; + RXByte <= next_RXByte; + RXStreamStatus <= next_RXStreamStatus; + RXPacketRdy <= next_RXPacketRdy; + RXFifoWEn <= next_RXFifoWEn; + RXFifoData <= next_RXFifoData; + RxPID <= next_RxPID; + SIERxTimeOutEn <= next_SIERxTimeOutEn; + end +end + +endmodule \ No newline at end of file

getpacket.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: softransmit.v =================================================================== --- softransmit.v (nonexistent) +++ softransmit.v (revision 40) @@ -0,0 +1,202 @@ + +// File : ../RTL/hostController/softransmit.v +// Generated : 11/10/06 05:37:21 +// From : ../RTL/hostController/softransmit.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// softransmit +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostControl_h.v" + + +module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn); +input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn +input SOFSyncEn; +input [15:0] SOFTimer; +input clk; +input rst; +input sendPacketArbiterGnt; +input sendPacketRdy; +output SOFSent; // single cycle pulse +output SOFTimerClr; // Single cycle pulse +output sendPacketArbiterReq; +output sendPacketWEn; + +wire SOFEnable; +reg SOFSent, next_SOFSent; +wire SOFSyncEn; +reg SOFTimerClr, next_SOFTimerClr; +wire [15:0] SOFTimer; +wire clk; +wire rst; +wire sendPacketArbiterGnt; +reg sendPacketArbiterReq, next_sendPacketArbiterReq; +wire sendPacketRdy; +reg sendPacketWEn, next_sendPacketWEn; + +// diagram signals declarations +reg [7:0]i, next_i; + +// BINARY ENCODED state machine: SOFTx +// State codes definitions: +`define START_STX 3'b000 +`define WAIT_SOF_NEAR 3'b001 +`define WAIT_SP_GNT 3'b010 +`define WAIT_SOF_NOW 3'b011 +`define SOF_FIN 3'b100 +`define DLY_SOF_CHK1 3'b101 +`define DLY_SOF_CHK2 3'b110 + +reg [2:0] CurrState_SOFTx; +reg [2:0] NextState_SOFTx; + + +//-------------------------------------------------------------------- +// Machine: SOFTx +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx) +begin : SOFTx_NextState + NextState_SOFTx <= CurrState_SOFTx; + // Set default values for outputs and signals + next_sendPacketArbiterReq <= sendPacketArbiterReq; + next_sendPacketWEn <= sendPacketWEn; + next_SOFTimerClr <= SOFTimerClr; + next_SOFSent <= SOFSent; + next_i <= i; + case (CurrState_SOFTx) + `START_STX: + NextState_SOFTx <= `WAIT_SOF_NEAR; + `WAIT_SOF_NEAR: + if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN || + (SOFSyncEn == 1'b1 && + SOFEnable == 1'b1)) + begin + NextState_SOFTx <= `WAIT_SP_GNT; + next_sendPacketArbiterReq <= 1'b1; + end + `WAIT_SP_GNT: + if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1) + NextState_SOFTx <= `WAIT_SOF_NOW; + `WAIT_SOF_NOW: + if (SOFTimer >= `SOF_TX_TIME) + begin + NextState_SOFTx <= `SOF_FIN; + next_sendPacketWEn <= 1'b1; + next_SOFTimerClr <= 1'b1; + next_SOFSent <= 1'b1; + end + else if (SOFEnable == 1'b0) + begin + NextState_SOFTx <= `SOF_FIN; + next_SOFTimerClr <= 1'b1; + end + `SOF_FIN: + begin + next_sendPacketWEn <= 1'b0; + next_SOFTimerClr <= 1'b0; + next_SOFSent <= 1'b0; + if (sendPacketRdy == 1'b1) + begin + NextState_SOFTx <= `DLY_SOF_CHK1; + next_i <= 8'h00; + end + end + `DLY_SOF_CHK1: + begin + next_i <= i + 1'b1; + if (i==8'hff) + begin + NextState_SOFTx <= `DLY_SOF_CHK2; + next_sendPacketArbiterReq <= 1'b0; + next_i <= 8'h00; + end + end + `DLY_SOF_CHK2: + begin + next_i <= i + 1'b1; + if (i==8'hff) + NextState_SOFTx <= `WAIT_SOF_NEAR; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : SOFTx_CurrentState + if (rst) + CurrState_SOFTx <= `START_STX; + else + CurrState_SOFTx <= NextState_SOFTx; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : SOFTx_RegOutput + if (rst) + begin + i <= 8'h00; + SOFSent <= 1'b0; + SOFTimerClr <= 1'b0; + sendPacketArbiterReq <= 1'b0; + sendPacketWEn <= 1'b0; + end + else + begin + i <= next_i; + SOFSent <= next_SOFSent; + SOFTimerClr <= next_SOFTimerClr; + sendPacketArbiterReq <= next_sendPacketArbiterReq; + sendPacketWEn <= next_sendPacketWEn; + end +end + +endmodule \ No newline at end of file

softransmit.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: getpacket.asf =================================================================== --- getpacket.asf (nonexistent) +++ getpacket.asf (revision 40) @@ -0,0 +1,287 @@ +VERSION=1.21 +HEADER +FILE="getpacket.asf" +FID=406f8b6a +LANGUAGE=VERILOG +ENTITY="getPacket" +FREEOID=261 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// getpacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n" +MULTIPLEARCHSTATUS=FALSE +SYNTHESISATTRIBUTES=TRUE +HEADER_PARAM="AUTHOR," +HEADER_PARAM="COMPANY," +HEADER_PARAM="CREATIONDATE," +HEADER_PARAM="TITLE,No Title" +BLOCKTABLE_FILE="" +BLOCKTABLE_TEMPL="0" +BLOCKTABLE_VISIBLE="1" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0 +B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 0,0 215900,279400 +MARGINS 12700,0 0,12700 +END +INSTHEADER 33 +PAGE 0,0 215900,279400 +MARGINS 12700,0 0,12700 +END +INSTHEADER 58 +PAGE 0,0 215900,279400 +MARGINS 12700,0 0,12700 +END +INSTHEADER 112 +PAGE 0,0 215900,279400 +MARGINS 12700,0 0,12700 +END +INSTHEADER 245 +PAGE 0,0 215900,279400 +MARGINS 12700,0 0,12700 +END +INSTHEADER 251 +PAGE 0,0 215900,279400 +MARGINS 12700,0 0,12700 +END +OBJECTS +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,251000 1 0 0 "Module: getPacket" +F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,2536 200200,203250 +L 7 6 0 TEXT "Labels" | 19389,199393 1 0 0 "getPkt" +L 8 9 0 TEXT "State Labels" | 74582,184064 1 0 0 "START_GP\n/12/" +S 9 6 57344 ELLIPSE "States" | 74582,184064 6500 6500 +L 10 11 0 TEXT "State Labels" | 103150,135436 1 0 0 "WAIT_PKT\n/13/" +S 11 6 61440 ELLIPSE "States" | 103150,135436 6500 6500 +L 14 15 0 TEXT "State Labels" | 139950,100636 1 0 0 "CHK_PKT_START\n/14/" +S 15 6 65536 ELLIPSE "States" | 139950,100636 6500 6500 +W 18 6 0 11 15 BEZIER "Transitions" | 107724,130820 114924,124320 128014,111586 135214,105086 +C 20 18 0 TEXT "Conditions" | 110328,129240 1 0 0 "RXDataValid == 1'b1" +L 22 23 0 TEXT "State Labels" | 103550,171836 1 0 0 "WAIT_EN\n/15/" +S 23 6 69632 ELLIPSE "States" | 103550,171836 6500 6500 +W 24 6 0 9 23 BEZIER "Transitions" | 80937,182699 85165,184911 97342,182136 103310,178316 +W 25 6 0 23 11 BEZIER "Transitions" | 103028,165364 102828,159364 102811,147904 102611,141904 +C 26 25 0 TEXT "Conditions" | 87910,162900 1 0 0 "getPacketEn == 1'b1" +A 30 23 4 TEXT "Actions" | 120169,181001 1 0 0 "RXPacketRdy <= 1'b0;\nSIERxTimeOutEn <= 1'b0;" +A 31 18 16 TEXT "Actions" | 117968,120998 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;" +H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +A 45 44 16 TEXT "Actions" | 155714,18540 1 0 0 "RXTimeOut <= 1'b1;" +W 44 6 8194 15 40 BEZIER "Transitions" | 146436,100221 157397,99882 178653,98883 184472,96849\ + 190292,94815 191648,87357 191987,79729 192326,72102\ + 192326,49050 188540,40462 184755,31874 169613,20574\ + 159556,17636 149499,14698 125714,14914 113171,14688 +C 43 41 0 TEXT "Conditions" | 74897,97810 1 0 0 "SIERxTimeOut == 1'b1" +A 42 41 16 TEXT "Actions" | 81060,86334 1 0 0 "RXTimeOut <= 1'b1;" +W 41 6 0 11 40 BEZIER "Transitions" | 96829,133925 92570,119964 92057,118384 90299,109215\ + 88541,100046 87971,93160 87641,80402 87312,67644\ + 87761,57427 92565,46663 97370,35899 95270,32842\ + 101102,18266 +S 40 6 73728 ELLIPSE "States" | 106676,14924 6500 6500 +L 39 40 0 TEXT "State Labels" | 106676,14924 1 0 0 "PKT_RDY\n/16/" +L 32 33 0 TEXT "State Labels" | 141010,60114 1 0 0 "PROC_PKT" +S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,60114 6500 6500 +W 34 6 8193 15 33 BEZIER "Transitions" | 139672,94164 139470,86993 141270,73756 141068,66585 +C 35 34 0 TEXT "Conditions" | 122408,84930 1 0 0 "RXStreamStatus == `RX_PACKET_START" +C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA" +C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE" +W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984 +W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842 +W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132 +S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500 +L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA" +S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500 +L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/" +S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500 +L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/" +I 49 46 0 Builtin Entry | 47660,248640 +I 50 46 0 Builtin Exit | 180308,72140 +L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/" +I 76 72 0 Builtin Exit | 187140,27160 +I 75 72 0 Builtin Entry | 33260,254940 +H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];" +C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1" +W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057 +C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM" +C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1" +W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562 +W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415 +S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500 +L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/" +S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500 +L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/" +W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334 +S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500 +W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\ + 26270,188186 26497,147369 28526,126511 30555,105653\ + 38448,63032 43352,51475 48257,39919 60065,36353\ + 65928,34549 +S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500 +L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/" +A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;" +S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500 +L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/" +S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500 +L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/" +W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127 +W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256 +C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1" +C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM" +A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;" +W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\ + 39882,146032 37743,135343 38221,127384 38700,119425\ + 42750,98275 45281,87925 47812,77575 53888,57325\ + 56840,51109 59793,44894 65013,39901 67881,37595 +S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500 +L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/" +S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500 +L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP" +W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827 +W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956 +C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1" +C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM" +A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;" +W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\ + 55031,85605 56613,76791 58364,71028 60116,65265\ + 65540,51027 67235,46846 68930,42665 69902,40249\ + 70580,39006 +H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +I 123 120 0 Builtin Entry | 33260,254940 +I 124 120 0 Builtin Exit | 117012,100084 +W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829 +C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1" +A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;" +L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/" +S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500 +W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103 +L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/" +S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500 +W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\ + 122651,219510 150577,206851 153176,201653 +C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1" +W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954 +A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;" +A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;" +L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/" +S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500 +W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\ + 136577,164328 115116,157816 103895,154496 +W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500 +C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM" +W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084 +A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;" +W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329 +A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];" +A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;" +W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\ + 99709,21131 138868,20336 151863,21045 164858,21755\ + 177616,25344 184028,27160 +I 169 6 0 Builtin Reset | 40672,195051 +W 170 6 0 169 9 BEZIER "Transitions" | 40672,195051 50149,193519 60549,191261 70258,188917 +A 173 40 4 TEXT "Actions" | 128094,33024 1 0 0 "RXPacketRdy <= 1'b1;" +W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\ + 138686,69264 146640,68588 151838,68757 157036,68927\ + 164174,70167 165417,70562 166660,70958 172486,71065\ + 172450,70926 172415,70788 176799,72082 177196,72140 +W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\ + 145039,100828 129179,95043 122324,92416 +W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\ + 176686,205938 186055,195197 188340,185143 190625,175090\ + 190396,145613 187654,132589 184913,119565 174172,96942\ + 167317,90830 160463,84718 143756,82720 138170,83176\ + 132585,83633 124984,88032 122129,89345 +L 178 179 0 TEXT "Labels" | 126132,235196 1 0 0 "getPacketEn" +I 179 0 2 Builtin InPort | 120132,235196 "" "" +L 180 181 0 TEXT "Labels" | 123932,239896 1 0 0 "RXPacketRdy" +I 181 0 2 Builtin OutPort | 117932,239896 "" "" +L 182 183 0 TEXT "Labels" | 120228,217946 1 0 0 "RXDataValid" +I 183 0 2 Builtin InPort | 114228,217946 "" "" +L 184 185 0 TEXT "Labels" | 146253,252499 1 0 0 "clk" +I 185 0 3 Builtin InPort | 140253,252499 "" "" +L 186 187 0 TEXT "Labels" | 146242,247212 1 0 0 "rst" +I 187 0 2 Builtin InPort | 140242,247212 "" "" +C 188 170 0 TEXT "Conditions" | 56486,189866 1 0 0 "rst" +L 189 190 0 TEXT "Labels" | 120408,208554 1 0 0 "RXStreamStatusIn[7:0]" +I 190 0 130 Builtin InPort | 114408,208554 "" "" +I 191 0 130 Builtin InPort | 114421,213294 "" "" +L 192 191 0 TEXT "Labels" | 120421,213294 1 0 0 "RXDataIn[7:0]" +L 193 194 0 TEXT "Labels" | 85500,224348 1 0 0 "SIERxTimeOut" +I 194 0 2 Builtin InPort | 79500,224348 "" "" +K 195 194 0 TEXT "Comments" | 107584,224332 1 0 0 "Single cycle pulse" +L 196 197 0 TEXT "Labels" | 22204,208708 1 0 0 "RXByte[7:0]" +I 197 0 130 Builtin Signal | 19204,208708 "" "" +L 198 199 0 TEXT "Labels" | 22068,231640 1 0 0 "RXOverflow" +I 199 0 2 Builtin Signal | 19068,231640 "" "" +L 200 201 0 TEXT "Labels" | 22380,226836 1 0 0 "NAKRxed" +I 201 0 2 Builtin Signal | 19380,226836 "" "" +L 202 203 0 TEXT "Labels" | 22840,218056 1 0 0 "stallRxed" +I 203 0 2 Builtin Signal | 19840,218056 "" "" +L 204 205 0 TEXT "Labels" | 22880,221704 1 0 0 "ACKRxed" +I 205 0 2 Builtin Signal | 19416,222168 "" "" +L 206 207 0 TEXT "Labels" | 83404,214212 1 0 0 "RXPktStatus[7:0]" +I 207 0 128 Builtin OutPort | 77404,214212 "" "" +L 208 209 0 TEXT "Labels" | 22024,236540 1 0 0 "RXTimeOut" +I 209 0 2 Builtin Signal | 19024,236540 "" "" +L 210 211 0 TEXT "Labels" | 21792,241180 1 0 0 "CRCError" +I 211 0 2 Builtin Signal | 18792,241180 "" "" +L 212 213 0 TEXT "Labels" | 22024,245588 1 0 0 "bitStuffError" +I 213 0 2 Builtin Signal | 19024,245588 "" "" +L 214 215 0 TEXT "Labels" | 22024,250228 1 0 0 "dataSequence" +I 215 0 2 Builtin Signal | 19024,250228 "" "" +I 216 0 130 Builtin Signal | 19488,213484 "" "" +L 217 216 0 TEXT "Labels" | 22488,213484 1 0 0 "RXStreamStatus[7:0]" +A 219 9 2 TEXT "Actions" | 18096,180744 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;" +A 220 11 4 TEXT "Actions" | 125976,168296 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;" +L 221 222 0 TEXT "Labels" | 55956,247152 1 0 0 "RXByteOld[7:0]" +I 222 0 130 Builtin Signal | 52956,247152 "" "" +W 239 6 0 33 40 BEZIER "Transitions" | 136204,55740 129157,46692 116484,29855 109437,20807 +I 238 0 130 Builtin OutPort | 77500,209104 "" "" +L 237 238 0 TEXT "Labels" | 83500,209104 1 0 0 "RxPID[3:0]" +A 236 34 16 TEXT "Actions" | 139444,78256 1 0 0 "RxPID <= RXByte[3:0];" +I 225 0 130 Builtin Signal | 52956,252400 "" "" +L 226 225 0 TEXT "Labels" | 55956,252400 1 0 0 "RXByteOldest[7:0]" +L 227 228 0 TEXT "Labels" | 85868,240540 1 0 0 "RXFifoFull" +I 228 0 2 Builtin InPort | 79868,240540 "" "" +L 229 230 0 TEXT "Labels" | 83548,235552 1 0 0 "RXFifoWEn" +I 230 0 2 Builtin OutPort | 77548,235552 "" "" +L 231 232 0 TEXT "Labels" | 83780,229752 1 0 0 "RXFifoData[7:0]" +I 232 0 130 Builtin OutPort | 77780,229752 "" "" +A 235 0 1 TEXT "Actions" | 156850,252790 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n RXPktStatus <= { \n dataSequence, ACKRxed, \n stallRxed, NAKRxed,\n RXTimeOut, RXOverflow, \n bitStuffError, CRCError};\nend" +W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760 +I 254 252 0 Builtin Exit | 129540,111760 +I 253 252 0 Builtin Entry | 86360,167640 +H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500 +L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2" +W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760 +I 248 246 0 Builtin Exit | 129540,111760 +I 247 246 0 Builtin Entry | 86360,167640 +H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500 +L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1" +W 240 6 0 40 23 BEZIER "Transitions" | 100228,15739 96139,18958 88201,22665 84938,28363\ + 81676,34062 76804,50418 74237,60292 71671,70167\ + 66277,93309 65842,105315 65407,117321 69061,142203\ + 71671,150468 74281,158733 81067,166911 84373,169042\ + 87679,171174 93835,171446 97054,171620 +A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;" +L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/" +S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500 +W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\ + 57686,214631 75382,223396 84426,228258 +L 259 260 0 TEXT "Labels" | 83376,219744 1 0 0 "SIERxTimeOutEn" +I 260 0 2 Builtin OutPort | 77376,219744 "" "" +END

getpacket.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: softransmit.asf =================================================================== --- softransmit.asf (nonexistent) +++ softransmit.asf (revision 40) @@ -0,0 +1,110 @@ +VERSION=1.15 +HEADER +FILE="softransmit.asf" +FID=405c2645 +LANGUAGE=VERILOG +ENTITY="SOFTransmit" +FRAMES=ON +FREEOID=95 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// softransmit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbHostControl_h.v\"\n\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +OBJECTS +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit" +F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561 +L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx" +L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/" +S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500 +L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/" +S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500 +L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/" +S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500 +L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/" +S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500 +I 31 0 130 Builtin InPort | 86106,205240 "" "" +L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]" +I 16 6 0 Builtin Reset | 76112,190530 +W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516 +W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\ + 119442,151760 119430,151725 119430,151571 +W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303 +W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583 +C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)" +C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1" +L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/" +S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500 +W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429 +C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME" +A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;" +I 47 0 2 Builtin OutPort | 83987,210042 "" "" +L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr" +A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;" +K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse" +I 41 0 2 Builtin OutPort | 83735,214646 "" "" +L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent" +L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn" +I 34 0 2 Builtin InPort | 85672,219426 "" "" +L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn" +I 32 0 2 Builtin OutPort | 29866,205279 "" "" +L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq" +I 62 0 2 Builtin OutPort | 29880,214737 "" "" +L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable" +I 60 0 2 Builtin InPort | 85642,229951 "" "" +L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy" +I 58 0 2 Builtin InPort | 32035,210006 "" "" +L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst" +I 56 0 130 Builtin InPort | 200475,245251 "" "" +C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst" +I 54 0 1 Builtin InPort | 200335,250729 "" "" +L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk" +A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;" +K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse" +S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500 +L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/" +A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;" +C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0" +W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\ + 105450,47318 105450,38252 107207,34228 108965,30205\ + 115846,23167 119361,19652 +A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;" +L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt" +I 64 0 2 Builtin InPort | 32202,219273 "" "" +K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn" +L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/" +S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500 +W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\ + 70296,21816 59880,36936 57948,44622 56016,52308\ + 59778,66554 61122,74366 +A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;" +C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff" +A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;" +W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345 +A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;" +C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff" +A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;" +I 87 0 130 Builtin Signal | 47362,241979 "" "" +L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]" +C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1" +W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302 +END

softransmit.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: speedCtrlMux.v =================================================================== --- speedCtrlMux.v (nonexistent) +++ speedCtrlMux.v (revision 40) @@ -0,0 +1,78 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// speedCtrlMux.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol); +input directCtrlRate; +input directCtrlPol; +input sendPacketRate; +input sendPacketPol; +input sendPacketSel; +output fullSpeedRate; +output fullSpeedPol; + +wire directCtrlRate; +wire directCtrlPol; +wire sendPacketRate; +wire sendPacketPol; +wire sendPacketSel; +reg fullSpeedRate; +reg fullSpeedPol; + + +always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel) +begin + if (sendPacketSel == 1'b1) + begin + fullSpeedRate <= sendPacketRate; + fullSpeedPol <= sendPacketPol; + end + else + begin + fullSpeedRate <= directCtrlRate; + fullSpeedPol <= directCtrlPol; + end +end + +endmodule

speedCtrlMux.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: directcontrol.asf =================================================================== --- directcontrol.asf (nonexistent) +++ directcontrol.asf (revision 40) @@ -0,0 +1,133 @@ +VERSION=1.15 +HEADER +FILE="directcontrol.asf" +FID=406ac3b6 +LANGUAGE=VERILOG +ENTITY="directControl" +FRAMES=ON +FREEOID=180 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// directControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 12700,12700 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 78 +PAGE 12700,12700 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 127 +PAGE 12700,12700 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk" +W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491 +I 13 6 0 Builtin Reset | 48900,215400 +S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500 +L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/" +S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500 +L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/" +L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl" +F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700 +A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION" +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: directControl" +C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1" +W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487 +W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666 +I 21 0 2 Builtin InPort | 57252,239123 "" "" +L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn" +C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst" +I 18 0 2 Builtin InPort | 181500,257400 "" "" +L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst" +I 16 0 3 Builtin InPort | 181300,263800 "" "" +W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309 +H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500 +L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL" +W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167 +A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "HCTxPortWEn <= 1'b0;" +S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500 +W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\ + 46421,89345 46021,97345 47471,100295 48921,103245\ + 55748,105011 58848,106911 +L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/" +S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500 +W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775 +L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/" +S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500 +C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "HCTxPortGnt == 1'b1" +W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413 +L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/" +C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1" +A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;" +S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500 +L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE" +W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\ + 47285,153175 50048,167625 56316,171290 62585,174956\ + 84856,175714 96012,175820 +I 124 79 0 Builtin Entry | 109800,175900 +I 122 79 0 Builtin Exit | 138103,36586 +S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500 +A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;" +A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;" +C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1" +W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465 +L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/" +S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500 +C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1" +W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914 +H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn" +I 158 0 2 Builtin OutPort | 109163,245109 "" "" +L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]" +I 156 0 130 Builtin OutPort | 109440,251139 "" "" +L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]" +I 154 0 130 Builtin OutPort | 108837,257571 "" "" +W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\ + 171826,160150 159742,169266 150997,171704 142252,174142\ + 120424,175336 108976,175654 +I 151 128 0 Builtin Exit | 67380,61048 +I 150 128 0 Builtin Entry | 67068,204814 +A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;" +L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/" +S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500 +W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309 +L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/" +W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048 +A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;" +A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;" +L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq" +I 164 0 2 Builtin OutPort | 160587,239893 "" "" +L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt" +I 162 0 2 Builtin InPort | 162999,244717 "" "" +L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy" +I 160 0 2 Builtin InPort | 111543,239893 "" "" +W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586 +C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0" +A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;" +L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]" +I 179 0 130 Builtin InPort | 57352,249414 "" "" +END

directcontrol.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sendpacket.asf =================================================================== --- sendpacket.asf (nonexistent) +++ sendpacket.asf (revision 40) @@ -0,0 +1,285 @@ +VERSION=1.15 +HEADER +FILE="sendpacket.asf" +FID=405e9201 +LANGUAGE=VERILOG +ENTITY="sendPacket" +FRAMES=ON +FREEOID=260 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 21 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 41 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 43 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 45 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 227 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 236 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/" +W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778 +W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392 +I 12 6 0 Builtin Reset | 74872,202290 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket" +A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n PIDNotPID <= { (PID ^ 4'hf), PID };\nend" +F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064 +L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt" +L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/" +S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500 +L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/" +S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500 +W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821 +I 29 25 0 Builtin Exit | 144780,121920 +I 28 25 0 Builtin Entry | 48013,256695 +L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/" +S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500 +H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +C 23 22 0 TEXT "Conditions" | 129137,121283 1 0 0 "HCTxPortGnt == 1'b1" +W 22 6 0 16 227 BEZIER "Transitions" | 115535,117920 120401,115274 154207,112243 162751,111806 +S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500 +L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID" +A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;" +C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1" +W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145 +S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500 +S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500 +L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/" +S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500 +L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1" +S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500 +L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF" +S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500 +L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP" +W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920 +A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;" +A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;" +C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1" +W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803 +S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500 +L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/" +H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284 +H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210 +W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203 +W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081 +C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP" +A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;" +W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\ + 84500,7962 56262,8416 48108,10114 39955,11813\ + 35575,18155 34480,31669 33386,45184 33386,92900\ + 35198,110038 37010,127177 44258,148015 49996,153300\ + 55734,158585 71438,158887 78535,158887 85632,158887\ + 97934,159370 104276,159219 +W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888 +W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311 +W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379 +H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688 +L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/" +C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1" +A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;" +W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351 +S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500 +L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/" +S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500 +I 84 51 0 Builtin Entry | 48374,241112 +I 83 51 0 Builtin Exit | 161275,73621 +W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006 +C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1" +C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF" +S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500 +L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/" +W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541 +C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1" +A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;" +A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;" +W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621 +S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500 +W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173 +I 110 58 0 Builtin Exit | 176204,35771 +I 111 58 0 Builtin Entry | 69864,225148 +S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500 +L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/" +S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500 +W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609 +A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;" +C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1" +L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/" +W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771 +A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;" +W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691 +A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;" +C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1" +L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/" +I 126 65 0 Builtin Entry | 68558,236856 +I 127 65 0 Builtin Exit | 176933,37229 +W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388 +S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500 +L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/" +W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714 +C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1" +A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;" +A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;" +S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500 +L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/" +L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/" +S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500 +W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614 +C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0" +S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500 +L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/" +W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531 +C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1" +A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;" +A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;" +S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500 +L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/" +W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\ + 57625,199045 54697,174705 54514,164091 54331,153478\ + 57228,135338 58326,126280 +W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\ + 139792,40658 161594,38692 165369,38074 169145,37457\ + 170179,37688 173765,37229 +L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty" +I 164 0 2 Builtin InPort | 101978,225284 "" "" +I 165 0 130 Builtin InPort | 102007,220336 "" "" +L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]" +L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn" +I 168 0 2 Builtin OutPort | 99800,215222 "" "" +L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn" +I 170 0 2 Builtin InPort | 35414,224168 "" "" +I 171 0 2 Builtin OutPort | 33427,218968 "" "" +L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy" +I 173 0 130 Builtin InPort | 35299,213676 "" "" +L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]" +I 175 0 2 Builtin OutPort | 155450,237706 "" "" +L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq" +I 177 0 2 Builtin InPort | 157583,232918 "" "" +L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt" +L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn" +I 180 0 2 Builtin OutPort | 155564,228002 "" "" +I 181 0 2 Builtin InPort | 158231,223036 "" "" +L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy" +I 183 0 130 Builtin OutPort | 156035,218266 "" "" +L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]" +I 185 0 130 Builtin OutPort | 156179,213226 "" "" +L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]" +L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk" +I 188 0 3 Builtin InPort | 198206,245948 "" "" +I 189 0 2 Builtin InPort | 198532,251890 "" "" +L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst" +C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst" +I 195 0 128 Builtin Signal | 35000,231468 "" "" +L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]" +A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;" +L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]" +I 199 0 130 Builtin InPort | 101972,241240 "" "" +L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]" +I 201 0 130 Builtin InPort | 101760,245904 "" "" +L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]" +I 203 0 130 Builtin OutPort | 102204,236768 "" "" +W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\ + 48213,88528 42471,75064 41184,67490 39897,59917\ + 40491,43087 47668,36800 54846,30514 82962,22198\ + 91674,19921 100386,17644 105983,17263 109349,16867 +L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/" +W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\ + 200128,135446 205472,144130 205681,151728 205890,159327\ + 201380,181037 194241,189595 187102,198154 163054,210680\ + 152909,214312 142764,217944 127179,220153 118913,221155 +W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933 +A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;" +S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500 +L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/" +S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500 +W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561 +A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;" +L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/" +S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500 +W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658 +A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;" +L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/" +S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500 +A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;" +W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976 +H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700 +S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500 +L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1" +I 230 229 0 Builtin Entry | 86360,167640 +I 231 229 0 Builtin Exit | 129540,111760 +W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760 +L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity" +I 234 0 2 Builtin InPort | 156660,245408 "" "" +L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP" +S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500 +W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764 +W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467 +W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\ + 202640,35412 197280,23183 191376,19540 185472,15898\ + 167213,13552 158043,13342 148873,13133 131482,15160\ + 122270,15913 +C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0" +H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500 +L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/" +I 250 241 0 Builtin Entry | 60577,248468 +I 251 241 0 Builtin Exit | 157344,113693 +W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594 +S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500 +L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/" +W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576 +C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1" +A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;" +A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;" +W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693 +END

sendpacket.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usbHostControl.v =================================================================== --- usbHostControl.v (nonexistent) +++ usbHostControl.v (revision 40) @@ -0,0 +1,397 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbHostControl.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module usbHostControl( + busClk, rstSyncToBusClk, + usbClk, rstSyncToUsbClk, + //sendPacket + TxFifoRE, TxFifoData, TxFifoEmpty, + //getPacket + RxFifoWE, RxFifoData, RxFifoFull, + RxByteStatus, RxData, RxDataValid, + SIERxTimeOut, SIERxTimeOutEn, + //speedCtrlMux + fullSpeedRate, fullSpeedPol, + //HCTxPortArbiter + HCTxPortEn, HCTxPortRdy, + HCTxPortData, HCTxPortCtrl, + //rxStatusMonitor + connectStateIn, + resumeDetectedIn, + //USBHostControlBI + busAddress, + busDataIn, + busDataOut, + busWriteEn, + busStrobe_i, + SOFSentIntOut, + connEventIntOut, + resumeIntOut, + transDoneIntOut, + hostControlSelect + ); + +input busClk; +input rstSyncToBusClk; +input usbClk; +input rstSyncToUsbClk; +//sendPacket +output TxFifoRE; +input [7:0] TxFifoData; +input TxFifoEmpty; +//getPacket +output RxFifoWE; +output [7:0] RxFifoData; +input RxFifoFull; +input [7:0] RxByteStatus; +input [7:0] RxData; +input RxDataValid; +input SIERxTimeOut; +output SIERxTimeOutEn; +//speedCtrlMux +output fullSpeedRate; +output fullSpeedPol; +//HCTxPortArbiter +output HCTxPortEn; +input HCTxPortRdy; +output [7:0] HCTxPortData; +output [7:0] HCTxPortCtrl; +//rxStatusMonitor +input [1:0] connectStateIn; +input resumeDetectedIn; +//USBHostControlBI +input [3:0] busAddress; +input [7:0] busDataIn; +output [7:0] busDataOut; +input busWriteEn; +input busStrobe_i; +output SOFSentIntOut; +output connEventIntOut; +output resumeIntOut; +output transDoneIntOut; +input hostControlSelect; + +wire busClk; +wire rstSyncToBusClk; +wire usbClk; +wire rstSyncToUsbClk; +wire [10:0] frameNum; +wire SOFSent; +wire TxFifoRE; +wire [7:0] TxFifoData; +wire TxFifoEmpty; +wire RxFifoWE; +wire [7:0] RxFifoData; +wire RxFifoFull; +wire [7:0] RxByteStatus; +wire [7:0] RxData; +wire RxDataValid; +wire SIERxTimeOut; +wire SIERxTimeOutEn; +wire fullSpeedRate; +wire fullSpeedPol; +wire HCTxPortEn; +wire HCTxPortRdy; +wire [7:0] HCTxPortData; +wire [7:0] HCTxPortCtrl; +wire [1:0] connectStateIn; +wire resumeDetectedIn; +wire [3:0] busAddress; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire busWriteEn; +wire busStrobe_i; +wire SOFSentIntOut; +wire connEventIntOut; +wire resumeIntOut; +wire transDoneIntOut; +wire hostControlSelect; + +//internal wiring +wire SOFTimerClr; +wire getPacketREn; +wire getPacketRdy; +wire HCTxGnt; +wire HCTxReq; +wire [3:0] HC_PID; +wire HC_SP_WEn; +wire SOFTxGnt; +wire SOFTxReq; +wire SOF_SP_WEn; +wire SOFEnable; +wire SOFSyncEn; +wire sendPacketCPReadyIn; +wire sendPacketCPReadyOut; +wire [3:0] sendPacketCPPIDIn; +wire [3:0] sendPacketCPPIDOut; +wire sendPacketCPWEnIn; +wire sendPacketCPWEnOut; +wire [7:0] SOFCntlCntl; +wire [7:0] SOFCntlData; +wire SOFCntlGnt; +wire SOFCntlReq; +wire SOFCntlWEn; +wire [7:0] directCntlCntl; +wire [7:0] directCntlData; +wire directCntlGnt; +wire directCntlReq; +wire directCntlWEn; +wire [7:0] sendPacketCntl; +wire [7:0] sendPacketData; +wire sendPacketGnt; +wire sendPacketReq; +wire sendPacketWEn; +wire [15:0] SOFTimer; +wire clrTxReq; +wire transDone; +wire transReq; +wire isoEn; +wire [1:0] transType; +wire preAmbleEnable; +wire [1:0] directLineState; +wire directLineCtrlEn; +wire [6:0] TxAddr; +wire [3:0] TxEndP; +wire [7:0] RxPktStatus; +wire [3:0] RxPID; +wire [1:0] connectStateOut; +wire resumeIntFromRxStatusMon; +wire connectionEventFromRxStatusMon; + +USBHostControlBI u_USBHostControlBI + (.address(busAddress), + .dataIn(busDataIn), + .dataOut(busDataOut), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .rstSyncToBusClk(rstSyncToBusClk), + .usbClk(usbClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .SOFSentIntOut(SOFSentIntOut), + .connEventIntOut(connEventIntOut), + .resumeIntOut(resumeIntOut), + .transDoneIntOut(transDoneIntOut), + .TxTransTypeReg(transType), + .TxSOFEnableReg(SOFEnable), + .TxAddrReg(TxAddr), + .TxEndPReg(TxEndP), + .frameNumIn(frameNum), + .RxPktStatusIn(RxPktStatus), + .RxPIDIn(RxPID), + .connectStateIn(connectStateOut), + .SOFSentIn(SOFSent), + .connEventIn(connectionEventFromRxStatusMon), + .resumeIntIn(resumeIntFromRxStatusMon), + .transDoneIn(transDone), + .hostControlSelect(hostControlSelect), + .clrTransReq(clrTxReq), + .preambleEn(preAmbleEnable), + .SOFSync(SOFSyncEn), + .TxLineState(directLineState), + .LineDirectControlEn(directLineCtrlEn), + .fullSpeedPol(fullSpeedPol), + .fullSpeedRate(fullSpeedRate), + .transReq(transReq), + .isoEn(isoEn), + .SOFTimer(SOFTimer) + ); + + +hostcontroller u_hostController + (.RXStatus(RxPktStatus), + .clearTXReq(clrTxReq), + .clk(usbClk), + .getPacketREn(getPacketREn), + .getPacketRdy(getPacketRdy), + .rst(rstSyncToUsbClk), + .sendPacketArbiterGnt(HCTxGnt), + .sendPacketArbiterReq(HCTxReq), + .sendPacketPID(HC_PID), + .sendPacketRdy(sendPacketCPReadyOut), + .sendPacketWEn(HC_SP_WEn), + .transDone(transDone), + .transReq(transReq), + .transType(transType), + .isoEn(isoEn) ); + +SOFController u_SOFController + (.HCTxPortCntl(SOFCntlCntl), + .HCTxPortData(SOFCntlData), + .HCTxPortGnt(SOFCntlGnt), + .HCTxPortRdy(HCTxPortRdy), + .HCTxPortReq(SOFCntlReq), + .HCTxPortWEn(SOFCntlWEn), + .SOFEnable(SOFEnable), + .SOFTimerClr(SOFTimerClr), + .SOFTimer(SOFTimer), + .clk(usbClk), + .rst(rstSyncToUsbClk) ); + +SOFTransmit u_SOFTransmit + (.SOFEnable(SOFEnable), + .SOFSent(SOFSent), + .SOFSyncEn(SOFSyncEn), + .SOFTimerClr(SOFTimerClr), + .SOFTimer(SOFTimer), + .clk(usbClk), + .rst(rstSyncToUsbClk), + .sendPacketArbiterGnt(SOFTxGnt), + .sendPacketArbiterReq(SOFTxReq), + .sendPacketRdy(sendPacketCPReadyOut), + .sendPacketWEn(SOF_SP_WEn) ); + + +sendPacketArbiter u_sendPacketArbiter + (.HCTxGnt(HCTxGnt), + .HCTxReq(HCTxReq), + .HC_PID(HC_PID), + .HC_SP_WEn(HC_SP_WEn), + .SOFTxGnt(SOFTxGnt), + .SOFTxReq(SOFTxReq), + .SOF_SP_WEn(SOF_SP_WEn), + .clk(usbClk), + .rst(rstSyncToUsbClk), + .sendPacketPID(sendPacketCPPIDIn), + .sendPacketWEnable(sendPacketCPWEnIn) ); + +sendPacketCheckPreamble u_sendPacketCheckPreamble + (.sendPacketCPPID(sendPacketCPPIDIn), + .clk(usbClk), + .preAmbleEnable(preAmbleEnable), + .rst(rstSyncToUsbClk), + .sendPacketCPReady(sendPacketCPReadyOut), + .sendPacketCPWEn(sendPacketCPWEnIn), + .sendPacketPID(sendPacketCPPIDOut), + .sendPacketRdy(sendPacketCPReadyIn), + .sendPacketWEn(sendPacketCPWEnOut) ); + +sendPacket u_sendPacket + (.HCTxPortCntl(sendPacketCntl), + .HCTxPortData(sendPacketData), + .HCTxPortGnt(sendPacketGnt), + .HCTxPortRdy(HCTxPortRdy), + .HCTxPortReq(sendPacketReq), + .HCTxPortWEn(sendPacketWEn), + .PID(sendPacketCPPIDOut), + .TxAddr(TxAddr), + .TxEndP(TxEndP), + .clk(usbClk), + .fifoData(TxFifoData), + .fifoEmpty(TxFifoEmpty), + .fifoReadEn(TxFifoRE), + .frameNum(frameNum), + .rst(rstSyncToUsbClk), + .sendPacketRdy(sendPacketCPReadyIn), + .sendPacketWEn(sendPacketCPWEnOut), + .fullSpeedPolarity(fullSpeedPol) ); + +directControl u_directControl + (.HCTxPortCntl(directCntlCntl), + .HCTxPortData(directCntlData), + .HCTxPortGnt(directCntlGnt), + .HCTxPortRdy(HCTxPortRdy), + .HCTxPortReq(directCntlReq), + .HCTxPortWEn(directCntlWEn), + .clk(usbClk), + .directControlEn(directLineCtrlEn), + .directControlLineState(directLineState), + .rst(rstSyncToUsbClk) ); + +HCTxPortArbiter u_HCTxPortArbiter + (.HCTxPortCntl(HCTxPortCtrl), + .HCTxPortData(HCTxPortData), + .HCTxPortWEnable(HCTxPortEn), + .SOFCntlCntl(SOFCntlCntl), + .SOFCntlData(SOFCntlData), + .SOFCntlGnt(SOFCntlGnt), + .SOFCntlReq(SOFCntlReq), + .SOFCntlWEn(SOFCntlWEn), + .clk(usbClk), + .directCntlCntl(directCntlCntl), + .directCntlData(directCntlData), + .directCntlGnt(directCntlGnt), + .directCntlReq(directCntlReq), + .directCntlWEn(directCntlWEn), + .rst(rstSyncToUsbClk), + .sendPacketCntl(sendPacketCntl), + .sendPacketData(sendPacketData), + .sendPacketGnt(sendPacketGnt), + .sendPacketReq(sendPacketReq), + .sendPacketWEn(sendPacketWEn) ); + +getPacket u_getPacket + (.RXDataIn(RxData), + .RXDataValid(RxDataValid), + .RXFifoData(RxFifoData), + .RXFifoFull(RxFifoFull), + .RXFifoWEn(RxFifoWE), + .RXPacketRdy(getPacketRdy), + .RXPktStatus(RxPktStatus), + .RXStreamStatusIn(RxByteStatus), + .RxPID(RxPID), + .SIERxTimeOut(SIERxTimeOut), + .SIERxTimeOutEn(SIERxTimeOutEn), + .clk(usbClk), + .getPacketEn(getPacketREn), + .rst(rstSyncToUsbClk) ); + +rxStatusMonitor u_rxStatusMonitor + (.connectStateIn(connectStateIn), + .connectStateOut(connectStateOut), + .resumeDetectedIn(resumeDetectedIn), + .connectionEventOut(connectionEventFromRxStatusMon), + .resumeIntOut(resumeIntFromRxStatusMon), + .clk(usbClk), + .rst(rstSyncToUsbClk) ); + +endmodule + + + + + + +

usbHostControl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hctxportarbiter.asf =================================================================== --- hctxportarbiter.asf (nonexistent) +++ hctxportarbiter.asf (revision 40) @@ -0,0 +1,130 @@ +VERSION=1.15 +HEADER +FILE="hctxportarbiter.asf" +FID=405ea588 +LANGUAGE=VERILOG +ENTITY="HCTxPortArbiter" +FRAMES=ON +FREEOID=101 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hctxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 12700,12700 431800,558800 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +OBJECTS +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter" +F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945 +L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb" +S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500 +L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/" +S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500 +L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/" +S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500 +L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/" +S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500 +L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/" +I 16 6 0 Builtin Reset | 178237,395710 +W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602 +W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531 +W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787 +W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756 +C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1" +C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1" +A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;" +A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;" +A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;" +C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst" +W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\ + 288786,359372 287077,371461 282417,376909 277757,382357\ + 274547,381487 268775,381564 263003,381642 254872,381366\ + 248267,378971 241663,376577 234289,371557 230118,369008 +W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\ + 166944,348155 168507,364217 173450,370590 178394,376963\ + 186275,384997 193806,383684 201338,382371 213515,373400\ + 220004,369229 +A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;" +C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0" +C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0" +A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;" +I 33 0 2 Builtin OutPort | 117425,484940 "" "" +L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt" +I 37 0 2 Builtin OutPort | 164033,485851 "" "" +L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt" +I 39 0 2 Builtin InPort | 197412,542480 "" "" +L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst" +I 41 0 3 Builtin InPort | 197495,536936 "" "" +I 44 0 130 Builtin InPort | 166169,499499 "" "" +L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]" +L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable" +I 35 0 2 Builtin OutPort | 164373,457796 "" "" +I 48 0 2 Builtin InPort | 120008,489821 "" "" +L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn" +I 52 0 2 Builtin InPort | 165981,490639 "" "" +L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn" +A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n `SOF_CTRL_MUX :\n begin \n HCTxPortWEnable <= SOFCntlWEn;\n HCTxPortData <= SOFCntlData;\n HCTxPortCntl <= SOFCntlCntl;\n end\n `DIRECT_CTRL_MUX :\n begin \n HCTxPortWEnable <= directCntlWEn;\n HCTxPortData <= directCntlData;\n HCTxPortCntl <= directCntlCntl;\n end\n `SEND_PACKET_MUX :\n begin \n HCTxPortWEnable <= sendPacketWEn;\n HCTxPortData <= sendPacketData;\n HCTxPortCntl <= sendPacketCntl;\n end\n default :\n begin \n HCTxPortWEnable <= 1'b0;\n HCTxPortData <= 8'h00;\n HCTxPortCntl <= 8'h00;\n end\nendcase \nend" +I 55 0 2 Builtin InPort | 119812,480347 "" "" +I 56 0 2 Builtin InPort | 166286,481063 "" "" +L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq" +L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq" +L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk" +I 62 0 130 Builtin InPort | 166256,495120 "" "" +L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]" +L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]" +I 58 0 130 Builtin OutPort | 164296,453278 "" "" +I 68 0 130 Builtin InPort | 119837,494606 "" "" +L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]" +I 70 0 130 Builtin InPort | 119737,499229 "" "" +L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]" +L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00" +I 73 0 263 Builtin Constant | 141050,542882 "" I "" "" +L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01" +I 75 0 263 Builtin Constant | 141050,538259 "" I "" "" +I 76 0 263 Builtin Constant | 140950,533626 "" I "" "" +L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10" +I 78 0 2 Builtin OutPort | 117944,457060 "" "" +L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt" +L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]" +I 66 0 130 Builtin OutPort | 164124,471556 "" "" +I 80 0 2 Builtin InPort | 120331,452467 "" "" +L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq" +I 82 0 2 Builtin InPort | 120527,461941 "" "" +L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn" +I 84 0 130 Builtin InPort | 120256,471349 "" "" +L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]" +I 86 0 130 Builtin InPort | 120356,466726 "" "" +L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]" +L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]" +I 89 0 130 Builtin Signal | 141050,528812 "" "" +L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/" +S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500 +W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395 +C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1" +A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;" +W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\ + 259846,282068 289467,282068 298484,284234 307501,286400\ + 313949,295065 315460,307759 316972,320453 316568,362568\ + 311430,375060 306292,387553 286404,388600 275724,388298\ + 265045,387996 242215,385739 236069,382112 229924,378486\ + 228216,373858 227209,371138 +C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0" +A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;" +END

hctxportarbiter.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sendpacketcheckpreamble.asf =================================================================== --- sendpacketcheckpreamble.asf (nonexistent) +++ sendpacketcheckpreamble.asf (revision 40) @@ -0,0 +1,146 @@ +VERSION=1.15 +HEADER +FILE="sendpacketcheckpreamble.asf" +FID=4061fc61 +LANGUAGE=VERILOG +ENTITY="sendPacketCheckPreamble" +FRAMES=ON +FREEOID=161 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketcheckpreamble\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 32 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 95 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492 +I 14 6 0 Builtin Reset | 71492,195262 +S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500 +L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/" +S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500 +L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/" +L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP" +F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble" +L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/" +S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500 +L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT" +C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1" +W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411 +C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1" +W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555 +W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497 +L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/" +C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1" +W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564 +S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500 +W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293 +W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634 +I 37 33 0 Builtin Exit | 189069,45293 +I 36 33 0 Builtin Entry | 59261,258101 +H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500 +C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1" +W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786 +L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/" +S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500 +A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;" +W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633 +S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500 +L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/" +L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/" +S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500 +L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/" +S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500 +A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;" +W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872 +C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1" +L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn" +I 85 0 2 Builtin InPort | 31234,242140 "" "" +L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]" +I 87 0 130 Builtin InPort | 31564,247430 "" "" +L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn" +I 91 0 2 Builtin OutPort | 139129,219071 "" "" +L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]" +I 93 0 130 Builtin OutPort | 139050,213623 "" "" +L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT" +S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500 +L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady" +I 89 0 2 Builtin OutPort | 29117,236671 "" "" +W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643 +H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 105 98 0 Builtin Entry | 69392,262686 +I 106 98 0 Builtin Exit | 199200,49878 +W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219 +S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500 +W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149 +C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1" +L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/" +S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500 +L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/" +S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500 +L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/" +W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221 +A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;" +W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878 +A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;" +L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/" +S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500 +A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;" +W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648 +W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858 +W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\ + 94907,51569 61918,50756 52575,52503 43232,54250\ + 38843,62050 37706,72734 36569,83418 36406,118357\ + 40062,129609 43718,140862 58507,150938 67687,153172\ + 76868,155407 98883,155302 109851,154734 +L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk" +I 141 0 3 Builtin InPort | 193053,251257 "" "" +L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst" +I 143 0 2 Builtin InPort | 192551,245909 "" "" +I 151 0 2 Builtin InPort | 34428,222262 "" "" +L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable" +L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy" +I 147 0 2 Builtin InPort | 141295,224322 "" "" +C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst" +A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;" +A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;" +A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;" +A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;" +L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/" +S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500 +L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/" +S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500 +W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011 +W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408 +END

sendpacketcheckpreamble.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sendpacketarbiter.asf =================================================================== --- sendpacketarbiter.asf (nonexistent) +++ sendpacketarbiter.asf (revision 40) @@ -0,0 +1,93 @@ +VERSION=1.15 +HEADER +FILE="sendpacketarbiter.asf" +FID=4053e959 +LANGUAGE=VERILOG +ENTITY="sendPacketArbiter" +FRAMES=ON +FREEOID=98 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendpacketarbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,0 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +OBJECTS +S 15 6 0 ELLIPSE "States" | 172430,18866 6500 6500 +L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "HC_ACT\n/0/" +S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500 +L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/" +S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500 +L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "SARB_WAIT_REQ\n/2/" +S 9 6 12288 ELLIPSE "States" | 128958,117844 6500 6500 +L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_SARB\n/3/" +L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "sendPktArb" +F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: sendPacketArbiter" +A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "HCTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b0;" +C 30 23 0 TEXT "Conditions" | 141765,76523 1 0 0 "HCTxReq == 1'b1" +C 29 24 0 TEXT "Conditions" | 88369,77278 1 0 0 "SOFTxReq == 1'b1" +W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230 +W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261 +W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005 +W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 114611,125692 123896,121919 +I 20 6 0 Builtin Reset | 86247,136033 +A 39 9 2 TEXT "Actions" | 134973,143961 1 0 0 "SOFTxGnt <= 1'b0;\nHCTxGnt <= 1'b0; \nmuxSOFNotHC <= 1'b0;" +A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "SOFTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b1;" +L 40 41 0 TEXT "Labels" | 42274,157869 1 0 0 "HCTxGnt" +I 41 0 2 Builtin OutPort | 36274,157869 "" "" +L 42 43 0 TEXT "Labels" | 168738,158202 1 0 0 "sendPacketWEnable" +I 43 0 2 Builtin OutPort | 162738,158202 "" "" +L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]" +I 45 0 130 Builtin OutPort | 162661,153684 "" "" +L 46 47 0 TEXT "Labels" | 95651,157673 1 0 0 "SOFTxGnt" +I 47 0 2 Builtin OutPort | 89651,157673 "" "" +L 48 49 0 TEXT "Labels" | 98038,153080 1 0 0 "SOFTxReq" +I 49 0 2 Builtin InPort | 92038,153080 "" "" +L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq" +I 51 0 2 Builtin InPort | 38527,153081 "" "" +L 52 53 0 TEXT "Labels" | 44410,162874 1 0 0 "HC_PID[3:0]" +I 53 0 130 Builtin InPort | 38410,162874 "" "" +L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk" +I 59 0 3 Builtin InPort | 200032,246137 "" "" +L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst" +I 61 0 2 Builtin InPort | 199418,251681 "" "" +C 62 21 0 TEXT "Conditions" | 108713,128484 1 0 0 "rst" +W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\ + 200193,83454 202194,93721 199799,97969 197405,102218\ + 189371,107780 182843,108050 176316,108321 158239,103840\ + 151634,101445 145030,99051 137656,94031 133485,91482 +C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0" +A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID) \nbegin\n if (muxSOFNotHC == 1'b1) \n begin\n sendPacketWEnable <= SOF_SP_WEn;\n sendPacketPID <= `SOF;\n end\n else\n begin\n sendPacketWEnable <= HC_SP_WEn;\n sendPacketPID <= HC_PID;\n end\nend" +C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0" +A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;" +W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\ + 70311,70629 71874,86691 76817,93064 81761,99437\ + 89642,107471 97173,106158 104705,104845 116882,95874\ + 123371,91703 +A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;" +I 85 0 2 Builtin InPort | 38222,167883 "" "" +L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn" +I 89 0 2 Builtin InPort | 92234,162554 "" "" +L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn" +L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC" +I 95 0 2 Builtin Signal | 187475,230225 "" "" +END

sendpacketarbiter.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sofcontroller.asf =================================================================== --- sofcontroller.asf (nonexistent) +++ sofcontroller.asf (revision 40) @@ -0,0 +1,93 @@ +VERSION=1.15 +HEADER +FILE="sofcontroller.asf" +FID=407b9607 +LANGUAGE=VERILOG +ENTITY="SOFController" +FRAMES=ON +FREEOID=65 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sofcontroller\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0 +B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0 +B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0 +END +INSTHEADER 1 +PAGE 12700,12700 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +OBJECTS +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController" +F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700 +L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "sofCntl" +L 8 9 0 TEXT "State Labels" | 101706,207040 1 0 0 "START_SC\n/0/" +S 9 6 0 ELLIPSE "States" | 101706,207040 6500 6500 +L 10 11 0 TEXT "State Labels" | 102510,174880 1 0 0 "WAIT_SOF_EN\n/1/" +S 11 6 4096 ELLIPSE "States" | 102510,174880 6500 6500 +W 12 6 0 9 11 BEZIER "Transitions" | 101472,200547 101472,195422 101786,186460 101786,181335 +I 13 6 0 Builtin Reset | 56682,217090 +W 14 6 0 13 9 BEZIER "Transitions" | 56682,217090 66531,215181 85597,210696 95446,208787 +L 15 16 0 TEXT "Labels" | 186096,262516 1 0 0 "clk" +I 16 0 3 Builtin InPort | 180096,262516 "" "" +L 17 18 0 TEXT "Labels" | 185694,255682 1 0 0 "rst" +I 18 0 2 Builtin InPort | 179694,255682 "" "" +C 19 14 0 TEXT "Conditions" | 80380,211899 1 0 0 "rst" +L 20 21 0 TEXT "State Labels" | 104118,144730 1 0 0 "WAIT_SEND_RESUME\n/2/" +S 21 6 8192 ELLIPSE "States" | 104118,144730 6500 6500 +W 22 6 0 11 50 BEZIER "Transitions" | 102807,168391 103209,163969 153274,157911 158500,157308 +L 23 24 0 TEXT "State Labels" | 107147,54820 1 0 0 "INC_TIMER\n/3/" +S 24 6 12288 ELLIPSE "States" | 107147,54820 6500 6500 +W 25 6 0 21 62 BEZIER "Transitions" | 104501,138249 108970,126031 113441,113813 117910,101595 +C 26 22 0 TEXT "Conditions" | 109587,169712 1 0 0 "SOFEnable == 1'b1" +C 27 25 0 TEXT "Conditions" | 106980,134689 1 0 0 "HCTxPortRdy == 1'b1" +A 29 25 16 TEXT "Actions" | 99582,127475 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_RESUME_START;" +A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n SOFTimer <= 16'h0000;\nelse\n SOFTimer <= SOFTimer + 1'b1;" +W 33 6 0 24 11 BEZIER "Transitions" | 101788,58497 95658,55482 71624,73399 68189,77671\ + 64755,81944 65727,99405 63767,113072 61807,126740\ + 62411,169554 65777,180659 69144,191764 82008,193372\ + 86530,192015 91053,190659 96125,183689 98738,180172 +C 35 33 0 TEXT "Conditions" | 56071,65104 1 0 0 "SOFEnable == 1'b0" +L 36 37 0 TEXT "Labels" | 26502,239200 1 0 0 "SOFTimer[15:0]" +I 37 0 130 Builtin OutPort | 20502,239200 "" "" +L 38 39 0 TEXT "Labels" | 28914,244024 1 0 0 "SOFEnable" +I 39 0 2 Builtin InPort | 22914,244024 "" "" +L 40 41 0 TEXT "Labels" | 90018,239200 1 0 0 "HCTxPortRdy" +I 41 0 2 Builtin InPort | 84018,239200 "" "" +I 42 0 2 Builtin OutPort | 81638,244416 "" "" +L 43 42 0 TEXT "Labels" | 87638,244416 1 0 0 "HCTxPortWEn" +I 44 0 130 Builtin OutPort | 81915,250446 "" "" +L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]" +I 46 0 130 Builtin OutPort | 81312,256878 "" "" +L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]" +I 60 0 2 Builtin InPort | 23316,251905 "" "" +L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr" +A 48 9 2 TEXT "Actions" | 121328,217354 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0; \nHCTxPortReq <= 1'b0;" +L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/" +S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500 +W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581 +C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1" +A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;" +A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;" +L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq" +I 56 0 2 Builtin OutPort | 133062,239200 "" "" +L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt" +I 58 0 2 Builtin InPort | 135474,244024 "" "" +L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/" +S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500 +A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;" +W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092 +END

sofcontroller.asf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rxStatusMonitor.v =================================================================== --- rxStatusMonitor.v (nonexistent) +++ rxStatusMonitor.v (revision 40) @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// rxStatusMonitor.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst); + +input [1:0] connectStateIn; +input resumeDetectedIn; +input clk; +input rst; +output connectionEventOut; +output [1:0] connectStateOut; +output resumeIntOut; + +wire [1:0] connectStateIn; +wire resumeDetectedIn; +reg connectionEventOut; +reg [1:0] connectStateOut; +reg resumeIntOut; +wire clk; +wire rst; + +reg [1:0]oldConnectState; +reg oldResumeDetected; + +always @(connectStateIn) +begin + connectStateOut <= connectStateIn; +end + + +always @(posedge clk) +begin + if (rst == 1'b1) + begin + oldConnectState <= connectStateIn; + oldResumeDetected <= resumeDetectedIn; + end + else + begin + oldConnectState <= connectStateIn; + oldResumeDetected <= resumeDetectedIn; + if (oldConnectState != connectStateIn) + connectionEventOut <= 1'b1; + else + connectionEventOut <= 1'b0; + if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0) + resumeIntOut <= 1'b1; + else + resumeIntOut <= 1'b0; + end +end + +endmodule

rxStatusMonitor.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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