URL
https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
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- This comparison shows the changes necessary to convert path
/usbhostslave/trunk/RTL/include
- from Rev 40 to Rev 43
- ↔ Reverse comparison
Rev 40 → Rev 43
/usbSerialInterfaceEngine_h.v
1,108 → 1,109
////////////////////////////////////////////////////////////////////// |
// usbSerialInterfaceEngine_h.v |
////////////////////////////////////////////////////////////////////// |
|
`ifdef usbSerialInterfaceEngine_h_vdefined |
`else |
`define usbSerialInterfaceEngine_h_vdefined |
|
// Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate |
`define FS_OVER_SAMPLE_RATE 4 |
`define LS_OVER_SAMPLE_RATE 32 |
|
//timeOuts |
`define RX_PACKET_TOUT 18 |
`define RX_EDGE_DET_TOUT 7 |
|
//TXStreamControlTypes |
`define TX_DIRECT_CONTROL 8'h00 |
`define TX_RESUME_START 8'h01 |
`define TX_PACKET_START 8'h02 |
`define TX_PACKET_STREAM 8'h03 |
`define TX_PACKET_STOP 8'h04 |
`define TX_IDLE 8'h05 |
`define TX_LS_KEEP_ALIVE 8'h06 |
|
//RXStreamControlTypes |
`define RX_PACKET_START 0 |
`define RX_PACKET_STREAM 1 |
`define RX_PACKET_STOP 2 |
|
//USBLineStates |
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo |
`define ONE_ZERO 2'b10 |
`define ZERO_ONE 2'b01 |
`define SE0 2'b00 |
`define SE1 2'b11 |
|
//RXStatusIndices |
`define CRC_ERROR_BIT 0 |
`define BIT_STUFF_ERROR_BIT 1 |
`define RX_OVERFLOW_BIT 2 |
`define NAK_RXED_BIT 3 |
`define STALL_RXED_BIT 4 |
`define ACK_RXED_BIT 5 |
`define DATA_SEQUENCE_BIT 6 |
|
//usbWireControlStates |
`define TRI_STATE 1'b0 |
`define DRIVE 1'b1 |
|
//limits |
`define MAX_CONSEC_SAME_BITS 4'h6 |
`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7 |
// RESUME_RX_WAIT_TIME defines the time period for resume detection |
// The resume counter is incremented at the bit rate, so |
// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed |
// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of |
// 2.5uS <= resumeDetectTime <= 100uS |
`define RESUME_RX_WAIT_TIME 5'd29 |
//`define RESUME_WAIT_TIME_MINUS1 9 |
// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate |
`ifdef SIM_COMPILE |
`define HOST_TX_RESUME_TIME 16'd10 |
`else |
`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS |
`endif |
//`define CONNECT_WAIT_TIME 8'd20 |
`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS |
//`define DISCONNECT_WAIT_TIME 8'd20 |
`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS |
|
//RXConnectStates |
`define DISCONNECT 2'b00 |
`define LOW_SPEED_CONNECT 2'b01 |
`define FULL_SPEED_CONNECT 2'b10 |
|
//TX_RX_InternalStreamTypes |
`define DATA_START 8'h00 |
`define DATA_STOP 8'h01 |
`define DATA_STREAM 8'h02 |
`define DATA_BIT_STUFF_ERROR 8'h03 |
|
//RXStMach states |
`define DISCONNECT_ST 4'h0 |
`define WAIT_FULL_SPEED_CONN_ST 4'h1 |
`define WAIT_LOW_SPEED_CONN_ST 4'h2 |
`define CONNECT_LOW_SPEED_ST 4'h3 |
`define CONNECT_FULL_SPEED_ST 4'h4 |
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5 |
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6 |
|
//RXBitStateMachStates |
`define IDLE_BIT_ST 2'b00 |
`define DATA_RECEIVE_BIT_ST 2'b01 |
`define WAIT_RESUME_ST 2'b10 |
`define RESUME_END_WAIT_ST 2'b11 |
|
//RXByteStateMachStates |
`define IDLE_BYTE_ST 3'b000 |
`define CHECK_SYNC_ST 3'b001 |
`define CHECK_PID_ST 3'b010 |
`define HS_BYTE_ST 3'b011 |
`define TOKEN_BYTE_ST 3'b100 |
`define DATA_BYTE_ST 3'b101 |
|
`endif //usbSerialInterfaceEngine_h_vdefined |
|
|
////////////////////////////////////////////////////////////////////// |
// usbSerialInterfaceEngine_h.v |
////////////////////////////////////////////////////////////////////// |
|
`ifdef usbSerialInterfaceEngine_h_vdefined |
`else |
`define usbSerialInterfaceEngine_h_vdefined |
|
// Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate |
`define FS_OVER_SAMPLE_RATE 4 |
`define LS_OVER_SAMPLE_RATE 32 |
|
//timeOuts |
`define RX_PACKET_TOUT 18 |
`define RX_EDGE_DET_TOUT 7 |
|
//TXStreamControlTypes |
`define TX_DIRECT_CONTROL 8'h00 |
`define TX_RESUME_START 8'h01 |
`define TX_PACKET_START 8'h02 |
`define TX_PACKET_STREAM 8'h03 |
`define TX_PACKET_STOP 8'h04 |
`define TX_IDLE 8'h05 |
`define TX_LS_KEEP_ALIVE 8'h06 |
|
//RXStreamControlTypes |
`define RX_PACKET_START 0 |
`define RX_PACKET_STREAM 1 |
`define RX_PACKET_STOP 2 |
|
//USBLineStates |
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo |
`define ONE_ZERO 2'b10 |
`define ZERO_ONE 2'b01 |
`define SE0 2'b00 |
`define SE1 2'b11 |
|
//RXStatusIndices |
`define CRC_ERROR_BIT 0 |
`define BIT_STUFF_ERROR_BIT 1 |
`define RX_OVERFLOW_BIT 2 |
`define NAK_RXED_BIT 3 |
`define STALL_RXED_BIT 4 |
`define ACK_RXED_BIT 5 |
`define DATA_SEQUENCE_BIT 6 |
|
//usbWireControlStates |
`define TRI_STATE 1'b0 |
`define DRIVE 1'b1 |
|
//limits |
`define MAX_CONSEC_SAME_BITS 4'h6 |
`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7 |
// RESUME_RX_WAIT_TIME defines the time period for resume detection |
// The resume counter is incremented at the bit rate, so |
// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed |
// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of |
// 2.5uS <= resumeDetectTime <= 100uS |
`define RESUME_RX_WAIT_TIME 5'd29 |
//`define RESUME_WAIT_TIME_MINUS1 9 |
// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate |
`ifdef SIM_COMPILE |
`define HOST_TX_RESUME_TIME 16'd10 |
`else |
`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS |
`endif |
//`define CONNECT_WAIT_TIME 8'd20 |
`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS |
//`define DISCONNECT_WAIT_TIME 8'd20 |
`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS |
|
//RXConnectStates |
`define DISCONNECT 2'b00 |
`define LOW_SPEED_CONNECT 2'b01 |
`define FULL_SPEED_CONNECT 2'b10 |
|
//TX_RX_InternalStreamTypes |
`define DATA_START 8'h00 |
`define DATA_STOP 8'h01 |
`define DATA_STREAM 8'h02 |
`define DATA_BIT_STUFF_ERROR 8'h03 |
`define DATA_STOP_PRE 8'h04 |
|
//RXStMach states |
`define DISCONNECT_ST 4'h0 |
`define WAIT_FULL_SPEED_CONN_ST 4'h1 |
`define WAIT_LOW_SPEED_CONN_ST 4'h2 |
`define CONNECT_LOW_SPEED_ST 4'h3 |
`define CONNECT_FULL_SPEED_ST 4'h4 |
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5 |
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6 |
|
//RXBitStateMachStates |
`define IDLE_BIT_ST 2'b00 |
`define DATA_RECEIVE_BIT_ST 2'b01 |
`define WAIT_RESUME_ST 2'b10 |
`define RESUME_END_WAIT_ST 2'b11 |
|
//RXByteStateMachStates |
`define IDLE_BYTE_ST 3'b000 |
`define CHECK_SYNC_ST 3'b001 |
`define CHECK_PID_ST 3'b010 |
`define HS_BYTE_ST 3'b011 |
`define TOKEN_BYTE_ST 3'b100 |
`define DATA_BYTE_ST 3'b101 |
|
`endif //usbSerialInterfaceEngine_h_vdefined |
|
|
/usbHostSlave_h.v
1,53 → 1,53
////////////////////////////////////////////////////////////////////// |
// usbHostSlave_h.v |
////////////////////////////////////////////////////////////////////// |
|
`ifdef usbHostSlave_h_vdefined |
`else |
`define usbHostSlave_h_vdefined |
|
// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports |
// control reads and writes to USB flash dongle |
// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect |
// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by |
// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full |
// speed, and TX resume is always low speed. |
// Fixed read clock recovery (readUSBWireData.v) issue which was resulting |
// in missing receive packets. |
// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission) |
// by adding kludged delay to softranmit. This needs to be fixed properly. |
// This version has undergone limited testing |
// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes. |
// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested |
// with uClinux, and is known to work with a full speed USB flash stick. |
// Moving Opencores project status from Beta to done. |
// TODO: Test isochronous mode, and low speed mode using uClinux driver |
// Create a seperate clock domain for the bus interface |
// Add frame period adjustment capability |
// Add compilation flags for slave only and host only versions |
// Create data bus width options beyond 8-bit |
// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock |
// Removed TX and RX fifo status registers, and removed |
// TX fifo data count register. |
// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. |
// Fixed slave mode bug which caused receive fifo to be filled with |
// incoming data when the slave was responding with a NAK, and the |
// data should have been discarded. |
// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut' |
// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever |
// there was no detected activity on the USB data lines. This caused an infrequent |
// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when |
// the higher level state machines are actively looking for receive packets. |
// Modified USB RX data clock recovery, so that data is sampled during the middle |
// of a USB bit period. Fixed a bug which could result in double sampling |
// of USB RX data if clock phase adjustments were required in the middle of a |
// USB packet. |
// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required |
// during migration to ActiveHDL 7.1. Released SystemC test bench. |
// Re-generated .v files using ActiveHDL 7.1 |
// Replaced individual timescale directives with `include "timescale.v |
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to |
// 'usbHostSlaveAvalonWrap' |
////////////////////////////////////////////////////////////////////// |
// usbHostSlave_h.v |
////////////////////////////////////////////////////////////////////// |
|
`ifdef usbHostSlave_h_vdefined |
`else |
`define usbHostSlave_h_vdefined |
|
// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports |
// control reads and writes to USB flash dongle |
// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect |
// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by |
// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full |
// speed, and TX resume is always low speed. |
// Fixed read clock recovery (readUSBWireData.v) issue which was resulting |
// in missing receive packets. |
// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission) |
// by adding kludged delay to softranmit. This needs to be fixed properly. |
// This version has undergone limited testing |
// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes. |
// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested |
// with uClinux, and is known to work with a full speed USB flash stick. |
// Moving Opencores project status from Beta to done. |
// TODO: Test isochronous mode, and low speed mode using uClinux driver |
// Create a seperate clock domain for the bus interface |
// Add frame period adjustment capability |
// Add compilation flags for slave only and host only versions |
// Create data bus width options beyond 8-bit |
// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock |
// Removed TX and RX fifo status registers, and removed |
// TX fifo data count register. |
// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. |
// Fixed slave mode bug which caused receive fifo to be filled with |
// incoming data when the slave was responding with a NAK, and the |
// data should have been discarded. |
// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut' |
// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever |
// there was no detected activity on the USB data lines. This caused an infrequent |
// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when |
// the higher level state machines are actively looking for receive packets. |
// Modified USB RX data clock recovery, so that data is sampled during the middle |
// of a USB bit period. Fixed a bug which could result in double sampling |
// of USB RX data if clock phase adjustments were required in the middle of a |
// USB packet. |
// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required |
// during migration to ActiveHDL 7.1. Released SystemC test bench. |
// Re-generated .v files using ActiveHDL 7.1 |
// Replaced individual timescale directives with `include "timescale.v |
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to |
// 'usbHostSlaveAvalonWrap' |
// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added |
// synchronizer to incoming USB wire data to avoid |
// metastability, and delay hazards. Not entirely sure, but it appears that |
66,15 → 66,22
// Modified cross-clock synchronisation of fifo resets |
// Added usbDevice, a standalone usb device implementation of usbhostslave |
// no additional hardware or software required |
|
|
// Most significant nibble corresponds to major revision. |
// Least significant nibble corresponds to minor revision. |
`define USBHOSTSLAVE_VERSION_NUM 8'h20 |
|
//Host slave common registers |
`define HOST_SLAVE_CONTROL_REG 1'b0 |
`define HOST_SLAVE_VERSION_REG 1'b1 |
|
`endif //usbHostSlave_h_vdefined |
|
// Version 2.1 - October 8th 2010. Fixed issues related to accessing low speed device via hub. |
// Changed USB PHY 'USBFullSpeed' edge rate control pin so that it is wired to |
// 'fullSpeedPolarityToSIE', rather than 'fullSpeedBitRateToSIE'. |
// Introduced delay into 'fullSpeedRate' in module writeUSBWireData.v. Thus matching |
// data delay with control delay. |
// Created new control flow constant DATA_STOP_PRE. This allows PREAMBLE PID to completed |
// without SEO (EOP), and ensures line state is left at state J. |
// Prevented PREAMBLE PID from preceding SOF when PREAMBLE is enabled. |
|
// Most significant nibble corresponds to major revision. |
// Least significant nibble corresponds to minor revision. |
`define USBHOSTSLAVE_VERSION_NUM 8'h21 |
|
//Host slave common registers |
`define HOST_SLAVE_CONTROL_REG 1'b0 |
`define HOST_SLAVE_VERSION_REG 1'b1 |
|
`endif //usbHostSlave_h_vdefined |
|