URL
https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
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/usbhostslave/trunk/RTL/slaveController
- from Rev 37 to Rev 40
- ↔ Reverse comparison
Rev 37 → Rev 40
/slaveSendpacket.v
0,0 → 1,252
|
// File : ../RTL/slaveController/slaveSendpacket.v |
// Generated : 11/10/06 05:37:26 |
// From : ../RTL/slaveController/slaveSendpacket.asf |
// By : FSM2VHDL ver. 5.0.0.9 |
|
////////////////////////////////////////////////////////////////////// |
//// //// |
//// slaveSendPacket |
//// //// |
//// This file is part of the usbhostslave opencores effort. |
//// http://www.opencores.org/cores/usbhostslave/ //// |
//// //// |
//// Module Description: //// |
//// |
//// //// |
//// To Do: //// |
//// |
//// //// |
//// Author(s): //// |
//// - Steve Fielding, sfielding@base2designs.com //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// |
`include "timescale.v" |
`include "usbSerialInterfaceEngine_h.v" |
`include "usbConstants_h.v" |
|
module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn); |
input [3:0] PID; |
input SCTxPortGnt; |
input SCTxPortRdy; |
input clk; |
input [7:0] fifoData; |
input fifoEmpty; |
input rst; |
input sendPacketWEn; |
output [7:0] SCTxPortCntl; |
output [7:0] SCTxPortData; |
output SCTxPortReq; |
output SCTxPortWEn; |
output fifoReadEn; |
output sendPacketRdy; |
|
wire [3:0] PID; |
reg [7:0] SCTxPortCntl, next_SCTxPortCntl; |
reg [7:0] SCTxPortData, next_SCTxPortData; |
wire SCTxPortGnt; |
wire SCTxPortRdy; |
reg SCTxPortReq, next_SCTxPortReq; |
reg SCTxPortWEn, next_SCTxPortWEn; |
wire clk; |
wire [7:0] fifoData; |
wire fifoEmpty; |
reg fifoReadEn, next_fifoReadEn; |
wire rst; |
reg sendPacketRdy, next_sendPacketRdy; |
wire sendPacketWEn; |
|
// diagram signals declarations |
reg [7:0]PIDNotPID; |
|
// BINARY ENCODED state machine: slvSndPkt |
// State codes definitions: |
`define START_SP1 4'b0000 |
`define SP_WAIT_ENABLE 4'b0001 |
`define SP1_WAIT_GNT 4'b0010 |
`define SP_SEND_PID_WAIT_RDY 4'b0011 |
`define SP_SEND_PID_FIN 4'b0100 |
`define FIN_SP1 4'b0101 |
`define SP_D0_D1_READ_FIFO 4'b0110 |
`define SP_D0_D1_WAIT_READ_FIFO 4'b0111 |
`define SP_D0_D1_FIFO_EMPTY 4'b1000 |
`define SP_D0_D1_FIN 4'b1001 |
`define SP_D0_D1_TERM_BYTE 4'b1010 |
`define SP_NOT_DATA 4'b1011 |
`define SP_D0_D1_CLR_WEN 4'b1100 |
`define SP_D0_D1_CLR_REN 4'b1101 |
|
reg [3:0] CurrState_slvSndPkt; |
reg [3:0] NextState_slvSndPkt; |
|
// Diagram actions (continuous assignments allowed only: assign ...) |
|
always @(PID) |
begin |
PIDNotPID <= { (PID ^ 4'hf), PID }; |
end |
|
//-------------------------------------------------------------------- |
// Machine: slvSndPkt |
//-------------------------------------------------------------------- |
//---------------------------------- |
// Next State Logic (combinatorial) |
//---------------------------------- |
always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt) |
begin : slvSndPkt_NextState |
NextState_slvSndPkt <= CurrState_slvSndPkt; |
// Set default values for outputs and signals |
next_sendPacketRdy <= sendPacketRdy; |
next_SCTxPortReq <= SCTxPortReq; |
next_SCTxPortWEn <= SCTxPortWEn; |
next_SCTxPortData <= SCTxPortData; |
next_SCTxPortCntl <= SCTxPortCntl; |
next_fifoReadEn <= fifoReadEn; |
case (CurrState_slvSndPkt) |
`START_SP1: |
NextState_slvSndPkt <= `SP_WAIT_ENABLE; |
`SP_WAIT_ENABLE: |
if (sendPacketWEn == 1'b1) |
begin |
NextState_slvSndPkt <= `SP1_WAIT_GNT; |
next_sendPacketRdy <= 1'b0; |
next_SCTxPortReq <= 1'b1; |
end |
`SP1_WAIT_GNT: |
if (SCTxPortGnt == 1'b1) |
NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY; |
`FIN_SP1: |
begin |
NextState_slvSndPkt <= `SP_WAIT_ENABLE; |
next_sendPacketRdy <= 1'b1; |
next_SCTxPortReq <= 1'b0; |
end |
`SP_NOT_DATA: |
NextState_slvSndPkt <= `FIN_SP1; |
`SP_SEND_PID_WAIT_RDY: |
if (SCTxPortRdy == 1'b1) |
begin |
NextState_slvSndPkt <= `SP_SEND_PID_FIN; |
next_SCTxPortWEn <= 1'b1; |
next_SCTxPortData <= PIDNotPID; |
next_SCTxPortCntl <= `TX_PACKET_START; |
end |
`SP_SEND_PID_FIN: |
begin |
next_SCTxPortWEn <= 1'b0; |
if (PID == `DATA0 || PID == `DATA1) |
NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY; |
else |
NextState_slvSndPkt <= `SP_NOT_DATA; |
end |
`SP_D0_D1_READ_FIFO: |
begin |
next_SCTxPortWEn <= 1'b1; |
next_SCTxPortData <= fifoData; |
next_SCTxPortCntl <= `TX_PACKET_STREAM; |
NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN; |
end |
`SP_D0_D1_WAIT_READ_FIFO: |
if (SCTxPortRdy == 1'b1) |
begin |
NextState_slvSndPkt <= `SP_D0_D1_CLR_REN; |
next_fifoReadEn <= 1'b1; |
end |
`SP_D0_D1_FIFO_EMPTY: |
if (fifoEmpty == 1'b0) |
NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO; |
else |
NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE; |
`SP_D0_D1_FIN: |
begin |
next_SCTxPortWEn <= 1'b0; |
NextState_slvSndPkt <= `FIN_SP1; |
end |
`SP_D0_D1_TERM_BYTE: |
if (SCTxPortRdy == 1'b1) |
begin |
NextState_slvSndPkt <= `SP_D0_D1_FIN; |
//Last byte is not valid data, |
//but the 'TX_PACKET_STOP' flag is required |
//by the SIE state machine to detect end of data packet |
next_SCTxPortWEn <= 1'b1; |
next_SCTxPortData <= 8'h00; |
next_SCTxPortCntl <= `TX_PACKET_STOP; |
end |
`SP_D0_D1_CLR_WEN: |
begin |
next_SCTxPortWEn <= 1'b0; |
NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY; |
end |
`SP_D0_D1_CLR_REN: |
begin |
next_fifoReadEn <= 1'b0; |
NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO; |
end |
endcase |
end |
|
//---------------------------------- |
// Current State Logic (sequential) |
//---------------------------------- |
always @ (posedge clk) |
begin : slvSndPkt_CurrentState |
if (rst) |
CurrState_slvSndPkt <= `START_SP1; |
else |
CurrState_slvSndPkt <= NextState_slvSndPkt; |
end |
|
//---------------------------------- |
// Registered outputs logic |
//---------------------------------- |
always @ (posedge clk) |
begin : slvSndPkt_RegOutput |
if (rst) |
begin |
sendPacketRdy <= 1'b1; |
SCTxPortReq <= 1'b0; |
SCTxPortWEn <= 1'b0; |
SCTxPortData <= 8'h00; |
SCTxPortCntl <= 8'h00; |
fifoReadEn <= 1'b0; |
end |
else |
begin |
sendPacketRdy <= next_sendPacketRdy; |
SCTxPortReq <= next_SCTxPortReq; |
SCTxPortWEn <= next_SCTxPortWEn; |
SCTxPortData <= next_SCTxPortData; |
SCTxPortCntl <= next_SCTxPortCntl; |
fifoReadEn <= next_fifoReadEn; |
end |
end |
|
endmodule |
slaveSendpacket.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slavecontroller.v
===================================================================
--- slavecontroller.v (nonexistent)
+++ slavecontroller.v (revision 40)
@@ -0,0 +1,475 @@
+
+// File : ../RTL/slaveController/slavecontroller.v
+// Generated : 11/10/06 05:37:25
+// From : ../RTL/slaveController/slavecontroller.asf
+// By : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveController
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);
+input CRCError;
+input [7:0] RxByte;
+input RxDataWEn;
+input RxOverflow;
+input [7:0] RxStatus;
+input RxTimeOut;
+input SCGlobalEn;
+input [4:0] USBEndPControlReg;
+input [6:0] USBTgtAddress;
+input bitStuffError;
+input clk;
+input getPacketRdy;
+input rst;
+input sendPacketRdy;
+output NAKSent;
+output SOFRxed;
+output [1:0] USBEndPNakTransTypeReg;
+output [1:0] USBEndPTransTypeReg;
+output [3:0] USBEndP;
+output clrEPRdy;
+output endPMuxErrorsWEn;
+output endPointReadyToGetPkt;
+output [10:0] frameNum;
+output getPacketREn;
+output [3:0] sendPacketPID;
+output sendPacketWEn;
+output stallSent;
+output transDone;
+
+wire CRCError;
+reg NAKSent, next_NAKSent;
+wire [7:0] RxByte;
+wire RxDataWEn;
+wire RxOverflow;
+wire [7:0] RxStatus;
+wire RxTimeOut;
+wire SCGlobalEn;
+reg SOFRxed, next_SOFRxed;
+wire [4:0] USBEndPControlReg;
+reg [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+reg [3:0] USBEndP, next_USBEndP;
+wire [6:0] USBTgtAddress;
+wire bitStuffError;
+wire clk;
+reg clrEPRdy, next_clrEPRdy;
+reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg [10:0] frameNum, next_frameNum;
+reg getPacketREn, next_getPacketREn;
+wire getPacketRdy;
+wire rst;
+reg [3:0] sendPacketPID, next_sendPacketPID;
+wire sendPacketRdy;
+reg sendPacketWEn, next_sendPacketWEn;
+reg stallSent, next_stallSent;
+reg transDone, next_transDone;
+
+// diagram signals declarations
+reg [7:0]PIDByte, next_PIDByte;
+reg [6:0]USBAddress, next_USBAddress;
+reg [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+reg [7:0]addrEndPTemp, next_addrEndPTemp;
+reg [7:0]endpCRCTemp, next_endpCRCTemp;
+reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0] CurrState_slvCntrl;
+reg [4:0] NextState_slvCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: slvCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or USBEndPControlReg or RxDataWEn or RxStatus or PIDByte or USBEndPControlRegCopy or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or sendPacketWEn or sendPacketPID or USBEndPTransTypeReg or USBEndPNakTransTypeReg or frameNum or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin : slvCntrl_NextState
+ NextState_slvCntrl <= CurrState_slvCntrl;
+ // Set default values for outputs and signals
+ next_stallSent <= stallSent;
+ next_NAKSent <= NAKSent;
+ next_SOFRxed <= SOFRxed;
+ next_PIDByte <= PIDByte;
+ next_transDone <= transDone;
+ next_clrEPRdy <= clrEPRdy;
+ next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+ next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_getPacketREn <= getPacketREn;
+ next_sendPacketWEn <= sendPacketWEn;
+ next_sendPacketPID <= sendPacketPID;
+ next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+ next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+ next_endpCRCTemp <= endpCRCTemp;
+ next_addrEndPTemp <= addrEndPTemp;
+ next_frameNum <= frameNum;
+ next_USBAddress <= USBAddress;
+ next_USBEndP <= USBEndP;
+ next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+ next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+ case (CurrState_slvCntrl)
+ `WAIT_RX1:
+ begin
+ next_stallSent <= 1'b0;
+ next_NAKSent <= 1'b0;
+ next_SOFRxed <= 1'b0;
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_START &&
+ RxByte[1:0] == `TOKEN)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+ next_PIDByte <= RxByte;
+ end
+ end
+ `FIN_SC:
+ begin
+ next_transDone <= 1'b0;
+ next_clrEPRdy <= 1'b0;
+ next_endPMuxErrorsWEn <= 1'b0;
+ NextState_slvCntrl <= `WAIT_RX1;
+ end
+ `CHK_PID:
+ if (PIDByte[3:0] == `SETUP)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if (PIDByte[3:0] == `OUT)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+ next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+ next_getPacketREn <= 1'b1;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ else if (PIDByte[3:0] == `IN)
+ begin
+ NextState_slvCntrl <= `CHK_RDY;
+ next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+ end
+ else
+ NextState_slvCntrl <= `PID_ERROR;
+ `PID_ERROR:
+ NextState_slvCntrl <= `WAIT_RX1;
+ `CHK_RDY:
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_transDone <= 1'b1;
+ next_clrEPRdy <= 1'b1;
+ next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else if (NAKSent == 1'b1)
+ begin
+ NextState_slvCntrl <= `FIN_SC;
+ next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+ next_endPMuxErrorsWEn <= 1'b1;
+ end
+ else
+ NextState_slvCntrl <= `FIN_SC;
+ `SETUP_OUT_CHK:
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `SETUP_OUT_SEND;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `ACK;
+ end
+ `SETUP_OUT_SEND:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ `SETUP_OUT_GET_PKT:
+ begin
+ next_getPacketREn <= 1'b0;
+ if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+ NextState_slvCntrl <= `CHK_RDY;
+ else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+ bitStuffError == 1'b0 &&
+ RxOverflow == 1'b0 &&
+ RxTimeOut == 1'b0))
+ NextState_slvCntrl <= `SETUP_OUT_CHK;
+ else if (getPacketRdy == 1'b1)
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ `IN_NAK_STALL:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ `IN_CHK_RDY:
+ if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `NAK;
+ next_NAKSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `IN_NAK_STALL;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `STALL;
+ next_stallSent <= 1'b1;
+ end
+ else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA0;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_DATA;
+ next_sendPacketWEn <= 1'b1;
+ next_sendPacketPID <= `DATA1;
+ end
+ `IN_RESP_GET_RESP:
+ begin
+ next_getPacketREn <= 1'b0;
+ if (getPacketRdy == 1'b1)
+ NextState_slvCntrl <= `CHK_RDY;
+ end
+ `IN_RESP_DATA:
+ begin
+ next_sendPacketWEn <= 1'b0;
+ if (sendPacketRdy == 1'b1)
+ NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+ end
+ `IN_RESP_CHK_ISO:
+ if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+ NextState_slvCntrl <= `CHK_RDY;
+ else
+ begin
+ NextState_slvCntrl <= `IN_RESP_GET_RESP;
+ next_getPacketREn <= 1'b1;
+ end
+ `START_S1:
+ NextState_slvCntrl <= `WAIT_RX1;
+ `GET_TOKEN_WAIT_CRC:
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+ next_endpCRCTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ NextState_slvCntrl <= `WAIT_RX1;
+ `GET_TOKEN_WAIT_ADDR:
+ if (RxDataWEn == 1'b1 &&
+ RxStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+ next_addrEndPTemp <= RxByte;
+ end
+ else if (RxDataWEn == 1'b1 &&
+ RxStatus != `RX_PACKET_STREAM)
+ NextState_slvCntrl <= `WAIT_RX1;
+ `GET_TOKEN_WAIT_STOP:
+ if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+ RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+ RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+ NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+ else if (RxDataWEn == 1'b1)
+ NextState_slvCntrl <= `WAIT_RX1;
+ `GET_TOKEN_CHK_SOF:
+ if (PIDByte[3:0] == `SOF)
+ begin
+ NextState_slvCntrl <= `WAIT_RX1;
+ next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+ next_SOFRxed <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvCntrl <= `GET_TOKEN_DELAY;
+ next_USBAddress <= addrEndPTemp[6:0];
+ next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+ end
+ `GET_TOKEN_DELAY: // Insert delay to allow USBEndP etc to update
+ NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+ `GET_TOKEN_CHK_ADDR:
+ if (USBEndP < `NUM_OF_ENDPOINTS &&
+ USBAddress == USBTgtAddress &&
+ SCGlobalEn == 1'b1 &&
+ USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+ begin
+ NextState_slvCntrl <= `CHK_PID;
+ next_USBEndPControlRegCopy <= USBEndPControlReg;
+ next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+ end
+ else
+ NextState_slvCntrl <= `WAIT_RX1;
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_CurrentState
+ if (rst)
+ CurrState_slvCntrl <= `START_S1;
+ else
+ CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_RegOutput
+ if (rst)
+ begin
+ tempUSBEndPTransTypeReg <= 2'b00;
+ addrEndPTemp <= 8'h00;
+ endpCRCTemp <= 8'h00;
+ USBAddress <= 7'b0000000;
+ PIDByte <= 8'h00;
+ USBEndPControlRegCopy <= 5'b00000;
+ transDone <= 1'b0;
+ getPacketREn <= 1'b0;
+ sendPacketPID <= 4'b0;
+ sendPacketWEn <= 1'b0;
+ clrEPRdy <= 1'b0;
+ USBEndPTransTypeReg <= 2'b00;
+ USBEndPNakTransTypeReg <= 2'b00;
+ NAKSent <= 1'b0;
+ stallSent <= 1'b0;
+ SOFRxed <= 1'b0;
+ endPMuxErrorsWEn <= 1'b0;
+ frameNum <= 11'b00000000000;
+ USBEndP <= 4'h0;
+ endPointReadyToGetPkt <= 1'b0;
+ end
+ else
+ begin
+ tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+ addrEndPTemp <= next_addrEndPTemp;
+ endpCRCTemp <= next_endpCRCTemp;
+ USBAddress <= next_USBAddress;
+ PIDByte <= next_PIDByte;
+ USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+ transDone <= next_transDone;
+ getPacketREn <= next_getPacketREn;
+ sendPacketPID <= next_sendPacketPID;
+ sendPacketWEn <= next_sendPacketWEn;
+ clrEPRdy <= next_clrEPRdy;
+ USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+ USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+ NAKSent <= next_NAKSent;
+ stallSent <= next_stallSent;
+ SOFRxed <= next_SOFRxed;
+ endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+ frameNum <= next_frameNum;
+ USBEndP <= next_USBEndP;
+ endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+ end
+end
+
+endmodule
\ No newline at end of file
slavecontroller.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sctxportarbiter.v
===================================================================
--- sctxportarbiter.v (nonexistent)
+++ sctxportarbiter.v (revision 40)
@@ -0,0 +1,202 @@
+
+// File : ../RTL/slaveController/sctxportarbiter.v
+// Generated : 11/10/06 05:37:24
+// From : ../RTL/slaveController/sctxportarbiter.asf
+// By : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SCTxPortArbiter
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input SCTxPortRdyIn;
+input clk;
+input [7:0] directCntlCntl;
+input [7:0] directCntlData;
+input directCntlReq;
+input directCntlWEn;
+input rst;
+input [7:0] sendPacketCntl;
+input [7:0] sendPacketData;
+input sendPacketReq;
+input sendPacketWEn;
+output [7:0] SCTxPortCntl;
+output [7:0] SCTxPortData;
+output SCTxPortRdyOut;
+output SCTxPortWEnable;
+output directCntlGnt;
+output sendPacketGnt;
+
+reg [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0] SCTxPortData, next_SCTxPortData;
+wire SCTxPortRdyIn;
+reg SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg SCTxPortWEnable, next_SCTxPortWEnable;
+wire clk;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+reg directCntlGnt, next_directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire rst;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+reg sendPacketGnt, next_sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_SCTxArb;
+reg [1:0] NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+ SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+ directCntlWEn or directCntlData or directCntlCntl or
+ directCntlWEn or directCntlData or directCntlCntl or
+ sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+ begin
+ SCTxPortWEnable <= directCntlWEn;
+ SCTxPortData <= directCntlData;
+ SCTxPortCntl <= directCntlCntl;
+ end
+else
+ begin
+ SCTxPortWEnable <= sendPacketWEn;
+ SCTxPortData <= sendPacketData;
+ SCTxPortCntl <= sendPacketCntl;
+ end
+end
+
+//--------------------------------------------------------------------
+// Machine: SCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin : SCTxArb_NextState
+ NextState_SCTxArb <= CurrState_SCTxArb;
+ // Set default values for outputs and signals
+ next_sendPacketGnt <= sendPacketGnt;
+ next_muxDCEn <= muxDCEn;
+ next_directCntlGnt <= directCntlGnt;
+ case (CurrState_SCTxArb)
+ `SARB1_WAIT_REQ:
+ if (sendPacketReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_SEND_PACKET;
+ next_sendPacketGnt <= 1'b1;
+ next_muxDCEn <= 1'b0;
+ end
+ else if (directCntlReq == 1'b1)
+ begin
+ NextState_SCTxArb <= `SARB_DC;
+ next_directCntlGnt <= 1'b1;
+ next_muxDCEn <= 1'b1;
+ end
+ `SARB_SEND_PACKET:
+ if (sendPacketReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_sendPacketGnt <= 1'b0;
+ end
+ `SARB_DC:
+ if (directCntlReq == 1'b0)
+ begin
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ next_directCntlGnt <= 1'b0;
+ end
+ `START_SARB:
+ NextState_SCTxArb <= `SARB1_WAIT_REQ;
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_CurrentState
+ if (rst)
+ CurrState_SCTxArb <= `START_SARB;
+ else
+ CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_RegOutput
+ if (rst)
+ begin
+ muxDCEn <= 1'b0;
+ sendPacketGnt <= 1'b0;
+ directCntlGnt <= 1'b0;
+ end
+ else
+ begin
+ muxDCEn <= next_muxDCEn;
+ sendPacketGnt <= next_sendPacketGnt;
+ directCntlGnt <= next_directCntlGnt;
+ end
+end
+
+endmodule
\ No newline at end of file
sctxportarbiter.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: USBSlaveControlBI.v
===================================================================
--- USBSlaveControlBI.v (nonexistent)
+++ USBSlaveControlBI.v (revision 40)
@@ -0,0 +1,714 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// USBSlaveControlBI.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v"
+
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+ strobe_i,
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut, vBusDetIntOut,
+ endP0TransTypeReg, endP0NAKTransTypeReg,
+ endP1TransTypeReg, endP1NAKTransTypeReg,
+ endP2TransTypeReg, endP2NAKTransTypeReg,
+ endP3TransTypeReg, endP3NAKTransTypeReg,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ EP0StatusReg,
+ EP1StatusReg,
+ EP2StatusReg,
+ EP3StatusReg,
+ SCAddrReg, frameNum,
+ connectStateIn,
+ vBusDetectIn,
+ SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+ slaveControlSelect,
+ clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+ TxLineState,
+ LineDirectControlEn,
+ fullSpeedPol,
+ fullSpeedRate,
+ connectSlaveToHost,
+ SCGlobalEn
+ );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+output vBusDetIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg;
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg;
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg;
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input vBusDetectIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol;
+output fullSpeedRate;
+output connectSlaveToHost;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+reg vBusDetIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP0ControlReg1;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP1ControlReg1;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP2ControlReg1;
+reg [4:0] endP3ControlReg;
+reg [4:0] endP3ControlReg1;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg [1:0] TxLineState_reg1;
+reg LineDirectControlEn;
+reg LineDirectControlEn_reg1;
+reg fullSpeedPol;
+reg fullSpeedPol_reg1;
+reg fullSpeedRate;
+reg fullSpeedRate_reg1;
+reg connectSlaveToHost;
+reg connectSlaveToHost_reg1;
+reg SCGlobalEn;
+reg SCGlobalEn_reg1;
+
+//internal wire and regs
+reg [6:0] SCControlReg;
+reg clrVBusDetReq;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg vBusDetInt;
+reg NAKSentInt;
+reg [5:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+reg [2:0] SOFRxedInExtend;
+reg [2:0] resetEventInExtend;
+reg [2:0] resumeIntInExtend;
+reg [2:0] transDoneInExtend;
+reg [2:0] NAKSentInExtend;
+reg [2:0] clrEP0ReadyExtend;
+reg [2:0] clrEP1ReadyExtend;
+reg [2:0] clrEP2ReadyExtend;
+reg [2:0] clrEP3ReadyExtend;
+
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg [2:0] NAKSentInSTB;
+reg [2:0] SOFRxedInSTB;
+reg [2:0] resetEventInSTB;
+reg [2:0] resumeIntInSTB;
+reg [2:0] transDoneInSTB;
+reg [2:0] clrEP0ReadySTB;
+reg [2:0] clrEP1ReadySTB;
+reg [2:0] clrEP2ReadySTB;
+reg [2:0] clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB;
+reg fullSpeedRateSTB;
+reg connectSlaveToHostSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP0StatusRegSTB_reg1;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP1StatusRegSTB_reg1;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP2StatusRegSTB_reg1;
+reg [7:0] EP3StatusRegSTB;
+reg [7:0] EP3StatusRegSTB_reg1;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0TransTypeRegSTB_reg1;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB_reg1;
+reg [1:0] endP1TransTypeRegSTB;
+reg [1:0] endP1TransTypeRegSTB_reg1;
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP1NAKTransTypeRegSTB_reg1;
+reg [1:0] endP2TransTypeRegSTB;
+reg [1:0] endP2TransTypeRegSTB_reg1;
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP2NAKTransTypeRegSTB_reg1;
+reg [1:0] endP3TransTypeRegSTB;
+reg [1:0] endP3TransTypeRegSTB_reg1;
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [1:0] endP3NAKTransTypeRegSTB_reg1;
+reg [10:0] frameNumSTB;
+reg [10:0] frameNumSTB_reg1;
+reg [2:0] vBusDetectInSTB;
+reg [1:0] connectStateInSTB;
+reg [1:0] connectStateInSTB_reg1;
+
+
+//sync write demux
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ EP0IsoEn <= 1'b0;
+ EP0SendStall <= 1'b0;
+ EP0DataSequence <= 1'b0;
+ EP0Enable <= 1'b0;
+ EP1IsoEn <= 1'b0;
+ EP1SendStall <= 1'b0;
+ EP1DataSequence <= 1'b0;
+ EP1Enable <= 1'b0;
+ EP2IsoEn <= 1'b0;
+ EP2SendStall <= 1'b0;
+ EP2DataSequence <= 1'b0;
+ EP2Enable <= 1'b0;
+ EP3IsoEn <= 1'b0;
+ EP3SendStall <= 1'b0;
+ EP3DataSequence <= 1'b0;
+ EP3Enable <= 1'b0;
+ SCControlReg <= 7'h00;
+ SCAddrReg <= 7'h00;
+ interruptMaskReg <= 6'h00;
+ end
+ else begin
+ clrVBusDetReq <= 1'b0;
+ clrNAKReq <= 1'b0;
+ clrSOFReq <= 1'b0;
+ clrResetReq <= 1'b0;
+ clrResInReq <= 1'b0;
+ clrTransDoneReq <= 1'b0;
+ EP0SetReady <= 1'b0;
+ EP1SetReady <= 1'b0;
+ EP2SetReady <= 1'b0;
+ EP3SetReady <= 1'b0;
+ if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+ begin
+ case (address)
+ `EP0_CTRL_REG : begin
+ EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP1_CTRL_REG : begin
+ EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP2_CTRL_REG : begin
+ EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `EP3_CTRL_REG : begin
+ EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+ EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+ EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+ EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+ EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+ end
+ `SC_CONTROL_REG : SCControlReg <= dataIn[6:0];
+ `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+ `SC_INTERRUPT_STATUS_REG : begin
+ clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT];
+ clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+ clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+ clrResetReq <= dataIn[`RESET_EVENT_BIT];
+ clrResInReq <= dataIn[`RESUME_INT_BIT];
+ clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+ end
+ `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[5:0];
+ endcase
+ end
+ end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ vBusDetInt <= 1'b0;
+ NAKSentInt <= 1'b0;
+ SOFRxedInt <= 1'b0;
+ resetEventInt <= 1'b0;
+ resumeInt <= 1'b0;
+ transDoneInt <= 1'b0;
+ end
+ else begin
+ if (vBusDetectInSTB[0] != vBusDetectInSTB[1])
+ vBusDetInt <= 1'b1;
+ else if (clrVBusDetReq == 1'b1)
+ vBusDetInt <= 1'b0;
+
+ if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0)
+ NAKSentInt <= 1'b1;
+ else if (clrNAKReq == 1'b1)
+ NAKSentInt <= 1'b0;
+
+ if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0)
+ SOFRxedInt <= 1'b1;
+ else if (clrSOFReq == 1'b1)
+ SOFRxedInt <= 1'b0;
+
+ if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0)
+ resetEventInt <= 1'b1;
+ else if (clrResetReq == 1'b1)
+ resetEventInt <= 1'b0;
+
+ if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
+ resumeInt <= 1'b1;
+ else if (clrResInReq == 1'b1)
+ resumeInt <= 1'b0;
+
+ if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
+ transDoneInt <= 1'b1;
+ else if (clrTransDoneReq == 1'b1)
+ transDoneInt <= 1'b0;
+ end
+end
+
+//mask interrupts
+always @(*) begin
+ transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+ resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+ resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+ SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+ NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+ vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT];
+end
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.
+always @(posedge busClk)
+begin
+ if (rstSyncToBusClk == 1'b1) begin
+ EP0Ready <= 1'b0;
+ EP1Ready <= 1'b0;
+ EP2Ready <= 1'b0;
+ EP3Ready <= 1'b0;
+ end
+ else begin
+ if (EP0SetReady == 1'b1)
+ EP0Ready <= 1'b1;
+ else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0)
+ EP0Ready <= 1'b0;
+
+ if (EP1SetReady == 1'b1)
+ EP1Ready <= 1'b1;
+ else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0)
+ EP1Ready <= 1'b0;
+
+ if (EP2SetReady == 1'b1)
+ EP2Ready <= 1'b1;
+ else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0)
+ EP2Ready <= 1'b0;
+
+ if (EP3SetReady == 1'b1)
+ EP3Ready <= 1'b1;
+ else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0)
+ EP3Ready <= 1'b0;
+ end
+end
+
+//break out control signals
+always @(SCControlReg) begin
+ SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+ TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+ LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+ fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
+ fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+ connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT];
+end
+
+//combine endpoint control signals
+always @(*)
+begin
+ endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+ endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+ endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+ endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+
+
+// async read mux
+always @(*)
+begin
+ case (address)
+ `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+ `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+ `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+ `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+ `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+ `EP1_STS_REG : dataOut <= EP1StatusRegSTB;
+ `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+ `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+ `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+ `EP2_STS_REG : dataOut <= EP2StatusRegSTB;
+ `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+ `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+ `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+ `EP3_STS_REG : dataOut <= EP3StatusRegSTB;
+ `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+ `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+ `SC_CONTROL_REG : dataOut <= SCControlReg;
+ `SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB};
+ `SC_INTERRUPT_STATUS_REG : dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+ `SC_INTERRUPT_MASK_REG : dataOut <= {2'b00, interruptMaskReg};
+ `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+ `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+ `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+ default: dataOut <= 8'h00;
+ endcase
+end
+
+
+//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick
+//pulses to 3 tick pulses
+always @(posedge usbClk) begin
+ if (rstSyncToUsbClk == 1'b1) begin
+ SOFRxedInExtend <= 3'b000;
+ resetEventInExtend <= 3'b000;
+ resumeIntInExtend <= 3'b000;
+ transDoneInExtend <= 3'b000;
+ NAKSentInExtend <= 3'b000;
+ clrEP0ReadyExtend <= 3'b000;
+ clrEP1ReadyExtend <= 3'b000;
+ clrEP2ReadyExtend <= 3'b000;
+ clrEP3ReadyExtend <= 3'b000;
+ end
+ else begin
+ if (SOFRxedIn == 1'b1)
+ SOFRxedInExtend <= 3'b111;
+ else
+ SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]};
+ if (resetEventIn == 1'b1)
+ resetEventInExtend <= 3'b111;
+ else
+ resetEventInExtend <= {1'b0, resetEventInExtend[2:1]};
+ if (resumeIntIn == 1'b1)
+ resumeIntInExtend <= 3'b111;
+ else
+ resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
+ if (transDoneIn == 1'b1)
+ transDoneInExtend <= 3'b111;
+ else
+ transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
+ if (NAKSentIn == 1'b1)
+ NAKSentInExtend <= 3'b111;
+ else
+ NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]};
+ if (clrEP0Ready == 1'b1)
+ clrEP0ReadyExtend <= 3'b111;
+ else
+ clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]};
+ if (clrEP1Ready == 1'b1)
+ clrEP1ReadyExtend <= 3'b111;
+ else
+ clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]};
+ if (clrEP2Ready == 1'b1)
+ clrEP2ReadyExtend <= 3'b111;
+ else
+ clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]};
+ if (clrEP3Ready == 1'b1)
+ clrEP3ReadyExtend <= 3'b111;
+ else
+ clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]};
+ end
+end
+
+//re-sync from busClk to usbClk.
+always @(posedge usbClk) begin
+ if (rstSyncToUsbClk == 1'b1) begin
+ endP0ControlReg <= {5{1'b0}};
+ endP0ControlReg1 <= {5{1'b0}};
+ endP1ControlReg <= {5{1'b0}};
+ endP1ControlReg1 <= {5{1'b0}};
+ endP2ControlReg <= {5{1'b0}};
+ endP2ControlReg1 <= {5{1'b0}};
+ endP3ControlReg <= {5{1'b0}};
+ endP3ControlReg1 <= {5{1'b0}};
+ SCGlobalEn <= 1'b0;
+ SCGlobalEn_reg1 <= 1'b0;
+ TxLineState <= 2'b00;
+ TxLineState_reg1 <= 2'b00;
+ LineDirectControlEn <= 1'b0;
+ LineDirectControlEn_reg1 <= 1'b0;
+ fullSpeedPol <= 1'b0;
+ fullSpeedPol_reg1 <= 1'b0;
+ fullSpeedRate <= 1'b0;
+ fullSpeedRate_reg1 <= 1'b0;
+ connectSlaveToHost <= 1'b0;
+ connectSlaveToHost_reg1 <= 1'b0;
+ end
+ else begin
+ endP0ControlReg1 <= endP0ControlRegSTB;
+ endP0ControlReg <= endP0ControlReg1;
+ endP1ControlReg1 <= endP1ControlRegSTB;
+ endP1ControlReg <= endP1ControlReg1;
+ endP2ControlReg1 <= endP2ControlRegSTB;
+ endP2ControlReg <= endP2ControlReg1;
+ endP3ControlReg1 <= endP3ControlRegSTB;
+ endP3ControlReg <= endP3ControlReg1;
+ SCGlobalEn_reg1 <= SCGlobalEnSTB;
+ SCGlobalEn <= SCGlobalEn_reg1;
+ TxLineState_reg1 <= TxLineStateSTB;
+ TxLineState <= TxLineState_reg1;
+ LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
+ LineDirectControlEn <= LineDirectControlEn_reg1;
+ fullSpeedPol_reg1 <= fullSpeedPolSTB;
+ fullSpeedPol <= fullSpeedPol_reg1;
+ fullSpeedRate_reg1 <= fullSpeedRateSTB;
+ fullSpeedRate <= fullSpeedRate_reg1;
+ connectSlaveToHost_reg1 <= connectSlaveToHostSTB;
+ connectSlaveToHost <= connectSlaveToHost_reg1;
+ end
+end
+
+//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc
+//are only asserted for 3 usbClk ticks
+//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq
+always @(posedge busClk) begin
+ if (rstSyncToBusClk == 1'b1) begin
+ vBusDetectInSTB <= 3'b000;
+ NAKSentInSTB <= 3'b000;
+ SOFRxedInSTB <= 3'b000;
+ resetEventInSTB <= 3'b000;
+ resumeIntInSTB <= 3'b000;
+ transDoneInSTB <= 3'b000;
+ clrEP0ReadySTB <= 3'b000;
+ clrEP1ReadySTB <= 3'b000;
+ clrEP2ReadySTB <= 3'b000;
+ clrEP3ReadySTB <= 3'b000;
+ EP0StatusRegSTB <= 8'h00;
+ EP0StatusRegSTB_reg1 <= 8'h00;
+ EP1StatusRegSTB <= 8'h00;
+ EP1StatusRegSTB_reg1 <= 8'h00;
+ EP2StatusRegSTB <= 8'h00;
+ EP2StatusRegSTB_reg1 <= 8'h00;
+ EP3StatusRegSTB <= 8'h00;
+ EP3StatusRegSTB_reg1 <= 8'h00;
+ endP0TransTypeRegSTB <= 2'b00;
+ endP0TransTypeRegSTB_reg1 <= 2'b00;
+ endP1TransTypeRegSTB <= 2'b00;
+ endP1TransTypeRegSTB_reg1 <= 2'b00;
+ endP2TransTypeRegSTB <= 2'b00;
+ endP2TransTypeRegSTB_reg1 <= 2'b00;
+ endP3TransTypeRegSTB <= 2'b00;
+ endP3TransTypeRegSTB_reg1 <= 2'b00;
+ endP0NAKTransTypeRegSTB <= 2'b00;
+ endP0NAKTransTypeRegSTB_reg1 <= 2'b00;
+ endP1NAKTransTypeRegSTB <= 2'b00;
+ endP1NAKTransTypeRegSTB_reg1 <= 2'b00;
+ endP2NAKTransTypeRegSTB <= 2'b00;
+ endP2NAKTransTypeRegSTB_reg1 <= 2'b00;
+ endP3NAKTransTypeRegSTB <= 2'b00;
+ endP3NAKTransTypeRegSTB_reg1 <= 2'b00;
+ frameNumSTB <= {11{1'b0}};
+ frameNumSTB_reg1 <= {11{1'b0}};
+ connectStateInSTB <= 2'b00;
+ connectStateInSTB_reg1 <= 2'b00;
+ end
+ else begin
+ vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]};
+ NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]};
+ SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]};
+ resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]};
+ resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
+ transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
+ clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]};
+ clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]};
+ clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]};
+ clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]};
+ EP0StatusRegSTB_reg1 <= EP0StatusReg;
+ EP0StatusRegSTB <= EP0StatusRegSTB_reg1;
+ EP1StatusRegSTB_reg1 <= EP1StatusReg;
+ EP1StatusRegSTB <= EP1StatusRegSTB_reg1;
+ EP2StatusRegSTB_reg1 <= EP2StatusReg;
+ EP2StatusRegSTB <= EP2StatusRegSTB_reg1;
+ EP3StatusRegSTB_reg1 <= EP3StatusReg;
+ EP3StatusRegSTB <= EP3StatusRegSTB_reg1;
+ endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg;
+ endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1;
+ endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg;
+ endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1;
+ endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg;
+ endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1;
+ endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg;
+ endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1;
+ endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg;
+ endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1;
+ endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg;
+ endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1;
+ endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg;
+ endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1;
+ endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg;
+ endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1;
+ frameNumSTB_reg1 <= frameNum;
+ frameNumSTB <= frameNumSTB_reg1;
+ connectStateInSTB_reg1 <= connectStateIn;
+ connectStateInSTB <= connectStateInSTB_reg1;
+ end
+end
+
+
+endmodule
USBSlaveControlBI.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slaveGetpacket.v
===================================================================
--- slaveGetpacket.v (nonexistent)
+++ slaveGetpacket.v (revision 40)
@@ -0,0 +1,357 @@
+
+// File : ../RTL/slaveController/slaveGetpacket.v
+// Generated : 11/10/06 05:37:25
+// From : ../RTL/slaveController/slaveGetpacket.asf
+// By : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveGetPacket
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
+input [7:0] RXDataIn;
+input RXDataValid;
+input RXFifoFull;
+input [7:0] RXStreamStatusIn;
+input SIERxTimeOut; // Single cycle pulse
+input clk;
+input endPointReady;
+input getPacketEn;
+input rst;
+output ACKRxed;
+output CRCError;
+output [7:0] RXFifoData;
+output RXFifoWEn;
+output RXOverflow;
+output RXPacketRdy;
+output RXTimeOut;
+output [3:0] RxPID;
+output SIERxTimeOutEn;
+output bitStuffError;
+output dataSequence;
+
+reg ACKRxed, next_ACKRxed;
+reg CRCError, next_CRCError;
+wire [7:0] RXDataIn;
+wire RXDataValid;
+reg [7:0] RXFifoData, next_RXFifoData;
+wire RXFifoFull;
+reg RXFifoWEn, next_RXFifoWEn;
+reg RXOverflow, next_RXOverflow;
+reg RXPacketRdy, next_RXPacketRdy;
+wire [7:0] RXStreamStatusIn;
+reg RXTimeOut, next_RXTimeOut;
+reg [3:0] RxPID, next_RxPID;
+wire SIERxTimeOut;
+reg SIERxTimeOutEn, next_SIERxTimeOutEn;
+reg bitStuffError, next_bitStuffError;
+wire clk;
+reg dataSequence, next_dataSequence;
+wire endPointReady;
+wire getPacketEn;
+wire rst;
+
+// diagram signals declarations
+reg [7:0]RXByteOld, next_RXByteOld;
+reg [7:0]RXByteOldest, next_RXByteOldest;
+reg [7:0]RXByte, next_RXByte;
+reg [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0] CurrState_slvGetPkt;
+reg [4:0] NextState_slvGetPkt;
+
+
+//--------------------------------------------------------------------
+// Machine: slvGetPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
+begin : slvGetPkt_NextState
+ NextState_slvGetPkt <= CurrState_slvGetPkt;
+ // Set default values for outputs and signals
+ next_CRCError <= CRCError;
+ next_bitStuffError <= bitStuffError;
+ next_RXOverflow <= RXOverflow;
+ next_RXTimeOut <= RXTimeOut;
+ next_ACKRxed <= ACKRxed;
+ next_dataSequence <= dataSequence;
+ next_SIERxTimeOutEn <= SIERxTimeOutEn;
+ next_RXByte <= RXByte;
+ next_RXStreamStatus <= RXStreamStatus;
+ next_RxPID <= RxPID;
+ next_RXPacketRdy <= RXPacketRdy;
+ next_RXByteOldest <= RXByteOldest;
+ next_RXByteOld <= RXByteOld;
+ next_RXFifoWEn <= RXFifoWEn;
+ next_RXFifoData <= RXFifoData;
+ case (CurrState_slvGetPkt)
+ `START_GP:
+ NextState_slvGetPkt <= `WAIT_EN;
+ `WAIT_PKT:
+ begin
+ next_CRCError <= 1'b0;
+ next_bitStuffError <= 1'b0;
+ next_RXOverflow <= 1'b0;
+ next_RXTimeOut <= 1'b0;
+ next_ACKRxed <= 1'b0;
+ next_dataSequence <= 1'b0;
+ next_SIERxTimeOutEn <= 1'b1;
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `CHK_PKT_START;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ else if (SIERxTimeOut == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ end
+ `CHK_PKT_START:
+ if (RXStreamStatus == `RX_PACKET_START)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+ next_RxPID <= RXByte[3:0];
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXTimeOut <= 1'b1;
+ end
+ `WAIT_EN:
+ begin
+ next_RXPacketRdy <= 1'b0;
+ next_SIERxTimeOutEn <= 1'b0;
+ if (getPacketEn == 1'b1)
+ NextState_slvGetPkt <= `WAIT_PKT;
+ end
+ `PKT_RDY:
+ begin
+ next_RXPacketRdy <= 1'b1;
+ NextState_slvGetPkt <= `WAIT_EN;
+ end
+ `PROC_PKT_CHK_PID:
+ if (RXByte[1:0] == `HANDSHAKE)
+ NextState_slvGetPkt <= `PROC_PKT_HS;
+ else if (RXByte[1:0] == `DATA)
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+ else
+ NextState_slvGetPkt <= `PKT_RDY;
+ `PROC_PKT_HS:
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PKT_RDY;
+ next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+ next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+ end
+ `PROC_PKT_DATA_W_D1:
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ `PROC_PKT_DATA_CHK_D1:
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+ next_RXByteOldest <= RXByte;
+ end
+ else
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ `PROC_PKT_DATA_W_D2:
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ `PROC_PKT_DATA_FIN:
+ begin
+ next_CRCError <= RXByte[`CRC_ERROR_BIT];
+ next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+ next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+ NextState_slvGetPkt <= `PKT_RDY;
+ end
+ `PROC_PKT_DATA_CHK_D2:
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+ next_RXByteOld <= RXByte;
+ end
+ else
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ `PROC_PKT_DATA_W_D3:
+ if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+ next_RXByte <= RXDataIn;
+ next_RXStreamStatus <= RXStreamStatusIn;
+ end
+ `PROC_PKT_DATA_CHK_D3:
+ if (RXStreamStatus == `RX_PACKET_STREAM)
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ else
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ `PROC_PKT_DATA_LOOP_CHK_FIFO:
+ if (endPointReady == 1'b0)
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+ else if (RXFifoFull == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+ next_RXOverflow <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ next_RXFifoWEn <= 1'b1;
+ next_RXFifoData <= RXByteOldest;
+ next_RXByteOldest <= RXByteOld;
+ next_RXByteOld <= RXByte;
+ end
+ `PROC_PKT_DATA_LOOP_FIFO_FULL:
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ `PROC_PKT_DATA_LOOP_W_D:
+ begin
+ next_RXFifoWEn <= 1'b0;
+ if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+ next_RXByte <= RXDataIn;
+ end
+ else if (RXDataValid == 1'b1)
+ begin
+ NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+ next_RXByte <= RXDataIn;
+ end
+ end
+ `PROC_PKT_DATA_LOOP_DELAY:
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+ `PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
+ NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_CurrentState
+ if (rst)
+ CurrState_slvGetPkt <= `START_GP;
+ else
+ CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_RegOutput
+ if (rst)
+ begin
+ RXByteOld <= 8'h00;
+ RXByteOldest <= 8'h00;
+ RXByte <= 8'h00;
+ RXStreamStatus <= 8'h00;
+ RXPacketRdy <= 1'b0;
+ RXFifoWEn <= 1'b0;
+ RXFifoData <= 8'h00;
+ CRCError <= 1'b0;
+ bitStuffError <= 1'b0;
+ RXOverflow <= 1'b0;
+ RXTimeOut <= 1'b0;
+ ACKRxed <= 1'b0;
+ dataSequence <= 1'b0;
+ SIERxTimeOutEn <= 1'b0;
+ RxPID <= 4'h0;
+ end
+ else
+ begin
+ RXByteOld <= next_RXByteOld;
+ RXByteOldest <= next_RXByteOldest;
+ RXByte <= next_RXByte;
+ RXStreamStatus <= next_RXStreamStatus;
+ RXPacketRdy <= next_RXPacketRdy;
+ RXFifoWEn <= next_RXFifoWEn;
+ RXFifoData <= next_RXFifoData;
+ CRCError <= next_CRCError;
+ bitStuffError <= next_bitStuffError;
+ RXOverflow <= next_RXOverflow;
+ RXTimeOut <= next_RXTimeOut;
+ ACKRxed <= next_ACKRxed;
+ dataSequence <= next_dataSequence;
+ SIERxTimeOutEn <= next_SIERxTimeOutEn;
+ RxPID <= next_RxPID;
+ end
+end
+
+endmodule
\ No newline at end of file
slaveGetpacket.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: usbSlaveControl.v
===================================================================
--- usbSlaveControl.v (nonexistent)
+++ usbSlaveControl.v (revision 40)
@@ -0,0 +1,521 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// usbSlaveControl.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSlaveControl(
+ busClk,
+ rstSyncToBusClk,
+ usbClk,
+ rstSyncToUsbClk,
+ //getPacket
+ RxByteStatus, RxData, RxDataValid,
+ SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
+ //speedCtrlMux
+ fullSpeedRate, fullSpeedPol,
+ connectSlaveToHost,
+ //SCTxPortArbiter
+ SCTxPortEn, SCTxPortRdy,
+ SCTxPortData, SCTxPortCtrl,
+ //rxStatusMonitor
+ vBusDetect,
+ connectStateIn,
+ resumeDetectedIn,
+ //USBHostControlBI
+ busAddress,
+ busDataIn,
+ busDataOut,
+ busWriteEn,
+ busStrobe_i,
+ SOFRxedIntOut,
+ resetEventIntOut,
+ resumeIntOut,
+ transDoneIntOut,
+ vBusDetIntOut,
+ NAKSentIntOut,
+ slaveControlSelect,
+ //fifoMux
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output SIERxTimeOutEn;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+output connectSlaveToHost;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input vBusDetect;
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI
+input [4:0] busAddress;
+input [7:0] busDataIn;
+output [7:0] busDataOut;
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output vBusDetIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire connectSlaveToHost;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn;
+wire [7:0] busDataOut;
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut;
+wire resetEventIntOut;
+wire resumeIntOut;
+wire transDoneIntOut;
+wire vBusDetIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed;
+wire CRCError;
+wire RXOverflow;
+wire RXTimeOut;
+wire bitStuffError;
+wire dataSequence;
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+ (.address(busAddress),
+ .dataIn(busDataIn),
+ .dataOut(busDataOut),
+ .writeEn(busWriteEn),
+ .strobe_i(busStrobe_i),
+ .busClk(busClk),
+ .rstSyncToBusClk(rstSyncToBusClk),
+ .usbClk(usbClk),
+ .rstSyncToUsbClk(rstSyncToUsbClk),
+ .SOFRxedIntOut(SOFRxedIntOut),
+ .resetEventIntOut(resetEventIntOut),
+ .resumeIntOut(resumeIntOut),
+ .transDoneIntOut(transDoneIntOut),
+ .vBusDetIntOut(vBusDetIntOut),
+ .NAKSentIntOut(NAKSentIntOut),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .EP0StatusReg(endP0StatusReg),
+ .EP1StatusReg(endP1StatusReg),
+ .EP2StatusReg(endP2StatusReg),
+ .EP3StatusReg(endP3StatusReg),
+ .SCAddrReg(USBTgtAddress),
+ .frameNum(frameNum),
+ .connectStateIn(connectStateOut),
+ .vBusDetectIn(vBusDetect),
+ .SOFRxedIn(SOFRxed),
+ .resetEventIn(resetEventFromRxStatusMon),
+ .resumeIntIn(resumeIntFromRxStatusMon),
+ .transDoneIn(transDone),
+ .NAKSentIn(NAKSent),
+ .slaveControlSelect(slaveControlSelect),
+ .clrEP0Ready(clrEP0Rdy),
+ .clrEP1Ready(clrEP1Rdy),
+ .clrEP2Ready(clrEP2Rdy),
+ .clrEP3Ready(clrEP3Rdy),
+ .TxLineState(directLineState),
+ .LineDirectControlEn(directLineCtrlEn),
+ .fullSpeedPol(fullSpeedPol),
+ .fullSpeedRate(fullSpeedRate),
+ .connectSlaveToHost(connectSlaveToHost),
+ .SCGlobalEn(SCGlobalEn)
+ );
+
+slavecontroller u_slavecontroller
+ (.CRCError(CRCError),
+ .NAKSent(NAKSent),
+ .RxByte(RxData),
+ .RxDataWEn(RxDataValid),
+ .RxOverflow(RXOverflow),
+ .RxStatus(RxByteStatus),
+ .RxTimeOut(RXTimeOut),
+ .SCGlobalEn(SCGlobalEn),
+ .SOFRxed(SOFRxed),
+ .USBEndPControlReg(endPControlReg),
+ .USBEndPNakTransTypeReg(transTypeNAK),
+ .USBEndPTransTypeReg(transType),
+ .USBEndP(currEndP),
+ .USBTgtAddress(USBTgtAddress),
+ .bitStuffError(bitStuffError),
+ .clk(usbClk),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .frameNum(frameNum),
+ .getPacketREn(getPacketREn),
+ .getPacketRdy(getPacketRdy),
+ .rst(rstSyncToUsbClk),
+ .sendPacketPID(slaveControllerPIDOut),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut),
+ .stallSent(stallSent),
+ .transDone(transDone),
+ .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+ );
+
+
+endpMux u_endpMux (
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk),
+ .currEndP(currEndP),
+ .NAKSent(NAKSent),
+ .stallSent(stallSent),
+ .CRCError(CRCError),
+ .bitStuffError(bitStuffError),
+ .RxOverflow(RXOverflow),
+ .RxTimeOut(RXTimeOut),
+ .dataSequence(dataSequence),
+ .ACKRxed(ACKRxed),
+ .transType(transType),
+ .transTypeNAK(transTypeNAK),
+ .endPControlReg(endPControlReg),
+ .clrEPRdy(clrEPRdy),
+ .endPMuxErrorsWEn(endPMuxErrorsWEn),
+ .endP0ControlReg(endP0ControlReg),
+ .endP1ControlReg(endP1ControlReg),
+ .endP2ControlReg(endP2ControlReg),
+ .endP3ControlReg(endP3ControlReg),
+ .endP0StatusReg(endP0StatusReg),
+ .endP1StatusReg(endP1StatusReg),
+ .endP2StatusReg(endP2StatusReg),
+ .endP3StatusReg(endP3StatusReg),
+ .endP0TransTypeReg(endP0TransTypeReg),
+ .endP1TransTypeReg(endP1TransTypeReg),
+ .endP2TransTypeReg(endP2TransTypeReg),
+ .endP3TransTypeReg(endP3TransTypeReg),
+ .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+ .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+ .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+ .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+ .clrEP0Rdy(clrEP0Rdy),
+ .clrEP1Rdy(clrEP1Rdy),
+ .clrEP2Rdy(clrEP2Rdy),
+ .clrEP3Rdy(clrEP3Rdy)
+ );
+
+slaveSendPacket u_slaveSendPacket
+ (.PID(slaveControllerPIDOut),
+ .SCTxPortCntl(sendPacketCntl),
+ .SCTxPortData(sendPacketData),
+ .SCTxPortGnt(sendPacketGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(sendPacketReq),
+ .SCTxPortWEn(sendPacketWEn),
+ .clk(usbClk),
+ .fifoData(TxFifoData),
+ .fifoEmpty(TxFifoEmpty),
+ .fifoReadEn(TxFifoRE),
+ .rst(rstSyncToUsbClk),
+ .sendPacketRdy(slaveControllerReadyIn),
+ .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+ (.SCTxPortCntl(directCntlCntl),
+ .SCTxPortData(directCntlData),
+ .SCTxPortGnt(directCntlGnt),
+ .SCTxPortRdy(SCTxPortArbRdyOut),
+ .SCTxPortReq(directCntlReq),
+ .SCTxPortWEn(directCntlWEn),
+ .clk(usbClk),
+ .directControlEn(directLineCtrlEn),
+ .directControlLineState(directLineState),
+ .rst(rstSyncToUsbClk) );
+
+SCTxPortArbiter u_SCTxPortArbiter
+ (.SCTxPortCntl(SCTxPortCtrl),
+ .SCTxPortData(SCTxPortData),
+ .SCTxPortRdyIn(SCTxPortRdy),
+ .SCTxPortRdyOut(SCTxPortArbRdyOut),
+ .SCTxPortWEnable(SCTxPortEn),
+ .clk(usbClk),
+ .directCntlCntl(directCntlCntl),
+ .directCntlData(directCntlData),
+ .directCntlGnt(directCntlGnt),
+ .directCntlReq(directCntlReq),
+ .directCntlWEn(directCntlWEn),
+ .rst(rstSyncToUsbClk),
+ .sendPacketCntl(sendPacketCntl),
+ .sendPacketData(sendPacketData),
+ .sendPacketGnt(sendPacketGnt),
+ .sendPacketReq(sendPacketReq),
+ .sendPacketWEn(sendPacketWEn) );
+
+
+slaveGetPacket u_slaveGetPacket
+ (.ACKRxed(ACKRxed),
+ .CRCError(CRCError),
+ .RXDataIn(RxData),
+ .RXDataValid(RxDataValid),
+ .RXFifoData(RxFifoData),
+ .RXFifoFull(RxFifoFull),
+ .RXFifoWEn(RxFifoWE),
+ .RXPacketRdy(getPacketRdy),
+ .RXStreamStatusIn(RxByteStatus),
+ .RxPID(RxPID),
+ .SIERxTimeOut(SIERxTimeOut),
+ .SIERxTimeOutEn(SIERxTimeOutEn),
+ .clk(usbClk),
+ .RXOverflow(RXOverflow),
+ .RXTimeOut(RXTimeOut),
+ .bitStuffError(bitStuffError),
+ .dataSequence(dataSequence),
+ .getPacketEn(getPacketREn),
+ .rst(rstSyncToUsbClk),
+ .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+ );
+
+slaveRxStatusMonitor u_slaveRxStatusMonitor
+ (.connectStateIn(connectStateIn),
+ .connectStateOut(connectStateOut),
+ .resumeDetectedIn(resumeDetectedIn),
+ .resetEventOut(resetEventFromRxStatusMon),
+ .resumeIntOut(resumeIntFromRxStatusMon),
+ .clk(usbClk),
+ .rst(rstSyncToUsbClk) );
+
+fifoMux u_fifoMux (
+ .currEndP(currEndP),
+ //TxFifo
+ .TxFifoREn(TxFifoRE),
+ .TxFifoEP0REn(TxFifoEP0REn),
+ .TxFifoEP1REn(TxFifoEP1REn),
+ .TxFifoEP2REn(TxFifoEP2REn),
+ .TxFifoEP3REn(TxFifoEP3REn),
+ .TxFifoData(TxFifoData),
+ .TxFifoEP0Data(TxFifoEP0Data),
+ .TxFifoEP1Data(TxFifoEP1Data),
+ .TxFifoEP2Data(TxFifoEP2Data),
+ .TxFifoEP3Data(TxFifoEP3Data),
+ .TxFifoEmpty(TxFifoEmpty),
+ .TxFifoEP0Empty(TxFifoEP0Empty),
+ .TxFifoEP1Empty(TxFifoEP1Empty),
+ .TxFifoEP2Empty(TxFifoEP2Empty),
+ .TxFifoEP3Empty(TxFifoEP3Empty),
+ //RxFifo
+ .RxFifoWEn(RxFifoWE),
+ .RxFifoEP0WEn(RxFifoEP0WEn),
+ .RxFifoEP1WEn(RxFifoEP1WEn),
+ .RxFifoEP2WEn(RxFifoEP2WEn),
+ .RxFifoEP3WEn(RxFifoEP3WEn),
+ .RxFifoFull(RxFifoFull),
+ .RxFifoEP0Full(RxFifoEP0Full),
+ .RxFifoEP1Full(RxFifoEP1Full),
+ .RxFifoEP2Full(RxFifoEP2Full),
+ .RxFifoEP3Full(RxFifoEP3Full)
+ );
+
+endmodule
+
+
+
+
+
+
+
usbSlaveControl.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slaveDirectcontrol.v
===================================================================
--- slaveDirectcontrol.v (nonexistent)
+++ slaveDirectcontrol.v (revision 40)
@@ -0,0 +1,197 @@
+
+// File : ../RTL/slaveController/slaveDirectcontrol.v
+// Generated : 11/10/06 05:37:25
+// From : ../RTL/slaveController/slaveDirectcontrol.asf
+// By : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveDirectControl
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/ ////
+//// ////
+//// Module Description: ////
+////
+//// ////
+//// To Do: ////
+////
+//// ////
+//// Author(s): ////
+//// - Steve Fielding, sfielding@base2designs.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input SCTxPortGnt;
+input SCTxPortRdy;
+input clk;
+input directControlEn;
+input [1:0] directControlLineState;
+input rst;
+output [7:0] SCTxPortCntl;
+output [7:0] SCTxPortData;
+output SCTxPortReq;
+output SCTxPortWEn;
+
+reg [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg [7:0] SCTxPortData, next_SCTxPortData;
+wire SCTxPortGnt;
+wire SCTxPortRdy;
+reg SCTxPortReq, next_SCTxPortReq;
+reg SCTxPortWEn, next_SCTxPortWEn;
+wire clk;
+wire directControlEn;
+wire [1:0] directControlLineState;
+wire rst;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_slvDrctCntl;
+reg [2:0] NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// diagram ACTION
+
+//--------------------------------------------------------------------
+// Machine: slvDrctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
+begin : slvDrctCntl_NextState
+ NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+ // Set default values for outputs and signals
+ next_SCTxPortReq <= SCTxPortReq;
+ next_SCTxPortWEn <= SCTxPortWEn;
+ next_SCTxPortData <= SCTxPortData;
+ next_SCTxPortCntl <= SCTxPortCntl;
+ case (CurrState_slvDrctCntl)
+ `START_SDC:
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ `CHK_DRCT_CNTL:
+ if (directControlEn == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ else
+ begin
+ NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+ next_SCTxPortReq <= 1'b1;
+ end
+ `DRCT_CNTL_WAIT_GNT:
+ if (SCTxPortGnt == 1'b1)
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ `DRCT_CNTL_CHK_LOOP:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ if (directControlEn == 1'b0)
+ begin
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ next_SCTxPortReq <= 1'b0;
+ end
+ else
+ NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+ end
+ `DRCT_CNTL_WAIT_RDY:
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= {6'b000000, directControlLineState};
+ next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+ end
+ `IDLE_FIN:
+ begin
+ next_SCTxPortWEn <= 1'b0;
+ next_SCTxPortReq <= 1'b0;
+ NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+ end
+ `IDLE_WAIT_GNT:
+ if (SCTxPortGnt == 1'b1)
+ NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+ `IDLE_WAIT_RDY:
+ if (SCTxPortRdy == 1'b1)
+ begin
+ NextState_slvDrctCntl <= `IDLE_FIN;
+ next_SCTxPortWEn <= 1'b1;
+ next_SCTxPortData <= 8'h00;
+ next_SCTxPortCntl <= `TX_IDLE;
+ end
+ endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_CurrentState
+ if (rst)
+ CurrState_slvDrctCntl <= `START_SDC;
+ else
+ CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_RegOutput
+ if (rst)
+ begin
+ SCTxPortCntl <= 8'h00;
+ SCTxPortData <= 8'h00;
+ SCTxPortWEn <= 1'b0;
+ SCTxPortReq <= 1'b0;
+ end
+ else
+ begin
+ SCTxPortCntl <= next_SCTxPortCntl;
+ SCTxPortData <= next_SCTxPortData;
+ SCTxPortWEn <= next_SCTxPortWEn;
+ SCTxPortReq <= next_SCTxPortReq;
+ end
+end
+
+endmodule
\ No newline at end of file
slaveDirectcontrol.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: fifoMux.v
===================================================================
--- fifoMux.v (nonexistent)
+++ fifoMux.v (revision 40)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// fifoMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module fifoMux (
+ currEndP,
+ //TxFifo
+ TxFifoREn,
+ TxFifoEP0REn,
+ TxFifoEP1REn,
+ TxFifoEP2REn,
+ TxFifoEP3REn,
+ TxFifoData,
+ TxFifoEP0Data,
+ TxFifoEP1Data,
+ TxFifoEP2Data,
+ TxFifoEP3Data,
+ TxFifoEmpty,
+ TxFifoEP0Empty,
+ TxFifoEP1Empty,
+ TxFifoEP2Empty,
+ TxFifoEP3Empty,
+ //RxFifo
+ RxFifoWEn,
+ RxFifoEP0WEn,
+ RxFifoEP1WEn,
+ RxFifoEP2WEn,
+ RxFifoEP3WEn,
+ RxFifoFull,
+ RxFifoEP0Full,
+ RxFifoEP1Full,
+ RxFifoEP2Full,
+ RxFifoEP3Full
+ );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+ //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+ //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+ TxFifoREn or
+ RxFifoWEn or
+ TxFifoEP0Data or
+ TxFifoEP1Data or
+ TxFifoEP2Data or
+ TxFifoEP3Data or
+ TxFifoEP0Empty or
+ TxFifoEP1Empty or
+ TxFifoEP2Empty or
+ TxFifoEP3Empty or
+ RxFifoEP0Full or
+ RxFifoEP1Full or
+ RxFifoEP2Full or
+ RxFifoEP3Full)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ TxFifoEP0REn <= TxFifoREn;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP0Data;
+ TxFifoEmpty <= TxFifoEP0Empty;
+ RxFifoEP0WEn <= RxFifoWEn;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP0Full;
+ end
+ 2'b01: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= TxFifoREn;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP1Data;
+ TxFifoEmpty <= TxFifoEP1Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= RxFifoWEn;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP1Full;
+ end
+ 2'b10: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= TxFifoREn;
+ TxFifoEP3REn <= 1'b0;
+ TxFifoData <= TxFifoEP2Data;
+ TxFifoEmpty <= TxFifoEP2Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= RxFifoWEn;
+ RxFifoEP3WEn <= 1'b0;
+ RxFifoFull <= RxFifoEP2Full;
+ end
+ 2'b11: begin
+ TxFifoEP0REn <= 1'b0;
+ TxFifoEP1REn <= 1'b0;
+ TxFifoEP2REn <= 1'b0;
+ TxFifoEP3REn <= TxFifoREn;
+ TxFifoData <= TxFifoEP3Data;
+ TxFifoEmpty <= TxFifoEP3Empty;
+ RxFifoEP0WEn <= 1'b0;
+ RxFifoEP1WEn <= 1'b0;
+ RxFifoEP2WEn <= 1'b0;
+ RxFifoEP3WEn <= RxFifoWEn;
+ RxFifoFull <= RxFifoEP3Full;
+ end
+ endcase
+end
+
+
+endmodule
fifoMux.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: endpMux.v
===================================================================
--- endpMux.v (nonexistent)
+++ endpMux.v (revision 40)
@@ -0,0 +1,259 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// endpMux.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v"
+
+module endpMux (
+ clk,
+ rst,
+ currEndP,
+ NAKSent,
+ stallSent,
+ CRCError,
+ bitStuffError,
+ RxOverflow,
+ RxTimeOut,
+ dataSequence,
+ ACKRxed,
+ transType,
+ transTypeNAK,
+ endPControlReg,
+ clrEPRdy,
+ endPMuxErrorsWEn,
+ endP0ControlReg,
+ endP1ControlReg,
+ endP2ControlReg,
+ endP3ControlReg,
+ endP0StatusReg,
+ endP1StatusReg,
+ endP2StatusReg,
+ endP3StatusReg,
+ endP0TransTypeReg,
+ endP1TransTypeReg,
+ endP2TransTypeReg,
+ endP3TransTypeReg,
+ endP0NAKTransTypeReg,
+ endP1NAKTransTypeReg,
+ endP2NAKTransTypeReg,
+ endP3NAKTransTypeReg,
+ clrEP0Rdy,
+ clrEP1Rdy,
+ clrEP2Rdy,
+ clrEP3Rdy);
+
+
+input clk;
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk;
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endPControlReg <= endP0ControlReg;
+ clrEP0Rdy <= clrEPRdy;
+ end
+ 2'b01: begin
+ endPControlReg <= endP1ControlReg;
+ clrEP1Rdy <= clrEPRdy;
+ end
+ 2'b10: begin
+ endPControlReg <= endP2ControlReg;
+ clrEP2Rdy <= clrEPRdy;
+ end
+ 2'b11: begin
+ endPControlReg <= endP3ControlReg;
+ clrEP3Rdy <= clrEPRdy;
+ end
+ endcase
+end
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+ if (rst) begin
+ endP0NAKTransTypeReg <= 2'b00;
+ endP1NAKTransTypeReg <= 2'b00;
+ endP2NAKTransTypeReg <= 2'b00;
+ endP3NAKTransTypeReg <= 2'b00;
+ endP0TransTypeReg <= 2'b00;
+ endP1TransTypeReg <= 2'b00;
+ endP2TransTypeReg <= 2'b00;
+ endP3TransTypeReg <= 2'b00;
+ endP0StatusReg <= 4'h0;
+ endP1StatusReg <= 4'h0;
+ endP2StatusReg <= 4'h0;
+ endP3StatusReg <= 4'h0;
+ end
+ else begin
+ if (endPMuxErrorsWEn == 1'b1) begin
+ if (NAKSent == 1'b1) begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0NAKTransTypeReg <= transTypeNAK;
+ endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
+ end
+ 2'b01: begin
+ endP1NAKTransTypeReg <= transTypeNAK;
+ endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
+ end
+ 2'b10: begin
+ endP2NAKTransTypeReg <= transTypeNAK;
+ endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
+ end
+ 2'b11: begin
+ endP3NAKTransTypeReg <= transTypeNAK;
+ endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
+ end
+ endcase
+ end
+ else begin
+ case (currEndP[1:0])
+ 2'b00: begin
+ endP0TransTypeReg <= transType;
+ endP0StatusReg <= endPStatusCombine;
+ end
+ 2'b01: begin
+ endP1TransTypeReg <= transType;
+ endP1StatusReg <= endPStatusCombine;
+ end
+ 2'b10: begin
+ endP2TransTypeReg <= transType;
+ endP2StatusReg <= endPStatusCombine;
+ end
+ 2'b11: begin
+ endP3TransTypeReg <= transType;
+ endP3StatusReg <= endPStatusCombine;
+ end
+ endcase
+ end
+ end
+ end
+end
+
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+ endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
endpMux.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slaveRxStatusMonitor.v
===================================================================
--- slaveRxStatusMonitor.v (nonexistent)
+++ slaveRxStatusMonitor.v (revision 40)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// slaveRxStatusMonitor.v ////
+//// ////
+//// This file is part of the usbhostslave opencores effort.
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+ connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst == 1'b1)
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ end
+ else
+ begin
+ oldConnectState <= connectStateIn;
+ oldResumeDetected <= resumeDetectedIn;
+ if (oldConnectState != connectStateIn)
+ resetEventOut <= 1'b1;
+ else
+ resetEventOut <= 1'b0;
+ if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+ resumeIntOut <= 1'b1;
+ else
+ resumeIntOut <= 1'b0;
+ end
+end
+
+endmodule
slaveRxStatusMonitor.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slaveSendpacket.asf
===================================================================
--- slaveSendpacket.asf (nonexistent)
+++ slaveSendpacket.asf (revision 40)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveSendPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
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+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
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+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
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+I 173 0 130 Builtin InPort | 35299,213676 "" ""
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+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
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+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
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+END
slaveSendpacket.asf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slavecontroller.asf
===================================================================
--- slavecontroller.asf (nonexistent)
+++ slavecontroller.asf (revision 40)
@@ -0,0 +1,408 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=863
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+ 30330,86104 25492,143212 35905,156667 46318,170122\
+ 96612,168665 117496,167729
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+L 819 820 0 TEXT "State Labels" | 67420,66064 1 0 0 "RESP"
+S 820 589 102404 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 67420,66064 6500 6500
+H 821 820 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 828 821 2 847 833 BEZIER "Transitions" | 143788,176826 110094,161523 73824,121282 61589,104841
+A 829 828 16 TEXT "Actions" | 74668,133998 1 0 0 "getPacketREn <= 1'b1;"
+W 830 821 1 847 832 BEZIER "Transitions" | 149052,177611 172803,163396 180803,116530 192775,92880
+C 831 830 0 TEXT "Conditions" | 112905,152704 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+I 832 821 0 Builtin Exit | 195662,92880
+S 833 821 106496 ELLIPSE "States" | 56676,100586 6500 6500
+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+S 847 821 114688 ELLIPSE "States" | 145546,183083 6500 6500
+I 862 0 2 Builtin OutPort | 120122,261308 "" ""
+L 861 862 0 TEXT "Labels" | 126122,261308 1 0 0 "endPointReadyToGetPkt"
+A 860 457 16 TEXT "Actions" | 93778,19821 1 0 0 "USBEndPControlRegCopy <= USBEndPControlReg;\nendPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT] ;"
+I 859 0 130 Builtin Signal | 35412,208838 "" ""
+L 858 859 0 TEXT "Labels" | 38412,208838 1 0 0 "USBEndPControlRegCopy[4:0]"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+I 587 589 0 Builtin Exit | 192962,45432
+I 588 589 0 Builtin Entry | 205195,243792
+L 848 847 0 TEXT "State Labels" | 145546,183083 1 0 0 "CHK_ISO\n/19/"
+I 850 821 0 Builtin Entry | 49920,240120
+W 851 821 0 850 839 BEZIER "Transitions" | 49920,237971 49996,228608 49199,210758 49275,201395
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
+ 187314,234737 186141,226528 176133,223346 166125,220164\
+ 127582,215026 108152,212765
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+A 599 601 16 TEXT "Actions" | 160934,183503 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 180237,108305 188996,66496 180453,87386 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 101725,211799 6500 6500
+W 606 589 0 588 800 BEZIER "Transitions" | 201176,243744 189026,243939 117602,246614 110257,246222
+C 607 601 0 TEXT "Conditions" | 120473,202106 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 62794,182643 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+ 41052,159480 41752,153900 40959,141711 40167,129522\
+ 46701,89176 50135,78506 53570,67837 54978,65340\
+ 57981,65109 60984,64878 60458,64813 61074,64659
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+ 162008,130636 151291,117855 140238,106874 129185,95894\
+ 77774,78896 71279,71294
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 116707,136533 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+ 46511,172964 33727,90292 34975,71611 36223,52930\
+ 35724,34993 37785,28932 39847,22872 46307,16188\
+ 54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+ 60053,165183 57484,160822 55722,148570 53960,136319\
+ 36935,95064 38880,77714 40826,60365 38327,20823\
+ 54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+ 108160,233400 112640,227800 113920,224400 115200,221000\
+ 116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+ 69948,104476 47394,95074 43302,84878 39210,74682\
+ 42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+ 39220,148925 36609,140943 36571,133460 36533,125977\
+ 38989,104026 47738,97617 56488,91209 87662,87731\
+ 103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+ 200304,203038 205920,186346 207441,167119 208962,147892\
+ 209430,87676 208962,71608 208494,55540 206154,51484\
+ 204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;\nUSBEndPControlRegCopy <= 5'b00000;\nendPointReadyToGetPkt <= 1'b0;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 82804,40533 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+ 46860,73975 46530,57145 47396,48771 48262,40398\
+ 52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+ 209214,43082 209522,23062 208983,17094 208444,11127\
+ 205980,7277 191773,6353 177567,5429 123205,5583\
+ 106804,9317 90403,13052 79161,27836 75696,31763\
+ 72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+ 53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+ 60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+ 105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 122196,51478 1 0 0 "Insert delay to allow USBEndP etc to update"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+ 197587,175015 201929,162657 202973,147251 204017,131846\
+ 203849,82580 202847,68719 201846,54859 198970,48147\
+ 197050,45058
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 69699,59883 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+H 805 800 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 800 589 98324 ELLIPSE "Junction" | 108538,243174 3500 3500
+L 801 800 0 TEXT "State Labels" | 108538,243174 1 0 0 "J4"
+W 802 805 0 804 803 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 803 805 0 Builtin Exit | 144780,101600
+I 804 805 0 Builtin Entry | 96520,152400
+W 807 589 2 800 617 BEZIER "Transitions" | 106097,240666 80398,219718 50449,190675 50573,178391
+W 810 589 3 800 587 BEZIER "Transitions" | 105040,243281 73377,254491 34925,221320 34178,196665\
+ 33432,172010 34721,79558 53522,54375 72324,29193\
+ 153226,30396 173104,33029 192983,35662 193169,40577\
+ 192962,43440
+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+END
slavecontroller.asf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sctxportarbiter.asf
===================================================================
--- sctxportarbiter.asf (nonexistent)
+++ sctxportarbiter.asf (revision 40)
@@ -0,0 +1,115 @@
+VERSION=1.21
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// SCTxPortArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
+BLOCKTABLE_FILE=""
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+END
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+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,530400 1 0 0 "Module: SCTxPortArbiter"
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+L 7 6 0 TEXT "Labels" | 153720,386820 1 0 0 "SCTxArb"
+S 8 6 12288 ELLIPSE "States" | 225591,382670 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,382670 1 0 0 "START_SARB\n/3/"
+S 10 6 0 ELLIPSE "States" | 224972,352339 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,350953 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 14 6 4096 ELLIPSE "States" | 269063,283692 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,283692 1 0 0 "SARB_SEND_PACKET\n/1/"
+I 16 6 0 Builtin Reset | 178237,383010
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,383010 187522,379237 210185,378778 219470,380486
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,376194 225070,371714 224938,363311 224784,358831
+W 19 6 4097 10 14 BEZIER "Transitions" | 229757,347941 236477,342379 258220,303210 265438,289087
+C 22 19 0 TEXT "Conditions" | 235353,345815 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,327240 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+A 25 8 2 TEXT "Actions" | 234434,398687 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+C 26 17 0 TEXT "Conditions" | 202073,378708 1 0 0 "rst"
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+ 288786,346672 287077,358761 282417,364209 277757,369657\
+ 274547,368787 268775,368864 263003,368942 254872,368666\
+ 248267,366271 241663,363877 234289,358857 230118,356308
+C 31 27 0 TEXT "Conditions" | 272024,302471 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,358479 1 0 0 "sendPacketGnt <= 1'b0;"
+I 35 0 2 Builtin OutPort | 164373,445096 "" ""
+L 36 35 0 TEXT "Labels" | 170373,445096 1 0 0 "SCTxPortWEnable"
+I 37 0 2 Builtin OutPort | 164033,473151 "" ""
+L 38 37 0 TEXT "Labels" | 170033,473151 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 189447,529426 "" ""
+L 40 39 0 TEXT "Labels" | 195447,529426 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 190061,523882 "" ""
+I 42 0 2 Builtin InPort | 166566,450081 "" ""
+L 43 42 0 TEXT "Labels" | 172566,450081 1 0 0 "SCTxPortRdyIn"
+I 44 0 130 Builtin InPort | 166169,486799 "" ""
+L 45 44 0 TEXT "Labels" | 172169,486799 1 0 0 "sendPacketData[7:0]"
+I 52 0 2 Builtin InPort | 165981,477939 "" ""
+L 53 52 0 TEXT "Labels" | 171981,477939 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 21871,406257 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n SCTxPortRdyOut <= SCTxPortRdyIn;\nend\n \nalways @(muxDCEn or\n directCntlWEn or directCntlData or directCntlCntl or\n directCntlWEn or directCntlData or directCntlCntl or\n sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n begin \n SCTxPortWEnable <= directCntlWEn;\n SCTxPortData <= directCntlData;\n SCTxPortCntl <= directCntlCntl;\n end\nelse\n begin \n SCTxPortWEnable <= sendPacketWEn;\n SCTxPortData <= sendPacketData;\n SCTxPortCntl <= sendPacketCntl;\n end\nend"
+I 56 0 2 Builtin InPort | 166286,468363 "" ""
+L 57 56 0 TEXT "Labels" | 172286,468363 1 0 0 "sendPacketReq"
+I 58 0 130 Builtin OutPort | 164296,440578 "" ""
+L 59 58 0 TEXT "Labels" | 170296,440578 1 0 0 "SCTxPortData[7:0]"
+L 61 41 0 TEXT "Labels" | 196061,523882 1 0 0 "clk"
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+L 63 62 0 TEXT "Labels" | 172256,482420 1 0 0 "sendPacketCntl[7:0]"
+I 64 0 2 Builtin OutPort | 164048,454434 "" ""
+L 65 64 0 TEXT "Labels" | 170048,454434 1 0 0 "SCTxPortRdyOut"
+I 66 0 130 Builtin OutPort | 164124,458856 "" ""
+L 67 66 0 TEXT "Labels" | 170124,458856 1 0 0 "SCTxPortCntl[7:0]"
+I 78 0 2 Builtin OutPort | 117944,444360 "" ""
+L 79 78 0 TEXT "Labels" | 123944,444360 1 0 0 "directCntlGnt"
+I 80 0 2 Builtin InPort | 120331,439767 "" ""
+L 81 80 0 TEXT "Labels" | 126331,439767 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,449241 "" ""
+L 83 82 0 TEXT "Labels" | 126527,449241 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,458649 "" ""
+L 85 84 0 TEXT "Labels" | 126256,458649 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,454026 "" ""
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+L 88 89 0 TEXT "Labels" | 144050,516112 1 0 0 "muxDCEn"
+I 89 0 2 Builtin Signal | 141050,516112 "" ""
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+A 95 92 16 TEXT "Actions" | 205993,298152 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
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+A 98 96 16 TEXT "Actions" | 290172,277428 1 0 0 "directCntlGnt <= 1'b0;"
+END
sctxportarbiter.asf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slaveGetpacket.asf
===================================================================
--- slaveGetpacket.asf (nonexistent)
+++ slaveGetpacket.asf (revision 40)
@@ -0,0 +1,292 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=294
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
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+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
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+W 288 120 1 137 287 BEZIER "Transitions" | 95908,234299 107108,237729 126700,246250 135590,247825\
+ 144480,249400 155451,246954 162031,246674
+W 289 120 0 287 150 BEZIER "Transitions" | 171165,238205 175575,227075 185570,206490 187145,196410\
+ 188720,186330 186200,168270 182490,161515 178780,154760\
+ 166460,145800 160440,144225 154420,142650 142660,145310\
+ 136360,146115 130060,146920 116620,147480 112140,147865\
+ 107660,148250 105485,148701 103245,149191
+C 290 288 0 TEXT "Conditions" | 109060,253040 1 0 0 "endPointReady == 1'b0"
+K 291 287 0 TEXT "Comments" | 165840,251410 1 0 0 "Discard data"
+L 292 293 0 TEXT "Labels" | 83089,231870 1 0 0 "SIERxTimeOutEn"
+I 293 0 2 Builtin OutPort | 77089,231870 "" ""
+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+ 190292,107515 191648,100057 191987,92429 192326,84802\
+ 192326,61750 188540,53162 184755,44574 169613,33274\
+ 159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+ 39882,146032 37743,135343 38221,127384 38700,119425\
+ 42750,98275 45281,87925 47812,77575 53888,57325\
+ 56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+ 26270,188186 26497,147369 28526,126511 30555,105653\
+ 38448,63032 43352,51475 48257,39919 60065,36353\
+ 65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+ 55031,85605 56613,76791 58364,71028 60116,65265\
+ 65540,51027 67235,46846 68930,42665 69902,40249\
+ 70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8194 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+ 122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,145171 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+ 136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8195 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+ 138686,69264 146640,68588 151838,68757 157036,68927\
+ 164174,70167 165417,70562 166660,70958 172486,71065\
+ 172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+ 99709,21131 138868,20336 151863,21045 164858,21755\
+ 177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+ 176686,205938 186055,195197 188340,185143 190625,175090\
+ 190396,145613 187654,132589 184913,119565 174172,96942\
+ 167317,90830 160463,84718 143756,82720 138170,83176\
+ 132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+ 145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+ 81676,46762 76804,63118 74237,72992 71671,82867\
+ 66277,106009 65842,118015 65407,130021 69061,154903\
+ 71671,163168 74281,171433 81067,179611 84373,181742\
+ 87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END
slaveGetpacket.asf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: slaveDirectcontrol.asf
===================================================================
--- slaveDirectcontrol.asf (nonexistent)
+++ slaveDirectcontrol.asf (revision 40)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveDirectControl\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 78
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 127
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
+W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
+I 13 6 0 Builtin Reset | 48900,215400
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_SDC\n/0/"
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "slvDrctCntl"
+F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: slaveDirectControl"
+C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
+W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
+W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
+H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
+W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
+A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "SCTxPortWEn <= 1'b0;"
+S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
+W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
+ 46421,89345 46021,97345 47471,100295 48921,103245\
+ 55748,105011 58848,106911
+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
+S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
+W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
+L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
+S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
+C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "SCTxPortGnt == 1'b1"
+W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "SCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+ 47285,153175 50048,167625 56316,171290 62585,174956\
+ 84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
+I 122 79 0 Builtin Exit | 138103,36586
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "SCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= 8'h00; \nSCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "SCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "SCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "SCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "SCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "SCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+ 171826,160150 159742,169266 150997,171704 142252,174142\
+ 120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "SCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "SCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121708,221292 1 0 0 "SCTxPortCntl <= 8'h00;\nSCTxPortData <= 8'h00;\nSCTxPortWEn <= 1'b0; \nSCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "SCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "SCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "SCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102262,47300 1 0 0 "SCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+END
slaveDirectcontrol.asf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property