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Rev 39 → Rev 40

/usbDeviceAlteraTop.v
0,0 → 1,425
//////////////////////////////////////////////////////////////////////
//// ////
//// usbDeviceAlteraTop.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module for Altera FPGA and NXP ISP1105 USB PHY.
//// Specifically it targets the Base2Designs Altera Development board.
//// Instantiates a PLL so that the lock signal can be used
//// to reset the logic, and ties unused control signals
//// to the off or disabled state
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`define PHY_ISP1105
module usbDeviceAlteraTop (
 
//
// Global signals
//
clk,
 
//
// SDRAM
//
mc_addr,
mc_ba,
mc_dqm,
mc_we_,
mc_cas_,
mc_ras_,
mc_cke_,
sdram_cs,
sdram_clk,
 
//
// SPI bus
//
spiClk,
spiMasterDataOut,
spiCS_n,
 
 
//
// USB host
//
//usbHostOE_n,
 
//
// USB slave
//
//usbSlaveVP,
//usbSlaveVM,
 
//usbSlaveOE_n,
//usbDPlusPullup,
//vBusDetect,
 
//
// Santa Cruz header
//
SC_P_CLK,
SC_RST_N,
SC_CS_N,
SC_P0,
SC_P1,
SC_P2,
SC_P3,
SC_P4,
SC_P5,
SC_P6,
SC_P7,
SC_P8,
SC_P9,
SC_P10,
SC_P11,
SC_P12,
SC_P13,
SC_P14,
SC_P15,
SC_P16,
SC_P17,
SC_P18,
SC_P19,
SC_P20,
SC_P21,
SC_P22,
SC_P23,
SC_P24,
SC_P25,
SC_P26,
SC_P27,
SC_P28,
SC_P29,
SC_P30,
SC_P31,
SC_P32,
SC_P33,
SC_P34,
SC_P35,
SC_P36,
SC_P37,
SC_P38,
SC_P39
 
 
 
);
//
// Global signals
//
input clk;
 
//
// SDRAM
//
output [11:0] mc_addr;
output [1:0] mc_ba;
output [3:0] mc_dqm;
output mc_we_;
output mc_cas_;
output mc_ras_;
output mc_cke_;
output sdram_cs;
output sdram_clk;
 
//
// SPI bus
//
output spiClk;
output spiMasterDataOut;
output spiCS_n;
 
//
// USB host
//
//output usbHostOE_n;
 
//
// USB slave
//
//inout usbSlaveVP;
//inout usbSlaveVM;
 
//output usbSlaveOE_n;
//output usbDPlusPullup;
//input vBusDetect;
 
`ifdef PHY_ISP1105
output SC_P_CLK;
output SC_RST_N;
output SC_CS_N;
output SC_P0;
output SC_P1;
output SC_P2;
output SC_P3;
output SC_P4;
output SC_P5;
output SC_P6;
output SC_P7;
output SC_P8;
output SC_P9;
output SC_P10;
output SC_P11;
output SC_P12;
output SC_P13;
output SC_P14;
output SC_P15;
output SC_P16;
output SC_P17;
output SC_P18;
output SC_P19;
input SC_P20;
output SC_P21;
inout SC_P22;
inout SC_P23;
output SC_P24;
output SC_P25;
output SC_P26;
output SC_P27;
output SC_P28;
output SC_P29;
output SC_P30;
output SC_P31;
output SC_P32;
output SC_P33;
output SC_P34;
output SC_P35;
output SC_P36;
output SC_P37;
output SC_P38;
output SC_P39;
`else
output SC_P_CLK;
output SC_RST_N;
output SC_CS_N;
output SC_P0;
output SC_P1;
input SC_P2;
output SC_P3;
input SC_P4;
output SC_P5;
output SC_P6;
output SC_P7;
output SC_P8;
output SC_P9;
output SC_P10;
output SC_P11;
output SC_P12;
output SC_P13;
output SC_P14;
output SC_P15;
output SC_P16;
output SC_P17;
output SC_P18;
output SC_P19;
output SC_P20;
output SC_P21;
input SC_P22;
output SC_P23;
input SC_P24;
output SC_P25;
output SC_P26;
output SC_P27;
output SC_P28;
output SC_P29;
output SC_P30;
output SC_P31;
output SC_P32;
output SC_P33;
output SC_P34;
output SC_P35;
output SC_P36;
output SC_P37;
output SC_P38;
output SC_P39;
`endif
 
 
 
//local wires and regs
reg [1:0] rstReg;
wire rst;
wire pll_locked;
wire usbSlaveVP_in;
wire usbSlaveVM_in;
wire usbSlaveVP_out;
wire usbSlaveVM_out;
wire usbSlaveFullSpeed;
 
assign mc_addr = {12{1'b0}};
assign mc_ba = 2'b00;
assign mc_dqm = 4'h0;
assign mc_we_ = 1'b1;
assign mc_cas_ = 1'b1;
assign mc_ras_ = 1'b1;
assign mc_cke_ = 1'b1;
assign sdram_cs = 1'b1;
assign sdram_clk = 1'b1;
assign spiClk = 1'b0;
assign spiMasterDataOut = 1'b0;
assign spiCS_n = 1'b1;
assign usbHostOE_n = 1'b1;
 
pll_48MHz pll_48MHz_inst (
.inclk0 ( clk ),
.locked( pll_locked)
);
 
//generate sync reset from pll lock signal
always @(posedge clk) begin
rstReg[1:0] <= {rstReg[0], ~pll_locked};
end
assign rst = rstReg[1];
 
 
usbDevice u_usbDevice (
.clk(clk),
.rst(rst),
.usbSlaveVP_in(usbSlaveVP_in),
.usbSlaveVM_in(usbSlaveVM_in),
.usbSlaveVP_out(usbSlaveVP_out),
.usbSlaveVM_out(usbSlaveVM_out),
.usbSlaveOE_n(usbSlaveOE_n),
.USBFullSpeed(usbSlaveFullSpeed),
.usbDPlusPullup(usbDPlusPullup),
.usbDMinusPullup(usbDMinusPullup),
.vBusDetect(vBusDetect)
);
 
`ifdef PHY_ISP1105
assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
`else
assign vBusDetect = 1'b1;
`endif
 
`ifdef PHY_ISP1105
assign SC_P_CLK = 1'b0;
assign SC_RST_N = 1'b0;
assign SC_CS_N = 1'b0;
assign SC_P0 = 1'b0;
assign SC_P1 = 1'b0;
assign SC_P2 = 1'b0;
assign SC_P3 = 1'b0;
assign SC_P4 = 1'b0;
assign SC_P5 = 1'b0;
assign SC_P6 = 1'b0;
assign SC_P7 = 1'b0;
assign SC_P8 = 1'b0;
assign SC_P9 = 1'b0;
assign SC_P10 = 1'b0;
assign SC_P11 = 1'b0;
assign SC_P12 = 1'b0;
assign SC_P13 = 1'b0;
assign SC_P14 = 1'b0;
assign SC_P15 = 1'b0;
assign SC_P16 = 1'b0;
assign SC_P17 = 1'b0;
assign SC_P18 = 1'b0;
assign SC_P19 = 1'b0;
assign vBusDetect = SC_P20;
assign SC_P21 = 1'b0;
assign SC_P22 = usbSlaveVM;
assign SC_P23 = usbSlaveVP;
assign SC_P24 = usbSlaveOE_n;
assign SC_P25 = 1'b0;
assign SC_P26 = usbDPlusPullup;
assign SC_P27 = 1'b0;
assign SC_P28 = usbHostOE_n;
assign SC_P29 = 1'b0;
assign SC_P30 = 1'b0;
assign SC_P31 = 1'b0;
assign SC_P32 = 1'b0;
assign SC_P33 = 1'b0;
assign SC_P34 = 1'b0;
assign SC_P35 = 1'b0;
assign SC_P36 = 1'b0;
assign SC_P37 = 1'b0;
assign SC_P38 = 1'b0;
assign SC_P39 = 1'b0;
`else
assign SC_P_CLK = 1'b0;
assign SC_RST_N = 1'b0;
assign SC_CS_N = 1'b0;
assign SC_P0 = usbSlaveFullSpeed;
assign SC_P1 = 1'b0;
assign usbSlaveVM_in = SC_P2;
assign SC_P3 = 1'b0;
assign usbSlaveVP_in = SC_P4;
assign SC_P5 = 1'b0;
assign SC_P6 = usbSlaveOE_n;
assign SC_P7 = 1'b0;
assign SC_P8 = usbSlaveVM_out;
assign SC_P9 = 1'b0;
assign SC_P10 = usbSlaveVP_out;
assign SC_P11 = 1'b0;
assign SC_P12 = usbDPlusPullup;
assign SC_P13 = 1'b0;
assign SC_P14 = usbDMinusPullup;
assign SC_P15 = 1'b0;
assign SC_P16 = 1'b0;
assign SC_P17 = 1'b0;
assign SC_P18 = 1'b0;
assign SC_P19 = 1'b0;
assign SC_P20 = 1'b0;
assign SC_P21 = 1'b0;
assign usbHostVM_in = SC_P22;
assign SC_P23 = 1'b0;
assign usbHostVP_in = SC_P24;
assign SC_P25 = usbHostOE_n;
assign SC_P26 = 1'b0;
assign SC_P27 = 1'b0;
assign SC_P28 = 1'b0;
assign SC_P29 = 1'b0;
assign SC_P30 = 1'b0;
assign SC_P31 = 1'b0;
assign SC_P32 = 1'b0;
assign SC_P33 = 1'b0;
assign SC_P34 = 1'b0;
assign SC_P35 = 1'b0;
assign SC_P36 = 1'b0;
assign SC_P37 = 1'b0;
assign SC_P38 = 1'b0;
assign SC_P39 = 1'b0;
`endif
 
 
 
endmodule
 
 
/usbDevice.v
0,0 → 1,235
//////////////////////////////////////////////////////////////////////
//// ////
//// usbDevice.v ////
//// ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module for usbDevice
//// Instantiates a usbSlave, and controllers for EP0 and EP1
//// If you wish to implement another type of HID, then you will
//// need to modify usbROM.v, and EP1Mouse.v
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
 
module usbDevice (
clk,
rst,
usbSlaveVP_in,
usbSlaveVM_in,
usbSlaveVP_out,
usbSlaveVM_out,
usbSlaveOE_n,
USBFullSpeed,
usbDPlusPullup,
usbDMinusPullup,
vBusDetect
);
 
input clk;
input rst;
input usbSlaveVP_in;
input usbSlaveVM_in;
output usbSlaveVP_out;
output usbSlaveVM_out;
output usbSlaveOE_n;
output USBFullSpeed;
output usbDPlusPullup;
output usbDMinusPullup;
input vBusDetect;
 
//local wires and regs
wire [7:0] wb_addr0;
wire wb_stb0;
wire wb_we0;
wire wbBusReq0;
wire wbBusGnt0;
wire [7:0] wb_addr1;
wire [7:0] wb_data_o1;
wire wb_stb1;
wire wb_we1;
wire wbBusReq1;
wire wbBusGnt1;
wire [7:0] wb_addr2;
wire [7:0] wb_data_o2;
wire wb_stb2;
wire wb_we2;
wire wbBusReq2;
wire wbBusGnt2;
wire [7:0] wb_adr;
wire [7:0] wb_dat_to_usb;
wire [7:0] wb_dat_from_usb;
wire wb_we;
wire wb_stb;
wire wb_ack;
reg [1:0] resetReg;
wire initComplete;
wire usbRstDet;
wire [7:0] memAddr;
wire [7:0] memData;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
 
 
//Parameters declaration:
defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
usbSlave usbSlaveInst (
.clk_i(clk),
.rst_i(rst),
.address_i(wb_adr),
.data_i(wb_dat_to_usb),
.data_o(wb_dat_from_usb),
.we_i(wb_we),
.strobe_i(wb_stb),
.ack_o(wb_ack),
.usbClk(clk),
.slaveSOFRxedIntOut(),
.slaveResetEventIntOut(),
.slaveResumeIntOut(),
.slaveTransDoneIntOut(),
.slaveNAKSentIntOut(),
.slaveVBusDetIntOut(),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed),
.USBDPlusPullup(usbDPlusPullup),
.USBDMinusPullup(usbDMinusPullup),
.vBusDetect(vBusDetect)
);
 
assign USBWireDataIn = {usbSlaveVP_in, usbSlaveVM_in};
assign {usbSlaveVP_out, usbSlaveVM_out} = USBWireDataOut;
assign usbSlaveOE_n = ~USBWireCtrlOut;
 
checkLineState u_checkLineState (
.clk(clk),
.rst(rst),
.initComplete(initComplete),
.usbRstDet(usbRstDet),
.wb_ack(wb_ack),
.wb_addr(wb_addr0),
.wb_data_i(wb_dat_from_usb),
.wb_stb(wb_stb0),
.wb_we(wb_we0),
.wbBusGnt(wbBusGnt0),
.wbBusReq(wbBusReq0)
);
 
 
EP0 u_EP0 (
.clk(clk),
.rst(rst | usbRstDet),
.initComplete(initComplete),
.wb_ack(wb_ack),
.wb_addr(wb_addr1),
.wb_data_i(wb_dat_from_usb),
.wb_data_o(wb_data_o1),
.wb_stb(wb_stb1),
.wb_we(wb_we1),
.wbBusGnt(wbBusGnt1),
.wbBusReq(wbBusReq1),
.memAddr(memAddr),
.memData(memData),
.memRdEn()
);
 
usbROM u_usbROM (
.clk(clk),
.addr(memAddr),
.data(memData)
);
 
 
EP1Mouse u_EP1Mouse (
.clk(clk),
.rst(rst | usbRstDet),
.initComplete(initComplete),
.wb_ack(wb_ack),
.wb_addr(wb_addr2),
.wb_data_i(wb_dat_from_usb),
.wb_data_o(wb_data_o2),
.wb_stb(wb_stb2),
.wb_we(wb_we2),
.wbBusGnt(wbBusGnt2),
.wbBusReq(wbBusReq2)
);
 
wishboneArb u_wishboneArb (
.clk(clk),
.rst(rst),
 
.addr0_i(wb_addr0),
.data0_i(8'h00),
.stb0_i(wb_stb0),
.we0_i(wb_we0),
.req0(wbBusReq0),
.gnt0(wbBusGnt0),
 
.addr1_i(wb_addr1),
.data1_i(wb_data_o1),
.stb1_i(wb_stb1),
.we1_i(wb_we1),
.req1(wbBusReq1),
.gnt1(wbBusGnt1),
 
.addr2_i(wb_addr2),
.data2_i(wb_data_o2),
.stb2_i(wb_stb2),
.we2_i(wb_we2),
.req2(wbBusReq2),
.gnt2(wbBusGnt2),
 
 
.addr_o(wb_adr),
.data_o(wb_dat_to_usb),
.stb_o(wb_stb),
.we_o(wb_we)
);
 
 
endmodule
 
/usbROM_logitech_mouse.v
0,0 → 1,213
// ----------------------------- usbROM ---------------------------
// if you modify this file, be sure to modify usbDevice_define.v
// Using RAM rather than logic resources might be a more efficient implememtation
// but this has the advantage of working with FPGAs that do not provide a
// mechanism for initialising RAM, eg Actel IGLOO
// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice
`include "usbDevice_define.v"
 
 
module usbROM (
clk,
addr,
data
);
input clk;
input [7:0] addr;
output [7:0] data;
reg [7:0] data;
 
always @(posedge clk) begin
case (addr)
// ====================================
// ===== DEVICE Descriptor =====
// ====================================
 
8'h00: data <= 8'h12; //BYTE bLength
8'h01: data <= 8'h01; //BYTE bDescriptorType
8'h02: data <= 8'h10; //WORD (Lo) bcdUSB version supported
8'h03: data <= 8'h01; //WORD (Hi) bcdUSB version supported
8'h04: data <= 8'h00; //BYTE bDeviceClass
8'h05: data <= 8'h00; //BYTE bDeviceSubClass
8'h06: data <= 8'h00; //BYTE bDeviceProtocol
8'h07: data <= `MAX_RESP_SIZE; //BYTE bMaxPacketSize
8'h08: data <= 8'h6d; //WORD (Lo) idVendor
8'h09: data <= 8'h04; //WORD (Hi) idVendor
8'h0a: data <= 8'h3d; //WORD (Lo) idProduct; For Logitech mouse
8'h0b: data <= 8'hc0; //WORD (Hi) idProduct; For Logitech Hub mouse
8'h0c: data <= 8'h00; //WORD (Lo) bcdDevice
8'h0d: data <= 8'h20; //WORD (Hi) bcdDevice
8'h0e: data <= 8'h01; //BYTE iManufacturer
8'h0f: data <= 8'h02; //BYTE iProduct
8'h10: data <= 8'h00; //BYTE iSerialNumber
8'h11: data <= 8'h01; //BYTE bNumConfigurations
 
// ====================================
// ===== Configuration Descriptor =====
// ====================================
8'h12: data <= 8'h09; //BYTE bLength (Configuration descriptor)
8'h13: data <= 8'h02; //BYTE bDescriptorType //Assigned by USB
8'h14: data <= 8'h22; //WORD (Lo) wTotalLength
8'h15: data <= 8'h00; //WORD (Hi) wTotalLength
8'h16: data <= 8'h01; //BYTE bNumInterfaces
8'h17: data <= 8'h01; //BYTE bConfigurationValue
8'h18: data <= 8'h00; //BYTE iConfiguration
8'h19: data <= 8'ha0; //BYTE bmAttributes, Bus powered and remote wakeup
8'h1a: data <= 8'h31; //BYTE MaxPower, 98mA
// ====================================
// ===== Interface Descriptor =====
// ====================================
8'h1b: data <= 8'h09; //BYTE bLength (Interface descriptor)
8'h1c: data <= 8'h04; //BYTE bDescriptionType; assigned by USB
8'h1d: data <= 8'h00; //BYTE bInterfaceNumber
8'h1e: data <= 8'h00; //BYTE bAlternateSetting
8'h1f: data <= 8'h01; //BYTE bNumEndpoints; uses 1 endpoints
8'h20: data <= 8'h03; //BYTE bInterfaceClass; HID Class - 0x03
8'h21: data <= 8'h01; //BYTE bInterfaceSubClass
8'h22: data <= 8'h02; //BYTE bInterfaceProtocol
8'h23: data <= 8'h00; //BYTE iInterface
// ====================================
// ===== HID Descriptor =====
// ====================================
8'h24: data <= 8'h09; //BYTE bLength (HID Descriptor)
8'h25: data <= 8'h21; //BYTE bDescriptorType
8'h26: data <= 8'h10; //WORD (Lo) bcdHID
8'h27: data <= 8'h01; //WORD (Hi) bcdHID
8'h28: data <= 8'h00; //BYTE bCountryCode
8'h29: data <= 8'h01; //BYTE bNumDescriptors
8'h2a: data <= 8'h22; //BYTE bReportDescriptorType
8'h2b: data <= 8'h32; //WORD (Lo) wItemLength
8'h2c: data <= 8'h00; //WORD (Hi) wItemLength
 
// ====================================
// ===== Endpoint 1 Descriptor =====
// ====================================
8'h2d: data <= 8'h07; //BYTE bLength (Endpoint Descriptor)
8'h2e: data <= 8'h05; //BYTE bDescriptorType; assigned by USB
8'h2f: data <= 8'h81; //BYTE bEndpointAddress; IN endpoint; endpoint 1
8'h30: data <= 8'h03; //BYTE bmAttributes; Interrupt endpoint
8'h31: data <= 8'h04; //WORD (Lo) wMaxPacketSize
8'h32: data <= 8'h00; //WORD (Hi) wMaxPacketSize
8'h33: data <= 8'h0a; //BYTE bInterval
 
// ====================================
// ===== Report Descriptor =====
// ====================================
 
8'h3a: data <= 8'h05; 8'h3b: data <= 8'h01; // USAGE_PAGE (Generic Desktop)
8'h3c: data <= 8'h09; 8'h3d: data <= 8'h02; // USAGE (Mouse)
8'h3e: data <= 8'ha1; 8'h3f: data <= 8'h01; // COLLECTION (Application)
8'h40: data <= 8'h09; 8'h41: data <= 8'h01; // USAGE (Pointer)
8'h42: data <= 8'ha1; 8'h43: data <= 8'h00; // COLLECTION (Physical)
8'h44: data <= 8'h05; 8'h45: data <= 8'h09; // USAGE_PAGE (Button)
8'h46: data <= 8'h19; 8'h47: data <= 8'h01; // USAGE_MINIMUM (Button 1)
8'h48: data <= 8'h29; 8'h49: data <= 8'h03; // USAGE_MAXIMUM (Button 3)
8'h4a: data <= 8'h15; 8'h4b: data <= 8'h00; // LOGICAL_MINIMUM (0)
8'h4c: data <= 8'h25; 8'h4d: data <= 8'h01; // LOGICAL_MAXIMUM (1)
8'h4e: data <= 8'h95; 8'h4f: data <= 8'h03; // REPORT_COUNT (3)
8'h50: data <= 8'h75; 8'h51: data <= 8'h01; // REPORT_SIZE (1)
8'h52: data <= 8'h81; 8'h53: data <= 8'h02; // INPUT (Data,Var,Abs)
8'h54: data <= 8'h95; 8'h55: data <= 8'h05; // REPORT_COUNT (5)
8'h56: data <= 8'h81; 8'h57: data <= 8'h03; // INPUT (Cnst,Var,Rel)
8'h58: data <= 8'h05; 8'h59: data <= 8'h01; // USAGE_PAGE (Generic Desktop)
8'h5a: data <= 8'h09; 8'h5b: data <= 8'h30; // USAGE (X)
8'h5c: data <= 8'h09; 8'h5d: data <= 8'h31; // USAGE (Y)
8'h5e: data <= 8'h09; 8'h5f: data <= 8'h38; // USAGE ?
8'h60: data <= 8'h15; 8'h61: data <= 8'h81; // LOGICAL_MINIMUM (-127)
8'h62: data <= 8'h25; 8'h63: data <= 8'h7f; // LOGICAL_MAXIMUM (127)
8'h64: data <= 8'h75; 8'h65: data <= 8'h08; // REPORT_SIZE (8)
8'h66: data <= 8'h95; 8'h67: data <= 8'h03; // REPORT_COUNT (3)
8'h68: data <= 8'h81; 8'h69: data <= 8'h06; // INPUT (Data,Var,Rel)
8'h6a: data <= 8'hc0; //END_COLLECTION
8'h6b: data <= 8'hc0; // END_COLLECTION
 
// ZERO_ZERO
8'h6c: data <= 8'h00;
8'h6d: data <= 8'h00;
// ONE_ZERO
8'h6e: data <= 8'h01;
8'h6f: data <= 8'h00;
// Vendor data
8'h70: data <= 8'h00;
8'h71: data <= 8'h00;
 
// =============================================
// ===== Language ID Descriptor(String0) =====
// =============================================
8'h80: data <= 8'h04; // bLength
8'h81: data <= 8'h03; // bDescriptorType = String Desc
8'h82: data <= 8'h09; // wLangID (Lo) (Lang ID for English = 0x0409)
8'h83: data <= 8'h04; // wLangID (Hi) (Lang ID for English = 0x0409)
 
// ====================================
// ===== string 1 Descriptor =====
// ====================================
8'h90: data <= 8'd26; // bLength
8'h91: data <= 8'h03; // bDescriptorType = String Desc
// Noting that text is always unicode, hence the 'padding'
8'h92: data <= "B"; 8'h93: data <= 8'h00;
8'h94: data <= "a"; 8'h95: data <= 8'h00;
8'h96: data <= "s"; 8'h97: data <= 8'h00;
8'h98: data <= "e"; 8'h99: data <= 8'h00;
8'h9a: data <= "2"; 8'h9b: data <= 8'h00;
8'h9c: data <= "D"; 8'h9d: data <= 8'h00;
8'h9e: data <= "e"; 8'h9f: data <= 8'h00;
8'ha0: data <= "s"; 8'ha1: data <= 8'h00;
8'ha2: data <= "i"; 8'ha3: data <= 8'h00;
8'ha4: data <= "g"; 8'ha5: data <= 8'h00;
8'ha6: data <= "n"; 8'ha7: data <= 8'h00;
8'ha8: data <= "s"; 8'ha9: data <= 8'h00;
 
 
 
// ====================================
// ===== string 2 Descriptor =====
// ====================================
8'hb0: data <= 8'd20; // bLength
8'hb1: data <= 8'h03; // bDescriptorType = String Desc
// Noting that text is always unicode, hence the 'padding'
8'hb2: data <= "B"; 8'hb3: data <= 8'h00;
8'hb4: data <= "2"; 8'hb5: data <= 8'h00;
8'hb6: data <= "D"; 8'hb7: data <= 8'h00;
8'hb8: data <= " "; 8'hb9: data <= 8'h00;
8'hba: data <= "M"; 8'hbb: data <= 8'h00;
8'hbc: data <= "o"; 8'hbd: data <= 8'h00;
8'hbe: data <= "u"; 8'hbf: data <= 8'h00;
8'hc0: data <= "s"; 8'hc1: data <= 8'h00;
8'hc2: data <= "e"; 8'hc3: data <= 8'h00;
 
// ====================================
// ===== string 3 Descriptor =====
// ====================================
8'hd0: data <= 8'd30; // bLength
8'hd1: data <= 8'h03; // bDescriptorType = String Desc
// Noting that text is always unicode, hence the 'padding'
8'hd2: data <= "L"; 8'hd3: data <= 8'h00;
8'hd4: data <= "i"; 8'hd5: data <= 8'h00;
8'hd6: data <= "m"; 8'hd7: data <= 8'h00;
8'hd8: data <= "i"; 8'hd9: data <= 8'h00;
8'hda: data <= "t"; 8'hdb: data <= 8'h00;
8'hdc: data <= "e"; 8'hdd: data <= 8'h00;
8'hde: data <= "d"; 8'hdf: data <= 8'h00;
8'he0: data <= "E"; 8'he1: data <= 8'h00;
8'he2: data <= "d"; 8'he3: data <= 8'h00;
8'he4: data <= "i"; 8'he5: data <= 8'h00;
8'he6: data <= "t"; 8'he7: data <= 8'h00;
8'he8: data <= "i"; 8'he9: data <= 8'h00;
8'hea: data <= "o"; 8'heb: data <= 8'h00;
8'hec: data <= "n"; 8'hed: data <= 8'h00;
 
 
 
default: data <= 8'h00;
endcase
end
 
endmodule
 
 
/EP1Mouse.v
0,0 → 1,295
 
//////////////////////////////////////////////////////////////////////
//// ////
//// EP1Mouse.v ////
//// ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Implements EP1 as a IN endpoint
//// simulating a mouse (a broken one) by
//// responding to IN requests with a constant (x,y) <= (1,1)
//// which causes the mouse pointer to move from
//// top left to bottom right of the screen
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostSlaveReg_define.v"
 
module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
input clk;
input initComplete;
input rst;
input wb_ack;
input [7:0]wb_data_i;
input wbBusGnt;
output [7:0]wb_addr;
output [7:0]wb_data_o;
output wb_stb;
output wb_we;
output wbBusReq;
 
wire clk;
wire initComplete;
wire rst;
wire wb_ack;
reg [7:0]wb_addr, next_wb_addr;
wire [7:0]wb_data_i;
reg [7:0]wb_data_o, next_wb_data_o;
reg wb_stb, next_wb_stb;
reg wb_we, next_wb_we;
wire wbBusGnt;
reg wbBusReq, next_wbBusReq;
 
// diagram signals declarations
reg [7:0]cnt, next_cnt;
reg dataSeq, next_dataSeq;
reg localRst, next_localRst;
reg transDone, next_transDone;
 
// BINARY ENCODED state machine: EP1St
// State codes definitions:
`define DO_TRANS_WT_GNT 4'b0000
`define DO_TRANS_TX_EMPTY 4'b0001
`define DO_TRANS_WR_TX_FIFO1 4'b0010
`define DO_TRANS_TRANS_GO 4'b0011
`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100
`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101
`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110
`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111
`define START 4'b1000
`define DO_TRANS_WR_TX_FIFO2 4'b1001
`define DO_TRANS_WR_TX_FIFO3 4'b1010
`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011
 
reg [3:0]CurrState_EP1St, NextState_EP1St;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: EP1St
 
// NextState logic (combinatorial)
always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St)
begin
NextState_EP1St <= CurrState_EP1St;
// Set default values for outputs and signals
next_wbBusReq <= wbBusReq;
next_wb_addr <= wb_addr;
next_wb_data_o <= wb_data_o;
next_wb_stb <= wb_stb;
next_wb_we <= wb_we;
next_dataSeq <= dataSeq;
next_transDone <= transDone;
next_cnt <= cnt;
case (CurrState_EP1St) // synopsys parallel_case full_case
`START:
begin
next_wbBusReq <= 1'b0;
next_wb_addr <= 8'h00;
next_wb_data_o <= 8'h00;
next_wb_stb <= 1'b0;
next_wb_we <= 1'b0;
next_cnt <= 8'h00;
next_dataSeq <= 1'b0;
next_transDone <= 1'b0;
if (initComplete == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WT_GNT;
end
end
`DO_TRANS_WT_GNT:
begin
next_wbBusReq <= 1'b1;
if (wbBusGnt == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_TX_EMPTY;
end
end
`DO_TRANS_TX_EMPTY:
begin
next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG;
next_wb_data_o <= 8'h01;
//force tx fifo empty
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1;
next_wb_stb <= 1'b0;
next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG;
next_wb_we <= 1'b1;
end
end
`DO_TRANS_WR_TX_FIFO1:
begin
next_wb_data_o <= 8'h00;
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2;
next_wb_stb <= 1'b0;
end
end
`DO_TRANS_TRANS_GO:
begin
next_wb_addr <= `RA_EP1_CONTROL_REG;
if (dataSeq == 1'b1)
next_wb_data_o <= 8'h07;
else
next_wb_data_o <= 8'h03;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
next_wb_stb <= 1'b0;
if (dataSeq == 1'b1)
next_dataSeq <= 1'b0;
else
next_dataSeq <= 1'b1;
next_transDone <= 1'b0;
end
end
`DO_TRANS_WR_TX_FIFO2:
begin
next_wb_data_o <= 8'h01;
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3;
next_wb_stb <= 1'b0;
end
end
`DO_TRANS_WR_TX_FIFO3:
begin
next_wb_data_o <= 8'h01;
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_TRANS_GO;
next_wb_stb <= 1'b0;
end
end
`DO_TRANS_WT_TRANS_DONE_WT_GNT:
begin
next_wbBusReq <= 1'b1;
if (wbBusGnt == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
end
end
`DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
begin
next_wb_addr <= `RA_EP1_CONTROL_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if (wb_ack == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
next_wb_stb <= 1'b0;
next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
end
end
`DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
begin
next_wbBusReq <= 1'b0;
if (wbBusGnt == 1'b0)
begin
NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
end
end
`DO_TRANS_WT_TRANS_DONE_CHK_DONE:
begin
if (transDone == 1'b1)
begin
NextState_EP1St <= `DO_TRANS_WT_GNT;
end
else
begin
NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL;
next_cnt <= 8'h00;
end
end
`DO_TRANS_WT_TRANS_DONE_DEL:
begin
next_cnt <= cnt + 1'b1;
if (cnt == `ONE_USEC_DEL)
begin
NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
end
end
endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_EP1St <= `START;
else
CurrState_EP1St <= NextState_EP1St;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
wbBusReq <= 1'b0;
wb_addr <= 8'h00;
wb_data_o <= 8'h00;
wb_stb <= 1'b0;
wb_we <= 1'b0;
dataSeq <= 1'b0;
transDone <= 1'b0;
cnt <= 8'h00;
end
else
begin
wbBusReq <= next_wbBusReq;
wb_addr <= next_wb_addr;
wb_data_o <= next_wb_data_o;
wb_stb <= next_wb_stb;
wb_we <= next_wb_we;
dataSeq <= next_dataSeq;
transDone <= next_transDone;
cnt <= next_cnt;
end
end
 
endmodule
/pll_48MHz.v
0,0 → 1,278
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll_48MHz.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_48MHz (
inclk0,
locked);
 
input inclk0;
output locked;
 
wire sub_wire0;
wire [0:0] sub_wire3 = 1'h0;
wire locked = sub_wire0;
wire sub_wire1 = inclk0;
wire [1:0] sub_wire2 = {sub_wire3, sub_wire1};
 
altpll altpll_component (
.inclk (sub_wire2),
.locked (sub_wire0),
.activeclock (),
.areset (1'b0),
.clk (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20833,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_48MHz",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_UNUSED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_48MHz.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_waveforms.html TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
/usbDevice_define.v
0,0 → 1,48
// ----------------------------- usbDevice_define ---------------------------
 
`define ZERO_ZERO_STAT_INDEX 8'h6c
`define ONE_ZERO_STAT_INDEX 8'h6e
`define VENDOR_DATA_STAT_INDEX 8'h70
`define DEV_DESC_INDEX 8'h00
`define DEV_DESC_SIZE 8'h12
//config descriptor is bundled with interface desc, HID desc, and EP1 desc
`define CFG_DESC_INDEX 8'h12
`define CFG_DESC_SIZE 8'h22
`define REP_DESC_INDEX 8'h3a
`define REP_DESC_SIZE 8'h32
`define LANGID_DESC_INDEX 8'h80
`define LANGID_DESC_SIZE 8'h04
`define STRING1_DESC_INDEX 8'h90
`define STRING1_DESC_SIZE 8'd26
`define STRING2_DESC_INDEX 8'hb0
`define STRING2_DESC_SIZE 8'd20
`define STRING3_DESC_INDEX 8'hd0
`define STRING3_DESC_SIZE 8'd30
 
`define DEV_DESC 8'h01
`define CFG_DESC 8'h02
`define REP_DESC 8'h22
`define STRING_DESC 8'h03
 
//delays at 48MHz
`ifdef SIM_COMPILE
`define ONE_MSEC_DEL 16'h0300
`else
`define ONE_MSEC_DEL 16'hbb80
`endif
`define ONE_USEC_DEL 8'h30
 
`define GET_STATUS 8'h00
`define CLEAR_FEATURE 8'h01
`define SET_FEATURE 8'h03
`define SET_ADDRESS 8'h05
`define GET_DESCRIPTOR 8'h06
`define SET_DESCRIPTOR 8'h07
`define GET_CONFIG 8'h08
`define SET_CONFIG 8'h09
`define GET_INTERFACE 8'h0a
`define SET_INTERFACE 8'h0b
`define SYNCH_FRAME 8'h0c
 
`define MAX_RESP_SIZE 8'h40
 
/wishboneArb.v
0,0 → 1,218
//////////////////////////////////////////////////////////////////////
//// ////
//// wishboneArb.v ////
//// ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Arbitrate between 3 wishbone bus controllers
//// Uses Round Robin access controller
////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
module wishboneArb (
clk,
rst,
 
addr0_i,
data0_i,
stb0_i,
we0_i,
req0,
gnt0,
 
addr1_i,
data1_i,
stb1_i,
we1_i,
req1,
gnt1,
 
addr2_i,
data2_i,
stb2_i,
we2_i,
req2,
gnt2,
 
 
addr_o,
data_o,
stb_o,
we_o
);
 
input clk;
input rst;
 
input [7:0] addr0_i;
input [7:0] data0_i;
input stb0_i;
input we0_i;
input req0;
output gnt0;
reg gnt0;
 
input [7:0] addr1_i;
input [7:0] data1_i;
input stb1_i;
input we1_i;
input req1;
output gnt1;
reg gnt1;
 
input [7:0] addr2_i;
input [7:0] data2_i;
input stb2_i;
input we2_i;
input req2;
output gnt2;
reg gnt2;
 
 
output [7:0] addr_o;
reg [7:0] addr_o;
output [7:0] data_o;
reg [7:0] data_o;
output stb_o;
reg stb_o;
output we_o;
reg we_o;
 
//local wires and regs
reg [1:0] muxSel;
reg [2:0] arbSt;
 
`define REQ_0 3'b000
`define REQ_1 3'b001
`define REQ_2 3'b010
`define GNT_0 3'b011
`define GNT_1 3'b100
`define GNT_2 3'b101
 
 
//arb
always @(posedge clk) begin
if (rst == 1'b1) begin
gnt0 <= 1'b0;
gnt1 <= 1'b0;
gnt2 <= 1'b0;
muxSel <= 2'b00;
arbSt <= `REQ_0;
end
else begin
case (arbSt)
`REQ_0: begin
if (req0 == 1'b1)
arbSt <= `GNT_0;
else
arbSt <= `REQ_1;
end
`REQ_1: begin
if (req1 == 1'b1)
arbSt <= `GNT_1;
else
arbSt <= `REQ_2;
end
`REQ_2: begin
if (req2 == 1'b1)
arbSt <= `GNT_2;
else
arbSt <= `REQ_0;
end
`GNT_0: begin
gnt0 <= 1'b1;
muxSel <= 2'b00;
if (req0 == 1'b0) begin
arbSt <= `REQ_1;
gnt0 <= 1'b0;
end
end
`GNT_1: begin
gnt1 <= 1'b1;
muxSel <= 2'b01;
if (req1 == 1'b0) begin
arbSt <= `REQ_2;
gnt1 <= 1'b0;
end
end
`GNT_2: begin
gnt2 <= 1'b1;
muxSel <= 2'b10;
if (req2 == 1'b0) begin
arbSt <= `REQ_0;
gnt2 <= 1'b0;
end
end
endcase
end
end
 
 
//mux
always @(*) begin
case (muxSel)
2'b00: begin
addr_o <= addr0_i;
data_o <= data0_i;
stb_o <= stb0_i;
we_o <= we0_i;
end
2'b01: begin
addr_o <= addr1_i;
data_o <= data1_i;
stb_o <= stb1_i;
we_o <= we1_i;
end
2'b10: begin
addr_o <= addr2_i;
data_o <= data2_i;
stb_o <= stb2_i;
we_o <= we2_i;
end
default: begin
addr_o <= addr0_i;
data_o <= data0_i;
stb_o <= stb0_i;
we_o <= we0_i;
end
endcase
end
 
 
endmodule
 
/EP0.v
0,0 → 1,869
 
//////////////////////////////////////////////////////////////////////
//// ////
//// EP0.v ////
//// ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Implements EP0 control endpoint
//// Responds to 8-byte SETUP packets
//// of type GET_STATUS, GET_DESCRIPTOR and
//// SET_ADDRESS
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostSlaveReg_define.v"
`include "usbDevice_define.v"
 
 
module EP0 (clk, initComplete, memAddr, memData, memRdEn, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
input clk;
input [7:0]memData;
input rst;
input wb_ack;
input [7:0]wb_data_i;
input wbBusGnt;
output initComplete;
output [7:0]memAddr;
output memRdEn;
output [7:0]wb_addr;
output [7:0]wb_data_o;
output wb_stb;
output wb_we;
output wbBusReq;
 
wire clk;
reg initComplete, next_initComplete;
reg [7:0]memAddr, next_memAddr;
wire [7:0]memData;
reg memRdEn, next_memRdEn;
wire rst;
wire wb_ack;
reg [7:0]wb_addr, next_wb_addr;
wire [7:0]wb_data_i;
reg [7:0]wb_data_o, next_wb_data_o;
reg wb_stb, next_wb_stb;
reg wb_we, next_wb_we;
wire wbBusGnt;
reg wbBusReq, next_wbBusReq;
 
// diagram signals declarations
reg bm_req_dir, next_bm_req_dir;
reg [4:0]bm_req_recp, next_bm_req_recp;
reg [1:0]bm_req_type, next_bm_req_type;
reg [7:0]bRequest, next_bRequest;
reg [7:0]cnt, next_cnt;
reg dataSeq, next_dataSeq;
reg [7:0]epStatus, next_epStatus;
reg [7:0]epTransType, next_epTransType;
reg localRst, next_localRst;
reg [15:0]rxDataSize, next_rxDataSize;
reg transDone, next_transDone;
reg [7:0]txDataIndex, next_txDataIndex;
reg [7:0]txDataSize, next_txDataSize;
reg [7:0]txPacketRemSize, next_txPacketRemSize;
reg updateUSBAddress, next_updateUSBAddress;
reg [7:0]USBAddress, next_USBAddress;
reg [15:0]wIndex, next_wIndex;
reg [15:0]wLength, next_wLength;
reg [15:0]wValue, next_wValue;
 
// BINARY ENCODED state machine: EP0St
// State codes definitions:
`define INIT_RST 6'b000000
`define INIT_WT_GNT 6'b000001
`define INIT_WT_RST 6'b000010
`define INIT_WT_VBUS 6'b000011
`define INIT_FIN 6'b000100
`define DO_TRANS_WT_GNT 6'b000101
`define DO_TRANS_TX_EMPTY 6'b000110
`define DO_TRANS_WR_TX_FIFO 6'b000111
`define DO_TRANS_RD_MEM 6'b001000
`define DO_TRANS_CHK_TX_DONE 6'b001001
`define DO_TRANS_TRANS_GO 6'b001010
`define DO_TRANS_WT_TRANS_DONE_WT_GNT 6'b001011
`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 6'b001100
`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 6'b001101
`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 6'b001110
`define CHK_TRANS_RD_STAT 6'b001111
`define CHK_TRANS_WT_GNT 6'b010000
`define CHK_TRANS_RD_RX_SIZE1 6'b010001
`define CHK_TRANS_RD_RX_SIZE2 6'b010010
`define CHK_TRANS_RD_TRANS_TYPE 6'b010011
`define CHK_TRANS_WT_UNGNT 6'b010100
`define SETUP_CHK_ERR 6'b010101
`define SETUP_GET_DATA_DAT1 6'b010110
`define SETUP_GET_DATA_WT_GNT 6'b010111
`define SETUP_GET_DATA_DAT2 6'b011000
`define SETUP_GET_DATA_DAT3 6'b011001
`define SETUP_GET_DATA_DAT4 6'b011010
`define SETUP_GET_DATA_DAT6 6'b011011
`define SETUP_GET_DATA_DAT5 6'b011100
`define SETUP_GET_DATA_DAT8 6'b011101
`define SETUP_GET_DATA_DAT7 6'b011110
`define SETUP_GET_DATA_WT_UNGNT 6'b011111
`define SETUP_GET_STAT 6'b100000
`define SETUP_SET_ADDR 6'b100001
`define SETUP_GET_DESC_S1 6'b100010
`define SETUP_CHK_MAX_LEN 6'b100011
`define OUT_CHK_SEQ 6'b100100
`define IN_CHK_ACK 6'b100101
`define IN_SET_PTR 6'b100110
`define IN_SET_ADDR 6'b100111
`define IN_WT_GNT 6'b101000
`define IN_WT_UNGNT 6'b101001
`define DO_TRANS_RX_EMPTY 6'b101010
`define DO_TRANS_WT_TRANS_DONE_DEL 6'b101011
`define START 6'b101100
`define INIT_CONN 6'b101101
`define INIT_WT_CONN 6'b101110
`define DO_TRANS_DEL 6'b101111
`define SETUP_PTR_SET 6'b110000
 
reg [5:0]CurrState_EP0St, NextState_EP0St;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: EP0St
 
// NextState logic (combinatorial)
always @ (wb_ack or wbBusGnt or cnt or wb_data_i or memData or txDataIndex or txDataSize or transDone or epStatus or epTransType or rxDataSize or bRequest or wValue or wLength or dataSeq or updateUSBAddress or txPacketRemSize or USBAddress or wb_addr or wb_data_o or wb_stb or wb_we or wbBusReq or initComplete or memAddr or memRdEn or bm_req_dir or bm_req_type or bm_req_recp or wIndex or CurrState_EP0St)
begin
NextState_EP0St <= CurrState_EP0St;
// Set default values for outputs and signals
next_wb_addr <= wb_addr;
next_wb_data_o <= wb_data_o;
next_wb_stb <= wb_stb;
next_wb_we <= wb_we;
next_cnt <= cnt;
next_wbBusReq <= wbBusReq;
next_initComplete <= initComplete;
next_memAddr <= memAddr;
next_memRdEn <= memRdEn;
next_txDataSize <= txDataSize;
next_txDataIndex <= txDataIndex;
next_transDone <= transDone;
next_epStatus <= epStatus;
next_rxDataSize <= rxDataSize;
next_epTransType <= epTransType;
next_bm_req_dir <= bm_req_dir;
next_bm_req_type <= bm_req_type;
next_bm_req_recp <= bm_req_recp;
next_bRequest <= bRequest;
next_wValue <= wValue;
next_wIndex <= wIndex;
next_wLength <= wLength;
next_txPacketRemSize <= txPacketRemSize;
next_USBAddress <= USBAddress;
next_updateUSBAddress <= updateUSBAddress;
next_dataSeq <= dataSeq;
case (CurrState_EP0St) // synopsys parallel_case full_case
`START:
begin
next_initComplete <= 1'b0;
next_wbBusReq <= 1'b0;
next_wb_addr <= 8'h00;
next_wb_data_o <= 8'h00;
next_wb_stb <= 1'b0;
next_wb_we <= 1'b0;
next_txPacketRemSize <= 8'h00;
next_txDataSize <= 8'h00;
next_txDataIndex <= 8'h00;
next_epTransType <= 8'h00;
next_epStatus <= 8'h00;
next_rxDataSize <= 16'h0000;
next_cnt <= 8'h00;
next_memRdEn <= 1'b0;
next_memAddr <= 8'h00;
next_updateUSBAddress <= 1'b0;
next_transDone <= 1'b0;
next_bm_req_type <= 2'b00;
next_bm_req_dir <= 1'b0;
next_bm_req_recp <= 5'b00000;
next_bRequest <= 8'h00;
next_wLength <= 16'h0000;
next_wIndex <= 16'h0000;
next_wValue <= 16'h0000;
next_dataSeq <= 1'b0;
next_USBAddress <= 8'h00;
NextState_EP0St <= `INIT_WT_GNT;
end
`CHK_TRANS_RD_STAT:
begin
next_wb_addr <= `RA_EP0_STATUS_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE1;
next_wb_stb <= 1'b0;
next_epStatus <= wb_data_i;
end
end
`CHK_TRANS_WT_GNT:
begin
if (wbBusGnt == 1'b1)
begin
NextState_EP0St <= `CHK_TRANS_RD_STAT;
end
end
`CHK_TRANS_RD_RX_SIZE1:
begin
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE2;
next_wb_stb <= 1'b0;
next_rxDataSize[15:8] <= wb_data_i;
end
end
`CHK_TRANS_RD_RX_SIZE2:
begin
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `CHK_TRANS_RD_TRANS_TYPE;
next_wb_stb <= 1'b0;
next_rxDataSize[7:0] <= wb_data_i;
end
end
`CHK_TRANS_RD_TRANS_TYPE:
begin
next_wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `CHK_TRANS_WT_UNGNT;
next_wb_stb <= 1'b0;
next_epTransType <= wb_data_i;
end
end
`CHK_TRANS_WT_UNGNT:
begin
next_wbBusReq <= 1'b0;
if ((wbBusGnt == 1'b0) && ((epStatus & 8'h0f) != 8'h00))
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_SETUP_TRANS))
begin
NextState_EP0St <= `SETUP_CHK_ERR;
end
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_IN_TRANS))
begin
NextState_EP0St <= `IN_CHK_ACK;
end
else if ((wbBusGnt == 1'b0) && (epTransType == `SC_OUTDATA_TRANS))
begin
NextState_EP0St <= `OUT_CHK_SEQ;
end
else if (wbBusGnt == 1'b0)
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
end
`DO_TRANS_WT_GNT:
begin
next_wbBusReq <= 1'b1;
if (wbBusGnt == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_TX_EMPTY;
end
end
`DO_TRANS_TX_EMPTY:
begin
next_wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG;
next_wb_data_o <= 8'h01;
//force tx fifo empty
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_RX_EMPTY;
next_wb_stb <= 1'b0;
end
end
`DO_TRANS_WR_TX_FIFO:
begin
next_wb_data_o <= memData;
next_wb_addr <= `RA_EP0_TX_FIFO_DATA_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_CHK_TX_DONE;
next_wb_stb <= 1'b0;
end
end
`DO_TRANS_RD_MEM:
begin
next_memAddr <= txDataIndex;
next_memRdEn <= 1'b1;
next_txDataSize <= txDataSize - 1'b1;
next_txDataIndex <= txDataIndex + 1'b1;
NextState_EP0St <= `DO_TRANS_DEL;
end
`DO_TRANS_CHK_TX_DONE:
begin
if (txDataSize == 8'h00)
begin
NextState_EP0St <= `DO_TRANS_TRANS_GO;
end
else
begin
NextState_EP0St <= `DO_TRANS_RD_MEM;
end
end
`DO_TRANS_TRANS_GO:
begin
next_wb_addr <= `RA_EP0_CONTROL_REG;
if (dataSeq == 1'b1)
next_wb_data_o <= 8'h07;
else
next_wb_data_o <= 8'h03;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
next_wb_stb <= 1'b0;
next_transDone <= 1'b0;
end
end
`DO_TRANS_RX_EMPTY:
begin
next_wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG;
next_wb_data_o <= 8'h01;
//force rx fifo empty
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if ((wb_ack == 1'b1) && (txDataSize != 8'h00))
begin
NextState_EP0St <= `DO_TRANS_RD_MEM;
next_wb_stb <= 1'b0;
end
else if (wb_ack == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_TRANS_GO;
next_wb_stb <= 1'b0;
end
end
`DO_TRANS_DEL:
begin
next_memRdEn <= 1'b0;
NextState_EP0St <= `DO_TRANS_WR_TX_FIFO;
end
`DO_TRANS_WT_TRANS_DONE_WT_GNT:
begin
next_wbBusReq <= 1'b1;
if (wbBusGnt == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
end
end
`DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
begin
next_wb_addr <= `RA_EP0_CONTROL_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
next_wb_stb <= 1'b0;
next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
end
end
`DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
begin
next_wbBusReq <= 1'b0;
if (wbBusGnt == 1'b0)
begin
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
end
end
`DO_TRANS_WT_TRANS_DONE_CHK_DONE:
begin
if (transDone == 1'b1)
begin
NextState_EP0St <= `CHK_TRANS_WT_GNT;
next_wbBusReq <= 1'b1;
end
else
begin
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_DEL;
next_cnt <= 8'h00;
end
end
`DO_TRANS_WT_TRANS_DONE_DEL:
begin
next_cnt <= cnt + 1'b1;
if (cnt == `ONE_USEC_DEL)
begin
NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
end
end
`SETUP_CHK_ERR:
begin
if (rxDataSize != 16'h0008)
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
else
begin
NextState_EP0St <= `SETUP_GET_DATA_WT_GNT;
next_wbBusReq <= 1'b1;
next_txDataSize <= 8'h00;
next_txPacketRemSize <= 8'h00;
//default tx packet size
next_dataSeq <= 1'b1;
next_wb_addr <= `RA_EP0_RX_FIFO_DATA_REG;
next_wb_we <= 1'b0;
end
end
`SETUP_GET_STAT:
begin
if (bm_req_type == 2'b00) begin
next_txPacketRemSize <= 8'h02;
if (bm_req_recp == 5'b00000)
next_txDataIndex <= `ONE_ZERO_STAT_INDEX;
else
next_txDataIndex <= `ZERO_ZERO_STAT_INDEX;
end
else if (bm_req_type == 2'b10) begin
next_txDataIndex <= `VENDOR_DATA_STAT_INDEX;
next_txPacketRemSize <= 8'h02;
end
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
end
`SETUP_SET_ADDR:
begin
if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin
next_USBAddress <= wValue[7:0];
next_updateUSBAddress <= 1'b1;
end
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
end
`SETUP_CHK_MAX_LEN:
begin
if (txPacketRemSize > wLength)
next_txPacketRemSize <= wLength;
NextState_EP0St <= `SETUP_PTR_SET;
end
`SETUP_PTR_SET:
begin
if (txPacketRemSize > `MAX_RESP_SIZE) begin
next_txDataSize <= `MAX_RESP_SIZE;
next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
end
else begin
next_txDataSize <= txPacketRemSize;
next_txPacketRemSize <= 8'h00;
end
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
`SETUP_GET_DATA_DAT1:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT2;
next_wb_stb <= 1'b0;
next_bm_req_dir <= wb_data_i[7];
next_bm_req_type <= wb_data_i[6:5];
next_bm_req_recp <= wb_data_i[4:0];
end
end
`SETUP_GET_DATA_WT_GNT:
begin
if (wbBusGnt == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT1;
end
end
`SETUP_GET_DATA_DAT2:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT3;
next_wb_stb <= 1'b0;
next_bRequest <= wb_data_i;
end
end
`SETUP_GET_DATA_DAT3:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT4;
next_wb_stb <= 1'b0;
next_wValue[7:0] <= wb_data_i;
end
end
`SETUP_GET_DATA_DAT4:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT5;
next_wb_stb <= 1'b0;
next_wValue[15:8] <= wb_data_i;
end
end
`SETUP_GET_DATA_DAT6:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT7;
next_wb_stb <= 1'b0;
next_wIndex[15:8] <= wb_data_i;
end
end
`SETUP_GET_DATA_DAT5:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT6;
next_wb_stb <= 1'b0;
next_wIndex[7:0] <= wb_data_i;
end
end
`SETUP_GET_DATA_DAT8:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_WT_UNGNT;
next_wb_stb <= 1'b0;
next_wLength[15:8] <= wb_data_i;
next_wbBusReq <= 1'b0;
end
end
`SETUP_GET_DATA_DAT7:
begin
next_wb_stb <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `SETUP_GET_DATA_DAT8;
next_wb_stb <= 1'b0;
next_wLength[7:0] <= wb_data_i;
end
end
`SETUP_GET_DATA_WT_UNGNT:
begin
if ((wbBusGnt == 1'b0) && (bRequest == `GET_STATUS))
begin
NextState_EP0St <= `SETUP_GET_STAT;
end
else if ((wbBusGnt == 1'b0) && (bRequest == `GET_DESCRIPTOR))
begin
NextState_EP0St <= `SETUP_GET_DESC_S1;
end
else if ((wbBusGnt == 1'b0) && (bRequest == `SET_ADDRESS))
begin
NextState_EP0St <= `SETUP_SET_ADDR;
end
else if (wbBusGnt == 1'b0)
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
end
`SETUP_GET_DESC_S1:
begin
case (wValue[15:8])
`DEV_DESC: begin
next_txPacketRemSize <= `DEV_DESC_SIZE;
next_txDataIndex <= `DEV_DESC_INDEX;
end
`CFG_DESC: begin
next_txPacketRemSize <= `CFG_DESC_SIZE;
next_txDataIndex <= `CFG_DESC_INDEX;
end
`REP_DESC: begin
next_txPacketRemSize <= `REP_DESC_SIZE;
next_txDataIndex <= `REP_DESC_INDEX;
end
`STRING_DESC: begin
case (wValue[3:0])
4'h0: begin
next_txPacketRemSize <= `LANGID_DESC_SIZE;
next_txDataIndex <= `LANGID_DESC_INDEX;
end
4'h1: begin
next_txPacketRemSize <= `STRING1_DESC_SIZE;
next_txDataIndex <= `STRING1_DESC_INDEX;
end
4'h2: begin
next_txPacketRemSize <= `STRING2_DESC_SIZE;
next_txDataIndex <= `STRING2_DESC_INDEX;
end
4'h3: begin
next_txPacketRemSize <= `STRING3_DESC_SIZE;
next_txDataIndex <= `STRING3_DESC_INDEX;
end
endcase
end
endcase
NextState_EP0St <= `SETUP_CHK_MAX_LEN;
end
`IN_CHK_ACK:
begin
if (epStatus[`SC_ACK_RXED_BIT] != 1'b1)
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
else if (updateUSBAddress == 1'b1)
begin
NextState_EP0St <= `IN_WT_GNT;
end
else
begin
NextState_EP0St <= `IN_SET_PTR;
end
end
`IN_SET_PTR:
begin
if (txPacketRemSize > `MAX_RESP_SIZE) begin
next_txDataSize <= `MAX_RESP_SIZE;
next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
end
else begin
next_txDataSize <= txPacketRemSize;
next_txPacketRemSize <= 8'h00;
end
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
`IN_SET_ADDR:
begin
next_wb_addr <= `RA_SC_ADDRESS;
next_wb_data_o <= USBAddress;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `IN_WT_UNGNT;
next_wb_stb <= 1'b0;
next_wbBusReq <= 1'b0;
end
end
`IN_WT_GNT:
begin
next_wbBusReq <= 1'b1;
next_updateUSBAddress <= 1'b0;
if (wbBusGnt == 1'b1)
begin
NextState_EP0St <= `IN_SET_ADDR;
end
end
`IN_WT_UNGNT:
begin
if (wbBusGnt == 1'b0)
begin
NextState_EP0St <= `IN_SET_PTR;
end
end
`OUT_CHK_SEQ:
begin
if (epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq)
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
else
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
next_dataSeq <= ~dataSeq;
end
end
`INIT_RST:
begin
next_wb_addr <= `RA_HOST_SLAVE_MODE;
next_wb_data_o <= 8'h2;
//reset usbHostSlave
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `INIT_WT_RST;
next_wb_stb <= 1'b0;
next_cnt <= 8'h00;
end
end
`INIT_WT_GNT:
begin
next_wbBusReq <= 1'b1;
if (wbBusGnt == 1'b1)
begin
NextState_EP0St <= `INIT_RST;
end
end
`INIT_WT_RST:
begin
next_cnt <= cnt + 1'b1;
if (cnt == 8'hff)
begin
NextState_EP0St <= `INIT_WT_VBUS;
end
end
`INIT_WT_VBUS:
begin
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if ((wb_ack == 1'b1) && (wb_data_i[`VBUS_PRES_BIT] == 1'b1))
begin
NextState_EP0St <= `INIT_CONN;
next_wb_stb <= 1'b0;
end
end
`INIT_FIN:
begin
next_wbBusReq <= 1'b0;
next_initComplete <= 1'b1;
if (wbBusGnt == 1'b0)
begin
NextState_EP0St <= `DO_TRANS_WT_GNT;
end
end
`INIT_CONN:
begin
next_wb_addr <= `RA_SC_CONTROL_REG;
next_wb_data_o <= 8'h71;
//connect to host, full speed
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_EP0St <= `INIT_WT_CONN;
next_wb_stb <= 1'b0;
end
end
`INIT_WT_CONN:
begin
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b0;
if ((wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT))
begin
NextState_EP0St <= `INIT_FIN;
next_wb_stb <= 1'b0;
end
end
endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_EP0St <= `START;
else
CurrState_EP0St <= NextState_EP0St;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
wb_addr <= 8'h00;
wb_data_o <= 8'h00;
wb_stb <= 1'b0;
wb_we <= 1'b0;
wbBusReq <= 1'b0;
initComplete <= 1'b0;
memAddr <= 8'h00;
memRdEn <= 1'b0;
cnt <= 8'h00;
txDataSize <= 8'h00;
txDataIndex <= 8'h00;
transDone <= 1'b0;
epStatus <= 8'h00;
rxDataSize <= 16'h0000;
epTransType <= 8'h00;
bm_req_dir <= 1'b0;
bm_req_type <= 2'b00;
bm_req_recp <= 5'b00000;
bRequest <= 8'h00;
wValue <= 16'h0000;
wIndex <= 16'h0000;
wLength <= 16'h0000;
txPacketRemSize <= 8'h00;
USBAddress <= 8'h00;
updateUSBAddress <= 1'b0;
dataSeq <= 1'b0;
end
else
begin
wb_addr <= next_wb_addr;
wb_data_o <= next_wb_data_o;
wb_stb <= next_wb_stb;
wb_we <= next_wb_we;
wbBusReq <= next_wbBusReq;
initComplete <= next_initComplete;
memAddr <= next_memAddr;
memRdEn <= next_memRdEn;
cnt <= next_cnt;
txDataSize <= next_txDataSize;
txDataIndex <= next_txDataIndex;
transDone <= next_transDone;
epStatus <= next_epStatus;
rxDataSize <= next_rxDataSize;
epTransType <= next_epTransType;
bm_req_dir <= next_bm_req_dir;
bm_req_type <= next_bm_req_type;
bm_req_recp <= next_bm_req_recp;
bRequest <= next_bRequest;
wValue <= next_wValue;
wIndex <= next_wIndex;
wLength <= next_wLength;
txPacketRemSize <= next_txPacketRemSize;
USBAddress <= next_USBAddress;
updateUSBAddress <= next_updateUSBAddress;
dataSeq <= next_dataSeq;
end
end
 
endmodule
/usbDeviceActelTop.v
0,0 → 1,88
 
module usbDeviceActelTop (
 
//
// Global signals
//
clk,
rst_n,
 
// eval board features
ledOut,
 
//
// USB
//
usbSlaveVP,
usbSlaveVM,
usbSlaveOE_n,
usbDPlusPullup
 
);
 
//
// Global signals
//
input clk;
input rst_n;
 
output [9:0] ledOut;
 
//
// USB
//
inout usbSlaveVP;
inout usbSlaveVM;
output usbSlaveOE_n;
output usbDPlusPullup;
 
//local wires and regs
reg [1:0] rstReg;
wire rst;
 
//generate sync reset
always @(posedge clk) begin
rstReg[1:0] <= {rstReg[0], ~rst_n};
end
assign rst = rstReg[1];
 
 
usbDevice u_usbDevice (
.clk(clk),
.rst(rst),
.usbSlaveVP_in(usbSlaveVP_in),
.usbSlaveVM_in(usbSlaveVM_in),
.usbSlaveVP_out(usbSlaveVP_out),
.usbSlaveVM_out(usbSlaveVM_out),
.usbSlaveOE_n(usbSlaveOE_n),
.usbDPlusPullup(usbDPlusPullup),
.vBusDetect(1'b1)
);
 
 
assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
 
 
// comfort lights
reg [9:0] ledCntReg;
reg [21:0] cnt;
 
assign ledOut = ledCntReg;
 
 
always @(posedge clk) begin
if (rst == 1'b1) begin
ledCntReg <= 10'b00_0000_0000;
cnt <= {22{1'b0}};
end
else begin
cnt <= cnt + 1'b1;
if (cnt == {22{1'b0}})
ledCntReg <= ledCntReg + 1'b1;
end
end
 
endmodule
 
 
/checkLineState.v
0,0 → 1,202
 
//////////////////////////////////////////////////////////////////////
//// ////
//// checkLineState.v ////
//// ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Checks USB line state. When reset state detected
//// asserts usbRstDet for one clock tick
//// usbRstDet is used to reset most of the logic.
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSlaveControl_h.v"
`include "usbHostSlaveReg_define.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbDevice_define.v"
module checkLineState (clk, initComplete, rst, usbRstDet, wb_ack, wb_addr, wb_data_i, wb_stb, wb_we, wbBusGnt, wbBusReq);
input clk;
input initComplete;
input rst;
input wb_ack;
input [7:0]wb_data_i;
input wbBusGnt;
output usbRstDet;
output [7:0]wb_addr;
output wb_stb;
output wb_we;
output wbBusReq;
 
wire clk;
wire initComplete;
wire rst;
reg usbRstDet, next_usbRstDet;
wire wb_ack;
reg [7:0]wb_addr, next_wb_addr;
wire [7:0]wb_data_i;
reg wb_stb, next_wb_stb;
reg wb_we, next_wb_we;
wire wbBusGnt;
reg wbBusReq, next_wbBusReq;
 
// diagram signals declarations
reg [15:0]cnt, next_cnt;
reg [1:0]resetState, next_resetState;
 
// BINARY ENCODED state machine: chkLSt
// State codes definitions:
`define START 3'b000
`define GET_STAT 3'b001
`define WT_GNT 3'b010
`define SET_RST_DET 3'b011
`define DEL_ONE_MSEC 3'b100
 
reg [2:0]CurrState_chkLSt, NextState_chkLSt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: chkLSt
 
// NextState logic (combinatorial)
always @ (initComplete or wb_ack or resetState or wbBusGnt or cnt or usbRstDet or wbBusReq or wb_addr or wb_stb or wb_we or CurrState_chkLSt)
begin
NextState_chkLSt <= CurrState_chkLSt;
// Set default values for outputs and signals
next_usbRstDet <= usbRstDet;
next_wbBusReq <= wbBusReq;
next_wb_addr <= wb_addr;
next_wb_stb <= wb_stb;
next_wb_we <= wb_we;
next_cnt <= cnt;
next_resetState <= resetState;
case (CurrState_chkLSt) // synopsys parallel_case full_case
`START:
begin
next_usbRstDet <= 1'b0;
next_wbBusReq <= 1'b0;
next_wb_addr <= 8'h00;
next_wb_stb <= 1'b0;
next_wb_we <= 1'b0;
next_cnt <= 16'h0000;
next_resetState <= 2'b00;
if (initComplete == 1'b1)
begin
NextState_chkLSt <= `WT_GNT;
end
end
`GET_STAT:
begin
next_wb_addr <= `RA_SC_LINE_STATUS_REG;
next_wb_stb <= 1'b1;
next_wb_we <= 1'b1;
if (wb_ack == 1'b1)
begin
NextState_chkLSt <= `SET_RST_DET;
next_wb_stb <= 1'b0;
if ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )
next_resetState <= {resetState[0], 1'b1};
else
next_resetState <= 2'b00;
next_wbBusReq <= 1'b0;
end
end
`WT_GNT:
begin
next_wbBusReq <= 1'b1;
if (wbBusGnt == 1'b1)
begin
NextState_chkLSt <= `GET_STAT;
end
end
`SET_RST_DET:
begin
NextState_chkLSt <= `DEL_ONE_MSEC;
if (resetState == 2'b11) // if reset condition aserted for 2mS
next_usbRstDet <= 1'b1;
next_cnt <= 16'h0000;
end
`DEL_ONE_MSEC:
begin
next_cnt <= cnt + 1'b1;
next_usbRstDet <= 1'b0;
if (cnt == `ONE_MSEC_DEL)
begin
NextState_chkLSt <= `WT_GNT;
end
end
endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_chkLSt <= `START;
else
CurrState_chkLSt <= NextState_chkLSt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
usbRstDet <= 1'b0;
wbBusReq <= 1'b0;
wb_addr <= 8'h00;
wb_stb <= 1'b0;
wb_we <= 1'b0;
cnt <= 16'h0000;
resetState <= 2'b00;
end
else
begin
usbRstDet <= next_usbRstDet;
wbBusReq <= next_wbBusReq;
wb_addr <= next_wb_addr;
wb_stb <= next_wb_stb;
wb_we <= next_wb_we;
cnt <= next_cnt;
resetState <= next_resetState;
end
end
 
endmodule
/usbROM.v
0,0 → 1,254
//////////////////////////////////////////////////////////////////////
//// ////
//// usbROM.v ////
//// ////
//// This file is part of the usbHostSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// if you modify this file, be sure to modify usbDevice_define.v
//// Using RAM rather than logic resources might be a more efficient implememtation
//// but this has the advantage of working with FPGAs that do not provide a
//// mechanism for initialising RAM, eg Actel IGLOO
//// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "usbDevice_define.v"
 
 
module usbROM (
clk,
addr,
data
);
input clk;
input [7:0] addr;
output [7:0] data;
reg [7:0] data;
 
always @(posedge clk) begin
case (addr)
// ====================================
// ===== DEVICE Descriptor =====
// ====================================
 
8'h00: data <= 8'h12; //BYTE bLength
8'h01: data <= 8'h01; //BYTE bDescriptorType
8'h02: data <= 8'h10; //WORD (Lo) bcdUSB version supported
8'h03: data <= 8'h01; //WORD (Hi) bcdUSB version supported
8'h04: data <= 8'h00; //BYTE bDeviceClass
8'h05: data <= 8'h00; //BYTE bDeviceSubClass
8'h06: data <= 8'h00; //BYTE bDeviceProtocol
8'h07: data <= `MAX_RESP_SIZE; //BYTE bMaxPacketSize
8'h08: data <= 8'hC7; //WORD (Lo) idVendor
8'h09: data <= 8'h05; //WORD (Hi) idVendor
8'h0a: data <= 8'h13; //WORD (Lo) idProduct; For Philips Hub mouse
8'h0b: data <= 8'h01; //WORD (Hi) idProduct; For Philips Hub mouse
8'h0c: data <= 8'h01; //WORD (Lo) bcdDevice
8'h0d: data <= 8'h00; //WORD (Hi) bcdDevice
8'h0e: data <= 8'h01; //BYTE iManufacturer
8'h0f: data <= 8'h02; //BYTE iProduct
8'h10: data <= 8'h03; //BYTE iSerialNumber
8'h11: data <= 8'h01; //BYTE bNumConfigurations
 
// ====================================
// ===== Configuration Descriptor =====
// ====================================
8'h12: data <= 8'h09; //BYTE bLength (Configuration descriptor)
8'h13: data <= 8'h02; //BYTE bDescriptorType //Assigned by USB
8'h14: data <= 8'd34; //WORD (Lo) wTotalLength
8'h15: data <= 8'h00; //WORD (Hi) wTotalLength
8'h16: data <= 8'h01; //BYTE bNumInterfaces
8'h17: data <= 8'h01; //BYTE bConfigurationValue
8'h18: data <= 8'h00; //BYTE iConfiguration
8'h19: data <= 8'ha0; //BYTE bmAttributes, Bus powered and remote wakeup
8'h1a: data <= 8'h32; //BYTE MaxPower, 100mA
// ====================================
// ===== Interface Descriptor =====
// ====================================
8'h1b: data <= 8'h09; //BYTE bLength (Interface descriptor)
8'h1c: data <= 8'h04; //BYTE bDescriptionType; assigned by USB
8'h1d: data <= 8'h00; //BYTE bInterfaceNumber
8'h1e: data <= 8'h00; //BYTE bAlternateSetting
8'h1f: data <= 8'h01; //BYTE bNumEndpoints; uses 1 endpoints
8'h20: data <= 8'h03; //BYTE bInterfaceClass; HID Class - 0x03
8'h21: data <= 8'h01; //BYTE bInterfaceSubClass
8'h22: data <= 8'h02; //BYTE bInterfaceProtocol
8'h23: data <= 8'h00; //BYTE iInterface
// ====================================
// ===== HID Descriptor =====
// ====================================
8'h24: data <= 8'h09; //BYTE bLength (HID Descriptor)
8'h25: data <= 8'h21; //BYTE bDescriptorType
8'h26: data <= 8'h10; //WORD (Lo) bcdHID
8'h27: data <= 8'h01; //WORD (Hi) bcdHID
8'h28: data <= 8'h00; //BYTE bCountryCode
8'h29: data <= 8'h01; //BYTE bNumDescriptors
8'h2a: data <= 8'h22; //BYTE bReportDescriptorType
8'h2b: data <= 8'h32; //WORD (Lo) wItemLength
8'h2c: data <= 8'h00; //WORD (Hi) wItemLength
 
// ====================================
// ===== Endpoint 1 Descriptor =====
// ====================================
8'h2d: data <= 8'h07; //BYTE bLength (Endpoint Descriptor)
8'h2e: data <= 8'h05; //BYTE bDescriptorType; assigned by USB
8'h2f: data <= 8'h81; //BYTE bEndpointAddress; IN endpoint; endpoint 1
8'h30: data <= 8'h03; //BYTE bmAttributes; Interrupt endpoint
8'h31: data <= 8'h10; //WORD (Lo) wMaxPacketSize
8'h32: data <= 8'h00; //WORD (Hi) wMaxPacketSize
8'h33: data <= 8'hFF; //BYTE bInterval
 
// ====================================
// ===== Report Descriptor =====
// ====================================
 
8'h3a: data <= 8'h05; 8'h3b: data <= 8'h01; // USAGE_PAGE (Generic Desktop)
8'h3c: data <= 8'h09; 8'h3d: data <= 8'h02; // USAGE (Mouse)
8'h3e: data <= 8'ha1; 8'h3f: data <= 8'h01; // COLLECTION (Application)
8'h40: data <= 8'h09; 8'h41: data <= 8'h01; // USAGE (Pointer)
8'h42: data <= 8'ha1; 8'h43: data <= 8'h00; // COLLECTION (Physical)
8'h44: data <= 8'h05; 8'h45: data <= 8'h09; // USAGE_PAGE (Button)
8'h46: data <= 8'h19; 8'h47: data <= 8'h01; // USAGE_MINIMUM (Button 1)
8'h48: data <= 8'h29; 8'h49: data <= 8'h03; // USAGE_MAXIMUM (Button 3)
8'h4a: data <= 8'h15; 8'h4b: data <= 8'h00; // LOGICAL_MINIMUM (0)
8'h4c: data <= 8'h25; 8'h4d: data <= 8'h01; // LOGICAL_MAXIMUM (1)
8'h4e: data <= 8'h95; 8'h4f: data <= 8'h03; // REPORT_COUNT (3)
8'h50: data <= 8'h75; 8'h51: data <= 8'h01; // REPORT_SIZE (1)
8'h52: data <= 8'h81; 8'h53: data <= 8'h02; // INPUT (Data,Var,Abs)
8'h54: data <= 8'h95; 8'h55: data <= 8'h01; // REPORT_COUNT (1)
8'h56: data <= 8'h75; 8'h57: data <= 8'h05; // REPORT_SIZE (5)
8'h58: data <= 8'h81; 8'h59: data <= 8'h01; // INPUT (Cnst,Var,Rel)
8'h5a: data <= 8'h05; 8'h5b: data <= 8'h01; // USAGE_PAGE (Generic Desktop)
8'h5c: data <= 8'h09; 8'h5d: data <= 8'h30; // USAGE (X)
8'h5e: data <= 8'h09; 8'h5f: data <= 8'h31; // USAGE (Y)
8'h60: data <= 8'h15; 8'h61: data <= 8'h81; // LOGICAL_MINIMUM (-127)
8'h62: data <= 8'h25; 8'h63: data <= 8'h7f; // LOGICAL_MAXIMUM (127)
8'h64: data <= 8'h75; 8'h65: data <= 8'h08; // REPORT_SIZE (8)
8'h66: data <= 8'h95; 8'h67: data <= 8'h02; // REPORT_COUNT (2)
8'h68: data <= 8'h81; 8'h69: data <= 8'h06; // INPUT (Data,Var,Rel)
8'h6a: data <= 8'hc0; //END_COLLECTION
8'h6b: data <= 8'hc0; // END_COLLECTION
 
// ZERO_ZERO
8'h6c: data <= 8'h00;
8'h6d: data <= 8'h00;
// ONE_ZERO
8'h6e: data <= 8'h01;
8'h6f: data <= 8'h00;
// Vendor data
8'h70: data <= 8'h00;
8'h71: data <= 8'h00;
 
// =============================================
// ===== Language ID Descriptor(String0) =====
// =============================================
8'h80: data <= 8'h04; // bLength
8'h81: data <= 8'h03; // bDescriptorType = String Desc
8'h82: data <= 8'h09; // wLangID (Lo) (Lang ID for English = 0x0409)
8'h83: data <= 8'h04; // wLangID (Hi) (Lang ID for English = 0x0409)
 
// ====================================
// ===== string 1 Descriptor =====
// ====================================
8'h90: data <= 8'd26; // bLength
8'h91: data <= 8'h03; // bDescriptorType = String Desc
// Noting that text is always unicode, hence the 'padding'
8'h92: data <= "B"; 8'h93: data <= 8'h00;
8'h94: data <= "a"; 8'h95: data <= 8'h00;
8'h96: data <= "s"; 8'h97: data <= 8'h00;
8'h98: data <= "e"; 8'h99: data <= 8'h00;
8'h9a: data <= "2"; 8'h9b: data <= 8'h00;
8'h9c: data <= "D"; 8'h9d: data <= 8'h00;
8'h9e: data <= "e"; 8'h9f: data <= 8'h00;
8'ha0: data <= "s"; 8'ha1: data <= 8'h00;
8'ha2: data <= "i"; 8'ha3: data <= 8'h00;
8'ha4: data <= "g"; 8'ha5: data <= 8'h00;
8'ha6: data <= "n"; 8'ha7: data <= 8'h00;
8'ha8: data <= "s"; 8'ha9: data <= 8'h00;
 
 
 
// ====================================
// ===== string 2 Descriptor =====
// ====================================
8'hb0: data <= 8'd20; // bLength
8'hb1: data <= 8'h03; // bDescriptorType = String Desc
// Noting that text is always unicode, hence the 'padding'
8'hb2: data <= "B"; 8'hb3: data <= 8'h00;
8'hb4: data <= "2"; 8'hb5: data <= 8'h00;
8'hb6: data <= "D"; 8'hb7: data <= 8'h00;
8'hb8: data <= " "; 8'hb9: data <= 8'h00;
8'hba: data <= "M"; 8'hbb: data <= 8'h00;
8'hbc: data <= "o"; 8'hbd: data <= 8'h00;
8'hbe: data <= "u"; 8'hbf: data <= 8'h00;
8'hc0: data <= "s"; 8'hc1: data <= 8'h00;
8'hc2: data <= "e"; 8'hc3: data <= 8'h00;
 
// ====================================
// ===== string 3 Descriptor =====
// ====================================
8'hd0: data <= 8'd30; // bLength
8'hd1: data <= 8'h03; // bDescriptorType = String Desc
// Noting that text is always unicode, hence the 'padding'
8'hd2: data <= "L"; 8'hd3: data <= 8'h00;
8'hd4: data <= "i"; 8'hd5: data <= 8'h00;
8'hd6: data <= "m"; 8'hd7: data <= 8'h00;
8'hd8: data <= "i"; 8'hd9: data <= 8'h00;
8'hda: data <= "t"; 8'hdb: data <= 8'h00;
8'hdc: data <= "e"; 8'hdd: data <= 8'h00;
8'hde: data <= "d"; 8'hdf: data <= 8'h00;
8'he0: data <= "E"; 8'he1: data <= 8'h00;
8'he2: data <= "d"; 8'he3: data <= 8'h00;
8'he4: data <= "i"; 8'he5: data <= 8'h00;
8'he6: data <= "t"; 8'he7: data <= 8'h00;
8'he8: data <= "i"; 8'he9: data <= 8'h00;
8'hea: data <= "o"; 8'heb: data <= 8'h00;
8'hec: data <= "n"; 8'hed: data <= 8'h00;
 
 
 
default: data <= 8'h00;
endcase
end
 
endmodule
 
 
/usbDeviceXilinxTop.v
0,0 → 1,92
 
module usbDeviceXilinxTop (
 
//
// Global signals
//
clk,
 
//
// misc Starter Kit control sigs
//
E_NRST,
SPI_SCK,
NF_CE,
SD_CS,
 
//
// USB slave
//
usbSlaveVP,
usbSlaveVM,
usbSlaveOE_n,
usbDPlusPullup
 
);
 
//
// Global signals
//
input clk;
 
//
// misc Starter Kit control sigs
//
output E_NRST;
output SPI_SCK;
output NF_CE;
output SD_CS;
 
//
// USB slave
//
inout usbSlaveVP;
inout usbSlaveVM;
output usbSlaveOE_n;
output usbDPlusPullup;
 
//local wires and regs
reg [1:0] rstReg;
wire rst;
wire pll_locked;
wire clk48MHz;
 
 
assign E_NRST = 1'b0;
assign SPI_SCK = 1'b0;
assign NF_CE = 1'b0;
assign SD_CS = 1'b1;
 
 
pll_48MHz_xilinx pll_48MHz_inst (
.CLKIN_IN ( clk ),
.CLK0_OUT (clk48MHz),
.LOCKED_OUT( pll_locked)
);
 
//generate sync reset from pll lock signal
always @(posedge clk48MHz) begin
rstReg[1:0] <= {rstReg[0], ~pll_locked};
end
assign rst = rstReg[1];
 
 
usbDevice u_usbDevice (
.clk(clk48MHz),
.rst(rst),
.usbSlaveVP_in(usbSlaveVP_in),
.usbSlaveVM_in(usbSlaveVM_in),
.usbSlaveVP_out(usbSlaveVP_out),
.usbSlaveVM_out(usbSlaveVM_out),
.usbSlaveOE_n(usbSlaveOE_n),
.usbDPlusPullup(usbDPlusPullup),
.vBusDetect(1'b1)
);
 
 
assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
 
endmodule
 
 
/usbHostSlaveReg_define.v
0,0 → 1,78
// ------------------------------ usbHostSlaveReg_define.v ----------------------------
`include "wishBoneBus_h.v"
`include "usbHostSlave_h.v"
 
 
 
`define RA_EP0_CONTROL_REG `SCREG_BASE+`ENDPOINT_CONTROL_REG
`define RA_EP0_STATUS_REG `SCREG_BASE+`ENDPOINT_STATUS_REG
`define RA_EP0_TRANSTYPE_STATUS_REG `SCREG_BASE+`ENDPOINT_TRANSTYPE_STATUS_REG
`define RA_EP0_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NAK_TRANSTYPE_STATUS_REG
`define RA_EP1_CONTROL_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_CONTROL_REG
`define RA_EP1_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_STATUS_REG
`define RA_EP1_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_TRANSTYPE_STATUS_REG
`define RA_EP1_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`NAK_TRANSTYPE_STATUS_REG
`define RA_EP2_CONTROL_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_CONTROL_REG
`define RA_EP2_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_STATUS_REG
`define RA_EP2_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)`+`ENDPOINT_TRANSTYPE_STATUS_REG
`define RA_EP2_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`NAK_TRANSTYPE_STATUS_REG
`define RA_EP3_CONTROL_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_CONTROL_REG
`define RA_EP3_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_STATUS_REG
`define RA_EP3_TRANSTYPE_STATUS_REG `SCREG_BASE+(NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_TRANSTYPE_STATUS_REG
`define RA_EP3_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`NAK_TRANSTYPE_STATUS_REG
`define RA_SC_CONTROL_REG `SCREG_BASE+`SC_CONTROL_REG
`define RA_SC_LINE_STATUS_REG `SCREG_BASE+`SC_LINE_STATUS_REG
`define RA_SC_INTERRUPT_STATUS_REG `SCREG_BASE+`SC_INTERRUPT_STATUS_REG
`define RA_SC_INTERRUPT_MASK_REG `SCREG_BASE+`SC_INTERRUPT_MASK_REG
`define RA_SC_ADDRESS `SCREG_BASE+`SC_ADDRESS
`define RA_SC_FRAME_NUM_MSP `SCREG_BASE+`SC_FRAME_NUM_MSP
`define RA_SC_FRAME_NUM_LSP `SCREG_BASE+`SC_FRAME_NUM_LSP
 
`define RA_EP0_RX_FIFO_DATA_REG `EP0_RX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP0_RX_FIFO_STATUS_REG `EP0_RX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP0_RX_FIFO_DATA_COUNT_MSB `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP0_RX_FIFO_DATA_COUNT_LSB `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP0_RX_FIFO_CONTROL_REG `EP0_RX_FIFO_BASE+`FIFO_CONTROL_REG
`define RA_EP0_TX_FIFO_DATA_REG `EP0_TX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP0_TX_FIFO_STATUS_REG `EP0_TX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP0_TX_FIFO_DATA_COUNT_MSB `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP0_TX_FIFO_DATA_COUNT_LSB `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP0_TX_FIFO_CONTROL_REG `EP0_TX_FIFO_BASE+`FIFO_CONTROL_REG
 
`define RA_EP1_RX_FIFO_DATA_REG `EP1_RX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP1_RX_FIFO_STATUS_REG `EP1_RX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP1_RX_FIFO_DATA_COUNT_MSB `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP1_RX_FIFO_DATA_COUNT_LSB `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP1_RX_FIFO_CONTROL_REG `EP1_RX_FIFO_BASE+`FIFO_CONTROL_REG
`define RA_EP1_TX_FIFO_DATA_REG `EP1_TX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP1_TX_FIFO_STATUS_REG `EP1_TX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP1_TX_FIFO_DATA_COUNT_MSB `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP1_TX_FIFO_DATA_COUNT_LSB `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP1_TX_FIFO_CONTROL_REG `EP1_TX_FIFO_BASE+`FIFO_CONTROL_REG
 
`define RA_EP2_RX_FIFO_DATA_REG `EP2_RX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP2_RX_FIFO_STATUS_REG `EP2_RX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP2_RX_FIFO_DATA_COUNT_MSB `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP2_RX_FIFO_DATA_COUNT_LSB `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP2_RX_FIFO_CONTROL_REG `EP2_RX_FIFO_BASE+`FIFO_CONTROL_REG
`define RA_EP2_TX_FIFO_DATA_REG `EP2_TX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP2_TX_FIFO_STATUS_REG `EP2_TX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP2_TX_FIFO_DATA_COUNT_MSB `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP2_TX_FIFO_DATA_COUNT_LSB `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP2_TX_FIFO_CONTROL_REG `EP2_TX_FIFO_BASE+`FIFO_CONTROL_REG
 
`define RA_EP3_RX_FIFO_DATA_REG `EP3_RX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP3_RX_FIFO_STATUS_REG `EP3_RX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP3_RX_FIFO_DATA_COUNT_MSB `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP3_RX_FIFO_DATA_COUNT_LSB `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP3_RX_FIFO_CONTROL_REG `EP3_RX_FIFO_BASE+`FIFO_CONTROL_REG
`define RA_EP3_TX_FIFO_DATA_REG `EP3_TX_FIFO_BASE+`FIFO_DATA_REG
`define RA_EP3_TX_FIFO_STATUS_REG `EP3_TX_FIFO_BASE+`FIFO_STATUS_REG
`define RA_EP3_TX_FIFO_DATA_COUNT_MSB `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
`define RA_EP3_TX_FIFO_DATA_COUNT_LSB `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
`define RA_EP3_TX_FIFO_CONTROL_REG `EP3_TX_FIFO_BASE+`FIFO_CONTROL_REG
 
`define RA_HOST_SLAVE_MODE `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG
`define RA_HOST_SLAVE_VERSION `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG
 
 

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