OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /usbhostslave/trunk/usbDevice/sim
    from Rev 37 to Rev 40
    ↔ Reverse comparison
  •

Rev 37 → Rev 40

/run_icarus.bat
0,0 → 1,2
vvp testHarness
 
/filelist.icarus
0,0 → 1,61
../../RTL/buffers/dpMem_dc.v
../../RTL/buffers/fifoRTL.v
../../RTL/buffers/RxFifoBI.v
../../RTL/buffers/TxFifoBI.v
../../RTL/buffers/RxFifo.v
../../RTL/buffers/TxFifo.v
../../RTL/busInterface/wishBoneBI.v
../../RTL/hostController/directControl.v
../../RTL/hostController/getPacket.v
../../RTL/hostController/hctxportarbiter.v
../../RTL/hostController/hostcontroller.v
../../RTL/hostController/rxStatusMonitor.v
../../RTL/hostController/sendPacket.v
../../RTL/hostController/sendpacketarbiter.v
../../RTL/hostController/sendpacketcheckpreamble.v
../../RTL/hostController/sofcontroller.v
../../RTL/hostController/softransmit.v
../../RTL/hostController/speedctrlMux.v
../../RTL/hostController/usbHostControl.v
../../RTL/hostController/USBHostControlBI.v
../../RTL/hostSlaveMux/hostSlaveMux.v
../../RTL/hostSlaveMux/hostSlaveMuxBI.v
../../RTL/serialInterfaceEngine/lineControlUpdate.v
../../RTL/serialInterfaceEngine/processRxBit.v
../../RTL/serialInterfaceEngine/processRxByte.v
../../RTL/serialInterfaceEngine/processTxByte.v
../../RTL/serialInterfaceEngine/readUSBWireData.v
../../RTL/serialInterfaceEngine/siereceiver.v
../../RTL/serialInterfaceEngine/SIETransmitter.v
../../RTL/serialInterfaceEngine/updateCRC5.v
../../RTL/serialInterfaceEngine/updateCRC16.v
../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
../../RTL/serialInterfaceEngine/writeUSBWireData.v
../../RTL/slaveController/endpMux.v
../../RTL/slaveController/fifoMux.v
../../RTL/slaveController/sctxportarbiter.v
../../RTL/slaveController/slavecontroller.v
../../RTL/slaveController/slaveDirectcontrol.v
../../RTL/slaveController/slaveGetpacket.v
../../RTL/slaveController/slaveRxStatusMonitor.v
../../RTL/slaveController/slaveSendpacket.v
../../RTL/slaveController/usbSlaveControl.v
../../RTL/slaveController/USBSlaveControlBI.v
../../RTL/wrapper/usbHost.v
../../RTL/wrapper/usbSlave.v
../RTL/checkLineState.v
../RTL/EP0.v
../RTL/EP1Mouse.v
../RTL/usbDevice.v
../RTL/usbROM.v
../RTL/wishboneArb.v
../model/wb_master_model.v
../bench/testHarness.v
../bench/testCase0.v
 
+incdir+../RTL
+incdir+../../RTL/include
+incdir+../bench
+define+SIM_COMPILE
 
/build_icarus.bat
0,0 → 1,4
iverilog -o testHarness -cfilelist.icarus
 
pause
 

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