URL
https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
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/usbhostslave/trunk/usbDevice/syn/altera
- from Rev 39 to Rev 40
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Rev 39 → Rev 40
/usbDeviceAlteraTop.qsf
0,0 → 1,202
# Copyright (C) 1991-2006 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
|
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# The default values for assignments are stored in the file |
# cyc_or12_mini_top_assignment_defaults.qdf |
# If this file doesn't exist, and for assignments not listed, see file |
# assignment_defaults.qdf |
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# Altera recommends that you do not modify this file. This |
# file is updated automatically by the Quartus II software |
# and any changes you make may be lost or overwritten. |
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set_global_assignment -name FAMILY "Cyclone II" |
set_global_assignment -name DEVICE EP2C20Q240C8 |
set_global_assignment -name TOP_LEVEL_ENTITY usbDeviceAlteraTop |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "06:48:46 JUNE 20, 2007" |
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3" |
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#48MHz local oscillator |
set_global_assignment -name FMAX_REQUIREMENT "20.83 ns" -section_id clk |
set_global_assignment -name DUTY_CYCLE 50 -section_id clk |
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set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" |
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" |
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON |
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set_location_assignment PIN_30 -to clk |
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set_location_assignment PIN_97 -to mc_addr[0] |
set_location_assignment PIN_96 -to mc_addr[1] |
set_location_assignment PIN_90 -to mc_addr[2] |
set_location_assignment PIN_166 -to mc_addr[3] |
set_location_assignment PIN_165 -to mc_addr[4] |
set_location_assignment PIN_164 -to mc_addr[5] |
set_location_assignment PIN_162 -to mc_addr[6] |
set_location_assignment PIN_161 -to mc_addr[7] |
set_location_assignment PIN_159 -to mc_addr[8] |
set_location_assignment PIN_157 -to mc_addr[9] |
set_location_assignment PIN_100 -to mc_addr[10] |
set_location_assignment PIN_109 -to mc_addr[11] |
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set_location_assignment PIN_106 -to mc_ba[0] |
set_location_assignment PIN_105 -to mc_ba[1] |
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set_location_assignment PIN_113 -to mc_cas_ |
set_location_assignment PIN_156 -to mc_cke_ |
set_location_assignment PIN_155 -to sdram_clk |
set_location_assignment PIN_110 -to sdram_cs |
set_location_assignment PIN_116 -to mc_dqm[0] |
set_location_assignment PIN_150 -to mc_dqm[1] |
set_location_assignment PIN_88 -to mc_dqm[2] |
set_location_assignment PIN_167 -to mc_dqm[3] |
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set_location_assignment PIN_111 -to mc_ras_ |
set_location_assignment PIN_114 -to mc_we_ |
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set_location_assignment PIN_47 -to spiClk |
set_location_assignment PIN_20 -to spiMasterDataOut |
set_location_assignment PIN_44 -to spiCS_n |
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#set_location_assignment PIN_18 -to usbHostOE_n |
#set_location_assignment PIN_8 -to usbSlaveVP |
#set_location_assignment PIN_7 -to usbSlaveVM |
#set_location_assignment PIN_9 -to usbSlaveOE_n |
#set_location_assignment PIN_13 -to usbDPlusPullup |
#set_location_assignment PIN_4 -to vBusDetect |
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# Santa Cruz Connector |
set_location_assignment PIN_16 -to SC_P_CLK |
set_location_assignment PIN_15 -to SC_PCS_N |
set_location_assignment PIN_188 -to SC_RST_N |
set_location_assignment PIN_191 -to SC_P0 |
set_location_assignment PIN_189 -to SC_P1 |
set_location_assignment PIN_194 -to SC_P2 |
set_location_assignment PIN_192 -to SC_P3 |
set_location_assignment PIN_199 -to SC_P4 |
set_location_assignment PIN_197 -to SC_P5 |
set_location_assignment PIN_208 -to SC_P6 |
set_location_assignment PIN_203 -to SC_P7 |
set_location_assignment PIN_218 -to SC_P8 |
set_location_assignment PIN_216 -to SC_P9 |
set_location_assignment PIN_226 -to SC_P10 |
set_location_assignment PIN_223 -to SC_P11 |
set_location_assignment PIN_231 -to SC_P12 |
set_location_assignment PIN_230 -to SC_P13 |
set_location_assignment PIN_234 -to SC_P14 |
set_location_assignment PIN_233 -to SC_P15 |
set_location_assignment PIN_236 -to SC_P16 |
set_location_assignment PIN_237 -to SC_P17 |
set_location_assignment PIN_238 -to SC_P18 |
set_location_assignment PIN_5 -to SC_P19 |
set_location_assignment PIN_4 -to SC_P20 |
set_location_assignment PIN_6 -to SC_P21 |
set_location_assignment PIN_7 -to SC_P22 |
set_location_assignment PIN_8 -to SC_P23 |
set_location_assignment PIN_9 -to SC_P24 |
set_location_assignment PIN_11 -to SC_P25 |
set_location_assignment PIN_13 -to SC_P26 |
set_location_assignment PIN_14 -to SC_P27 |
set_location_assignment PIN_18 -to SC_P28 |
set_location_assignment PIN_184 -to SC_P29 |
set_location_assignment PIN_185 -to SC_P30 |
set_location_assignment PIN_186 -to SC_P31 |
set_location_assignment PIN_187 -to SC_P32 |
set_location_assignment PIN_195 -to SC_P33 |
set_location_assignment PIN_200 -to SC_P34 |
set_location_assignment PIN_214 -to SC_P35 |
set_location_assignment PIN_222 -to SC_P36 |
set_location_assignment PIN_228 -to SC_P37 |
set_location_assignment PIN_232 -to SC_P38 |
set_location_assignment PIN_235 -to SC_P39 |
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set_global_assignment -name ENABLE_SIGNALTAP ON |
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp |
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set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 1000 |
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF |
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON |
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set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON |
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set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL" |
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" |
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" |
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top |
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" |
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" |
set_instance_assignment -name CLOCK_SETTINGS clk -to clk |
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top |
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set_global_assignment -name USER_LIBRARIES "..\\..\\..\\rtl\\include;..\\..\\rtl" |
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set_global_assignment -name VERILOG_FILE ../../../RTL/wrapper/usbSlave.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/USBSlaveControlBI.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/endpMux.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/fifoMux.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/sctxportarbiter.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slavecontroller.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveDirectcontrol.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveGetpacket.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveRxStatusMonitor.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveSendpacket.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/usbSlaveControl.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/writeUSBWireData.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/lineControlUpdate.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxBit.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxByte.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processTxByte.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/readUSBWireData.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/siereceiver.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/SIETransmitter.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC5.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC16.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbTxWireArbiter.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMuxBI.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMux.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/busInterface/wishBoneBI.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifoBI.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/dpMem_dc.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/fifoRTL.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifo.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifoBI.v |
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifo.v |
set_global_assignment -name VERILOG_FILE ../../RTL/wishboneArb.v |
set_global_assignment -name VERILOG_FILE ../../RTL/checkLineState.v |
set_global_assignment -name VERILOG_FILE ../../RTL/EP0.v |
set_global_assignment -name VERILOG_FILE ../../RTL/EP1Mouse.v |
set_global_assignment -name VERILOG_FILE ../../RTL/pll_48MHz.v |
set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice.v |
set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice_define.v |
set_global_assignment -name VERILOG_FILE ../../RTL/usbDeviceAlteraTop.v |
set_global_assignment -name VERILOG_FILE ../../RTL/usbHostSlaveReg_define.v |
set_global_assignment -name VERILOG_FILE ../../RTL/usbROM.v |
set_global_assignment -name SDC_FILE usbDeviceAlteraTop.sdc |
/usbDeviceAlteraTop.qpf
0,0 → 1,23
# Copyright (C) 1991-2007 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
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QUARTUS_VERSION = "7.2" |
DATE = "13:52:36 August 08, 2008" |
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# Revisions |
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PROJECT_REVISION = "usbDeviceAlteraTop" |
/usbDeviceAlteraTop.cof
0,0 → 1,17
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?> |
<cof> |
<eprom_name>NONE</eprom_name> |
<output_filename>usbDeviceAlteraTop.rbf</output_filename> |
<n_pages>1</n_pages> |
<width>1</width> |
<mode>0</mode> |
<sof_data> |
<page_flags>1</page_flags> |
<bit0> |
<sof_filename>usbDeviceAlteraTop.sof</sof_filename> |
</bit0> |
</sof_data> |
<version>4</version> |
<options> |
</options> |
</cof> |
/download.bat
0,0 → 1,3
fpgaConfig -i usbDeviceAlteraTop.rbf -r -a 0 -w -l |
pause |
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/usbDeviceAlteraTop.sdc
0,0 → 1,114
## Generated SDC file "cyc_or12_mini_top.sdc" |
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## Copyright (C) 1991-2007 Altera Corporation |
## Your use of Altera Corporation's design tools, logic functions |
## and other software and tools, and its AMPP partner logic |
## functions, and any output files from any of the foregoing |
## (including device programming or simulation files), and any |
## associated documentation or information are expressly subject |
## to the terms and conditions of the Altera Program License |
## Subscription Agreement, Altera MegaCore Function License |
## Agreement, or other applicable license agreement, including, |
## without limitation, that your use is for the sole purpose of |
## programming logic devices manufactured by Altera and sold by |
## Altera or its authorized distributors. Please refer to the |
## applicable agreement for further details. |
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## VENDOR "Altera" |
## PROGRAM "Quartus II" |
## VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition" |
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## DATE "Fri May 16 09:55:20 2008" |
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## |
## DEVICE "EP2C20Q240C8" |
## |
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#************************************************************** |
# Time Information |
#************************************************************** |
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set_time_format -unit ns -decimal_places 3 |
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#************************************************************** |
# Create Clock |
#************************************************************** |
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create_clock -name {clk} -period 20.830 -waveform { 0.000 10.415 } [get_ports {clk}] -add |
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#************************************************************** |
# Create Generated Clock |
#************************************************************** |
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derive_pll_clocks -use_tan_name |
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#************************************************************** |
# Set Clock Latency |
#************************************************************** |
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#************************************************************** |
# Set Clock Uncertainty |
#************************************************************** |
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#************************************************************** |
# Set Input Delay |
#************************************************************** |
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#************************************************************** |
# Set Output Delay |
#************************************************************** |
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#************************************************************** |
# Set Clock Groups |
#************************************************************** |
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#************************************************************** |
# Set False Path |
#************************************************************** |
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#************************************************************** |
# Set Multicycle Path |
#************************************************************** |
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#************************************************************** |
# Set Maximum Delay |
#************************************************************** |
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#************************************************************** |
# Set Minimum Delay |
#************************************************************** |
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#************************************************************** |
# Set Input Transition |
#************************************************************** |
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#************************************************************** |
# Set Load |
#************************************************************** |
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