OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

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  • This comparison shows the changes necessary to convert path 
    /usbhostslave/trunk/usbDevice/syn
    from Rev 39 to Rev 40
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  •

Rev 39 → Rev 40

/altera/usbDeviceAlteraTop.qsf
0,0 → 1,202
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
# The default values for assignments are stored in the file
# cyc_or12_mini_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
 
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
 
 
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY usbDeviceAlteraTop
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "06:48:46 JUNE 20, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
 
#48MHz local oscillator
set_global_assignment -name FMAX_REQUIREMENT "20.83 ns" -section_id clk
set_global_assignment -name DUTY_CYCLE 50 -section_id clk
 
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
 
 
set_location_assignment PIN_30 -to clk
 
 
set_location_assignment PIN_97 -to mc_addr[0]
set_location_assignment PIN_96 -to mc_addr[1]
set_location_assignment PIN_90 -to mc_addr[2]
set_location_assignment PIN_166 -to mc_addr[3]
set_location_assignment PIN_165 -to mc_addr[4]
set_location_assignment PIN_164 -to mc_addr[5]
set_location_assignment PIN_162 -to mc_addr[6]
set_location_assignment PIN_161 -to mc_addr[7]
set_location_assignment PIN_159 -to mc_addr[8]
set_location_assignment PIN_157 -to mc_addr[9]
set_location_assignment PIN_100 -to mc_addr[10]
set_location_assignment PIN_109 -to mc_addr[11]
 
set_location_assignment PIN_106 -to mc_ba[0]
set_location_assignment PIN_105 -to mc_ba[1]
 
set_location_assignment PIN_113 -to mc_cas_
set_location_assignment PIN_156 -to mc_cke_
set_location_assignment PIN_155 -to sdram_clk
set_location_assignment PIN_110 -to sdram_cs
set_location_assignment PIN_116 -to mc_dqm[0]
set_location_assignment PIN_150 -to mc_dqm[1]
set_location_assignment PIN_88 -to mc_dqm[2]
set_location_assignment PIN_167 -to mc_dqm[3]
 
set_location_assignment PIN_111 -to mc_ras_
set_location_assignment PIN_114 -to mc_we_
 
set_location_assignment PIN_47 -to spiClk
set_location_assignment PIN_20 -to spiMasterDataOut
set_location_assignment PIN_44 -to spiCS_n
 
#set_location_assignment PIN_18 -to usbHostOE_n
#set_location_assignment PIN_8 -to usbSlaveVP
#set_location_assignment PIN_7 -to usbSlaveVM
#set_location_assignment PIN_9 -to usbSlaveOE_n
#set_location_assignment PIN_13 -to usbDPlusPullup
#set_location_assignment PIN_4 -to vBusDetect
 
# Santa Cruz Connector
set_location_assignment PIN_16 -to SC_P_CLK
set_location_assignment PIN_15 -to SC_PCS_N
set_location_assignment PIN_188 -to SC_RST_N
set_location_assignment PIN_191 -to SC_P0
set_location_assignment PIN_189 -to SC_P1
set_location_assignment PIN_194 -to SC_P2
set_location_assignment PIN_192 -to SC_P3
set_location_assignment PIN_199 -to SC_P4
set_location_assignment PIN_197 -to SC_P5
set_location_assignment PIN_208 -to SC_P6
set_location_assignment PIN_203 -to SC_P7
set_location_assignment PIN_218 -to SC_P8
set_location_assignment PIN_216 -to SC_P9
set_location_assignment PIN_226 -to SC_P10
set_location_assignment PIN_223 -to SC_P11
set_location_assignment PIN_231 -to SC_P12
set_location_assignment PIN_230 -to SC_P13
set_location_assignment PIN_234 -to SC_P14
set_location_assignment PIN_233 -to SC_P15
set_location_assignment PIN_236 -to SC_P16
set_location_assignment PIN_237 -to SC_P17
set_location_assignment PIN_238 -to SC_P18
set_location_assignment PIN_5 -to SC_P19
set_location_assignment PIN_4 -to SC_P20
set_location_assignment PIN_6 -to SC_P21
set_location_assignment PIN_7 -to SC_P22
set_location_assignment PIN_8 -to SC_P23
set_location_assignment PIN_9 -to SC_P24
set_location_assignment PIN_11 -to SC_P25
set_location_assignment PIN_13 -to SC_P26
set_location_assignment PIN_14 -to SC_P27
set_location_assignment PIN_18 -to SC_P28
set_location_assignment PIN_184 -to SC_P29
set_location_assignment PIN_185 -to SC_P30
set_location_assignment PIN_186 -to SC_P31
set_location_assignment PIN_187 -to SC_P32
set_location_assignment PIN_195 -to SC_P33
set_location_assignment PIN_200 -to SC_P34
set_location_assignment PIN_214 -to SC_P35
set_location_assignment PIN_222 -to SC_P36
set_location_assignment PIN_228 -to SC_P37
set_location_assignment PIN_232 -to SC_P38
set_location_assignment PIN_235 -to SC_P39
 
 
 
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
 
 
 
 
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 1000
 
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
 
 
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
 
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name CLOCK_SETTINGS clk -to clk
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
 
set_global_assignment -name USER_LIBRARIES "..\\..\\..\\rtl\\include;..\\..\\rtl"
 
set_global_assignment -name VERILOG_FILE ../../../RTL/wrapper/usbSlave.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/USBSlaveControlBI.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/endpMux.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/fifoMux.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/sctxportarbiter.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slavecontroller.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveDirectcontrol.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveGetpacket.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveRxStatusMonitor.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveSendpacket.v
set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/usbSlaveControl.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/writeUSBWireData.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/lineControlUpdate.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxBit.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxByte.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processTxByte.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/readUSBWireData.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/siereceiver.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/SIETransmitter.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC5.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC16.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMuxBI.v
set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMux.v
set_global_assignment -name VERILOG_FILE ../../../RTL/busInterface/wishBoneBI.v
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifoBI.v
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/dpMem_dc.v
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/fifoRTL.v
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifo.v
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifoBI.v
set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifo.v
set_global_assignment -name VERILOG_FILE ../../RTL/wishboneArb.v
set_global_assignment -name VERILOG_FILE ../../RTL/checkLineState.v
set_global_assignment -name VERILOG_FILE ../../RTL/EP0.v
set_global_assignment -name VERILOG_FILE ../../RTL/EP1Mouse.v
set_global_assignment -name VERILOG_FILE ../../RTL/pll_48MHz.v
set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice.v
set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice_define.v
set_global_assignment -name VERILOG_FILE ../../RTL/usbDeviceAlteraTop.v
set_global_assignment -name VERILOG_FILE ../../RTL/usbHostSlaveReg_define.v
set_global_assignment -name VERILOG_FILE ../../RTL/usbROM.v
set_global_assignment -name SDC_FILE usbDeviceAlteraTop.sdc
/altera/usbDeviceAlteraTop.qpf
0,0 → 1,23
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
 
QUARTUS_VERSION = "7.2"
DATE = "13:52:36 August 08, 2008"
 
 
# Revisions
 
PROJECT_REVISION = "usbDeviceAlteraTop"
/altera/usbDeviceAlteraTop.cof
0,0 → 1,17
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<eprom_name>NONE</eprom_name>
<output_filename>usbDeviceAlteraTop.rbf</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>0</mode>
<sof_data>
<page_flags>1</page_flags>
<bit0>
<sof_filename>usbDeviceAlteraTop.sof</sof_filename>
</bit0>
</sof_data>
<version>4</version>
<options>
</options>
</cof>
/altera/download.bat
0,0 → 1,3
fpgaConfig -i usbDeviceAlteraTop.rbf -r -a 0 -w -l
pause
 
/altera/usbDeviceAlteraTop.sdc
0,0 → 1,114
## Generated SDC file "cyc_or12_mini_top.sdc"
 
## Copyright (C) 1991-2007 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
 
 
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition"
 
## DATE "Fri May 16 09:55:20 2008"
 
##
## DEVICE "EP2C20Q240C8"
##
 
 
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {clk} -period 20.830 -waveform { 0.000 10.415 } [get_ports {clk}] -add
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
derive_pll_clocks -use_tan_name
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
 
 
#**************************************************************
# Set Load
#**************************************************************
 
/Actel/copyRTLtoActelHDLFolder.bat
0,0 → 1,11
copy /Y ..\..\RTL\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\buffers\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\busInterface\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\hostSlaveMux\hostSlaveMuxBI.v.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\include\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\serialInterfaceEngine\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\slaveController\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\wrapper\usbSlave.v usbDeviceActelTop\hdl
 
pause
 
/Actel/usbDeviceActelTop/usbDeviceActelTop.prj
0,0 → 1,504
KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\RTL"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "IGLOO"
KEY VendorTechnology_Die "IS6X6M2LP"
KEY VendorTechnology_Package "fg256"
KEY ProjectLocation "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "usbDeviceActelTop::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\constraint\usbDeviceActelTop.pdc,pdc"
STATE="utd"
TIME="1207237677"
SIZE="6506"
ENDFILE
VALUE "<project>\designer\impl1\usbDevice.adb,adb"
STATE="ood"
TIME="1219427579"
SIZE="1078784"
ENDFILE
VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
STATE="utd"
TIME="1219440016"
SIZE="1136640"
ENDFILE
VALUE "<project>\designer\impl1\usbDeviceActelTop.pdb,pdb"
STATE="utd"
TIME="1219441261"
SIZE="16384"
ENDFILE
VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
STATE="utd"
TIME="1219441266"
SIZE="293941"
ENDFILE
VALUE "<project>\hdl\checkLineState.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="6885"
ENDFILE
VALUE "<project>\hdl\dpMem_dc.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="3862"
ENDFILE
VALUE "<project>\hdl\endpMux.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="8260"
ENDFILE
VALUE "<project>\hdl\EP0.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="25833"
ENDFILE
VALUE "<project>\hdl\EP1Mouse.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="9454"
ENDFILE
VALUE "<project>\hdl\fifoMux.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="6575"
ENDFILE
VALUE "<project>\hdl\fifoRTL.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="6307"
ENDFILE
VALUE "<project>\hdl\hostSlaveMuxBI.v,hdl"
STATE="utd"
TIME="1219427436"
SIZE="4931"
ENDFILE
VALUE "<project>\hdl\lineControlUpdate.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="3451"
ENDFILE
VALUE "<project>\hdl\processRxBit.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="15071"
ENDFILE
VALUE "<project>\hdl\processRxByte.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="17214"
ENDFILE
VALUE "<project>\hdl\processTxByte.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="15227"
ENDFILE
VALUE "<project>\hdl\readUSBWireData.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="10944"
ENDFILE
VALUE "<project>\hdl\RxFifo.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5079"
ENDFILE
VALUE "<project>\hdl\RxFifoBI.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5600"
ENDFILE
VALUE "<project>\hdl\sctxportarbiter.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="7476"
ENDFILE
VALUE "<project>\hdl\siereceiver.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="9992"
ENDFILE
VALUE "<project>\hdl\SIETransmitter.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="24223"
ENDFILE
VALUE "<project>\hdl\slavecontroller.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="17626"
ENDFILE
VALUE "<project>\hdl\slaveDirectcontrol.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="7433"
ENDFILE
VALUE "<project>\hdl\slaveGetpacket.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="12832"
ENDFILE
VALUE "<project>\hdl\slaveRxStatusMonitor.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="3985"
ENDFILE
VALUE "<project>\hdl\slaveSendpacket.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="9072"
ENDFILE
VALUE "<project>\hdl\timescale.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="230"
ENDFILE
VALUE "<project>\hdl\TxFifo.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5002"
ENDFILE
VALUE "<project>\hdl\TxFifoBI.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5596"
ENDFILE
VALUE "<project>\hdl\updateCRC16.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="4076"
ENDFILE
VALUE "<project>\hdl\updateCRC5.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="4274"
ENDFILE
VALUE "<project>\hdl\usbConstants_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="706"
ENDFILE
VALUE "<project>\hdl\usbDevice.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="6821"
ENDFILE
VALUE "<project>\hdl\usbDeviceActelTop.v,hdl"
STATE="utd"
TIME="1219440128"
SIZE="1329"
ENDFILE
VALUE "<project>\hdl\usbDevice_define.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="1297"
ENDFILE
VALUE "<project>\hdl\usbHostControl_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="2187"
ENDFILE
VALUE "<project>\hdl\usbHostSlaveReg_define.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="5597"
ENDFILE
VALUE "<project>\hdl\usbHostSlave_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="5297"
ENDFILE
VALUE "<project>\hdl\usbROM.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="12466"
ENDFILE
VALUE "<project>\hdl\usbSerialInterfaceEngine.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="11255"
ENDFILE
VALUE "<project>\hdl\usbSerialInterfaceEngine_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="3284"
ENDFILE
VALUE "<project>\hdl\usbSlave.v,hdl"
STATE="utd"
TIME="1219427483"
SIZE="15345"
ENDFILE
VALUE "<project>\hdl\usbSlaveControl.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="15326"
ENDFILE
VALUE "<project>\hdl\USBSlaveControlBI.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="24769"
ENDFILE
VALUE "<project>\hdl\usbSlaveControl_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="2718"
ENDFILE
VALUE "<project>\hdl\usbTxWireArbiter.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="7513"
ENDFILE
VALUE "<project>\hdl\wishboneArb.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="5708"
ENDFILE
VALUE "<project>\hdl\wishBoneBI.v,hdl"
STATE="utd"
TIME="1219427420"
SIZE="8684"
ENDFILE
VALUE "<project>\hdl\wishBoneBus_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="1041"
ENDFILE
VALUE "<project>\hdl\writeUSBWireData.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="8542"
ENDFILE
VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
STATE="utd"
TIME="1219427525"
SIZE="3585871"
ENDFILE
VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
STATE="utd"
TIME="1219439810"
SIZE="3661567"
ENDFILE
VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1219439810"
SIZE="376"
ENDFILE
VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1219427525"
SIZE="376"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "usbDevice::work"
FILE "<project>\hdl\usbDevice.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\usbDevice.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDevice.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDevice_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDevice.adb,adb"
VALUE "<project>\designer\impl1\usbDevice.prb,prb"
VALUE "<project>\designer\impl1\usbDevice.stp,stp"
VALUE "<project>\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "usbDeviceActelTop::work"
FILE "<project>\hdl\usbDeviceActelTop.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideDESIGNER(<project>\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
ideSYNTHESIS(<project>\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDeviceActelTop.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.prb,prb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
VALUE "<project>\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=coreconsole
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=C:\Libero\Synplify\Synplify_902A2\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=C:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=C:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=C:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "usbDevice::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\usbDevice.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDevice.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDevice_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDevice.adb,adb"
VALUE "<project>\designer\impl1\usbDevice.prb,prb"
VALUE "<project>\designer\impl1\usbDevice.stp,stp"
VALUE "<project>\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "usbDeviceActelTop::work"
LIST Impl1
LiberoState=Post_Layout
ideDESIGNER(<project>\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
ideSYNTHESIS(<project>\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDeviceActelTop.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.prb,prb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
VALUE "<project>\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
ACTIVE_VIEW:0
ENDLIST
/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.ide_des
0,0 → 1,19
KEY IDE_DES_TOOL "Designer"
KEY IDE_DES_FAMILY "IGLOO"
KEY IDE_DES_DIE "IS6X6M2LP"
KEY IDE_DES_PACKAGE "fg256"
KEY IDE_DES_TOP_CELL_NAME "usbDeviceActelTop"
KEY IDE_DES_KEEP_PHY_CONSTR "FALSE"
KEY IDE_DES_KEEP_TIME_CONSTR "TRUE"
KEY IDE_DES_LAYOUT_DONE "TRUE"
KEY IDE_DES_BA_EXPORTED "FALSE"
KEY IDE_DES_ERROR_FOUND "FALSE"
KEY IDE_DES_ADB_PATH "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\designer\impl1\usbDeviceActelTop.adb"
LIST SOURCE_FILES
VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\synthesis\usbDeviceActelTop.edn;edn"
VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\synthesis\usbDeviceActelTop_sdc.sdc;sdc"
VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\constraint\usbDeviceActelTop.pdc;pdc"
ENDLIST
LIST OPTIONAL_FILES
VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\synthesis\usbDeviceActelTop_sdc.sdc;Used"
ENDLIST
/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.tcl
0,0 → 1,8
# Created by Libero Project Manager 8.3.0.22
# Fri Aug 22 14:28:19 2008
 
# (OPEN DESIGN)
 
 
# set default back-annotation base-name
set_defvar "BA_NAME" "usbDeviceActelTop_ba"
/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.pdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.pdb
Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.pdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb =================================================================== --- Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb (nonexistent) +++ Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb (revision 40)
Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.stp =================================================================== --- Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.stp (nonexistent) +++ Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.stp (revision 40) @@ -0,0 +1,4349 @@ +NOTE "CREATOR" "Designer Version: 8.3.0.22"; +NOTE "CAPTURE" "8.3.0.22"; +NOTE "DEVICE" "AGL600V5"; +NOTE "PACKAGE" "AGL600V5-fg256"; +NOTE "DATE" "2008/08/22"; +NOTE "STAPL_VERSION" "JESD71"; +NOTE "IDCODE" "03b261cf"; +NOTE "DESIGN" "usbDeviceActelTop"; +NOTE "CHECKSUM" "E537"; +NOTE "SECURITY" "Disable"; +NOTE "ALG_VERSION" "17"; +NOTE "MAP_VERSION" "1"; +NOTE "TOOL_VERSION" "1"; +NOTE "MAX_FREQ" "10000000"; +NOTE "SILSIG" "00000000"; +NOTE "TRACKING_SAR" "72850"; +NOTE "SPEED_GRAD" "STD"; +NOTE "TEMP_GRAD" "COM"; +NOTE "PRG_BSR_SET_IO" "Z"; + +ACTION PROGRAM = + W_INITIALIZE, + DO_ERASE, + DO_PROGRAM, + DO_VERIFY_BOL, + DO_PROGRAM_RLOCK, + DO_EXIT; +ACTION PROGRAM_ARRAY = + AW_INITIALIZE, + DO_ERASE_ARRAY, + DO_PROGRAM, + DO_VERIFY_BOL, + DO_PROGRAM_RLOCK, + DO_EXIT; +ACTION ERASE_ARRAY = + AW_INITIALIZE, + DO_ERASE_ARRAY_ONLY, + DO_EXIT; +ACTION ERASE = + W_INITIALIZE, + DO_ERASE_ONLY, + DO_EXIT; +ACTION ERASE_ALL = + INITIALIZE, + DO_ERASE_ALL, + DO_EXIT; +ACTION VERIFY = + R_INITIALIZE, + DO_VERIFY_EOL, + DO_EXIT; +ACTION VERIFY_ARRAY = + AR_INITIALIZE, + DO_VERIFY_EOL, + DO_EXIT; +ACTION READ_IDCODE = + DO_READ_IDCODE; +ACTION VERIFY_DEVICE_INFO = + READ_INITIALIZE, + READ_IDCODE_ONLY, + DO_VERIFY_DEVICE_INFO, + DO_EXIT; +ACTION DEVICE_INFO = + READ_INITIALIZE, + READ_IDCODE_ONLY, + DO_DEVICE_INFO, + DO_QUERY_SECURITY, + DO_EXIT; + + + +DATA CONSTBLOCK; + INTEGER IEEE1532=0; + INTEGER STAPL=1; + INTEGER DIRECTC=2; + INTEGER PDB=3; + INTEGER SVF=4; + INTEGER FP=0; + INTEGER FPLITE=1; + INTEGER FP3=2; + INTEGER SCULPTW=3; + INTEGER BPW=4; + INTEGER DIRECTCP=5; + INTEGER STP=6; + INTEGER FP33=0; + INTEGER FP34=1; + INTEGER FP40=2; + INTEGER FP41=3; + INTEGER FP42=4; + INTEGER FP50=5; + INTEGER FP51=6; + INTEGER FP60=7; + INTEGER FP61=8; + INTEGER FP62=9; + INTEGER UNKNOWN=127; + INTEGER UNSPECIFIED=0; + INTEGER QN132=1; + INTEGER VQ100=2; + INTEGER TQ144=3; + INTEGER PQ208=4; + INTEGER FG144=5; + INTEGER FG256=6; + INTEGER FG484=7; + INTEGER FG676=8; + INTEGER FG896=9; + INTEGER QN108=10; + INTEGER QN180=11; + INTEGER TQ100=12; + INTEGER CQ208=13; + INTEGER FG1152=14; + INTEGER BG456=15; + INTEGER UNDEFINED=63; + INTEGER GRADE_UNSPEC=0; + INTEGER GRADE_1=1; + INTEGER GRADE_2=2; + INTEGER GRADE_3=3; + INTEGER GRADE_F=4; + INTEGER GRADE_STD=5; + INTEGER GRADE_4=6; + INTEGER GRADE_UNDEF=7; +ENDDATA; + +DATA PARAMETERS; + INTEGER FREQ =4; +ENDDATA; + +DATA GV; + INTEGER ULOPT1_BITLOCATION =11; + INTEGER ULOPT0_BITLOCATION =10; + INTEGER ULUWE_BITLOCATION =9; + INTEGER ULARE_BITLOCATION =8; + INTEGER ULUPC_BITLOCATION =7; + INTEGER ULUFE_BITLOCATION =6; + INTEGER ULUFP_BITLOCATION =5; + INTEGER ULUFJ_BITLOCATION =4; + INTEGER ULFLR_BITLOCATION =3; + INTEGER ULULR_BITLOCATION =2; + INTEGER ULAWE_BITLOCATION =1; + INTEGER ULARD_BITLOCATION =0; + BOOLEAN BUFF128[128]; + BOOLEAN BUFF32[32]; + INTEGER I; + INTEGER J; + INTEGER TEMP; + INTEGER SDNUMBER; + INTEGER ROWNUMBER; + INTEGER DATAINDEX =0; + INTEGER FROMROWNUMBER =1; + INTEGER AESBLOCK; + BOOLEAN ID[32]; + BOOLEAN PASS = 1; + BOOLEAN FADDR[3]; + INTEGER STATUS =0; + BOOLEAN SILSIG[32] = $00000000; + BOOLEAN ISC_CONFIG_RESULT[18]; + BOOLEAN VERIFYEOL[2]; + BOOLEAN COMBERASESELECT[23]; + BOOLEAN SECKEY_OK = 1; + BOOLEAN SECREG[44]; + BOOLEAN ULUWE = 0; + BOOLEAN ULARE = 0; + BOOLEAN ULUPC = 0; + BOOLEAN ULUFE = 0; + BOOLEAN ULUFP = 0; + BOOLEAN ULUFJ = 0; + BOOLEAN ULFLR = 0; + BOOLEAN ULULR = 0; + BOOLEAN ULAWE = 0; + BOOLEAN ULARD = 0; + BOOLEAN ULOPT[2]; + BOOLEAN SUROWCHECKSUM[16]; + INTEGER SUROWCYCLECOUNT =0; + INTEGER ACT_UROW_CYCLE_COUNT =0; + BOOLEAN ACT_UROW_DESIGN_NAME[70] = $2be746469b7978e9c1; + BOOLEAN SUROWDESIGNNAME[70]; + BOOLEAN SUROWPROGMETHOD[3]; + BOOLEAN ACT_UROW_ALGO_VERSION[7] = $11; + BOOLEAN SUROWALGOVERSION[7]; + BOOLEAN SUROW_PKG_TYPE[6]; + BOOLEAN ACT_UROW_SW_VERSION[7]; + BOOLEAN SUROW_SW_VERSION[7]; + INTEGER PLAYERVERSIONVARIABLE =0; + INTEGER SCULPTORMAJORBASE =4; + INTEGER SCULPTORMINORBASE =50; + INTEGER PLAYER_VERSION_VARIABLE =0; + INTEGER SCULPTOR_MAJOR_BASE =4; + INTEGER SCULPTOR_MINOR_BASE =50; + BOOLEAN ACT_UROW_PROGRAM_SW[4] = $f; + BOOLEAN SUROWPROGRAMSW[4]; + BOOLEAN SUROW_SPEED_GRADE[3]; + BOOLEAN SUROW_SRAM_DISTURB[1]; + BOOLEAN ISERASEONLY = 0; + BOOLEAN ISRESTOREDESIGN = 0; + BOOLEAN FLAGDISPLAYCYC = 0; + BOOLEAN BSRPATTERN[1056] = $924924924924924924924924924924924924924924924924 + 924924924924924924924924924924924924924924924924924924924924924924924924 + 924924924924924924924924924924924924924924924924924924924924924924924924 + 924924924924924924924924924924924924924924924924924924924924924924924924 + ; + BOOLEAN SAMPLEMASK[1056] = $000000000000000000000000000000000000000000000000 + 000000000000000000000000000000000000000000000000000000000000000000000000 + 000000000000000000000000000000000000000000000000000000000000000000000000 + 000000000000000000000000000000000000000000000000000000000000000000000000 + ; + BOOLEAN RLOCK[1248] = $7fffffcffffffbfffffeffffffbfffffefffffffffffffffffff3 + fffffcffffff3fffffcffffff3fffffcffffff3fffffdffffff3fffffcffffff3fffffcf + fffff3fffffcffffff3fffffdffffff3fffffcffffff3fffffcffffff3fffffcffffff3f + ffffdffffff3fffffcffffff3fffffcffffff3fffffcffffff3fffffdfffffffffffffff + fffffffffffffffffffffffffffffffffffffffffff; + BOOLEAN ARRAYRONLY = 1; + BOOLEAN CHKARRAY = 0; + BOOLEAN FROMRONLY = 1; + BOOLEAN CHKFROM = 0; + BOOLEAN CHKNVM = 0; + BOOLEAN CHKSEC = 1; + BOOLEAN PERMLOCK = 0; + INTEGER HEX[16] = 70,69,68,67,66,65,57,56,55,54,53,52,51,50,49,48; + INTEGER NUMBEROFFROMROWS =8; + BOOLEAN INITIALIZE_DATA[5] = $00; + INTEGER SDTILE; + INTEGER NUMBEROFSDTILES =6; + INTEGER NUMBEROFMAPROWS =3444; + INTEGER IDREV; + INTEGER IDFAB; + INTEGER BM7DEVICE =0; + INTEGER BM1DEVICE =0; + BOOLEAN M1BUFF[128] = $acdd6548ccb488863e291eb18fe95077; + BOOLEAN M7BUFF[128] = $e137623a2eeee91126015f3f73664945; + BOOLEAN IDCODEVALUE[32] = $03b261cf; + BOOLEAN IDMASK[32] = $06ffffff; + INTEGER SECKEYCHK =0; + INTEGER DESIGNPKGTYPE =6; + BOOLEAN ACT_UROW_PROG_METHOD[3] = $1; + INTEGER LABEL_SEPARATOR =0; +ENDDATA; + +DATA BITSTREAM; + BOOLEAN UROW[128]; + BOOLEAN UROW_MASK[128] = $fffffffffffffffffffffffffe01ffc0; + BOOLEAN DATASTREAM[4298112] = @mA320000110040W0W000020G000400108002200000Ww0 + rssso0000p@@lF999IjjjQp0000_@x@@IYaatcjD50000y_@V3HIIIORRRR36eXaa49jjDR1 + 0000@x_@HIg11I30000yxxt7Ig69u@@VCDCK3Wm61000_@V1H0vssMj90008@@z@69HIo000 + 049IIICIII2761000Gaaa0Yaa4O3CGaaa4XaaaQu0aaaaWaaag1g0Oaa89Wa4910GDy0IIII + 10000100602WaaaC16a47q570000GIIIID8dsssMssssS899H9000ejjLRkjDRpIIaa7000u + sijjqgjj4HIII00000RRRRORRB1aaayU8e6G0sMMaQW2ossWg1Aejj59DiGDW4sORRssba89 + 7000mskWKWaaa4P0000B99Hoba89dscjTc499RIaaa9IIIiPRRxHIIIMIIIY899HWjjjQ899 + HZaa89IIYCHRhsMIIaqIIaaa85IMYPRRRGQIQIDW0A98qijjb8D99a6AGIYjTQW0a899IYaa + 89qsc68e6uX9999kjjjw899HcaaKG8Gssscjaaa8B10999JT4WaaaurPGnYWSb1899f90008 + GIIY90000GIIa600r02W00000IQYa00000a89110000aC9D100W0G6IMoHpWQ01T2LK3S109 + 9fQ07wTCeOXW103g1EeohWQ02Qo800004100WQW30000M2jmSG1r0408000010HM44f19q85 + HDm5H3CKGiWQRRRE9991Q70jjjLWaa4X00W922KRRRSCT00000ijj5fRAeMqMETJ1iXjfYaa + a8080K3KWssMeqW5ORaaa6aGD07OIIIIvEe6G1QRRRmsssS999Hi@@t@sscjZjDRRIIaam@z + @FRN3GWsZa499y@_@7Rrssqgjz6HIIISDm1cjl9h1KWRRBYaaaOV@@Ff15ej999DGXQW2w4G + e6O3LIII4@@@zjjjPpQRhWW04@@@_GRRrMRRpsijLRxlDRRtMjjTtijjNrss6pssssssscss + sMJRRRMQRRLYjjPRijLppsMD01IORRrMRVpqejLRBjCRPnMjjDskjjPrss6poss8DmWQ02ij + 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W4UFuWQ0kgW0A4000a6W10A99J3W04999r00Hd0HK3mL54uGKEwD0m@30ml080WecUO9T5lF + YXSCkBOuIwjYpKH_FqwOwNcniWRe605kmhX9QHBLLC_md00081R3OWW04WV28uni2cVrWr0E + 0810viI5aB23RrJmJ1Ia6TKXM@G898L30a9b7L66P6QjC30yVQDn_qB7bHS18W4Ws2CBdWPI + Rcew64CE1bQOEblc7AE1HgLGlSfui0dPJhHbJLrAr1cAvcXU4o2998PdqBGGIKgqK42VrW2g + te60d2Vj2f999r0G0f98fQ0CW4a4499fhS28GQIKYaa4qE1O0GIIId0581999QW680915QjN + DCi2W08WaaKBH4U28PmGh@Fm9Pp9mo2FoGYa4Kx7PK3G3ab4a2jMhS2meJWC0IIIcJGPfEGJ + 14K5Qz@XM@Ver@7QDm30y@00O7GR39N_V1eAd3wf30qyrwTbuxFv4yGGTDcVCO9NES1rf6Qz + @TM@VerblzoOj5yJE1n5Qznn9yVer@7gJO99nPeEoSRJ6XMpKdqDGMIKALL6AeU31998XMBM + tgDGMIKAqw2a5aaajj7r04Ler9baKRn_zVeEWdM3dfSTNerla8IWv4mPu4Sgjjjb1000c@RV + VIIIaQQRrc1000y@c@@b499lDRRB0000uz@@FYaaamssss606uXaa49jjTD0Cf100W0000@3 + 00OI000R100a000Wy100O40003WmaBWOIIIX270aaa4WaaqxL78IIIYGIIID07Waaaivv3g1 + 0A0610dxl0I000G20091SGzm4i1W1GIIIQoeXcPK8bO3g1eA400Wr0eGT17awG2iiajvGIIY + I000GRRhsSR9scba89F000mjPRRfLRRBIbo6ORRR3RRRhWaaaz08e60dq000m600WB100C00 + WK78WB00Wa00WD08GIIIYRP29EjjjwijjPtaa89JYaaORhssRRssUIaaa8HIIYPRRRKRRR39 + 999aaaaWsssiqssgbaai60ca000O200WR100CB00W9000o400Gs000i68SY20IQJcwG1@SJ0 + 0GIRa4800000ZpeWjkFOyX4oNGXQ0Q2Wa0m8ZM01000810GUu702081I0WG945q_k2jYVGM4 + JK30IzROGD08qaU154SWQBGRE999DKS0a6mM1III4200YgZ0rsssrQe0ssss2qDO002g1m9r + aaaO200c1d00000OHII49000089H2QRhsmsRiT99IIi@z@@sgjjZLjRRYaaaG@@@FssssWjj + jPIIIYm@@lVijDRJRRNMG0Y@@@Q0Uocaa4iaa4LIII4@JIai99How9HIca499_499Xsijjsi + @jPpssstMosERRRRTxVRUjjjPijaPxjjLRjjDRZssnAAWjjjDijjDpsssCsssinssM30Jsaa + aqsssQRIIYSRRhsD99IcjjQxta89nsgjz08ek@3Vjy10_FqwNQtqW8wX8ek@3jkb25OewwF3 + Ev@WJ_Fuaw3uy@m_fEua@3Ev@10_FrXI11004SIij4MGZ9@7So@1gZLmm@7e_@1EzVm9mcNZ + 11dyVm9FJG2Ig60609996So@jI020110040Gv0G040G0004002080022K3GX; + INTEGER CHECKSUM =58679; +ENDDATA; + + +PROCEDURE DO_EXIT USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $81; + WAIT IDLE, 20 USEC; + IF ( ! (STATUS!=0) ) THEN GOTO Label_0; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $07; + WAIT IDLE, 1 CYCLES; + Label_0: + WAIT 200 USEC; + STATE RESET ; + EXIT STATUS; +ENDPROC; + +PROCEDURE DO_READ_SECURITY USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a4; + WAIT IDLE, 3 CYCLES; + DRSCAN 44, $00000000000, CAPTURE SECREG[]; + ULUWE = SECREG[ULUWE_BITLOCATION]; + ULARE = SECREG[ULARE_BITLOCATION]; + ULUPC = SECREG[ULUPC_BITLOCATION]; + ULUFE = SECREG[ULUFE_BITLOCATION]; + ULUFP = SECREG[ULUFP_BITLOCATION]; + ULUFJ = SECREG[ULUFJ_BITLOCATION]; + ULFLR = SECREG[ULFLR_BITLOCATION]; + ULULR = SECREG[ULULR_BITLOCATION]; + ULAWE = SECREG[ULAWE_BITLOCATION]; + ULARD = SECREG[ULARD_BITLOCATION]; + ULOPT[1] = SECREG[ULOPT1_BITLOCATION]; + ULOPT[0] = SECREG[ULOPT0_BITLOCATION]; +ENDPROC; + +PROCEDURE DO_OUTPUT_SECURITY USES GV; + PRINT "Security Settings :"; + IF ( ! (ULUFP==1) ) THEN GOTO Label_1; + PRINT "FlashROM Write/Erase protected by pass key."; + Label_1: + IF ( ! (ULUFJ==1) ) THEN GOTO Label_2; + PRINT "FlashROM Read protected by pass key."; + Label_2: + IF ( ! (ULAWE==1) ) THEN GOTO Label_3; + PRINT "Array Write/Erase protected by pass key."; + Label_3: + IF ( ! (ULARD==1) ) THEN GOTO Label_4; + PRINT "Array Verify protected by pass key."; + Label_4: + IF ( ! (ULUFE==1) ) THEN GOTO Label_5; + PRINT "Encrypted FlashROM Programming Enabled."; + Label_5: + IF ( ! (ULARE==1) ) THEN GOTO Label_6; + PRINT "Encrypted FPGA Array Programming Enabled."; + Label_6: + PRINT "========================================="; +ENDPROC; + +PROCEDURE DO_QUERY_SECURITY USES DO_READ_SECURITY,DO_OUTPUT_SECURITY; + CALL DO_READ_SECURITY; + CALL DO_OUTPUT_SECURITY; +ENDPROC; + +PROCEDURE READ_UROW USES BITSTREAM,GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a8; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE UROW[]; + SUROWALGOVERSION[6..0] = $00; + IF ( ! ( (UROW[5]==0)&&(UROW[0]==1)) ) THEN GOTO Label_7; + SUROWALGOVERSION[5..4] = UROW[24..23]; + Label_7: + IF ( ! ( (UROW[5]==1)&&(UROW[0]==0)) ) THEN GOTO Label_8; + SUROWALGOVERSION[5..4] = UROW[24..23]; + SUROWALGOVERSION[6] = 1; + Label_8: + SUROWCHECKSUM[15..0] = UROW[127..112]; + SUROWCYCLECOUNT = INT(UROW[111..102]); + SUROWDESIGNNAME[69..0] = UROW[101..32]; + SUROWPROGMETHOD[2..0] = UROW[31..29]; + SUROWALGOVERSION[3..0] = UROW[28..25]; + SUROW_PKG_TYPE[5..0] = UROW[22..17]; + SUROW_SW_VERSION[6..0] = UROW[16..10]; + SUROWPROGRAMSW[3..0] = UROW[9..6]; + SUROW_SRAM_DISTURB[0] = UROW[4]; + SUROW_SPEED_GRADE[2..0] = UROW[3..1]; + ACT_UROW_CYCLE_COUNT = SUROWCYCLECOUNT; +ENDPROC; + +PROCEDURE FIX_INT_ARRAYS USES GV; + IF ( ! (HEX[0]!=48) ) THEN GOTO Label_9; + FOR I = 0 TO 7; + TEMP = HEX[I]; + HEX[I] = HEX[(15-I)]; + HEX[(15-I)] = TEMP; + NEXT I; + Label_9: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DISP_CHKSUM_DESIGN USES GV,FIX_INT_ARRAYS; + CALL FIX_INT_ARRAYS; + PRINT "CHECKSUM: ",CHR$(HEX[INT(SUROWCHECKSUM[15..12])]),CHR$(HEX[INT(SUROWCHECKSUM[11..8])]) + ,CHR$(HEX[INT(SUROWCHECKSUM[7..4])]),CHR$(HEX[INT(SUROWCHECKSUM[3..0])]); + PRINT "Design Name: ",CHR$(INT(SUROWDESIGNNAME[63..69])),CHR$(INT(SUROWDESIGNNAME[56..62])) + ,CHR$(INT(SUROWDESIGNNAME[49..55])),CHR$(INT(SUROWDESIGNNAME[42..48])),CHR$(INT(SUROWDESIGNNAME[35..41])) + ,CHR$(INT(SUROWDESIGNNAME[28..34])),CHR$(INT(SUROWDESIGNNAME[21..27])),CHR$(INT(SUROWDESIGNNAME[14..20])) + ,CHR$(INT(SUROWDESIGNNAME[7..13])),CHR$(INT(SUROWDESIGNNAME[0..6])); +ENDPROC; + +PROCEDURE DISPLAY_UROW USES CONSTBLOCK,GV,DISP_CHKSUM_DESIGN; + PRINT "User information: "; + CALL DISP_CHKSUM_DESIGN; + IF ( ! (FLAGDISPLAYCYC==1) ) THEN GOTO Label_10; + PRINT "CYCLE COUNT: ",SUROWCYCLECOUNT; + Label_10: + INTEGER TMPINT =INT(SUROWPROGMETHOD[]); + INTEGER TMPINT2 =0; + INTEGER TMPINT3 =0; + INTEGER TMPINT4 =0; + INTEGER TMPINT5 =0; + IF ( ! (TMPINT==IEEE1532) ) THEN GOTO Label_11; + PRINT "Programming Method: IEEE1532"; + Label_11: + IF ( ! (TMPINT==STAPL) ) THEN GOTO Label_12; + PRINT "Programming Method: STAPL"; + Label_12: + IF ( ! (TMPINT==DIRECTC) ) THEN GOTO Label_13; + PRINT "Programming Method: DirectC"; + Label_13: + IF ( ! (TMPINT==PDB) ) THEN GOTO Label_14; + PRINT "Programming Method: PDB"; + Label_14: + IF ( ! (TMPINT==SVF) ) THEN GOTO Label_15; + PRINT "Programming Method: SVF"; + Label_15: + PRINT "Algorithm Version: ",INT(SUROWALGOVERSION[6..0]); + TMPINT = INT(SUROW_PKG_TYPE[]); + IF ( ! (TMPINT==UNSPECIFIED) ) THEN GOTO Label_16; + PRINT "Device Package Type: package information not available from device"; + Label_16: + IF ( ! (TMPINT==QN132) ) THEN GOTO Label_17; + PRINT "Device Package Type: QN132/QNG132"; + Label_17: + IF ( ! (TMPINT==VQ100) ) THEN GOTO Label_18; + PRINT "Device Package Type: VQ100/VQG100"; + Label_18: + IF ( ! (TMPINT==TQ144) ) THEN GOTO Label_19; + PRINT "Device Package Type: TQ144/TQG144"; + Label_19: + IF ( ! (TMPINT==PQ208) ) THEN GOTO Label_20; + PRINT "Device Package Type: PQ208/PQG208"; + Label_20: + IF ( ! (TMPINT==FG144) ) THEN GOTO Label_21; + PRINT "Device Package Type: FG144/FGG144"; + Label_21: + IF ( ! (TMPINT==FG256) ) THEN GOTO Label_22; + PRINT "Device Package Type: FG256/FGG256"; + Label_22: + IF ( ! (TMPINT==FG484) ) THEN GOTO Label_23; + PRINT "Device Package Type: FG484/FGG484"; + Label_23: + IF ( ! (TMPINT==FG676) ) THEN GOTO Label_24; + PRINT "Device Package Type: FG676/FGG676"; + Label_24: + IF ( ! (TMPINT==FG896) ) THEN GOTO Label_25; + PRINT "Device Package Type: FG896/FGG896"; + Label_25: + IF ( ! (TMPINT==QN108) ) THEN GOTO Label_26; + PRINT "Device Package Type: QN108/QNG108"; + Label_26: + IF ( ! (TMPINT==QN180) ) THEN GOTO Label_27; + PRINT "Device Package Type: QN180/QNG180"; + Label_27: + IF ( ! (TMPINT==TQ100) ) THEN GOTO Label_28; + PRINT "Device Package Type: TQ100/TQG100"; + Label_28: + IF ( ! (TMPINT==CQ208) ) THEN GOTO Label_29; + PRINT "Device Package Type: CQ208/CQG208"; + Label_29: + IF ( ! (TMPINT==FG1152) ) THEN GOTO Label_30; + PRINT "Device Package Type: FG1152/FGG1152"; + Label_30: + IF ( ! (TMPINT==BG456) ) THEN GOTO Label_31; + PRINT "Device Package Type: BG456/BGG456"; + Label_31: + IF ( ! (TMPINT==UNDEFINED) ) THEN GOTO Label_32; + PRINT "Device Package Type: package information not available from device"; + Label_32: + TMPINT = INT(SUROW_SPEED_GRADE[]); + IF ( ! (TMPINT==GRADE_UNSPEC) ) THEN GOTO Label_33; + PRINT "Device Speed Grade: speed grade information not available from device"; + Label_33: + IF ( ! (TMPINT==GRADE_1) ) THEN GOTO Label_34; + PRINT "Device Speed Grade: -1"; + Label_34: + IF ( ! (TMPINT==GRADE_2) ) THEN GOTO Label_35; + PRINT "Device Speed Grade: -2"; + Label_35: + IF ( ! (TMPINT==GRADE_3) ) THEN GOTO Label_36; + PRINT "Device Speed Grade: -3"; + Label_36: + IF ( ! (TMPINT==GRADE_F) ) THEN GOTO Label_37; + PRINT "Device Speed Grade: -F"; + Label_37: + IF ( ! (TMPINT==GRADE_STD) ) THEN GOTO Label_38; + PRINT "Device Speed Grade: STD"; + Label_38: + IF ( ! (TMPINT==GRADE_4) ) THEN GOTO Label_39; + PRINT "Device Speed Grade: -4"; + Label_39: + IF ( ! (TMPINT==GRADE_UNDEF) ) THEN GOTO Label_40; + PRINT "Device Speed Grade: speed grade information not available from device"; + Label_40: + TMPINT = INT(SUROWPROGRAMSW[]); + IF ( ! (TMPINT==FP) ) THEN GOTO Label_41; + PRINT "Programmer: FlashPro"; + Label_41: + IF ( ! (TMPINT==FPLITE) ) THEN GOTO Label_42; + PRINT "Programmer: FlashPro Lite"; + Label_42: + IF ( ! (TMPINT==FP3) ) THEN GOTO Label_43; + PRINT "Programmer: FlashPro3"; + Label_43: + IF ( ! (TMPINT==SCULPTW) ) THEN GOTO Label_44; + PRINT "Programmer: SiliconSculptor II"; + Label_44: + IF ( ! (TMPINT==BPW) ) THEN GOTO Label_45; + PRINT "Programmer: BP Programmer"; + Label_45: + IF ( ! (TMPINT==DIRECTCP) ) THEN GOTO Label_46; + PRINT "Programmer: DirectC"; + Label_46: + IF ( ! (TMPINT==STP) ) THEN GOTO Label_47; + PRINT "Programmer: Actel JAM Player"; + Label_47: + IF ( ! ( ( (TMPINT==FP)||(TMPINT==FPLITE))||(TMPINT==FP3)) ) THEN GOTO Label_59; + TMPINT2 = INT(SUROW_SW_VERSION[]); + IF ( ! (TMPINT2==FP33) ) THEN GOTO Label_48; + PRINT "Software: FlashPro v3.3"; + Label_48: + IF ( ! (TMPINT2==FP34) ) THEN GOTO Label_49; + PRINT "Software: FlashPro v3.4"; + Label_49: + IF ( ! (TMPINT2==FP40) ) THEN GOTO Label_50; + PRINT "Software: FlashPro v4.0"; + Label_50: + IF ( ! (TMPINT2==FP41) ) THEN GOTO Label_51; + PRINT "Software: FlashPro v4.1"; + Label_51: + IF ( ! (TMPINT2==FP42) ) THEN GOTO Label_52; + PRINT "Software: FlashPro v4.2"; + Label_52: + IF ( ! (TMPINT2==FP50) ) THEN GOTO Label_53; + PRINT "Software: FlashPro v5.0"; + Label_53: + IF ( ! (TMPINT2==FP51) ) THEN GOTO Label_54; + PRINT "Software: FlashPro v5.1"; + Label_54: + IF ( ! (TMPINT2==FP60) ) THEN GOTO Label_55; + PRINT "Software: FlashPro v6.0"; + Label_55: + IF ( ! (TMPINT2==FP61) ) THEN GOTO Label_56; + PRINT "Software: FlashPro v6.1"; + Label_56: + IF ( ! (TMPINT2==FP62) ) THEN GOTO Label_57; + PRINT "Software: FlashPro v6.2"; + Label_57: + IF ( ! (TMPINT2==UNKNOWN) ) THEN GOTO Label_58; + PRINT "Software: FlashPro vX.X"; + Label_58: + LABEL_SEPARATOR = 0; + Label_59: + IF ( ! ( (TMPINT==SCULPTW)||(TMPINT==BPW)) ) THEN GOTO Label_63; + TMPINT3 = (INT(SUROW_SW_VERSION[6..5])+SCULPTORMAJORBASE); + TMPINT4 = (INT(SUROW_SW_VERSION[4..1])+SCULPTORMINORBASE); + TMPINT5 = 0; + IF ( ! (SUROW_SW_VERSION[0]==1) ) THEN GOTO Label_60; + TMPINT5 = 1; + Label_60: + IF ( ! (TMPINT==SCULPTW) ) THEN GOTO Label_61; + PRINT "Software: Sculptor Win v",TMPINT3,".",TMPINT4,".",TMPINT5; + Label_61: + IF ( ! (TMPINT==BPW) ) THEN GOTO Label_62; + PRINT "Software: BP Win v",TMPINT3,".",TMPINT4,".",TMPINT5; + Label_62: + LABEL_SEPARATOR = 0; + Label_63: + PRINT "========================================="; +ENDPROC; + +PROCEDURE READ_F_ROW USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $f9; + DRSCAN 3, FADDR[]; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $bf; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[]; +ENDPROC; + +PROCEDURE DO_DEVICE_INFO USES GV,READ_UROW,DISPLAY_UROW,READ_F_ROW; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0e; + WAIT IDLE, 1 CYCLES; + DRSCAN 32, $00000000, CAPTURE BUFF32[]; + EXPORT "SILSIG", BUFF32[]; + CALL READ_UROW; + CALL DISPLAY_UROW; + FADDR[] = $0; + CALL READ_F_ROW; + EXPORT "FSN", BUFF128[55..8]; + PRINT "========================================="; +ENDPROC; + +PROCEDURE INIT_AES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $dd; + DRSCAN 128, $00000000000000000000000000000000; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 120 USEC; +ENDPROC; + +PROCEDURE DO_VERIFY_DEVICE_INFO USES GV,BITSTREAM,DO_EXIT,DO_READ_SECURITY,READ_UROW + ,DISP_CHKSUM_DESIGN; + CALL READ_UROW; + CALL DISP_CHKSUM_DESIGN; + CALL DO_READ_SECURITY; + BUFF32[31..0] = BOOL(CHECKSUM); + UROW[127..112] = BUFF32[15..0]; + UROW[101..32] = ACT_UROW_DESIGN_NAME[69..0]; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a8; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 264 USEC; + DRSCAN 128, $00000000000000000000000000000000,COMPARE UROW[],$ffff003fffffffffffffffff00000000 + ,PASS; + IF ( ! (PASS==0) ) THEN GOTO UROW_CMP_OK; + STATUS = -43; + PRINT "UROW setting error."; + CALL DO_EXIT; + UROW_CMP_OK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE READ_IDCODE_ONLY USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0f; + WAIT IDLE, 1 CYCLES; + DRSCAN 32, $00000000, CAPTURE ID[]; + EXPORT "IDCODE", ID[]; +ENDPROC; + +PROCEDURE VERIFY_ID_DMK USES GV,DO_EXIT,INIT_AES; + CALL INIT_AES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0a; + DRSCAN 128, M7BUFF[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 128 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[],COMPARE $c0000000000000000000000000000000 + ,$c0000000000000000000000000000000,PASS; + IF ( ! (BUFF128[127]==0) ) THEN GOTO M7VERDONE; + STATUS = -31; + PRINT "Failed to verify AES Sec."; + CALL DO_EXIT; + M7VERDONE: + IF ( ! ( (BUFF128[126]==0)||(BM7DEVICE==0)) ) THEN GOTO MXIDOK; + IF ( ! ( (BUFF128[126]==1)&&(BM7DEVICE==0)) ) THEN GOTO LDETECTM1; + STATUS = -32; + PRINT "Failed to verify IDCODE."; + PRINT "M7 Device detected."; + CALL DO_EXIT; + LDETECTM1: + IF ( ! (BUFF128[126]==0) ) THEN GOTO Label_66; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0a; + DRSCAN 128, M1BUFF[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 128 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[],COMPARE $c0000000000000000000000000000000 + ,$c0000000000000000000000000000000,PASS; + IF ( ! (BUFF128[127]==0) ) THEN GOTO M1VERDONE; + STATUS = -31; + PRINT "Failed to verify AES Sec."; + CALL DO_EXIT; + M1VERDONE: + BOOLEAN BTMPBUFFBIT126 = BUFF128[126]; + IF ( ! ( (BTMPBUFFBIT126==1)&&(BM1DEVICE==0)) ) THEN GOTO REGDEV; + STATUS = -32; + PRINT "Failed to verify IDCODE."; + PRINT "M1 Device detected."; + CALL DO_EXIT; + REGDEV: + IF ( ! ( (BTMPBUFFBIT126==0)&&(BM7DEVICE==1)) ) THEN GOTO Label_64; + STATUS = -32; + PRINT "Failed to verify IDCODE."; + PRINT "The Target is not an M7 Device."; + CALL DO_EXIT; + Label_64: + IF ( ! ( (BTMPBUFFBIT126==0)&&(BM1DEVICE==1)) ) THEN GOTO Label_65; + STATUS = -32; + PRINT "Failed to verify IDCODE."; + PRINT "The Target is not an M1 Device."; + CALL DO_EXIT; + Label_65: + LABEL_SEPARATOR = 0; + Label_66: + LABEL_SEPARATOR = 0; + MXIDOK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE VERIFY_IDCODE USES GV,PARAMETERS,DO_EXIT; + FREQUENCY (FREQ*1000000); + WAIT RESET, 5 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0f; + DRSCAN 32, $00000000; + WAIT IDLE, 1 CYCLES; + DRSCAN 32, $00000000, CAPTURE ID[],COMPARE IDCODEVALUE[],IDMASK[],PASS; + IF ( ! (PASS==0) ) THEN GOTO IDOK; + STATUS = 6; + PRINT "Failed to verify IDCODE"; + CALL DO_EXIT; + IDOK: + IDREV = INT(ID[31..28]); + IDFAB = INT(ID[24..24]); +ENDPROC; + +PROCEDURE IS_SECOK USES GV,DO_EXIT; + IF ( ! (SECKEY_OK==0) ) THEN GOTO SECOK; + STATUS = -35; + PRINT "Error, pass key match failure"; + CALL DO_EXIT; + SECOK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_CHECK_R USES GV,DO_EXIT,DO_READ_SECURITY; + CALL DO_READ_SECURITY; + IF ( ! (ULARE==1) ) THEN GOTO ARRAYEPR; + STATUS = -33; + PRINT "FPGA Array Encryption is enforced. Plain text verification is prohibited."; + CALL DO_EXIT; + ARRAYEPR: + IF ( ! (ULARD==1) ) THEN GOTO SKIPRCHK1; + STATUS = -30; + PRINT "FPGA Array Verification is protected by pass key."; + PRINT "A valid pass key needs to be provided."; + CALL DO_EXIT; + SKIPRCHK1: + IF ( ! (ULARD==0) ) THEN GOTO Label_67; + CHKSEC = 0; + Label_67: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_CHECK_W USES GV,DO_EXIT,DO_READ_SECURITY; + CALL DO_READ_SECURITY; + IF ( ! (ULAWE==1) ) THEN GOTO ARRAYWP; + STATUS = -28; + PRINT "FPGA Array Write/Erase is protected by pass key."; + PRINT "A valid pass key needs to be provided."; + CALL DO_EXIT; + ARRAYWP: + IF ( ! (ULARD==1) ) THEN GOTO ARRAYRPW; + STATUS = -30; + PRINT "FPGA Array Verification is protected by pass key."; + PRINT "A valid pass key needs to be provided."; + CALL DO_EXIT; + ARRAYRPW: + IF ( ! (ULARE==1) ) THEN GOTO ARRAYEPW; + STATUS = -33; + PRINT "FPGA Array Encryption is enforced. Plain text programming is prohibited."; + CALL DO_EXIT; + ARRAYEPW: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE BP_VER USES GV; + BOOLEAN PLAYER_VERSION_BOOLEAN[32]; + PLAYER_VERSION_BOOLEAN[31..0] = BOOL(PLAYERVERSIONVARIABLE); + INTEGER PLAYER_MAJOR_VERSION =(INT(PLAYER_VERSION_BOOLEAN[23..16])-SCULPTORMAJORBASE); + INTEGER PLAYER_MINOR_VERSION =(INT(PLAYER_VERSION_BOOLEAN[15..8])-SCULPTORMINORBASE); + ACT_UROW_SW_VERSION[6..5] = BOOL(PLAYER_MAJOR_VERSION); + ACT_UROW_SW_VERSION[4..1] = BOOL(PLAYER_MINOR_VERSION); + ACT_UROW_SW_VERSION[0] = PLAYER_VERSION_BOOLEAN[0]; +ENDPROC; + +PROCEDURE DO_INITIALIZE USES GV,DO_EXIT,VERIFY_ID_DMK,VERIFY_IDCODE,DO_CHECK_R,DO_CHECK_W + ,BP_VER; + CALL VERIFY_IDCODE; + BOOLEAN BSR[1056]; + BOOLEAN SAMPLE_DEVICE[1056]; + BSR[1055..0] = BSRPATTERN[1055..0]; + BOOLEAN SHIFT_DATA[1056]; + IRSCAN 8, $01; + DRSCAN 1056, BSR[]; + WAIT IDLE, 1 CYCLES; + DRSCAN 1056, SHIFT_DATA[], CAPTURE SAMPLE_DEVICE[]; + FOR I = 0 TO 1055; + IF ( ! (SAMPLEMASK[I]==1) ) THEN GOTO Label_68; + BSR[I] = SAMPLE_DEVICE[I]; + Label_68: + LABEL_SEPARATOR = 0; + NEXT I; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $01; + DRSCAN 1056, BSR[]; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $80; + DRSCAN 18, $00000; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 1000 USEC; + DRSCAN 18, $00000,COMPARE $30000,$30000,PASS; + IF ( ! (PASS==0) ) THEN GOTO CRCOK; + STATUS = -26; + PRINT "Failed to enter programming mode."; + EXPORT "ISC_Config_Result", ISC_CONFIG_RESULT[]; + CALL DO_EXIT; + CRCOK: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $84; + DRSCAN 5, INITIALIZE_DATA[], CAPTURE INITIALIZE_DATA[]; + WAIT IDLE, 1 CYCLES; + IF ( ! (INITIALIZE_DATA[2]==1) ) THEN GOTO JTAGOK; + STATUS = -25; + PRINT "Failed to enter programming mode"; + CALL DO_EXIT; + JTAGOK: + CALL VERIFY_ID_DMK; + IF ( ! (CHKARRAY==1) ) THEN GOTO SKIPCHKARRAY; + IF ( ! (ARRAYRONLY==0) ) THEN GOTO Label_69; + CALL DO_CHECK_W; + Label_69: + IF ( ! (ARRAYRONLY==1) ) THEN GOTO Label_70; + CALL DO_CHECK_R; + Label_70: + LABEL_SEPARATOR = 0; + SKIPCHKARRAY: + IF ( ! (PLAYERVERSIONVARIABLE!=0) ) THEN GOTO Label_71; + CALL BP_VER; + Label_71: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE READ_INITIALIZE USES GV,DO_INITIALIZE; + CHKFROM = 0; + CHKARRAY = 0; + CHKNVM = 0; + CHKSEC = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE NW_INITIALIZE USES GV,DO_INITIALIZE; + CHKFROM = 0; + CHKARRAY = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE NR_INITIALIZE USES GV,DO_INITIALIZE; + CHKFROM = 0; + CHKARRAY = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE AW_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 0; + CHKFROM = 0; + CHKARRAY = 1; + CHKNVM = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE AR_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 1; + CHKFROM = 0; + CHKARRAY = 1; + CHKNVM = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE W_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 0; + CHKARRAY = 1; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE R_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 1; + CHKARRAY = 1; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 0; + FROMRONLY = 0; + CHKFROM = 1; + CHKARRAY = 1; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE POLL_ERASE USES GV; + PASS = 0; + INTEGER ILOOP_0; + FOR ILOOP_0 = 262141 - 1 TO 0 STEP -1; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $84; + WAIT IDLE, 1 CYCLES; + WAIT IDLE, 1000 USEC; + DRSCAN 5, $00,COMPARE $00,$03,PASS; + IF PASS THEN ILOOP_0 = 0; + NEXT ILOOP_0; +ENDPROC; + +PROCEDURE POLL_PROGRAM USES GV; + INTEGER ILOOP_1; + FOR ILOOP_1 = 16381 - 1 TO 0 STEP -1; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $84; + WAIT IDLE, 1 CYCLES; + WAIT IDLE, 100 USEC; + DRSCAN 5, $00,COMPARE $00,$0b,PASS; + IF PASS THEN ILOOP_1 = 0; + NEXT ILOOP_1; +ENDPROC; + +PROCEDURE PROGRAM_UROW USES GV,BITSTREAM,DO_EXIT,POLL_PROGRAM; + FOR FROMROWNUMBER = NUMBEROFFROMROWS TO 1 STEP -1; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $9f; + DRSCAN 3, BOOL((FROMROWNUMBER-1)); + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $9b; + DRSCAN 128, $ffffffffffffffffffffffffffffffff; + WAIT IDLE, 5 CYCLES; + WAIT IDLE, 10000 USEC; + NEXT FROMROWNUMBER; + IF ( ! (ISERASEONLY==0) ) THEN GOTO SKIP_CYC_INCREMENT; + IF ( ! (ACT_UROW_CYCLE_COUNT==1023) ) THEN GOTO Label_72; + ACT_UROW_CYCLE_COUNT = (ACT_UROW_CYCLE_COUNT+1); + Label_72: + LABEL_SEPARATOR = 0; + SKIP_CYC_INCREMENT: + IF ( ! (ISERASEONLY==1) ) THEN GOTO Label_73; + UROW[] = $ffffffffffffffffffffffffffffffff; + Label_73: + IF ( ! ( (PERMLOCK==1)&&(ULAWE==1)) ) THEN GOTO Label_74; + ISRESTOREDESIGN = 1; + Label_74: + IF ( ! ( (ISERASEONLY==0)||(ISRESTOREDESIGN==1)) ) THEN GOTO SKIP_DESIGN_INFO; + BUFF32[31..0] = BOOL(CHECKSUM); + IF ( ! ( !ISRESTOREDESIGN) ) THEN GOTO Label_75; + UROW[127..112] = BUFF32[15..0]; + Label_75: + IF ( ! ISRESTOREDESIGN ) THEN GOTO Label_76; + UROW[127..112] = SUROWCHECKSUM[15..0]; + Label_76: + IF ( ! ( !ISRESTOREDESIGN) ) THEN GOTO Label_77; + UROW[101..32] = ACT_UROW_DESIGN_NAME[69..0]; + Label_77: + IF ( ! ISRESTOREDESIGN ) THEN GOTO Label_78; + UROW[101..32] = SUROWDESIGNNAME[69..0]; + Label_78: + LABEL_SEPARATOR = 0; + SKIP_DESIGN_INFO: + BUFF32[31..0] = BOOL(ACT_UROW_CYCLE_COUNT); + UROW[111..102] = BUFF32[9..0]; + UROW[31..29] = ACT_UROW_PROG_METHOD[2..0]; + UROW[28..25] = ACT_UROW_ALGO_VERSION[3..0]; + UROW[16..10] = ACT_UROW_SW_VERSION[6..0]; + UROW[9..6] = ACT_UROW_PROGRAM_SW[3..0]; + UROW[4] = SUROW_SRAM_DISTURB[0]; + IF ( ! (ACT_UROW_ALGO_VERSION[6]==1) ) THEN GOTO Label_79; + UROW[5] = 1; + UROW[0] = 0; + UROW[24..23] = ACT_UROW_ALGO_VERSION[5..4]; + Label_79: + IF ( ! (ACT_UROW_ALGO_VERSION[6]==0) ) THEN GOTO Label_80; + UROW[5] = 0; + UROW[0] = 1; + UROW[24..23] = ACT_UROW_ALGO_VERSION[5..4]; + Label_80: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a7; + DRSCAN 128, UROW[]; + WAIT IDLE, 15 CYCLES; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO PROGRAM_OK3; + STATUS = -24; + PRINT "Failed to program UROW"; + CALL DO_EXIT; + PROGRAM_OK3: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a8; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + DRSCAN 128, $00000000000000000000000000000000,COMPARE UROW[],UROW_MASK[],PASS; + IF ( ! (PASS==0) ) THEN GOTO UROW_OK; + STATUS = -24; + PRINT "Failed to program UROW"; + CALL DO_EXIT; + UROW_OK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE FAIL_ERASE USES GV,DO_EXIT; + STATUS = 8; + PRINT "Failed Erase Operation"; + CALL DO_EXIT; +ENDPROC; + +PROCEDURE EXE_ERASE USES BITSTREAM,GV,READ_UROW,POLL_ERASE,PROGRAM_UROW,FAIL_ERASE; + IF ( ! (COMBERASESELECT[14]==1) ) THEN GOTO SKIPRUROW; + CALL READ_UROW; + EXPORT "ACTEL_SLOG_UROW", UROW[]; + SKIPRUROW: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $85; + DRSCAN 23, COMBERASESELECT[]; + WAIT IDLE, 3 CYCLES; + CALL POLL_ERASE; + IF ( ! (PASS==0) ) THEN GOTO ERASEOK; + CALL FAIL_ERASE; + ERASEOK: + IF ( ! (COMBERASESELECT[14]==1) ) THEN GOTO Label_81; + CALL PROGRAM_UROW; + Label_81: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_ERASE USES GV,EXE_ERASE; + PRINT "Erase ..."; + COMBERASESELECT[22..0] = $004000; + COMBERASESELECT[0] = 1; + CALL EXE_ERASE; + PRINT "Completed erase"; +ENDPROC; + +PROCEDURE DO_ERASE_ARRAY USES GV,EXE_ERASE; + PRINT "Erase FPGA Array ..."; + COMBERASESELECT[22..0] = $004001; + CALL EXE_ERASE; +ENDPROC; + +PROCEDURE DO_ERASE_ONLY USES GV,DO_ERASE; + ISERASEONLY = 1; + CALL DO_ERASE; +ENDPROC; + +PROCEDURE DO_ERASE_ARRAY_ONLY USES GV,DO_ERASE_ARRAY; + ISERASEONLY = 1; + CALL DO_ERASE_ARRAY; +ENDPROC; + +PROCEDURE DO_ERASE_ALL USES GV,EXE_ERASE; + IF ( ! ( (BM7DEVICE==1)||(BM1DEVICE==1)) ) THEN GOTO Label_82; + PRINT "Erase FPGA Array and FlashROM ..."; + Label_82: + IF ( ! ( (BM7DEVICE!=1)&&(BM1DEVICE!=1)) ) THEN GOTO Label_83; + PRINT "Erase FPGA Array, FlashROM and Security Settings ..."; + Label_83: + COMBERASESELECT[22..0] = $7fc00f; + ISERASEONLY = 1; + CALL EXE_ERASE; +ENDPROC; + +PROCEDURE LOAD_ROW_DATA USES BITSTREAM,GV; + FOR SDTILE = 1 TO NUMBEROFSDTILES; + FOR I = 1 TO 8; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $89; + DRSCAN 26, DATASTREAM[(DATAINDEX+25)..DATAINDEX]; + WAIT IDLE, 3 CYCLES; + DATAINDEX = (DATAINDEX+26); + NEXT I; + NEXT SDTILE; +ENDPROC; + +PROCEDURE EXE_PROGRAM USES GV,DO_EXIT,POLL_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $83; + WAIT IDLE, 3 CYCLES; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_84; + STATUS = 10; + PRINT "Failed to program FPGA array at row ",ROWNUMBER,"."; + CALL DO_EXIT; + Label_84: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE EXE_VERIFY USES GV,DO_EXIT,POLL_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $8d; + DRSCAN 2, VERIFYEOL[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_85; + STATUS = 11; + PRINT "Verify 0 failed at row ",ROWNUMBER,"."; + CALL DO_EXIT; + Label_85: + IRSCAN 8, $8d; + DRSCAN 2, VERIFYEOL[],COMPARE $0,$3,PASS; + IF ( ! (PASS==0) ) THEN GOTO Label_86; + STATUS = 11; + PRINT "Verify 0 failed at row ",ROWNUMBER,"."; + CALL DO_EXIT; + Label_86: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $8e; + DRSCAN 2, VERIFYEOL[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_87; + STATUS = 11; + PRINT "Verify 1 failed at row ",ROWNUMBER,"."; + CALL DO_EXIT; + Label_87: + IRSCAN 8, $8e; + DRSCAN 2, VERIFYEOL[],COMPARE $0,$3,PASS; + IF ( ! (PASS==0) ) THEN GOTO Label_88; + STATUS = 11; + PRINT "Verify 1 failed at row ",ROWNUMBER,"."; + CALL DO_EXIT; + Label_88: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_PROGRAM USES GV,LOAD_ROW_DATA,EXE_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $2; + WAIT IDLE, 3 CYCLES; + PRINT "Programming FPGA Array"; + DATAINDEX = 0; + ROWNUMBER = (NUMBEROFMAPROWS-1); + INTEGER IREPEAT_0; + FOR IREPEAT_0 = NUMBEROFMAPROWS - 1 TO 0 STEP -1; + CALL LOAD_ROW_DATA; + CALL EXE_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $3; + WAIT IDLE, 3 CYCLES; + EXPORT "PERCENT_DONE", ((100*((NUMBEROFMAPROWS-ROWNUMBER)+1))/NUMBEROFMAPROWS); + ROWNUMBER = (ROWNUMBER-1); + NEXT IREPEAT_0; +ENDPROC; + +PROCEDURE DO_VERIFY USES GV,LOAD_ROW_DATA,EXE_VERIFY; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $2; + WAIT IDLE, 3 CYCLES; + PRINT "Verifying FPGA Array"; + DATAINDEX = 0; + ROWNUMBER = (NUMBEROFMAPROWS-1); + INTEGER IREPEAT_1; + FOR IREPEAT_1 = NUMBEROFMAPROWS - 1 TO 0 STEP -1; + CALL LOAD_ROW_DATA; + CALL EXE_VERIFY; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $3; + WAIT IDLE, 3 CYCLES; + EXPORT "PERCENT_DONE", ((100*((NUMBEROFMAPROWS-ROWNUMBER)+1))/NUMBEROFMAPROWS); + ROWNUMBER = (ROWNUMBER-1); + NEXT IREPEAT_1; + PRINT " Verifying FPGA Array -- pass"; +ENDPROC; + +PROCEDURE DO_VERIFY_BOL USES GV,DO_VERIFY; + VERIFYEOL[0] = 0; + CALL DO_VERIFY; +ENDPROC; + +PROCEDURE DO_VERIFY_EOL USES GV,DO_VERIFY; + VERIFYEOL[0] = 1; + CALL DO_VERIFY; +ENDPROC; + +PROCEDURE DO_PROGRAM_RLOCK USES GV,DO_EXIT,POLL_PROGRAM; + DATAINDEX = 0; + INTEGER IREPEAT_2; + FOR IREPEAT_2 = NUMBEROFSDTILES - 1 TO 0 STEP -1; + FOR I = 1 TO 8; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $89; + DRSCAN 26, RLOCK[(DATAINDEX+25)..DATAINDEX]; + WAIT IDLE, 3 CYCLES; + DATAINDEX = (DATAINDEX+26); + NEXT I; + NEXT IREPEAT_2; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $8c; + WAIT IDLE, 3 CYCLES; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_89; + STATUS = 10; + PRINT "Failed to program Rlock."; + CALL DO_EXIT; + Label_89: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_READ_IDCODE USES READ_IDCODE_ONLY; + WAIT RESET, 5 CYCLES; + CALL READ_IDCODE_ONLY; + EXIT 0; +ENDPROC; + + +CRC C470; Index: Actel/usbDeviceActelTop/smartgen/smartgen.aws =================================================================== --- Actel/usbDeviceActelTop/smartgen/smartgen.aws (nonexistent) +++ Actel/usbDeviceActelTop/smartgen/smartgen.aws (revision 40) @@ -0,0 +1 @@ +smartgenVerilogVerilog \ No newline at end of file Index: Actel/usbDeviceActelTop/constraint/usbDeviceActelTop.pdc =================================================================== --- Actel/usbDeviceActelTop/constraint/usbDeviceActelTop.pdc (nonexistent) +++ Actel/usbDeviceActelTop/constraint/usbDeviceActelTop.pdc (revision 40) @@ -0,0 +1,41 @@ +# Actel Physical design constraints file +# Version: 8.0 SP2 8.0.3.9 +# Design Name: usbDeviceActelTop +# Input Netlist Format: edif +# Family: IGLOO , Die: AGL600V2 , Package: 256 FBGA , Speed grade: STD +# Date generated: Thu Oct 25 13:06:12 2007 + +# +# IO banks setting +# + +set_iobank Bank3 -vcci 3.30 -fixed no +set_iobank Bank2 -vcci 3.30 -fixed no +set_iobank Bank1 -vcci 3.30 -fixed no +set_iobank Bank0 -vcci 3.30 -fixed no + +# +# I/O constraints +# + +set_io ledOut\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname B7 -fixed yes +set_io ledOut\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname C7 -fixed yes +set_io ledOut\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P5 -fixed yes +set_io ledOut\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname T2 -fixed yes +set_io ledOut\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P4 -fixed yes +set_io ledOut\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname R3 -fixed yes +set_io ledOut\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P2 -fixed yes +set_io ledOut\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P1 -fixed yes +set_io ledOut\[8\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname R1 -fixed yes +set_io ledOut\[9\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname R2 -fixed yes + +set_io clk -iostd LVTTL -REGISTER No -RES_PULL None -pinname G13 -fixed yes +set_io rst_n -iostd LVTTL -REGISTER No -RES_PULL None -pinname N6 -fixed yes + +set_io usbSlaveVP -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname A8 -fixed yes +set_io usbSlaveVM -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname D7 -fixed yes +set_io usbSlaveOE_n -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname E8 -fixed yes +set_io usbDPlusPullup -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname C8 -fixed yes + + + Index: Actel/usbDeviceActelTop/hdl/processRxByte.v =================================================================== --- Actel/usbDeviceActelTop/hdl/processRxByte.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/processRxByte.v (revision 40) @@ -0,0 +1,493 @@ + +// File : ../RTL/serialInterfaceEngine/processRxByte.v +// Generated : 11/10/06 05:37:22 +// From : ../RTL/serialInterfaceEngine/processRxByte.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// processRxByte +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + +module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC); +input [15:0] CRC16Result; +input CRC16UpdateRdy; +input [4:0] CRC5Result; +input CRC5UpdateRdy; +input [7:0] RxByteIn; +input [7:0] RxCtrlIn; +input clk; +input processRxDataInWEn; +input rst; +output CRC16En; +output CRC5En; +output CRC5_8Bit; +output [7:0] CRCData; +output [7:0] RxCtrlOut; +output RxDataOutWEn; +output [7:0] RxDataOut; +output processRxByteRdy; +output rstCRC; + +reg CRC16En, next_CRC16En; +wire [15:0] CRC16Result; +wire CRC16UpdateRdy; +reg CRC5En, next_CRC5En; +wire [4:0] CRC5Result; +wire CRC5UpdateRdy; +reg CRC5_8Bit, next_CRC5_8Bit; +reg [7:0] CRCData, next_CRCData; +wire [7:0] RxByteIn; +wire [7:0] RxCtrlIn; +reg [7:0] RxCtrlOut, next_RxCtrlOut; +reg RxDataOutWEn, next_RxDataOutWEn; +reg [7:0] RxDataOut, next_RxDataOut; +wire clk; +reg processRxByteRdy, next_processRxByteRdy; +wire processRxDataInWEn; +wire rst; +reg rstCRC, next_rstCRC; + +// diagram signals declarations +reg ACKRxed, next_ACKRxed; +reg CRCError, next_CRCError; +reg NAKRxed, next_NAKRxed; +reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState; +reg [9:0]RXDataByteCnt, next_RXDataByteCnt; +reg [7:0]RxByte, next_RxByte; +reg [7:0]RxCtrl, next_RxCtrl; +reg RxOverflow, next_RxOverflow; +reg [7:0]RxStatus; +reg RxTimeOut, next_RxTimeOut; +reg Signal1, next_Signal1; +reg bitStuffError, next_bitStuffError; +reg dataSequence, next_dataSequence; +reg stallRxed, next_stallRxed; + +// BINARY ENCODED state machine: prRxByte +// State codes definitions: +`define CHK_ST 4'b0000 +`define START_PRBY 4'b0001 +`define WAIT_BYTE 4'b0010 +`define IDLE_CHK_START 4'b0011 +`define CHK_SYNC_DO 4'b0100 +`define CHK_PID_DO_CHK 4'b0101 +`define CHK_PID_FIRST_BYTE_PROC 4'b0110 +`define HSHAKE_FIN 4'b0111 +`define HSHAKE_CHK 4'b1000 +`define TOKEN_CHK_STRM 4'b1001 +`define TOKEN_FIN 4'b1010 +`define DATA_FIN 4'b1011 +`define DATA_CHK_STRM 4'b1100 +`define TOKEN_WAIT_CRC 4'b1101 +`define DATA_WAIT_CRC 4'b1110 + +reg [3:0] CurrState_prRxByte; +reg [3:0] NextState_prRxByte; + +// Diagram actions (continuous assignments allowed only: assign ...) + +always @ +(next_CRCError or next_bitStuffError or + next_RxOverflow or next_NAKRxed or + next_stallRxed or next_ACKRxed or + next_dataSequence) +begin + RxStatus <= + {1'b0, next_dataSequence, + next_ACKRxed, + next_stallRxed, next_NAKRxed, + next_RxOverflow, + next_bitStuffError, next_CRCError }; +end + +//-------------------------------------------------------------------- +// Machine: prRxByte +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte) +begin : prRxByte_NextState + NextState_prRxByte <= CurrState_prRxByte; + // Set default values for outputs and signals + next_RxByte <= RxByte; + next_RxCtrl <= RxCtrl; + next_RXByteStMachCurrState <= RXByteStMachCurrState; + next_CRCError <= CRCError; + next_bitStuffError <= bitStuffError; + next_RxOverflow <= RxOverflow; + next_RxTimeOut <= RxTimeOut; + next_NAKRxed <= NAKRxed; + next_stallRxed <= stallRxed; + next_ACKRxed <= ACKRxed; + next_dataSequence <= dataSequence; + next_RxDataOut <= RxDataOut; + next_RxCtrlOut <= RxCtrlOut; + next_RxDataOutWEn <= RxDataOutWEn; + next_rstCRC <= rstCRC; + next_CRCData <= CRCData; + next_CRC5En <= CRC5En; + next_CRC5_8Bit <= CRC5_8Bit; + next_CRC16En <= CRC16En; + next_RXDataByteCnt <= RXDataByteCnt; + next_processRxByteRdy <= processRxByteRdy; + case (CurrState_prRxByte) + `CHK_ST: + if (RXByteStMachCurrState == `HS_BYTE_ST) + NextState_prRxByte <= `HSHAKE_CHK; + else if (RXByteStMachCurrState == `TOKEN_BYTE_ST) + NextState_prRxByte <= `TOKEN_WAIT_CRC; + else if (RXByteStMachCurrState == `DATA_BYTE_ST) + NextState_prRxByte <= `DATA_WAIT_CRC; + else if (RXByteStMachCurrState == `IDLE_BYTE_ST) + NextState_prRxByte <= `IDLE_CHK_START; + else if (RXByteStMachCurrState == `CHECK_SYNC_ST) + NextState_prRxByte <= `CHK_SYNC_DO; + else if (RXByteStMachCurrState == `CHECK_PID_ST) + NextState_prRxByte <= `CHK_PID_DO_CHK; + `START_PRBY: + begin + next_RxByte <= 8'h00; + next_RxCtrl <= 8'h00; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + next_CRCError <= 1'b0; + next_bitStuffError <= 1'b0; + next_RxOverflow <= 1'b0; + next_RxTimeOut <= 1'b0; + next_NAKRxed <= 1'b0; + next_stallRxed <= 1'b0; + next_ACKRxed <= 1'b0; + next_dataSequence <= 1'b0; + next_RxDataOut <= 8'h00; + next_RxCtrlOut <= 8'h00; + next_RxDataOutWEn <= 1'b0; + next_rstCRC <= 1'b0; + next_CRCData <= 8'h00; + next_CRC5En <= 1'b0; + next_CRC5_8Bit <= 1'b0; + next_CRC16En <= 1'b0; + next_RXDataByteCnt <= 10'h00; + next_processRxByteRdy <= 1'b1; + NextState_prRxByte <= `WAIT_BYTE; + end + `WAIT_BYTE: + if (processRxDataInWEn == 1'b1) + begin + NextState_prRxByte <= `CHK_ST; + next_RxByte <= RxByteIn; + next_RxCtrl <= RxCtrlIn; + next_processRxByteRdy <= 1'b0; + end + `HSHAKE_FIN: + begin + next_RxDataOutWEn <= 1'b0; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + NextState_prRxByte <= `WAIT_BYTE; + next_processRxByteRdy <= 1'b1; + end + `HSHAKE_CHK: + begin + NextState_prRxByte <= `HSHAKE_FIN; + if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error + next_RxOverflow <= 1'b1; + next_RxDataOut <= RxStatus; + next_RxCtrlOut <= `RX_PACKET_STOP; + next_RxDataOutWEn <= 1'b1; + end + `CHK_PID_DO_CHK: + if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf) + begin + NextState_prRxByte <= `WAIT_BYTE; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + next_processRxByteRdy <= 1'b1; + end + else + begin + NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC; + next_CRCError <= 1'b0; + next_bitStuffError <= 1'b0; + next_RxOverflow <= 1'b0; + next_NAKRxed <= 1'b0; + next_stallRxed <= 1'b0; + next_ACKRxed <= 1'b0; + next_dataSequence <= 1'b0; + next_RxTimeOut <= 1'b0; + next_RXDataByteCnt <= 10'h000; + next_RxDataOut <= RxByte; + next_RxCtrlOut <= `RX_PACKET_START; + next_RxDataOutWEn <= 1'b1; + next_rstCRC <= 1'b1; + end + `CHK_PID_FIRST_BYTE_PROC: + begin + next_rstCRC <= 1'b0; + next_RxDataOutWEn <= 1'b0; + case (RxByte[1:0] ) + `SPECIAL: //Special PID. + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + `TOKEN: //Token PID + begin + next_RXByteStMachCurrState <= `TOKEN_BYTE_ST; + next_RXDataByteCnt <= 0; + end + `HANDSHAKE: //Handshake PID + begin + case (RxByte[3:2] ) + 2'b00: + next_ACKRxed <= 1'b1; + 2'b10: + next_NAKRxed <= 1'b1; + 2'b11: + next_stallRxed <= 1'b1; + default: + begin + $display ("Invalid Handshake PID detected in ProcessRXByte\n"); + end + endcase + next_RXByteStMachCurrState <= `HS_BYTE_ST; + end + `DATA: //Data PID + begin + case (RxByte[3:2] ) + 2'b00: + next_dataSequence <= 1'b0; + 2'b10: + next_dataSequence <= 1'b1; + default: + $display ("Invalid DATA PID detected in ProcessRXByte\n"); + endcase + next_RXByteStMachCurrState <= `DATA_BYTE_ST; + next_RXDataByteCnt <= 0; + end + endcase + NextState_prRxByte <= `WAIT_BYTE; + next_processRxByteRdy <= 1'b1; + end + `DATA_FIN: + begin + next_CRC16En <= 1'b0; + next_RxDataOutWEn <= 1'b0; + NextState_prRxByte <= `WAIT_BYTE; + next_processRxByteRdy <= 1'b1; + end + `DATA_CHK_STRM: + begin + next_RXDataByteCnt <= RXDataByteCnt + 1'b1; + case (RxCtrl) + `DATA_STOP: + begin + if (CRC16Result != 16'hb001) + next_CRCError <= 1'b1; + next_RxDataOut <= RxStatus; + next_RxCtrlOut <= `RX_PACKET_STOP; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + `DATA_BIT_STUFF_ERROR: + begin + next_bitStuffError <= 1'b1; + next_RxDataOut <= RxStatus; + next_RxCtrlOut <= `RX_PACKET_STOP; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + `DATA_STREAM: + begin + next_RxDataOut <= RxByte; + next_RxCtrlOut <= `RX_PACKET_STREAM; + next_CRCData <= RxByte; + next_CRC16En <= 1'b1; + end + default: + begin + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + endcase + next_RxDataOutWEn <= 1'b1; + NextState_prRxByte <= `DATA_FIN; + end + `DATA_WAIT_CRC: + if (CRC16UpdateRdy == 1'b1) + NextState_prRxByte <= `DATA_CHK_STRM; + `TOKEN_CHK_STRM: + begin + next_RXDataByteCnt <= RXDataByteCnt + 1'b1; + case (RxCtrl) + `DATA_STOP: + begin + if (CRC5Result != 5'h6) + next_CRCError <= 1'b1; + next_RxDataOut <= RxStatus; + next_RxCtrlOut <= `RX_PACKET_STOP; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + `DATA_BIT_STUFF_ERROR: + begin + next_bitStuffError <= 1'b1; + next_RxDataOut <= RxStatus; + next_RxCtrlOut <= `RX_PACKET_STOP; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + `DATA_STREAM: + begin + if (RXDataByteCnt > 10'h2) + begin + next_RxOverflow <= 1'b1; + next_RxDataOut <= RxStatus; + next_RxCtrlOut <= `RX_PACKET_STOP; + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + else + begin + next_RxDataOut <= RxByte; + next_RxCtrlOut <= `RX_PACKET_STREAM; + next_CRCData <= RxByte; + next_CRC5_8Bit <= 1'b1; + next_CRC5En <= 1'b1; + end + end + default: + begin + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + end + endcase + next_RxDataOutWEn <= 1'b1; + NextState_prRxByte <= `TOKEN_FIN; + end + `TOKEN_FIN: + begin + next_CRC5En <= 1'b0; + next_RxDataOutWEn <= 1'b0; + NextState_prRxByte <= `WAIT_BYTE; + next_processRxByteRdy <= 1'b1; + end + `TOKEN_WAIT_CRC: + if (CRC5UpdateRdy == 1'b1) + NextState_prRxByte <= `TOKEN_CHK_STRM; + `CHK_SYNC_DO: + begin + if (RxByte == `SYNC_BYTE) + next_RXByteStMachCurrState <= `CHECK_PID_ST; + else + next_RXByteStMachCurrState <= `IDLE_BYTE_ST; + NextState_prRxByte <= `WAIT_BYTE; + next_processRxByteRdy <= 1'b1; + end + `IDLE_CHK_START: + begin + if (RxCtrl == `DATA_START) + next_RXByteStMachCurrState <= `CHECK_SYNC_ST; + NextState_prRxByte <= `WAIT_BYTE; + next_processRxByteRdy <= 1'b1; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : prRxByte_CurrentState + if (rst) + CurrState_prRxByte <= `START_PRBY; + else + CurrState_prRxByte <= NextState_prRxByte; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : prRxByte_RegOutput + if (rst) + begin + RxByte <= 8'h00; + RxCtrl <= 8'h00; + RXByteStMachCurrState <= `IDLE_BYTE_ST; + CRCError <= 1'b0; + bitStuffError <= 1'b0; + RxOverflow <= 1'b0; + RxTimeOut <= 1'b0; + NAKRxed <= 1'b0; + stallRxed <= 1'b0; + ACKRxed <= 1'b0; + dataSequence <= 1'b0; + RXDataByteCnt <= 10'h00; + RxDataOut <= 8'h00; + RxCtrlOut <= 8'h00; + RxDataOutWEn <= 1'b0; + rstCRC <= 1'b0; + CRCData <= 8'h00; + CRC5En <= 1'b0; + CRC5_8Bit <= 1'b0; + CRC16En <= 1'b0; + processRxByteRdy <= 1'b1; + end + else + begin + RxByte <= next_RxByte; + RxCtrl <= next_RxCtrl; + RXByteStMachCurrState <= next_RXByteStMachCurrState; + CRCError <= next_CRCError; + bitStuffError <= next_bitStuffError; + RxOverflow <= next_RxOverflow; + RxTimeOut <= next_RxTimeOut; + NAKRxed <= next_NAKRxed; + stallRxed <= next_stallRxed; + ACKRxed <= next_ACKRxed; + dataSequence <= next_dataSequence; + RXDataByteCnt <= next_RXDataByteCnt; + RxDataOut <= next_RxDataOut; + RxCtrlOut <= next_RxCtrlOut; + RxDataOutWEn <= next_RxDataOutWEn; + rstCRC <= next_rstCRC; + CRCData <= next_CRCData; + CRC5En <= next_CRC5En; + CRC5_8Bit <= next_CRC5_8Bit; + CRC16En <= next_CRC16En; + processRxByteRdy <= next_processRxByteRdy; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v =================================================================== --- Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v (revision 40) @@ -0,0 +1,124 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// hostSlaveMuxBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostSlave_h.v" + +module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk, + hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut); + +input [7:0] dataIn; +input address; +input writeEn; +input strobe_i; +input busClk; +input usbClk; +output [7:0] dataOut; +input hostSlaveMuxSel; +output hostMode; +input rstFromWire; +output rstSyncToBusClkOut; +output rstSyncToUsbClkOut; + +wire [7:0] dataIn; +wire address; +wire writeEn; +wire strobe_i; +wire busClk; +wire usbClk; +reg [7:0] dataOut; +wire hostSlaveMuxSel; +reg hostMode; +wire rstFromWire; +reg rstSyncToBusClkOut; +reg rstSyncToUsbClkOut; + +//internal wire and regs +reg [5:0] rstShift; +reg rstFromBus; +reg rstSyncToUsbClkFirst; + +//sync write demux +always @(posedge busClk) +begin + if (rstSyncToBusClkOut == 1'b1) + hostMode <= 1'b0; + else begin + if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG ) + hostMode <= dataIn[0]; + end + if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 ) + rstFromBus <= 1'b1; + else + rstFromBus <= 1'b0; +end + +// async read mux +always @(address or hostMode) +begin + case (address) + `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode}; + `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM; + endcase +end + +// reset control +//generate 'rstSyncToBusClk' +//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz +always @(posedge busClk) begin + if (rstFromWire == 1'b1 || rstFromBus == 1'b1) + rstShift <= 6'b111111; + else + rstShift <= {1'b0, rstShift[5:1]}; +end + +always @(rstShift) + rstSyncToBusClkOut <= rstShift[0]; + +// double sync across clock domains to generate 'forceEmptySyncToWrClk' +always @(posedge usbClk) begin + rstSyncToUsbClkFirst <= rstSyncToBusClkOut; + rstSyncToUsbClkOut <= rstSyncToUsbClkFirst; +end + +endmodule Index: Actel/usbDeviceActelTop/hdl/slavecontroller.v =================================================================== --- Actel/usbDeviceActelTop/hdl/slavecontroller.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/slavecontroller.v (revision 40) @@ -0,0 +1,475 @@ + +// File : ../RTL/slaveController/slavecontroller.v +// Generated : 11/10/06 05:37:25 +// From : ../RTL/slaveController/slavecontroller.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// slaveController +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbSlaveControl_h.v" +`include "usbConstants_h.v" + + +module slavecontroller (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone); +input CRCError; +input [7:0] RxByte; +input RxDataWEn; +input RxOverflow; +input [7:0] RxStatus; +input RxTimeOut; +input SCGlobalEn; +input [4:0] USBEndPControlReg; +input [6:0] USBTgtAddress; +input bitStuffError; +input clk; +input getPacketRdy; +input rst; +input sendPacketRdy; +output NAKSent; +output SOFRxed; +output [1:0] USBEndPNakTransTypeReg; +output [1:0] USBEndPTransTypeReg; +output [3:0] USBEndP; +output clrEPRdy; +output endPMuxErrorsWEn; +output endPointReadyToGetPkt; +output [10:0] frameNum; +output getPacketREn; +output [3:0] sendPacketPID; +output sendPacketWEn; +output stallSent; +output transDone; + +wire CRCError; +reg NAKSent, next_NAKSent; +wire [7:0] RxByte; +wire RxDataWEn; +wire RxOverflow; +wire [7:0] RxStatus; +wire RxTimeOut; +wire SCGlobalEn; +reg SOFRxed, next_SOFRxed; +wire [4:0] USBEndPControlReg; +reg [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg; +reg [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg; +reg [3:0] USBEndP, next_USBEndP; +wire [6:0] USBTgtAddress; +wire bitStuffError; +wire clk; +reg clrEPRdy, next_clrEPRdy; +reg endPMuxErrorsWEn, next_endPMuxErrorsWEn; +reg endPointReadyToGetPkt, next_endPointReadyToGetPkt; +reg [10:0] frameNum, next_frameNum; +reg getPacketREn, next_getPacketREn; +wire getPacketRdy; +wire rst; +reg [3:0] sendPacketPID, next_sendPacketPID; +wire sendPacketRdy; +reg sendPacketWEn, next_sendPacketWEn; +reg stallSent, next_stallSent; +reg transDone, next_transDone; + +// diagram signals declarations +reg [7:0]PIDByte, next_PIDByte; +reg [6:0]USBAddress, next_USBAddress; +reg [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy; +reg [7:0]addrEndPTemp, next_addrEndPTemp; +reg [7:0]endpCRCTemp, next_endpCRCTemp; +reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg; + +// BINARY ENCODED state machine: slvCntrl +// State codes definitions: +`define WAIT_RX1 5'b00000 +`define FIN_SC 5'b00001 +`define GET_TOKEN_WAIT_CRC 5'b00010 +`define GET_TOKEN_WAIT_ADDR 5'b00011 +`define GET_TOKEN_WAIT_STOP 5'b00100 +`define CHK_PID 5'b00101 +`define GET_TOKEN_CHK_SOF 5'b00110 +`define PID_ERROR 5'b00111 +`define CHK_RDY 5'b01000 +`define IN_NAK_STALL 5'b01001 +`define IN_CHK_RDY 5'b01010 +`define SETUP_OUT_CHK 5'b01011 +`define SETUP_OUT_SEND 5'b01100 +`define SETUP_OUT_GET_PKT 5'b01101 +`define START_S1 5'b01110 +`define GET_TOKEN_DELAY 5'b01111 +`define GET_TOKEN_CHK_ADDR 5'b10000 +`define IN_RESP_GET_RESP 5'b10001 +`define IN_RESP_DATA 5'b10010 +`define IN_RESP_CHK_ISO 5'b10011 + +reg [4:0] CurrState_slvCntrl; +reg [4:0] NextState_slvCntrl; + + +//-------------------------------------------------------------------- +// Machine: slvCntrl +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or USBEndPControlReg or RxDataWEn or RxStatus or PIDByte or USBEndPControlRegCopy or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or sendPacketWEn or sendPacketPID or USBEndPTransTypeReg or USBEndPNakTransTypeReg or frameNum or endPointReadyToGetPkt or CurrState_slvCntrl) +begin : slvCntrl_NextState + NextState_slvCntrl <= CurrState_slvCntrl; + // Set default values for outputs and signals + next_stallSent <= stallSent; + next_NAKSent <= NAKSent; + next_SOFRxed <= SOFRxed; + next_PIDByte <= PIDByte; + next_transDone <= transDone; + next_clrEPRdy <= clrEPRdy; + next_endPMuxErrorsWEn <= endPMuxErrorsWEn; + next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg; + next_getPacketREn <= getPacketREn; + next_sendPacketWEn <= sendPacketWEn; + next_sendPacketPID <= sendPacketPID; + next_USBEndPTransTypeReg <= USBEndPTransTypeReg; + next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg; + next_endpCRCTemp <= endpCRCTemp; + next_addrEndPTemp <= addrEndPTemp; + next_frameNum <= frameNum; + next_USBAddress <= USBAddress; + next_USBEndP <= USBEndP; + next_USBEndPControlRegCopy <= USBEndPControlRegCopy; + next_endPointReadyToGetPkt <= endPointReadyToGetPkt; + case (CurrState_slvCntrl) + `WAIT_RX1: + begin + next_stallSent <= 1'b0; + next_NAKSent <= 1'b0; + next_SOFRxed <= 1'b0; + if (RxDataWEn == 1'b1 && + RxStatus == `RX_PACKET_START && + RxByte[1:0] == `TOKEN) + begin + NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR; + next_PIDByte <= RxByte; + end + end + `FIN_SC: + begin + next_transDone <= 1'b0; + next_clrEPRdy <= 1'b0; + next_endPMuxErrorsWEn <= 1'b0; + NextState_slvCntrl <= `WAIT_RX1; + end + `CHK_PID: + if (PIDByte[3:0] == `SETUP) + begin + NextState_slvCntrl <= `SETUP_OUT_GET_PKT; + next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS; + next_getPacketREn <= 1'b1; + end + else if (PIDByte[3:0] == `OUT) + begin + NextState_slvCntrl <= `SETUP_OUT_GET_PKT; + next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS; + next_getPacketREn <= 1'b1; + end + else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0)) + begin + NextState_slvCntrl <= `IN_CHK_RDY; + next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS; + end + else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)) + begin + NextState_slvCntrl <= `IN_RESP_DATA; + next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA0; + end + else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) + begin + NextState_slvCntrl <= `IN_RESP_DATA; + next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA1; + end + else if (PIDByte[3:0] == `IN) + begin + NextState_slvCntrl <= `CHK_RDY; + next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS; + end + else + NextState_slvCntrl <= `PID_ERROR; + `PID_ERROR: + NextState_slvCntrl <= `WAIT_RX1; + `CHK_RDY: + if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1) + begin + NextState_slvCntrl <= `FIN_SC; + next_transDone <= 1'b1; + next_clrEPRdy <= 1'b1; + next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg; + next_endPMuxErrorsWEn <= 1'b1; + end + else if (NAKSent == 1'b1) + begin + NextState_slvCntrl <= `FIN_SC; + next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg; + next_endPMuxErrorsWEn <= 1'b1; + end + else + NextState_slvCntrl <= `FIN_SC; + `SETUP_OUT_CHK: + if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0) + begin + NextState_slvCntrl <= `SETUP_OUT_SEND; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `NAK; + next_NAKSent <= 1'b1; + end + else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1) + begin + NextState_slvCntrl <= `SETUP_OUT_SEND; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `STALL; + next_stallSent <= 1'b1; + end + else + begin + NextState_slvCntrl <= `SETUP_OUT_SEND; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `ACK; + end + `SETUP_OUT_SEND: + begin + next_sendPacketWEn <= 1'b0; + if (sendPacketRdy == 1'b1) + NextState_slvCntrl <= `CHK_RDY; + end + `SETUP_OUT_GET_PKT: + begin + next_getPacketREn <= 1'b0; + if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)) + NextState_slvCntrl <= `CHK_RDY; + else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 && + bitStuffError == 1'b0 && + RxOverflow == 1'b0 && + RxTimeOut == 1'b0)) + NextState_slvCntrl <= `SETUP_OUT_CHK; + else if (getPacketRdy == 1'b1) + NextState_slvCntrl <= `CHK_RDY; + end + `IN_NAK_STALL: + begin + next_sendPacketWEn <= 1'b0; + if (sendPacketRdy == 1'b1) + NextState_slvCntrl <= `CHK_RDY; + end + `IN_CHK_RDY: + if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0) + begin + NextState_slvCntrl <= `IN_NAK_STALL; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `NAK; + next_NAKSent <= 1'b1; + end + else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1) + begin + NextState_slvCntrl <= `IN_NAK_STALL; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `STALL; + next_stallSent <= 1'b1; + end + else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0) + begin + NextState_slvCntrl <= `IN_RESP_DATA; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA0; + end + else + begin + NextState_slvCntrl <= `IN_RESP_DATA; + next_sendPacketWEn <= 1'b1; + next_sendPacketPID <= `DATA1; + end + `IN_RESP_GET_RESP: + begin + next_getPacketREn <= 1'b0; + if (getPacketRdy == 1'b1) + NextState_slvCntrl <= `CHK_RDY; + end + `IN_RESP_DATA: + begin + next_sendPacketWEn <= 1'b0; + if (sendPacketRdy == 1'b1) + NextState_slvCntrl <= `IN_RESP_CHK_ISO; + end + `IN_RESP_CHK_ISO: + if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1) + NextState_slvCntrl <= `CHK_RDY; + else + begin + NextState_slvCntrl <= `IN_RESP_GET_RESP; + next_getPacketREn <= 1'b1; + end + `START_S1: + NextState_slvCntrl <= `WAIT_RX1; + `GET_TOKEN_WAIT_CRC: + if (RxDataWEn == 1'b1 && + RxStatus == `RX_PACKET_STREAM) + begin + NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP; + next_endpCRCTemp <= RxByte; + end + else if (RxDataWEn == 1'b1 && + RxStatus != `RX_PACKET_STREAM) + NextState_slvCntrl <= `WAIT_RX1; + `GET_TOKEN_WAIT_ADDR: + if (RxDataWEn == 1'b1 && + RxStatus == `RX_PACKET_STREAM) + begin + NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC; + next_addrEndPTemp <= RxByte; + end + else if (RxDataWEn == 1'b1 && + RxStatus != `RX_PACKET_STREAM) + NextState_slvCntrl <= `WAIT_RX1; + `GET_TOKEN_WAIT_STOP: + if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 && + RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 && + RxByte [`RX_OVERFLOW_BIT] == 1'b0)) + NextState_slvCntrl <= `GET_TOKEN_CHK_SOF; + else if (RxDataWEn == 1'b1) + NextState_slvCntrl <= `WAIT_RX1; + `GET_TOKEN_CHK_SOF: + if (PIDByte[3:0] == `SOF) + begin + NextState_slvCntrl <= `WAIT_RX1; + next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp}; + next_SOFRxed <= 1'b1; + end + else + begin + NextState_slvCntrl <= `GET_TOKEN_DELAY; + next_USBAddress <= addrEndPTemp[6:0]; + next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]}; + end + `GET_TOKEN_DELAY: // Insert delay to allow USBEndP etc to update + NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR; + `GET_TOKEN_CHK_ADDR: + if (USBEndP < `NUM_OF_ENDPOINTS && + USBAddress == USBTgtAddress && + SCGlobalEn == 1'b1 && + USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1) + begin + NextState_slvCntrl <= `CHK_PID; + next_USBEndPControlRegCopy <= USBEndPControlReg; + next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT]; + end + else + NextState_slvCntrl <= `WAIT_RX1; + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : slvCntrl_CurrentState + if (rst) + CurrState_slvCntrl <= `START_S1; + else + CurrState_slvCntrl <= NextState_slvCntrl; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : slvCntrl_RegOutput + if (rst) + begin + tempUSBEndPTransTypeReg <= 2'b00; + addrEndPTemp <= 8'h00; + endpCRCTemp <= 8'h00; + USBAddress <= 7'b0000000; + PIDByte <= 8'h00; + USBEndPControlRegCopy <= 5'b00000; + transDone <= 1'b0; + getPacketREn <= 1'b0; + sendPacketPID <= 4'b0; + sendPacketWEn <= 1'b0; + clrEPRdy <= 1'b0; + USBEndPTransTypeReg <= 2'b00; + USBEndPNakTransTypeReg <= 2'b00; + NAKSent <= 1'b0; + stallSent <= 1'b0; + SOFRxed <= 1'b0; + endPMuxErrorsWEn <= 1'b0; + frameNum <= 11'b00000000000; + USBEndP <= 4'h0; + endPointReadyToGetPkt <= 1'b0; + end + else + begin + tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg; + addrEndPTemp <= next_addrEndPTemp; + endpCRCTemp <= next_endpCRCTemp; + USBAddress <= next_USBAddress; + PIDByte <= next_PIDByte; + USBEndPControlRegCopy <= next_USBEndPControlRegCopy; + transDone <= next_transDone; + getPacketREn <= next_getPacketREn; + sendPacketPID <= next_sendPacketPID; + sendPacketWEn <= next_sendPacketWEn; + clrEPRdy <= next_clrEPRdy; + USBEndPTransTypeReg <= next_USBEndPTransTypeReg; + USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg; + NAKSent <= next_NAKSent; + stallSent <= next_stallSent; + SOFRxed <= next_SOFRxed; + endPMuxErrorsWEn <= next_endPMuxErrorsWEn; + frameNum <= next_frameNum; + USBEndP <= next_USBEndP; + endPointReadyToGetPkt <= next_endPointReadyToGetPkt; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/processTxByte.v =================================================================== --- Actel/usbDeviceActelTop/hdl/processTxByte.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/processTxByte.v (revision 40) @@ -0,0 +1,448 @@ + +// File : ../RTL/serialInterfaceEngine/processTxByte.v +// Generated : 11/10/06 05:37:23 +// From : ../RTL/serialInterfaceEngine/processTxByte.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// processTxByte +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + +module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst); +input [1:0] JBit; +input [1:0] KBit; +input [7:0] TxByteCtrlIn; +input TxByteFullSpeedRateIn; +input [7:0] TxByteIn; +input USBWireGnt; +input USBWireRdy; +input clk; +input processTxByteWEn; +input rst; +output USBWireCtrl; +output [1:0] USBWireData; +output USBWireFullSpeedRate; +output USBWireReq; +output USBWireWEn; +output processTxByteRdy; + +wire [1:0] JBit; +wire [1:0] KBit; +wire [7:0] TxByteCtrlIn; +wire TxByteFullSpeedRateIn; +wire [7:0] TxByteIn; +reg USBWireCtrl, next_USBWireCtrl; +reg [1:0] USBWireData, next_USBWireData; +reg USBWireFullSpeedRate, next_USBWireFullSpeedRate; +wire USBWireGnt; +wire USBWireRdy; +reg USBWireReq, next_USBWireReq; +reg USBWireWEn, next_USBWireWEn; +wire clk; +reg processTxByteRdy, next_processTxByteRdy; +wire processTxByteWEn; +wire rst; + +// diagram signals declarations +reg [1:0]TXLineState, next_TXLineState; +reg [3:0]TXOneCount, next_TXOneCount; +reg [7:0]TxByteCtrl, next_TxByteCtrl; +reg TxByteFullSpeedRate, next_TxByteFullSpeedRate; +reg [7:0]TxByte, next_TxByte; +reg [3:0]i, next_i; + +// BINARY ENCODED state machine: prcTxB +// State codes definitions: +`define START_PTBY 5'b00000 +`define PTBY_WAIT_EN 5'b00001 +`define SEND_BYTE_UPDATE_BYTE 5'b00010 +`define SEND_BYTE_WAIT_RDY 5'b00011 +`define SEND_BYTE_CHK 5'b00100 +`define SEND_BYTE_BIT_STUFF 5'b00101 +`define SEND_BYTE_WAIT_RDY2 5'b00110 +`define SEND_BYTE_CHK_FIN 5'b00111 +`define PTBY_WAIT_GNT 5'b01000 +`define STOP_SND_SE0_2 5'b01001 +`define STOP_SND_SE0_1 5'b01010 +`define STOP_CHK 5'b01011 +`define STOP_SND_J 5'b01100 +`define STOP_SND_IDLE 5'b01101 +`define STOP_FIN 5'b01110 +`define WAIT_RDY_WIRE 5'b01111 +`define WAIT_RDY_PKT 5'b10000 +`define LS_START_SND_IDLE3 5'b10001 +`define LS_START_SND_J1 5'b10010 +`define LS_START_SND_IDLE1 5'b10011 +`define LS_START_SND_IDLE2 5'b10100 +`define LS_START_FIN 5'b10101 +`define LS_START_W_RDY1 5'b10110 +`define LS_START_W_RDY2 5'b10111 +`define LS_START_W_RDY3 5'b11000 +`define STOP_W_RDY1 5'b11001 +`define STOP_W_RDY2 5'b11010 +`define STOP_W_RDY3 5'b11011 +`define STOP_W_RDY4 5'b11100 + +reg [4:0] CurrState_prcTxB; +reg [4:0] NextState_prcTxB; + + +//-------------------------------------------------------------------- +// Machine: prcTxB +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB) +begin : prcTxB_NextState + NextState_prcTxB <= CurrState_prcTxB; + // Set default values for outputs and signals + next_processTxByteRdy <= processTxByteRdy; + next_USBWireData <= USBWireData; + next_USBWireCtrl <= USBWireCtrl; + next_USBWireReq <= USBWireReq; + next_USBWireWEn <= USBWireWEn; + next_i <= i; + next_TxByte <= TxByte; + next_TxByteCtrl <= TxByteCtrl; + next_TXLineState <= TXLineState; + next_TXOneCount <= TXOneCount; + next_USBWireFullSpeedRate <= USBWireFullSpeedRate; + next_TxByteFullSpeedRate <= TxByteFullSpeedRate; + case (CurrState_prcTxB) + `START_PTBY: + begin + next_processTxByteRdy <= 1'b0; + next_USBWireData <= 2'b00; + next_USBWireCtrl <= `TRI_STATE; + next_USBWireReq <= 1'b0; + next_USBWireWEn <= 1'b0; + next_i <= 4'h0; + next_TxByte <= 8'h00; + next_TxByteCtrl <= 8'h00; + next_TXLineState <= 2'b0; + next_TXOneCount <= 4'h0; + next_USBWireFullSpeedRate <= 1'b0; + next_TxByteFullSpeedRate <= 1'b0; + NextState_prcTxB <= `PTBY_WAIT_EN; + end + `PTBY_WAIT_EN: + begin + next_processTxByteRdy <= 1'b1; + if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START)) + begin + NextState_prcTxB <= `PTBY_WAIT_GNT; + next_processTxByteRdy <= 1'b0; + next_TxByte <= TxByteIn; + next_TxByteCtrl <= TxByteCtrlIn; + next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn; + next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn; + next_TXOneCount <= 4'h0; + next_TXLineState <= JBit; + next_USBWireReq <= 1'b1; + end + else if (processTxByteWEn == 1'b1) + begin + NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE; + next_processTxByteRdy <= 1'b0; + next_TxByte <= TxByteIn; + next_TxByteCtrl <= TxByteCtrlIn; + next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn; + next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn; + next_i <= 4'h0; + end + end + `PTBY_WAIT_GNT: + if (USBWireGnt == 1'b1) + NextState_prcTxB <= `WAIT_RDY_WIRE; + `WAIT_RDY_WIRE: + if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0)) + NextState_prcTxB <= `LS_START_SND_IDLE1; + else if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `WAIT_RDY_PKT; + //actively drive the first J bit + next_USBWireData <= JBit; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `WAIT_RDY_PKT: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE; + next_i <= 4'h0; + end + `SEND_BYTE_UPDATE_BYTE: + begin + next_i <= i + 1'b1; + next_TxByte <= {1'b0, TxByte[7:1] }; + if (TxByte[0] == 1'b1) //If this bit is 1, then + next_TXOneCount <= TXOneCount + 1'b1; + //increment 'TXOneCount' + else //else this is a zero bit + begin + next_TXOneCount <= 4'h0; + //reset 'TXOneCount' + if (TXLineState == JBit) + next_TXLineState <= KBit; + //toggle the line state + else + next_TXLineState <= JBit; + end + NextState_prcTxB <= `SEND_BYTE_WAIT_RDY; + end + `SEND_BYTE_WAIT_RDY: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `SEND_BYTE_CHK; + next_USBWireWEn <= 1'b1; + next_USBWireData <= TXLineState; + next_USBWireCtrl <= `DRIVE; + end + `SEND_BYTE_CHK: + begin + next_USBWireWEn <= 1'b0; + if (TXOneCount == `MAX_CONSEC_SAME_BITS) + NextState_prcTxB <= `SEND_BYTE_BIT_STUFF; + else if (i != 4'h8) + NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE; + else + NextState_prcTxB <= `STOP_CHK; + end + `SEND_BYTE_BIT_STUFF: + begin + next_TXOneCount <= 4'h0; + //reset 'TXOneCount' + if (TXLineState == JBit) + next_TXLineState <= KBit; + //toggle the line state + else + next_TXLineState <= JBit; + NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2; + end + `SEND_BYTE_WAIT_RDY2: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `SEND_BYTE_CHK_FIN; + next_USBWireWEn <= 1'b1; + next_USBWireData <= TXLineState; + next_USBWireCtrl <= `DRIVE; + end + `SEND_BYTE_CHK_FIN: + begin + next_USBWireWEn <= 1'b0; + if (i == 4'h8) + NextState_prcTxB <= `STOP_CHK; + else + NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE; + end + `STOP_SND_SE0_2: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `STOP_W_RDY2; + end + `STOP_SND_SE0_1: + NextState_prcTxB <= `STOP_W_RDY1; + `STOP_CHK: + if (TxByteCtrl == `DATA_STOP) + NextState_prcTxB <= `STOP_SND_SE0_1; + else + NextState_prcTxB <= `PTBY_WAIT_EN; + `STOP_SND_J: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `STOP_W_RDY3; + end + `STOP_SND_IDLE: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `STOP_W_RDY4; + end + `STOP_FIN: + begin + next_USBWireWEn <= 1'b0; + next_USBWireReq <= 1'b0; + //release the wire + NextState_prcTxB <= `PTBY_WAIT_EN; + end + `STOP_W_RDY1: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `STOP_SND_SE0_2; + next_USBWireWEn <= 1'b1; + next_USBWireData <= `SE0; + next_USBWireCtrl <= `DRIVE; + end + `STOP_W_RDY2: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `STOP_SND_J; + next_USBWireWEn <= 1'b1; + next_USBWireData <= `SE0; + next_USBWireCtrl <= `DRIVE; + end + `STOP_W_RDY3: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `STOP_SND_IDLE; + next_USBWireWEn <= 1'b1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `DRIVE; + end + `STOP_W_RDY4: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `STOP_FIN; + next_USBWireWEn <= 1'b1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `TRI_STATE; + end + `LS_START_SND_IDLE3: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `LS_START_W_RDY2; + end + `LS_START_SND_J1: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `LS_START_W_RDY3; + end + `LS_START_SND_IDLE1: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `LS_START_SND_IDLE2; + next_USBWireWEn <= 1'b1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `TRI_STATE; + end + `LS_START_SND_IDLE2: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `LS_START_W_RDY1; + end + `LS_START_FIN: + begin + next_USBWireWEn <= 1'b0; + NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE; + next_i <= 4'h0; + end + `LS_START_W_RDY1: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `LS_START_SND_IDLE3; + next_USBWireWEn <= 1'b1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `TRI_STATE; + end + `LS_START_W_RDY2: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `LS_START_SND_J1; + next_USBWireWEn <= 1'b1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `TRI_STATE; + end + `LS_START_W_RDY3: + if (USBWireRdy == 1'b1) + begin + NextState_prcTxB <= `LS_START_FIN; + //Drive the first JBit + next_USBWireWEn <= 1'b1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `DRIVE; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : prcTxB_CurrentState + if (rst) + CurrState_prcTxB <= `START_PTBY; + else + CurrState_prcTxB <= NextState_prcTxB; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : prcTxB_RegOutput + if (rst) + begin + i <= 4'h0; + TxByte <= 8'h00; + TxByteCtrl <= 8'h00; + TXLineState <= 2'b0; + TXOneCount <= 4'h0; + TxByteFullSpeedRate <= 1'b0; + processTxByteRdy <= 1'b0; + USBWireData <= 2'b00; + USBWireCtrl <= `TRI_STATE; + USBWireReq <= 1'b0; + USBWireWEn <= 1'b0; + USBWireFullSpeedRate <= 1'b0; + end + else + begin + i <= next_i; + TxByte <= next_TxByte; + TxByteCtrl <= next_TxByteCtrl; + TXLineState <= next_TXLineState; + TXOneCount <= next_TXOneCount; + TxByteFullSpeedRate <= next_TxByteFullSpeedRate; + processTxByteRdy <= next_processTxByteRdy; + USBWireData <= next_USBWireData; + USBWireCtrl <= next_USBWireCtrl; + USBWireReq <= next_USBWireReq; + USBWireWEn <= next_USBWireWEn; + USBWireFullSpeedRate <= next_USBWireFullSpeedRate; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/Copy of EP1Mouse.v =================================================================== --- Actel/usbDeviceActelTop/hdl/Copy of EP1Mouse.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/Copy of EP1Mouse.v (revision 40) @@ -0,0 +1,290 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// EP1Mouse.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostSlaveReg_define.v" + +module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq); +input clk; +input initComplete; +input rst; +input wb_ack; +input [7:0]wb_data_i; +input wbBusGnt; +output [7:0]wb_addr; +output [7:0]wb_data_o; +output wb_stb; +output wb_we; +output wbBusReq; + +wire clk; +wire initComplete; +wire rst; +wire wb_ack; +reg [7:0]wb_addr, next_wb_addr; +wire [7:0]wb_data_i; +reg [7:0]wb_data_o, next_wb_data_o; +reg wb_stb, next_wb_stb; +reg wb_we, next_wb_we; +wire wbBusGnt; +reg wbBusReq, next_wbBusReq; + +// diagram signals declarations +reg [7:0]cnt, next_cnt; +reg dataSeq, next_dataSeq; +reg localRst, next_localRst; +reg transDone, next_transDone; + +// BINARY ENCODED state machine: EP1St +// State codes definitions: +`define DO_TRANS_WT_GNT 4'b0000 +`define DO_TRANS_TX_EMPTY 4'b0001 +`define DO_TRANS_WR_TX_FIFO1 4'b0010 +`define DO_TRANS_TRANS_GO 4'b0011 +`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100 +`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101 +`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110 +`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111 +`define START 4'b1000 +`define DO_TRANS_WR_TX_FIFO2 4'b1001 +`define DO_TRANS_WR_TX_FIFO3 4'b1010 +`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011 + +reg [3:0]CurrState_EP1St, NextState_EP1St; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: EP1St + +// NextState logic (combinatorial) +always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St) +begin + NextState_EP1St <= CurrState_EP1St; + // Set default values for outputs and signals + next_wbBusReq <= wbBusReq; + next_wb_addr <= wb_addr; + next_wb_data_o <= wb_data_o; + next_wb_stb <= wb_stb; + next_wb_we <= wb_we; + next_transDone <= transDone; + next_cnt <= cnt; + next_dataSeq <= dataSeq; + case (CurrState_EP1St) // synopsys parallel_case full_case + `START: + begin + next_wbBusReq <= 1'b0; + next_wb_addr <= 8'h00; + next_wb_data_o <= 8'h00; + next_wb_stb <= 1'b0; + next_wb_we <= 1'b0; + next_cnt <= 8'h00; + next_dataSeq <= 1'b0; + next_transDone <= 1'b0; + if (initComplete == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_GNT; + end + end + `DO_TRANS_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_TX_EMPTY; + end + end + `DO_TRANS_TX_EMPTY: + begin + next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG; + next_wb_data_o <= 8'h01; + //force tx fifo empty + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1; + next_wb_stb <= 1'b0; + next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG; + next_wb_we <= 1'b1; + end + end + `DO_TRANS_WR_TX_FIFO1: + begin + next_wb_data_o <= 8'h00; + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_TRANS_GO: + begin + next_wb_addr <= `RA_EP1_CONTROL_REG; + if (dataSeq == 1'b1) + next_wb_data_o <= 8'h07; + else + next_wb_data_o <= 8'h03; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT; + next_wb_stb <= 1'b0; + next_transDone <= 1'b0; + end + end + `DO_TRANS_WR_TX_FIFO2: + begin + next_wb_data_o <= 8'h01; + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_WR_TX_FIFO3: + begin + next_wb_data_o <= 8'h01; + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_TRANS_GO; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_WT_TRANS_DONE_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS; + end + end + `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS: + begin + next_wb_addr <= `RA_EP1_CONTROL_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT; + next_wb_stb <= 1'b0; + next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT]; + end + end + `DO_TRANS_WT_TRANS_DONE_WT_UNGNT: + begin + next_wbBusReq <= 1'b0; + if (wbBusGnt == 1'b0) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE; + end + end + `DO_TRANS_WT_TRANS_DONE_CHK_DONE: + begin + if (transDone == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_GNT; + end + else + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL; + next_cnt <= 8'h00; + end + end + `DO_TRANS_WT_TRANS_DONE_DEL: + begin + next_cnt <= cnt + 1'b1; + if (cnt == `ONE_USEC_DEL) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_EP1St <= `START; + else + CurrState_EP1St <= NextState_EP1St; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + wbBusReq <= 1'b0; + wb_addr <= 8'h00; + wb_data_o <= 8'h00; + wb_stb <= 1'b0; + wb_we <= 1'b0; + transDone <= 1'b0; + cnt <= 8'h00; + dataSeq <= 1'b0; + end + else + begin + wbBusReq <= next_wbBusReq; + wb_addr <= next_wb_addr; + wb_data_o <= next_wb_data_o; + wb_stb <= next_wb_stb; + wb_we <= next_wb_we; + transDone <= next_transDone; + cnt <= next_cnt; + dataSeq <= next_dataSeq; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/updateCRC16.v =================================================================== --- Actel/usbDeviceActelTop/hdl/updateCRC16.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/updateCRC16.v (revision 40) @@ -0,0 +1,105 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// updateCRC16.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst); +input rstCRC; +input CRCEn; +input [7:0] dataIn; +input clk; +input rst; +output [15:0] CRCResult; +output ready; + +wire rstCRC; +wire CRCEn; +wire [7:0] dataIn; +wire clk; +wire rst; +reg [15:0] CRCResult; +reg ready; + +reg doUpdateCRC; +reg [7:0] data; +reg [3:0] i; + +always @(posedge clk) +begin + if (rst == 1'b1 || rstCRC == 1'b1) begin + doUpdateCRC <= 1'b0; + i <= 4'h0; + CRCResult <= 16'hffff; + ready <= 1'b1; + end + else + begin + if (doUpdateCRC == 1'b0) + begin + if (CRCEn == 1'b1) begin + doUpdateCRC <= 1'b1; + data <= dataIn; + ready <= 1'b0; + end + end + else begin + i <= i + 1'b1; + if ( (CRCResult[0] ^ data[0]) == 1'b1) begin + CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001; + end + else begin + CRCResult <= {1'b0, CRCResult[15:1]}; + end + data <= {1'b0, data[7:1]}; + if (i == 4'h7) + begin + doUpdateCRC <= 1'b0; + i <= 4'h0; + ready <= 1'b1; + end + end + end +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbDevice_define.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbDevice_define.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbDevice_define.v (revision 40) @@ -0,0 +1,48 @@ +// ----------------------------- usbDevice_define --------------------------- + +`define ZERO_ZERO_STAT_INDEX 8'h6c +`define ONE_ZERO_STAT_INDEX 8'h6e +`define VENDOR_DATA_STAT_INDEX 8'h70 +`define DEV_DESC_INDEX 8'h00 +`define DEV_DESC_SIZE 8'h12 +//config descriptor is bundled with interface desc, HID desc, and EP1 desc +`define CFG_DESC_INDEX 8'h12 +`define CFG_DESC_SIZE 8'h22 +`define REP_DESC_INDEX 8'h3a +`define REP_DESC_SIZE 8'h32 +`define LANGID_DESC_INDEX 8'h80 +`define LANGID_DESC_SIZE 8'h04 +`define STRING1_DESC_INDEX 8'h90 +`define STRING1_DESC_SIZE 8'd26 +`define STRING2_DESC_INDEX 8'hb0 +`define STRING2_DESC_SIZE 8'd20 +`define STRING3_DESC_INDEX 8'hd0 +`define STRING3_DESC_SIZE 8'd30 + +`define DEV_DESC 8'h01 +`define CFG_DESC 8'h02 +`define REP_DESC 8'h22 +`define STRING_DESC 8'h03 + +//delays at 48MHz +`ifdef SIM_COMPILE +`define ONE_MSEC_DEL 16'h0300 +`else +`define ONE_MSEC_DEL 16'hbb80 +`endif +`define ONE_USEC_DEL 8'h30 + +`define GET_STATUS 8'h00 +`define CLEAR_FEATURE 8'h01 +`define SET_FEATURE 8'h03 +`define SET_ADDRESS 8'h05 +`define GET_DESCRIPTOR 8'h06 +`define SET_DESCRIPTOR 8'h07 +`define GET_CONFIG 8'h08 +`define SET_CONFIG 8'h09 +`define GET_INTERFACE 8'h0a +`define SET_INTERFACE 8'h0b +`define SYNCH_FRAME 8'h0c + +`define MAX_RESP_SIZE 8'h40 + Index: Actel/usbDeviceActelTop/hdl/usbSlave.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbSlave.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbSlave.v (revision 40) @@ -0,0 +1,474 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbSlave.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Top level module +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module usbSlave( + clk_i, + rst_i, + address_i, + data_i, + data_o, + we_i, + strobe_i, + ack_o, + usbClk, + slaveVBusDetIntOut, + slaveNAKSentIntOut, + slaveSOFRxedIntOut, + slaveResetEventIntOut, + slaveResumeIntOut, + slaveTransDoneIntOut, + USBWireDataIn, + USBWireDataInTick, + USBWireDataOut, + USBWireDataOutTick, + USBWireCtrlOut, + USBFullSpeed, + USBDPlusPullup, + USBDMinusPullup, + vBusDetect + ); + parameter EP0_FIFO_DEPTH = 64; + parameter EP0_FIFO_ADDR_WIDTH = 6; + parameter EP1_FIFO_DEPTH = 64; + parameter EP1_FIFO_ADDR_WIDTH = 6; + parameter EP2_FIFO_DEPTH = 64; + parameter EP2_FIFO_ADDR_WIDTH = 6; + parameter EP3_FIFO_DEPTH = 64; + parameter EP3_FIFO_ADDR_WIDTH = 6; + +input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz +input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic +input [7:0] address_i; //Wishbone bus address in +input [7:0] data_i; //Wishbone bus data in +output [7:0] data_o; //Wishbone bus data out +input we_i; //Wishbone bus write enable in +input strobe_i; //Wishbone bus strobe in +output ack_o; //Wishbone bus acknowledge out +input usbClk; //usb clock. 48Mhz +/-0.25% +output slaveSOFRxedIntOut; +output slaveResetEventIntOut; +output slaveResumeIntOut; +output slaveTransDoneIntOut; +output slaveNAKSentIntOut; +output slaveVBusDetIntOut; +input [1:0] USBWireDataIn; +output [1:0] USBWireDataOut; +output USBWireDataOutTick; +output USBWireDataInTick; +output USBWireCtrlOut; +output USBFullSpeed; +output USBDPlusPullup; +output USBDMinusPullup; +input vBusDetect; + +wire clk_i; +wire rst_i; +wire [7:0] address_i; +wire [7:0] data_i; +wire [7:0] data_o; +wire we_i; +wire strobe_i; +wire ack_o; +wire usbClk; +wire slaveSOFRxedIntOut; +wire slaveResetEventIntOut; +wire slaveResumeIntOut; +wire slaveTransDoneIntOut; +wire slaveNAKSentIntOut; +wire slaveVBusDetIntOut; +wire [1:0] USBWireDataIn; +wire [1:0] USBWireDataOut; +wire USBWireDataOutTick; +wire USBWireDataInTick; +wire USBWireCtrlOut; +wire USBFullSpeed; +wire USBDPlusPullup; +wire USBDMinusPullup; +wire vBusDetect; + +//internal wiring +wire slaveControlSel; +wire hostSlaveMuxSel; +wire [7:0] dataFromSlaveControl; +wire [7:0] dataFromHostSlaveMux; +wire [7:0] RxCtrlOut; +wire [7:0] RxDataFromSIE; +wire RxDataOutWEn; +wire fullSpeedBitRateFromSlave; +wire fullSpeedPolarityFromSlave; +wire SIEPortWEnFromSlave; +wire SIEPortTxRdy; +wire [7:0] SIEPortDataInFromSlave; +wire [7:0] SIEPortCtrlInFromSlave; +wire [1:0] connectState; +wire resumeDetected; +wire [7:0] SIEPortDataInToSIE; +wire SIEPortWEnToSIE; +wire [7:0] SIEPortCtrlInToSIE; +wire fullSpeedPolarityToSIE; +wire fullSpeedBitRateToSIE; +wire connectSlaveToHost; +wire noActivityTimeOut; +wire TxFifoEP0REn; +wire TxFifoEP1REn; +wire TxFifoEP2REn; +wire TxFifoEP3REn; +wire [7:0] TxFifoEP0Data; +wire [7:0] TxFifoEP1Data; +wire [7:0] TxFifoEP2Data; +wire [7:0] TxFifoEP3Data; +wire TxFifoEP0Empty; +wire TxFifoEP1Empty; +wire TxFifoEP2Empty; +wire TxFifoEP3Empty; +wire RxFifoEP0WEn; +wire RxFifoEP1WEn; +wire RxFifoEP2WEn; +wire RxFifoEP3WEn; +wire RxFifoEP0Full; +wire RxFifoEP1Full; +wire RxFifoEP2Full; +wire RxFifoEP3Full; +wire [7:0] slaveRxFifoData; +wire [7:0] dataFromEP0RxFifo; +wire [7:0] dataFromEP1RxFifo; +wire [7:0] dataFromEP2RxFifo; +wire [7:0] dataFromEP3RxFifo; +wire [7:0] dataFromEP0TxFifo; +wire [7:0] dataFromEP1TxFifo; +wire [7:0] dataFromEP2TxFifo; +wire [7:0] dataFromEP3TxFifo; +wire slaveEP0RxFifoSel; +wire slaveEP1RxFifoSel; +wire slaveEP2RxFifoSel; +wire slaveEP3RxFifoSel; +wire slaveEP0TxFifoSel; +wire slaveEP1TxFifoSel; +wire slaveEP2TxFifoSel; +wire slaveEP3TxFifoSel; +wire rstSyncToBusClk; +wire rstSyncToUsbClk; +wire noActivityTimeOutEnableToSIE; +wire noActivityTimeOutEnableFromHost; +wire noActivityTimeOutEnableFromSlave; + +assign USBFullSpeed = fullSpeedBitRateToSIE; +assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost); +assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost); + +usbSlaveControl u_usbSlaveControl( + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .usbClk(usbClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .RxByteStatus(RxCtrlOut), + .RxData(RxDataFromSIE), + .RxDataValid(RxDataOutWEn), + .SIERxTimeOut(noActivityTimeOut), + .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave), + .RxFifoData(slaveRxFifoData), + .connectSlaveToHost(connectSlaveToHost), + .fullSpeedRate(fullSpeedBitRateFromSlave), + .fullSpeedPol(fullSpeedPolarityFromSlave), + .SCTxPortEn(SIEPortWEnFromSlave), + .SCTxPortRdy(SIEPortTxRdy), + .SCTxPortData(SIEPortDataInFromSlave), + .SCTxPortCtrl(SIEPortCtrlInFromSlave), + .vBusDetect(vBusDetect), + .connectStateIn(connectState), + .resumeDetectedIn(resumeDetected), + .busAddress(address_i[4:0]), + .busDataIn(data_i), + .busDataOut(dataFromSlaveControl), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .SOFRxedIntOut(slaveSOFRxedIntOut), + .resetEventIntOut(slaveResetEventIntOut), + .resumeIntOut(slaveResumeIntOut), + .transDoneIntOut(slaveTransDoneIntOut), + .NAKSentIntOut(slaveNAKSentIntOut), + .vBusDetIntOut(slaveVBusDetIntOut), + .slaveControlSelect(slaveControlSel), + .TxFifoEP0REn(TxFifoEP0REn), + .TxFifoEP1REn(TxFifoEP1REn), + .TxFifoEP2REn(TxFifoEP2REn), + .TxFifoEP3REn(TxFifoEP3REn), + .TxFifoEP0Data(TxFifoEP0Data), + .TxFifoEP1Data(TxFifoEP1Data), + .TxFifoEP2Data(TxFifoEP2Data), + .TxFifoEP3Data(TxFifoEP3Data), + .TxFifoEP0Empty(TxFifoEP0Empty), + .TxFifoEP1Empty(TxFifoEP1Empty), + .TxFifoEP2Empty(TxFifoEP2Empty), + .TxFifoEP3Empty(TxFifoEP3Empty), + .RxFifoEP0WEn(RxFifoEP0WEn), + .RxFifoEP1WEn(RxFifoEP1WEn), + .RxFifoEP2WEn(RxFifoEP2WEn), + .RxFifoEP3WEn(RxFifoEP3WEn), + .RxFifoEP0Full(RxFifoEP0Full), + .RxFifoEP1Full(RxFifoEP1Full), + .RxFifoEP2Full(RxFifoEP2Full), + .RxFifoEP3Full(RxFifoEP3Full) + ); + + +wishBoneBI u_wishBoneBI ( + .address(address_i), + .dataIn(data_i), + .dataOut(data_o), + .writeEn(we_i), + .strobe_i(strobe_i), + .ack_o(ack_o), + .clk(clk_i), + .rst(rstSyncToBusClk), + .hostControlSel(), + .hostRxFifoSel(), + .hostTxFifoSel(), + .slaveControlSel(slaveControlSel), + .slaveEP0RxFifoSel(slaveEP0RxFifoSel), + .slaveEP1RxFifoSel(slaveEP1RxFifoSel), + .slaveEP2RxFifoSel(slaveEP2RxFifoSel), + .slaveEP3RxFifoSel(slaveEP3RxFifoSel), + .slaveEP0TxFifoSel(slaveEP0TxFifoSel), + .slaveEP1TxFifoSel(slaveEP1TxFifoSel), + .slaveEP2TxFifoSel(slaveEP2TxFifoSel), + .slaveEP3TxFifoSel(slaveEP3TxFifoSel), + .hostSlaveMuxSel(hostSlaveMuxSel), + .dataFromHostControl(8'h00), + .dataFromHostRxFifo(8'h00), + .dataFromHostTxFifo(8'h00), + .dataFromSlaveControl(dataFromSlaveControl), + .dataFromEP0RxFifo(dataFromEP0RxFifo), + .dataFromEP1RxFifo(dataFromEP1RxFifo), + .dataFromEP2RxFifo(dataFromEP2RxFifo), + .dataFromEP3RxFifo(dataFromEP3RxFifo), + .dataFromEP0TxFifo(dataFromEP0TxFifo), + .dataFromEP1TxFifo(dataFromEP1TxFifo), + .dataFromEP2TxFifo(dataFromEP2TxFifo), + .dataFromEP3TxFifo(dataFromEP3TxFifo), + .dataFromHostSlaveMux(dataFromHostSlaveMux) + ); + + + +assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave; +assign SIEPortDataInToSIE = SIEPortDataInFromSlave; +assign SIEPortWEnToSIE = SIEPortWEnFromSlave; +assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave; +assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave; +assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave; + +hostSlaveMuxBI u_hostSlaveMuxBI ( + .dataIn(data_i), + .dataOut(dataFromHostSlaveMux), + .address(address_i[0]), + .writeEn(we_i), + .strobe_i(strobe_i), + .usbClk(usbClk), + .busClk(clk_i), + .hostSlaveMuxSel(hostSlaveMuxSel), + .hostMode(), + .rstFromWire(rst_i), + .rstSyncToBusClkOut(rstSyncToBusClk), + .rstSyncToUsbClkOut(rstSyncToUsbClk) +); + +usbSerialInterfaceEngine u_usbSerialInterfaceEngine( + .clk(usbClk), + .rst(rstSyncToUsbClk), + .USBWireDataIn(USBWireDataIn), + .USBWireDataOut(USBWireDataOut), + .USBWireDataInTick(USBWireDataInTick), + .USBWireDataOutTick(USBWireDataOutTick), + .USBWireCtrlOut(USBWireCtrlOut), + .connectState(connectState), + .resumeDetected(resumeDetected), + .RxCtrlOut(RxCtrlOut), + .RxDataOutWEn(RxDataOutWEn), + .RxDataOut(RxDataFromSIE), + .SIEPortCtrlIn(SIEPortCtrlInToSIE), + .SIEPortDataIn(SIEPortDataInToSIE), + .SIEPortTxRdy(SIEPortTxRdy), + .SIEPortWEn(SIEPortWEnToSIE), + .fullSpeedPolarity(fullSpeedPolarityToSIE), + .fullSpeedBitRate(fullSpeedBitRateToSIE), + .noActivityTimeOut(noActivityTimeOut), + .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE) +); + + + +//---Slave fifos + +TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo ( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoREn(TxFifoEP0REn), + .fifoEmpty(TxFifoEP0Empty), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP0TxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP0TxFifo), + .fifoDataOut(TxFifoEP0Data) ); + +TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo ( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoREn(TxFifoEP1REn), + .fifoEmpty(TxFifoEP1Empty), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP1TxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP1TxFifo), + .fifoDataOut(TxFifoEP1Data) ); + +TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo ( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoREn(TxFifoEP2REn), + .fifoEmpty(TxFifoEP2Empty), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP2TxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP2TxFifo), + .fifoDataOut(TxFifoEP2Data) ); + +TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo ( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoREn(TxFifoEP3REn), + .fifoEmpty(TxFifoEP3Empty), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP3TxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP3TxFifo), + .fifoDataOut(TxFifoEP3Data) ); + +RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoWEn(RxFifoEP0WEn), + .fifoFull(RxFifoEP0Full), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP0RxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP0RxFifo), + .fifoDataIn(slaveRxFifoData) ); + +RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoWEn(RxFifoEP1WEn), + .fifoFull(RxFifoEP1Full), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP1RxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP1RxFifo), + .fifoDataIn(slaveRxFifoData) ); + +RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoWEn(RxFifoEP2WEn), + .fifoFull(RxFifoEP2Full), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP2RxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP2RxFifo), + .fifoDataIn(slaveRxFifoData) ); + +RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo( + .usbClk(usbClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .fifoWEn(RxFifoEP3WEn), + .fifoFull(RxFifoEP3Full), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(slaveEP3RxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromEP3RxFifo), + .fifoDataIn(slaveRxFifoData) ); + + + +endmodule + + + + + + + Index: Actel/usbDeviceActelTop/hdl/usbSlaveControl.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbSlaveControl.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbSlaveControl.v (revision 40) @@ -0,0 +1,521 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbSlaveControl.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module usbSlaveControl( + busClk, + rstSyncToBusClk, + usbClk, + rstSyncToUsbClk, + //getPacket + RxByteStatus, RxData, RxDataValid, + SIERxTimeOut, RxFifoData, SIERxTimeOutEn, + //speedCtrlMux + fullSpeedRate, fullSpeedPol, + connectSlaveToHost, + //SCTxPortArbiter + SCTxPortEn, SCTxPortRdy, + SCTxPortData, SCTxPortCtrl, + //rxStatusMonitor + vBusDetect, + connectStateIn, + resumeDetectedIn, + //USBHostControlBI + busAddress, + busDataIn, + busDataOut, + busWriteEn, + busStrobe_i, + SOFRxedIntOut, + resetEventIntOut, + resumeIntOut, + transDoneIntOut, + vBusDetIntOut, + NAKSentIntOut, + slaveControlSelect, + //fifoMux + TxFifoEP0REn, + TxFifoEP1REn, + TxFifoEP2REn, + TxFifoEP3REn, + TxFifoEP0Data, + TxFifoEP1Data, + TxFifoEP2Data, + TxFifoEP3Data, + TxFifoEP0Empty, + TxFifoEP1Empty, + TxFifoEP2Empty, + TxFifoEP3Empty, + RxFifoEP0WEn, + RxFifoEP1WEn, + RxFifoEP2WEn, + RxFifoEP3WEn, + RxFifoEP0Full, + RxFifoEP1Full, + RxFifoEP2Full, + RxFifoEP3Full + ); + +input busClk; +input rstSyncToBusClk; +input usbClk; +input rstSyncToUsbClk; +//getPacket +input [7:0] RxByteStatus; +input [7:0] RxData; +input RxDataValid; +input SIERxTimeOut; +output SIERxTimeOutEn; +output [7:0] RxFifoData; +//speedCtrlMux +output fullSpeedRate; +output fullSpeedPol; +output connectSlaveToHost; +//HCTxPortArbiter +output SCTxPortEn; +input SCTxPortRdy; +output [7:0] SCTxPortData; +output [7:0] SCTxPortCtrl; +//rxStatusMonitor +input vBusDetect; +input [1:0] connectStateIn; +input resumeDetectedIn; +//USBHostControlBI +input [4:0] busAddress; +input [7:0] busDataIn; +output [7:0] busDataOut; +input busWriteEn; +input busStrobe_i; +output SOFRxedIntOut; +output resetEventIntOut; +output resumeIntOut; +output transDoneIntOut; +output vBusDetIntOut; +output NAKSentIntOut; +input slaveControlSelect; +//fifoMux +output TxFifoEP0REn; +output TxFifoEP1REn; +output TxFifoEP2REn; +output TxFifoEP3REn; +input [7:0] TxFifoEP0Data; +input [7:0] TxFifoEP1Data; +input [7:0] TxFifoEP2Data; +input [7:0] TxFifoEP3Data; +input TxFifoEP0Empty; +input TxFifoEP1Empty; +input TxFifoEP2Empty; +input TxFifoEP3Empty; +output RxFifoEP0WEn; +output RxFifoEP1WEn; +output RxFifoEP2WEn; +output RxFifoEP3WEn; +input RxFifoEP0Full; +input RxFifoEP1Full; +input RxFifoEP2Full; +input RxFifoEP3Full; + +wire busClk; +wire rstSyncToBusClk; +wire usbClk; +wire rstSyncToUsbClk; +wire [7:0] RxByteStatus; +wire [7:0] RxData; +wire RxDataValid; +wire SIERxTimeOut; +wire SIERxTimeOutEn; +wire [7:0] RxFifoData; +wire fullSpeedRate; +wire fullSpeedPol; +wire connectSlaveToHost; +wire [7:0] SCTxPortData; +wire [7:0] SCTxPortCtrl; +wire [1:0] connectStateIn; +wire resumeDetectedIn; +wire [4:0] busAddress; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire busWriteEn; +wire busStrobe_i; +wire SOFRxedIntOut; +wire resetEventIntOut; +wire resumeIntOut; +wire transDoneIntOut; +wire vBusDetIntOut; +wire NAKSentIntOut; +wire slaveControlSelect; +wire TxFifoEP0REn; +wire TxFifoEP1REn; +wire TxFifoEP2REn; +wire TxFifoEP3REn; +wire [7:0] TxFifoEP0Data; +wire [7:0] TxFifoEP1Data; +wire [7:0] TxFifoEP2Data; +wire [7:0] TxFifoEP3Data; +wire TxFifoEP0Empty; +wire TxFifoEP1Empty; +wire TxFifoEP2Empty; +wire TxFifoEP3Empty; +wire RxFifoEP0WEn; +wire RxFifoEP1WEn; +wire RxFifoEP2WEn; +wire RxFifoEP3WEn; +wire RxFifoEP0Full; +wire RxFifoEP1Full; +wire RxFifoEP2Full; +wire RxFifoEP3Full; + +//internal wiring +wire [7:0] directCntlCntl; +wire [7:0] directCntlData; +wire directCntlGnt; +wire directCntlReq; +wire directCntlWEn; +wire [7:0] sendPacketCntl; +wire [7:0] sendPacketData; +wire sendPacketGnt; +wire sendPacketReq; +wire sendPacketWEn; +wire SCTxPortArbRdyOut; +wire transDone; +wire [1:0] directLineState; +wire directLineCtrlEn; +wire [3:0] RxPID; +wire [1:0] connectStateOut; +wire resumeIntFromRxStatusMon; +wire [1:0] endP0TransTypeReg; +wire [1:0] endP1TransTypeReg; +wire [1:0] endP2TransTypeReg; +wire [1:0] endP3TransTypeReg; +wire [1:0] endP0NAKTransTypeReg; +wire [1:0] endP1NAKTransTypeReg; +wire [1:0] endP2NAKTransTypeReg; +wire [1:0] endP3NAKTransTypeReg; +wire [4:0] endP0ControlReg; +wire [4:0] endP1ControlReg; +wire [4:0] endP2ControlReg; +wire [4:0] endP3ControlReg; +wire [7:0] endP0StatusReg; +wire [7:0] endP1StatusReg; +wire [7:0] endP2StatusReg; +wire [7:0] endP3StatusReg; +wire [6:0] USBTgtAddress; +wire [10:0] frameNum; +wire clrEP0Rdy; +wire clrEP1Rdy; +wire clrEP2Rdy; +wire clrEP3Rdy; +wire SCGlobalEn; +wire ACKRxed; +wire CRCError; +wire RXOverflow; +wire RXTimeOut; +wire bitStuffError; +wire dataSequence; +wire stallSent; +wire NAKSent; +wire SOFRxed; +wire [4:0] endPControlReg; +wire [1:0] transTypeNAK; +wire [1:0] transType; +wire [3:0] currEndP; +wire getPacketREn; +wire getPacketRdy; +wire [3:0] slaveControllerPIDOut; +wire slaveControllerReadyIn; +wire slaveControllerWEnOut; +wire TxFifoRE; +wire [7:0] TxFifoData; +wire TxFifoEmpty; +wire RxFifoWE; +wire RxFifoFull; +wire resetEventFromRxStatusMon; +wire clrEPRdy; +wire endPMuxErrorsWEn; +wire endPointReadyFromSlaveCtrlrToGetPkt; + +USBSlaveControlBI u_USBSlaveControlBI + (.address(busAddress), + .dataIn(busDataIn), + .dataOut(busDataOut), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .rstSyncToBusClk(rstSyncToBusClk), + .usbClk(usbClk), + .rstSyncToUsbClk(rstSyncToUsbClk), + .SOFRxedIntOut(SOFRxedIntOut), + .resetEventIntOut(resetEventIntOut), + .resumeIntOut(resumeIntOut), + .transDoneIntOut(transDoneIntOut), + .vBusDetIntOut(vBusDetIntOut), + .NAKSentIntOut(NAKSentIntOut), + .endP0TransTypeReg(endP0TransTypeReg), + .endP0NAKTransTypeReg(endP0NAKTransTypeReg), + .endP1TransTypeReg(endP1TransTypeReg), + .endP1NAKTransTypeReg(endP1NAKTransTypeReg), + .endP2TransTypeReg(endP2TransTypeReg), + .endP2NAKTransTypeReg(endP2NAKTransTypeReg), + .endP3TransTypeReg(endP3TransTypeReg), + .endP3NAKTransTypeReg(endP3NAKTransTypeReg), + .endP0ControlReg(endP0ControlReg), + .endP1ControlReg(endP1ControlReg), + .endP2ControlReg(endP2ControlReg), + .endP3ControlReg(endP3ControlReg), + .EP0StatusReg(endP0StatusReg), + .EP1StatusReg(endP1StatusReg), + .EP2StatusReg(endP2StatusReg), + .EP3StatusReg(endP3StatusReg), + .SCAddrReg(USBTgtAddress), + .frameNum(frameNum), + .connectStateIn(connectStateOut), + .vBusDetectIn(vBusDetect), + .SOFRxedIn(SOFRxed), + .resetEventIn(resetEventFromRxStatusMon), + .resumeIntIn(resumeIntFromRxStatusMon), + .transDoneIn(transDone), + .NAKSentIn(NAKSent), + .slaveControlSelect(slaveControlSelect), + .clrEP0Ready(clrEP0Rdy), + .clrEP1Ready(clrEP1Rdy), + .clrEP2Ready(clrEP2Rdy), + .clrEP3Ready(clrEP3Rdy), + .TxLineState(directLineState), + .LineDirectControlEn(directLineCtrlEn), + .fullSpeedPol(fullSpeedPol), + .fullSpeedRate(fullSpeedRate), + .connectSlaveToHost(connectSlaveToHost), + .SCGlobalEn(SCGlobalEn) + ); + +slavecontroller u_slavecontroller + (.CRCError(CRCError), + .NAKSent(NAKSent), + .RxByte(RxData), + .RxDataWEn(RxDataValid), + .RxOverflow(RXOverflow), + .RxStatus(RxByteStatus), + .RxTimeOut(RXTimeOut), + .SCGlobalEn(SCGlobalEn), + .SOFRxed(SOFRxed), + .USBEndPControlReg(endPControlReg), + .USBEndPNakTransTypeReg(transTypeNAK), + .USBEndPTransTypeReg(transType), + .USBEndP(currEndP), + .USBTgtAddress(USBTgtAddress), + .bitStuffError(bitStuffError), + .clk(usbClk), + .clrEPRdy(clrEPRdy), + .endPMuxErrorsWEn(endPMuxErrorsWEn), + .frameNum(frameNum), + .getPacketREn(getPacketREn), + .getPacketRdy(getPacketRdy), + .rst(rstSyncToUsbClk), + .sendPacketPID(slaveControllerPIDOut), + .sendPacketRdy(slaveControllerReadyIn), + .sendPacketWEn(slaveControllerWEnOut), + .stallSent(stallSent), + .transDone(transDone), + .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt) + ); + + +endpMux u_endpMux ( + .clk(usbClk), + .rst(rstSyncToUsbClk), + .currEndP(currEndP), + .NAKSent(NAKSent), + .stallSent(stallSent), + .CRCError(CRCError), + .bitStuffError(bitStuffError), + .RxOverflow(RXOverflow), + .RxTimeOut(RXTimeOut), + .dataSequence(dataSequence), + .ACKRxed(ACKRxed), + .transType(transType), + .transTypeNAK(transTypeNAK), + .endPControlReg(endPControlReg), + .clrEPRdy(clrEPRdy), + .endPMuxErrorsWEn(endPMuxErrorsWEn), + .endP0ControlReg(endP0ControlReg), + .endP1ControlReg(endP1ControlReg), + .endP2ControlReg(endP2ControlReg), + .endP3ControlReg(endP3ControlReg), + .endP0StatusReg(endP0StatusReg), + .endP1StatusReg(endP1StatusReg), + .endP2StatusReg(endP2StatusReg), + .endP3StatusReg(endP3StatusReg), + .endP0TransTypeReg(endP0TransTypeReg), + .endP1TransTypeReg(endP1TransTypeReg), + .endP2TransTypeReg(endP2TransTypeReg), + .endP3TransTypeReg(endP3TransTypeReg), + .endP0NAKTransTypeReg(endP0NAKTransTypeReg), + .endP1NAKTransTypeReg(endP1NAKTransTypeReg), + .endP2NAKTransTypeReg(endP2NAKTransTypeReg), + .endP3NAKTransTypeReg(endP3NAKTransTypeReg), + .clrEP0Rdy(clrEP0Rdy), + .clrEP1Rdy(clrEP1Rdy), + .clrEP2Rdy(clrEP2Rdy), + .clrEP3Rdy(clrEP3Rdy) + ); + +slaveSendPacket u_slaveSendPacket + (.PID(slaveControllerPIDOut), + .SCTxPortCntl(sendPacketCntl), + .SCTxPortData(sendPacketData), + .SCTxPortGnt(sendPacketGnt), + .SCTxPortRdy(SCTxPortArbRdyOut), + .SCTxPortReq(sendPacketReq), + .SCTxPortWEn(sendPacketWEn), + .clk(usbClk), + .fifoData(TxFifoData), + .fifoEmpty(TxFifoEmpty), + .fifoReadEn(TxFifoRE), + .rst(rstSyncToUsbClk), + .sendPacketRdy(slaveControllerReadyIn), + .sendPacketWEn(slaveControllerWEnOut) ); + +slaveDirectControl u_slaveDirectControl + (.SCTxPortCntl(directCntlCntl), + .SCTxPortData(directCntlData), + .SCTxPortGnt(directCntlGnt), + .SCTxPortRdy(SCTxPortArbRdyOut), + .SCTxPortReq(directCntlReq), + .SCTxPortWEn(directCntlWEn), + .clk(usbClk), + .directControlEn(directLineCtrlEn), + .directControlLineState(directLineState), + .rst(rstSyncToUsbClk) ); + +SCTxPortArbiter u_SCTxPortArbiter + (.SCTxPortCntl(SCTxPortCtrl), + .SCTxPortData(SCTxPortData), + .SCTxPortRdyIn(SCTxPortRdy), + .SCTxPortRdyOut(SCTxPortArbRdyOut), + .SCTxPortWEnable(SCTxPortEn), + .clk(usbClk), + .directCntlCntl(directCntlCntl), + .directCntlData(directCntlData), + .directCntlGnt(directCntlGnt), + .directCntlReq(directCntlReq), + .directCntlWEn(directCntlWEn), + .rst(rstSyncToUsbClk), + .sendPacketCntl(sendPacketCntl), + .sendPacketData(sendPacketData), + .sendPacketGnt(sendPacketGnt), + .sendPacketReq(sendPacketReq), + .sendPacketWEn(sendPacketWEn) ); + + +slaveGetPacket u_slaveGetPacket + (.ACKRxed(ACKRxed), + .CRCError(CRCError), + .RXDataIn(RxData), + .RXDataValid(RxDataValid), + .RXFifoData(RxFifoData), + .RXFifoFull(RxFifoFull), + .RXFifoWEn(RxFifoWE), + .RXPacketRdy(getPacketRdy), + .RXStreamStatusIn(RxByteStatus), + .RxPID(RxPID), + .SIERxTimeOut(SIERxTimeOut), + .SIERxTimeOutEn(SIERxTimeOutEn), + .clk(usbClk), + .RXOverflow(RXOverflow), + .RXTimeOut(RXTimeOut), + .bitStuffError(bitStuffError), + .dataSequence(dataSequence), + .getPacketEn(getPacketREn), + .rst(rstSyncToUsbClk), + .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt) + ); + +slaveRxStatusMonitor u_slaveRxStatusMonitor + (.connectStateIn(connectStateIn), + .connectStateOut(connectStateOut), + .resumeDetectedIn(resumeDetectedIn), + .resetEventOut(resetEventFromRxStatusMon), + .resumeIntOut(resumeIntFromRxStatusMon), + .clk(usbClk), + .rst(rstSyncToUsbClk) ); + +fifoMux u_fifoMux ( + .currEndP(currEndP), + //TxFifo + .TxFifoREn(TxFifoRE), + .TxFifoEP0REn(TxFifoEP0REn), + .TxFifoEP1REn(TxFifoEP1REn), + .TxFifoEP2REn(TxFifoEP2REn), + .TxFifoEP3REn(TxFifoEP3REn), + .TxFifoData(TxFifoData), + .TxFifoEP0Data(TxFifoEP0Data), + .TxFifoEP1Data(TxFifoEP1Data), + .TxFifoEP2Data(TxFifoEP2Data), + .TxFifoEP3Data(TxFifoEP3Data), + .TxFifoEmpty(TxFifoEmpty), + .TxFifoEP0Empty(TxFifoEP0Empty), + .TxFifoEP1Empty(TxFifoEP1Empty), + .TxFifoEP2Empty(TxFifoEP2Empty), + .TxFifoEP3Empty(TxFifoEP3Empty), + //RxFifo + .RxFifoWEn(RxFifoWE), + .RxFifoEP0WEn(RxFifoEP0WEn), + .RxFifoEP1WEn(RxFifoEP1WEn), + .RxFifoEP2WEn(RxFifoEP2WEn), + .RxFifoEP3WEn(RxFifoEP3WEn), + .RxFifoFull(RxFifoFull), + .RxFifoEP0Full(RxFifoEP0Full), + .RxFifoEP1Full(RxFifoEP1Full), + .RxFifoEP2Full(RxFifoEP2Full), + .RxFifoEP3Full(RxFifoEP3Full) + ); + +endmodule + + + + + + + Index: Actel/usbDeviceActelTop/hdl/checkLineState.v =================================================================== --- Actel/usbDeviceActelTop/hdl/checkLineState.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/checkLineState.v (revision 40) @@ -0,0 +1,202 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// checkLineState.v //// +//// //// +//// This file is part of the usbHostSlave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Checks USB line state. When reset state detected +//// asserts usbRstDet for one clock tick +//// usbRstDet is used to reset most of the logic. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSlaveControl_h.v" +`include "usbHostSlaveReg_define.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbDevice_define.v" +module checkLineState (clk, initComplete, rst, usbRstDet, wb_ack, wb_addr, wb_data_i, wb_stb, wb_we, wbBusGnt, wbBusReq); +input clk; +input initComplete; +input rst; +input wb_ack; +input [7:0]wb_data_i; +input wbBusGnt; +output usbRstDet; +output [7:0]wb_addr; +output wb_stb; +output wb_we; +output wbBusReq; + +wire clk; +wire initComplete; +wire rst; +reg usbRstDet, next_usbRstDet; +wire wb_ack; +reg [7:0]wb_addr, next_wb_addr; +wire [7:0]wb_data_i; +reg wb_stb, next_wb_stb; +reg wb_we, next_wb_we; +wire wbBusGnt; +reg wbBusReq, next_wbBusReq; + +// diagram signals declarations +reg [15:0]cnt, next_cnt; +reg [1:0]resetState, next_resetState; + +// BINARY ENCODED state machine: chkLSt +// State codes definitions: +`define START 3'b000 +`define GET_STAT 3'b001 +`define WT_GNT 3'b010 +`define SET_RST_DET 3'b011 +`define DEL_ONE_MSEC 3'b100 + +reg [2:0]CurrState_chkLSt, NextState_chkLSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: chkLSt + +// NextState logic (combinatorial) +always @ (initComplete or wb_ack or resetState or wbBusGnt or cnt or usbRstDet or wbBusReq or wb_addr or wb_stb or wb_we or CurrState_chkLSt) +begin + NextState_chkLSt <= CurrState_chkLSt; + // Set default values for outputs and signals + next_usbRstDet <= usbRstDet; + next_wbBusReq <= wbBusReq; + next_wb_addr <= wb_addr; + next_wb_stb <= wb_stb; + next_wb_we <= wb_we; + next_cnt <= cnt; + next_resetState <= resetState; + case (CurrState_chkLSt) // synopsys parallel_case full_case + `START: + begin + next_usbRstDet <= 1'b0; + next_wbBusReq <= 1'b0; + next_wb_addr <= 8'h00; + next_wb_stb <= 1'b0; + next_wb_we <= 1'b0; + next_cnt <= 16'h0000; + next_resetState <= 2'b00; + if (initComplete == 1'b1) + begin + NextState_chkLSt <= `WT_GNT; + end + end + `GET_STAT: + begin + next_wb_addr <= `RA_SC_LINE_STATUS_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_chkLSt <= `SET_RST_DET; + next_wb_stb <= 1'b0; + if ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) ) + next_resetState <= {resetState[0], 1'b1}; + else + next_resetState <= 2'b00; + next_wbBusReq <= 1'b0; + end + end + `WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_chkLSt <= `GET_STAT; + end + end + `SET_RST_DET: + begin + NextState_chkLSt <= `DEL_ONE_MSEC; + if (resetState == 2'b11) // if reset condition aserted for 2mS + next_usbRstDet <= 1'b1; + next_cnt <= 16'h0000; + end + `DEL_ONE_MSEC: + begin + next_cnt <= cnt + 1'b1; + next_usbRstDet <= 1'b0; + if (cnt == `ONE_MSEC_DEL) + begin + NextState_chkLSt <= `WT_GNT; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_chkLSt <= `START; + else + CurrState_chkLSt <= NextState_chkLSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + usbRstDet <= 1'b0; + wbBusReq <= 1'b0; + wb_addr <= 8'h00; + wb_stb <= 1'b0; + wb_we <= 1'b0; + cnt <= 16'h0000; + resetState <= 2'b00; + end + else + begin + usbRstDet <= next_usbRstDet; + wbBusReq <= next_wbBusReq; + wb_addr <= next_wb_addr; + wb_stb <= next_wb_stb; + wb_we <= next_wb_we; + cnt <= next_cnt; + resetState <= next_resetState; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/processRxBit.v =================================================================== --- Actel/usbDeviceActelTop/hdl/processRxBit.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/processRxBit.v (revision 40) @@ -0,0 +1,403 @@ + +// File : ../RTL/serialInterfaceEngine/processRxBit.v +// Generated : 11/10/06 05:37:22 +// From : ../RTL/serialInterfaceEngine/processRxBit.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// processrxbit +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + + +module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst); +input [1:0] JBit; +input [1:0] KBit; +input [1:0] RxBitsIn; +input RxWireActive; +input clk; +input processRxBitsWEn; +input processRxByteRdy; +input rst; +output [7:0] RxCtrlOut; +output [7:0] RxDataOut; +output processRxBitRdy; +output processRxByteWEn; +output resumeDetected; + +wire [1:0] JBit; +wire [1:0] KBit; +wire [1:0] RxBitsIn; +reg [7:0] RxCtrlOut, next_RxCtrlOut; +reg [7:0] RxDataOut, next_RxDataOut; +wire RxWireActive; +wire clk; +reg processRxBitRdy, next_processRxBitRdy; +wire processRxBitsWEn; +wire processRxByteRdy; +reg processRxByteWEn, next_processRxByteWEn; +reg resumeDetected, next_resumeDetected; +wire rst; + +// diagram signals declarations +reg [3:0]RXBitCount, next_RXBitCount; +reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState; +reg [7:0]RXByte, next_RXByte; +reg [3:0]RXSameBitCount, next_RXSameBitCount; +reg [1:0]RxBits, next_RxBits; +reg bitStuffError, next_bitStuffError; +reg [1:0]oldRXBits, next_oldRXBits; +reg [4:0]resumeWaitCnt, next_resumeWaitCnt; + +// BINARY ENCODED state machine: prRxBit +// State codes definitions: +`define START 4'b0000 +`define IDLE_FIRST_BIT 4'b0001 +`define WAIT_BITS 4'b0010 +`define IDLE_CHK_KBIT 4'b0011 +`define DATA_RX_LAST_BIT 4'b0100 +`define DATA_RX_CHK_SE0 4'b0101 +`define DATA_RX_DATA_DESTUFF 4'b0110 +`define DATA_RX_BYTE_SEND2 4'b0111 +`define DATA_RX_BYTE_WAIT_RDY 4'b1000 +`define RES_RX_CHK 4'b1001 +`define DATA_RX_ERROR_CHK_RES 4'b1010 +`define RES_END_CHK1 4'b1011 +`define IDLE_WAIT_PRB_RDY 4'b1100 +`define DATA_RX_WAIT_PRB_RDY 4'b1101 +`define DATA_RX_ERROR_WAIT_RDY 4'b1110 + +reg [3:0] CurrState_prRxBit; +reg [3:0] NextState_prRxBit; + + +//-------------------------------------------------------------------- +// Machine: prRxBit +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit) +begin : prRxBit_NextState + NextState_prRxBit <= CurrState_prRxBit; + // Set default values for outputs and signals + next_processRxByteWEn <= processRxByteWEn; + next_RxCtrlOut <= RxCtrlOut; + next_RxDataOut <= RxDataOut; + next_resumeDetected <= resumeDetected; + next_RXBitStMachCurrState <= RXBitStMachCurrState; + next_RxBits <= RxBits; + next_RXSameBitCount <= RXSameBitCount; + next_RXBitCount <= RXBitCount; + next_oldRXBits <= oldRXBits; + next_RXByte <= RXByte; + next_bitStuffError <= bitStuffError; + next_resumeWaitCnt <= resumeWaitCnt; + next_processRxBitRdy <= processRxBitRdy; + case (CurrState_prRxBit) + `START: + begin + next_processRxByteWEn <= 1'b0; + next_RxCtrlOut <= 8'h00; + next_RxDataOut <= 8'h00; + next_resumeDetected <= 1'b0; + next_RXBitStMachCurrState <= `IDLE_BIT_ST; + next_RxBits <= 2'b00; + next_RXSameBitCount <= 4'h0; + next_RXBitCount <= 4'h0; + next_oldRXBits <= 2'b00; + next_RXByte <= 8'h00; + next_bitStuffError <= 1'b0; + next_resumeWaitCnt <= 5'h0; + next_processRxBitRdy <= 1'b1; + NextState_prRxBit <= `WAIT_BITS; + end + `WAIT_BITS: + if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST)) + begin + NextState_prRxBit <= `RES_RX_CHK; + next_RxBits <= RxBitsIn; + next_processRxBitRdy <= 1'b0; + end + else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST)) + begin + NextState_prRxBit <= `DATA_RX_CHK_SE0; + next_RxBits <= RxBitsIn; + next_processRxBitRdy <= 1'b0; + end + else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST)) + begin + NextState_prRxBit <= `IDLE_CHK_KBIT; + next_RxBits <= RxBitsIn; + next_processRxBitRdy <= 1'b0; + end + else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST)) + begin + NextState_prRxBit <= `RES_END_CHK1; + next_RxBits <= RxBitsIn; + next_processRxBitRdy <= 1'b0; + end + `IDLE_FIRST_BIT: + begin + next_processRxByteWEn <= 1'b0; + next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST; + next_RXSameBitCount <= 4'h0; + next_RXBitCount <= 4'h1; + next_oldRXBits <= RxBits; + //zero is always the first RZ data bit of a new packet + next_RXByte <= 8'h00; + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `IDLE_CHK_KBIT: + if ((RxBits == KBit) && (RxWireActive == 1'b1)) + NextState_prRxBit <= `IDLE_WAIT_PRB_RDY; + else + begin + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `IDLE_WAIT_PRB_RDY: + if (processRxByteRdy == 1'b1) + begin + NextState_prRxBit <= `IDLE_FIRST_BIT; + next_RxDataOut <= 8'h00; + //redundant data + next_RxCtrlOut <= `DATA_START; + //start of packet + next_processRxByteWEn <= 1'b1; + end + `DATA_RX_LAST_BIT: + begin + next_processRxByteWEn <= 1'b0; + next_RXBitStMachCurrState <= `IDLE_BIT_ST; + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `DATA_RX_CHK_SE0: + begin + next_bitStuffError <= 1'b0; + if (RxBits == `SE0) + NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY; + else + begin + NextState_prRxBit <= `DATA_RX_DATA_DESTUFF; + if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then + begin + next_RXSameBitCount <= RXSameBitCount + 1'b1; + //inc 'RXSameBitCount' + if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error + next_bitStuffError <= 1'b1; + //flag 'bitStuffError' + else //else no bit stuffing error + begin + next_RXBitCount <= RXBitCount + 1'b1; + if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin + next_processRxBitRdy <= 1'b1; + //early indication of ready + end + next_RXByte <= { 1'b1, RXByte[7:1]}; + //RZ bit = 1 (ie no change in 'RxBits') + end + end + else //else current 'RxBits' are different from old 'RxBits' + begin + if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then + begin + next_RXBitCount <= RXBitCount + 1'b1; + if (RXBitCount != 4'h7) begin + next_processRxBitRdy <= 1'b1; + //early indication of ready + end + next_RXByte <= {1'b0, RXByte[7:1]}; + //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits') + end + next_RXSameBitCount <= 4'h0; + //reset 'RXSameBitCount' + end + next_oldRXBits <= RxBits; + end + end + `DATA_RX_WAIT_PRB_RDY: + if (processRxByteRdy == 1'b1) + begin + NextState_prRxBit <= `DATA_RX_LAST_BIT; + next_RxDataOut <= 8'h00; + //redundant data + next_RxCtrlOut <= `DATA_STOP; + //end of packet + next_processRxByteWEn <= 1'b1; + end + `DATA_RX_DATA_DESTUFF: + if (RXBitCount == 4'h8 & bitStuffError == 1'b0) + NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY; + else if (bitStuffError == 1'b1) + NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY; + else + begin + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `DATA_RX_BYTE_SEND2: + begin + next_processRxByteWEn <= 1'b0; + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `DATA_RX_BYTE_WAIT_RDY: + if (processRxByteRdy == 1'b1) + begin + NextState_prRxBit <= `DATA_RX_BYTE_SEND2; + next_RXBitCount <= 4'h0; + next_RxDataOut <= RXByte; + next_RxCtrlOut <= `DATA_STREAM; + next_processRxByteWEn <= 1'b1; + end + `DATA_RX_ERROR_CHK_RES: + begin + next_processRxByteWEn <= 1'b0; + if (RxBits == JBit) //if current bit is a JBit, then + next_RXBitStMachCurrState <= `IDLE_BIT_ST; + //next state is idle + else //else + begin + next_RXBitStMachCurrState <= `WAIT_RESUME_ST; + //check for resume + next_resumeWaitCnt <= 5'h0; + end + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `DATA_RX_ERROR_WAIT_RDY: + if (processRxByteRdy == 1'b1) + begin + NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES; + next_RxDataOut <= 8'h00; + //redundant data + next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR; + next_processRxByteWEn <= 1'b1; + end + `RES_RX_CHK: + begin + if (RxBits != KBit) //can only be a resume if line remains in Kbit state + next_RXBitStMachCurrState <= `IDLE_BIT_ST; + else + begin + next_resumeWaitCnt <= resumeWaitCnt + 1'b1; + //if we've waited long enough, then + if (resumeWaitCnt == `RESUME_RX_WAIT_TIME) + begin + next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST; + next_resumeDetected <= 1'b1; + //report resume detected + end + end + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + `RES_END_CHK1: + begin + if (RxBits != KBit) //line must leave KBit state for the end of resume + begin + next_RXBitStMachCurrState <= `IDLE_BIT_ST; + next_resumeDetected <= 1'b0; + //clear resume detected flag + end + NextState_prRxBit <= `WAIT_BITS; + next_processRxBitRdy <= 1'b1; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : prRxBit_CurrentState + if (rst) + CurrState_prRxBit <= `START; + else + CurrState_prRxBit <= NextState_prRxBit; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : prRxBit_RegOutput + if (rst) + begin + RXBitStMachCurrState <= `IDLE_BIT_ST; + RxBits <= 2'b00; + RXSameBitCount <= 4'h0; + RXBitCount <= 4'h0; + oldRXBits <= 2'b00; + RXByte <= 8'h00; + bitStuffError <= 1'b0; + resumeWaitCnt <= 5'h0; + processRxByteWEn <= 1'b0; + RxCtrlOut <= 8'h00; + RxDataOut <= 8'h00; + resumeDetected <= 1'b0; + processRxBitRdy <= 1'b1; + end + else + begin + RXBitStMachCurrState <= next_RXBitStMachCurrState; + RxBits <= next_RxBits; + RXSameBitCount <= next_RXSameBitCount; + RXBitCount <= next_RXBitCount; + oldRXBits <= next_oldRXBits; + RXByte <= next_RXByte; + bitStuffError <= next_bitStuffError; + resumeWaitCnt <= next_resumeWaitCnt; + processRxByteWEn <= next_processRxByteWEn; + RxCtrlOut <= next_RxCtrlOut; + RxDataOut <= next_RxDataOut; + resumeDetected <= next_resumeDetected; + processRxBitRdy <= next_processRxBitRdy; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/usbDeviceXilinxTop.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbDeviceXilinxTop.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbDeviceXilinxTop.v (revision 40) @@ -0,0 +1,92 @@ + +module usbDeviceXilinxTop ( + + // + // Global signals + // + clk, + + // + // misc Starter Kit control sigs + // + E_NRST, + SPI_SCK, + NF_CE, + SD_CS, + + // + // USB slave + // + usbSlaveVP, + usbSlaveVM, + usbSlaveOE_n, + usbDPlusPullup + +); + + // + // Global signals + // + input clk; + + // + // misc Starter Kit control sigs + // + output E_NRST; + output SPI_SCK; + output NF_CE; + output SD_CS; + + // + // USB slave + // + inout usbSlaveVP; + inout usbSlaveVM; + output usbSlaveOE_n; + output usbDPlusPullup; + +//local wires and regs +reg [1:0] rstReg; +wire rst; +wire pll_locked; +wire clk48MHz; + + +assign E_NRST = 1'b0; +assign SPI_SCK = 1'b0; +assign NF_CE = 1'b0; +assign SD_CS = 1'b1; + + +pll_48MHz_xilinx pll_48MHz_inst ( + .CLKIN_IN ( clk ), + .CLK0_OUT (clk48MHz), + .LOCKED_OUT( pll_locked) + ); + +//generate sync reset from pll lock signal +always @(posedge clk48MHz) begin + rstReg[1:0] <= {rstReg[0], ~pll_locked}; +end +assign rst = rstReg[1]; + + +usbDevice u_usbDevice ( + .clk(clk48MHz), + .rst(rst), + .usbSlaveVP_in(usbSlaveVP_in), + .usbSlaveVM_in(usbSlaveVM_in), + .usbSlaveVP_out(usbSlaveVP_out), + .usbSlaveVM_out(usbSlaveVM_out), + .usbSlaveOE_n(usbSlaveOE_n), + .usbDPlusPullup(usbDPlusPullup), + .vBusDetect(1'b1) +); + + +assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM}; +assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz; + +endmodule + + Index: Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v (revision 40) @@ -0,0 +1,78 @@ +// ------------------------------ usbHostSlaveReg_define.v ---------------------------- +`include "wishBoneBus_h.v" +`include "usbHostSlave_h.v" + + + +`define RA_EP0_CONTROL_REG `SCREG_BASE+`ENDPOINT_CONTROL_REG +`define RA_EP0_STATUS_REG `SCREG_BASE+`ENDPOINT_STATUS_REG +`define RA_EP0_TRANSTYPE_STATUS_REG `SCREG_BASE+`ENDPOINT_TRANSTYPE_STATUS_REG +`define RA_EP0_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NAK_TRANSTYPE_STATUS_REG +`define RA_EP1_CONTROL_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_CONTROL_REG +`define RA_EP1_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_STATUS_REG +`define RA_EP1_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_TRANSTYPE_STATUS_REG +`define RA_EP1_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`NAK_TRANSTYPE_STATUS_REG +`define RA_EP2_CONTROL_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_CONTROL_REG +`define RA_EP2_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_STATUS_REG +`define RA_EP2_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)`+`ENDPOINT_TRANSTYPE_STATUS_REG +`define RA_EP2_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`NAK_TRANSTYPE_STATUS_REG +`define RA_EP3_CONTROL_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_CONTROL_REG +`define RA_EP3_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_STATUS_REG +`define RA_EP3_TRANSTYPE_STATUS_REG `SCREG_BASE+(NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_TRANSTYPE_STATUS_REG +`define RA_EP3_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`NAK_TRANSTYPE_STATUS_REG +`define RA_SC_CONTROL_REG `SCREG_BASE+`SC_CONTROL_REG +`define RA_SC_LINE_STATUS_REG `SCREG_BASE+`SC_LINE_STATUS_REG +`define RA_SC_INTERRUPT_STATUS_REG `SCREG_BASE+`SC_INTERRUPT_STATUS_REG +`define RA_SC_INTERRUPT_MASK_REG `SCREG_BASE+`SC_INTERRUPT_MASK_REG +`define RA_SC_ADDRESS `SCREG_BASE+`SC_ADDRESS +`define RA_SC_FRAME_NUM_MSP `SCREG_BASE+`SC_FRAME_NUM_MSP +`define RA_SC_FRAME_NUM_LSP `SCREG_BASE+`SC_FRAME_NUM_LSP + +`define RA_EP0_RX_FIFO_DATA_REG `EP0_RX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP0_RX_FIFO_STATUS_REG `EP0_RX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP0_RX_FIFO_DATA_COUNT_MSB `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP0_RX_FIFO_DATA_COUNT_LSB `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP0_RX_FIFO_CONTROL_REG `EP0_RX_FIFO_BASE+`FIFO_CONTROL_REG +`define RA_EP0_TX_FIFO_DATA_REG `EP0_TX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP0_TX_FIFO_STATUS_REG `EP0_TX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP0_TX_FIFO_DATA_COUNT_MSB `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP0_TX_FIFO_DATA_COUNT_LSB `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP0_TX_FIFO_CONTROL_REG `EP0_TX_FIFO_BASE+`FIFO_CONTROL_REG + +`define RA_EP1_RX_FIFO_DATA_REG `EP1_RX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP1_RX_FIFO_STATUS_REG `EP1_RX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP1_RX_FIFO_DATA_COUNT_MSB `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP1_RX_FIFO_DATA_COUNT_LSB `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP1_RX_FIFO_CONTROL_REG `EP1_RX_FIFO_BASE+`FIFO_CONTROL_REG +`define RA_EP1_TX_FIFO_DATA_REG `EP1_TX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP1_TX_FIFO_STATUS_REG `EP1_TX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP1_TX_FIFO_DATA_COUNT_MSB `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP1_TX_FIFO_DATA_COUNT_LSB `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP1_TX_FIFO_CONTROL_REG `EP1_TX_FIFO_BASE+`FIFO_CONTROL_REG + +`define RA_EP2_RX_FIFO_DATA_REG `EP2_RX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP2_RX_FIFO_STATUS_REG `EP2_RX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP2_RX_FIFO_DATA_COUNT_MSB `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP2_RX_FIFO_DATA_COUNT_LSB `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP2_RX_FIFO_CONTROL_REG `EP2_RX_FIFO_BASE+`FIFO_CONTROL_REG +`define RA_EP2_TX_FIFO_DATA_REG `EP2_TX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP2_TX_FIFO_STATUS_REG `EP2_TX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP2_TX_FIFO_DATA_COUNT_MSB `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP2_TX_FIFO_DATA_COUNT_LSB `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP2_TX_FIFO_CONTROL_REG `EP2_TX_FIFO_BASE+`FIFO_CONTROL_REG + +`define RA_EP3_RX_FIFO_DATA_REG `EP3_RX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP3_RX_FIFO_STATUS_REG `EP3_RX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP3_RX_FIFO_DATA_COUNT_MSB `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP3_RX_FIFO_DATA_COUNT_LSB `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP3_RX_FIFO_CONTROL_REG `EP3_RX_FIFO_BASE+`FIFO_CONTROL_REG +`define RA_EP3_TX_FIFO_DATA_REG `EP3_TX_FIFO_BASE+`FIFO_DATA_REG +`define RA_EP3_TX_FIFO_STATUS_REG `EP3_TX_FIFO_BASE+`FIFO_STATUS_REG +`define RA_EP3_TX_FIFO_DATA_COUNT_MSB `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB +`define RA_EP3_TX_FIFO_DATA_COUNT_LSB `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB +`define RA_EP3_TX_FIFO_CONTROL_REG `EP3_TX_FIFO_BASE+`FIFO_CONTROL_REG + +`define RA_HOST_SLAVE_MODE `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG +`define RA_HOST_SLAVE_VERSION `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG + + Index: Actel/usbDeviceActelTop/hdl/usbConstants_h.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbConstants_h.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbConstants_h.v (revision 40) @@ -0,0 +1,32 @@ +////////////////////////////////////////////////////////////////////// +//// usbConstants_h.v +/////////////////////////////////////////////////////////////////////// + +`ifdef usbConstants_h_vdefined +`else +`define usbConstants_h_vdefined + +//PIDTypes +`define OUT 4'h1 +`define IN 4'h9 +`define SOF 4'h5 +`define SETUP 4'hd +`define DATA0 4'h3 +`define DATA1 4'hb +`define ACK 4'h2 +`define NAK 4'ha +`define STALL 4'he +`define PREAMBLE 4'hc + + +//PIDGroups +`define SPECIAL 2'b00 +`define TOKEN 2'b01 +`define HANDSHAKE 2'b10 +`define DATA 2'b11 + +// start of packet SyncByte +`define SYNC_BYTE 8'h80 + +`endif //usbConstants_h_vdefined + Index: Actel/usbDeviceActelTop/hdl/usbHostControl_h.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbHostControl_h.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbHostControl_h.v (revision 40) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +// usbHostControl_h.v +////////////////////////////////////////////////////////////////////// + +`ifdef usbHostControl_h_vdefined +`else +`define usbHostControl_h_vdefined + +//HCRegIndices +`define TX_CONTROL_REG 4'h0 +`define TX_TRANS_TYPE_REG 4'h1 +`define TX_LINE_CONTROL_REG 4'h2 +`define TX_SOF_ENABLE_REG 4'h3 +`define TX_ADDR_REG 4'h4 +`define TX_ENDP_REG 4'h5 +`define FRAME_NUM_MSB_REG 4'h6 +`define FRAME_NUM_LSB_REG 4'h7 +`define INTERRUPT_STATUS_REG 4'h8 +`define INTERRUPT_MASK_REG 4'h9 +`define RX_STATUS_REG 4'ha +`define RX_PID_REG 4'hb +`define RX_ADDR_REG 4'hc +`define RX_ENDP_REG 4'hd +`define RX_CONNECT_STATE_REG 4'he +`define HOST_SOF_TIMER_MSB_REG 4'hf + +`define HCREG_BUFFER_LEN 4'hf +`define HCREG_MASK 4'hf + +//TXControlRegIndices +`define TRANS_REQ_BIT 0 +`define SOF_SYNC_BIT 1 +`define PREAMBLE_ENABLE_BIT 2 +`define ISO_ENABLE_BIT 3 + +//interruptRegIndices +`define TRANS_DONE_BIT 0 +`define RESUME_INT_BIT 1 +`define CONNECTION_EVENT_BIT 2 +`define SOF_SENT_BIT 3 + +//TXTransactionTypes +`define SETUP_TRANS 0 +`define IN_TRANS 1 +`define OUTDATA0_TRANS 2 +`define OUTDATA1_TRANS 3 + + //TXLineControlIndices +`define TX_LINE_STATE_LSBIT 0 +`define TX_LINE_STATE_MSBIT 1 +`define DIRECT_CONTROL_BIT 2 +`define FULL_SPEED_LINE_POLARITY_BIT 3 +`define FULL_SPEED_LINE_RATE_BIT 4 + +//TXSOFEnableIndices +`define SOF_EN_BIT 0 + +//SOFTimeConstants +//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval +//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer +`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock. +//`define SOF_TX_MARGIN 2 +`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak + +//Host RXStatusRegIndices +`define HC_CRC_ERROR_BIT 0 +`define HC_BIT_STUFF_ERROR_BIT 1 +`define HC_RX_OVERFLOW_BIT 2 +`define HC_RX_TIME_OUT_BIT 3 +`define HC_NAK_RXED_BIT 4 +`define HC_STALL_RXED_BIT 5 +`define HC_ACK_RXED_BIT 6 +`define HC_DATA_SEQUENCE_BIT 7 + +`endif //usbHostControl_h_vdefined Index: Actel/usbDeviceActelTop/hdl/updateCRC5.v =================================================================== --- Actel/usbDeviceActelTop/hdl/updateCRC5.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/updateCRC5.v (revision 40) @@ -0,0 +1,112 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// updateCRC5.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst); +input rstCRC; +input CRCEn; +input CRC5_8BitIn; +input [7:0] dataIn; +input clk; +input rst; +output [4:0] CRCResult; +output ready; + +wire rstCRC; +wire CRCEn; +wire CRC5_8BitIn; +wire [7:0] dataIn; +wire clk; +wire rst; +reg [4:0] CRCResult; +reg ready; + +reg doUpdateCRC; +reg [7:0] data; +reg [3:0] loopEnd; +reg [3:0] i; + +always @(posedge clk) +begin + if (rst == 1'b1 || rstCRC == 1'b1) begin + doUpdateCRC <= 1'b0; + i <= 4'h0; + CRCResult <= 5'h1f; + ready <= 1'b1; + end + else + begin + if (doUpdateCRC == 1'b0) begin + if (CRCEn == 1'b1) begin + ready <= 1'b0; + doUpdateCRC <= 1'b1; + data <= dataIn; + if (CRC5_8BitIn == 1'b1) begin + loopEnd <= 4'h7; + end + else begin + loopEnd <= 4'h2; + end + end + end + else begin + i <= i + 1'b1; + if ( (CRCResult[0] ^ data[0]) == 1'b1) begin + CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14; + end + else begin + CRCResult <= {1'b0, CRCResult[4:1]}; + end + data <= {1'b0, data[7:1]}; + if (i == loopEnd) begin + doUpdateCRC <= 1'b0; + i <= 4'h0; + ready <= 1'b1; + end + end + end +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/sctxportarbiter.v =================================================================== --- Actel/usbDeviceActelTop/hdl/sctxportarbiter.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/sctxportarbiter.v (revision 40) @@ -0,0 +1,202 @@ + +// File : ../RTL/slaveController/sctxportarbiter.v +// Generated : 11/10/06 05:37:24 +// From : ../RTL/slaveController/sctxportarbiter.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// SCTxPortArbiter +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn); +input SCTxPortRdyIn; +input clk; +input [7:0] directCntlCntl; +input [7:0] directCntlData; +input directCntlReq; +input directCntlWEn; +input rst; +input [7:0] sendPacketCntl; +input [7:0] sendPacketData; +input sendPacketReq; +input sendPacketWEn; +output [7:0] SCTxPortCntl; +output [7:0] SCTxPortData; +output SCTxPortRdyOut; +output SCTxPortWEnable; +output directCntlGnt; +output sendPacketGnt; + +reg [7:0] SCTxPortCntl, next_SCTxPortCntl; +reg [7:0] SCTxPortData, next_SCTxPortData; +wire SCTxPortRdyIn; +reg SCTxPortRdyOut, next_SCTxPortRdyOut; +reg SCTxPortWEnable, next_SCTxPortWEnable; +wire clk; +wire [7:0] directCntlCntl; +wire [7:0] directCntlData; +reg directCntlGnt, next_directCntlGnt; +wire directCntlReq; +wire directCntlWEn; +wire rst; +wire [7:0] sendPacketCntl; +wire [7:0] sendPacketData; +reg sendPacketGnt, next_sendPacketGnt; +wire sendPacketReq; +wire sendPacketWEn; + +// diagram signals declarations +reg muxDCEn, next_muxDCEn; + +// BINARY ENCODED state machine: SCTxArb +// State codes definitions: +`define SARB1_WAIT_REQ 2'b00 +`define SARB_SEND_PACKET 2'b01 +`define SARB_DC 2'b10 +`define START_SARB 2'b11 + +reg [1:0] CurrState_SCTxArb; +reg [1:0] NextState_SCTxArb; + +// Diagram actions (continuous assignments allowed only: assign ...) + +// SOFController/directContol/sendPacket mux +always @(SCTxPortRdyIn) +begin + SCTxPortRdyOut <= SCTxPortRdyIn; +end +always @(muxDCEn or + directCntlWEn or directCntlData or directCntlCntl or + directCntlWEn or directCntlData or directCntlCntl or + sendPacketWEn or sendPacketData or sendPacketCntl) +begin +if (muxDCEn == 1'b1) + begin + SCTxPortWEnable <= directCntlWEn; + SCTxPortData <= directCntlData; + SCTxPortCntl <= directCntlCntl; + end +else + begin + SCTxPortWEnable <= sendPacketWEn; + SCTxPortData <= sendPacketData; + SCTxPortCntl <= sendPacketCntl; + end +end + +//-------------------------------------------------------------------- +// Machine: SCTxArb +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb) +begin : SCTxArb_NextState + NextState_SCTxArb <= CurrState_SCTxArb; + // Set default values for outputs and signals + next_sendPacketGnt <= sendPacketGnt; + next_muxDCEn <= muxDCEn; + next_directCntlGnt <= directCntlGnt; + case (CurrState_SCTxArb) + `SARB1_WAIT_REQ: + if (sendPacketReq == 1'b1) + begin + NextState_SCTxArb <= `SARB_SEND_PACKET; + next_sendPacketGnt <= 1'b1; + next_muxDCEn <= 1'b0; + end + else if (directCntlReq == 1'b1) + begin + NextState_SCTxArb <= `SARB_DC; + next_directCntlGnt <= 1'b1; + next_muxDCEn <= 1'b1; + end + `SARB_SEND_PACKET: + if (sendPacketReq == 1'b0) + begin + NextState_SCTxArb <= `SARB1_WAIT_REQ; + next_sendPacketGnt <= 1'b0; + end + `SARB_DC: + if (directCntlReq == 1'b0) + begin + NextState_SCTxArb <= `SARB1_WAIT_REQ; + next_directCntlGnt <= 1'b0; + end + `START_SARB: + NextState_SCTxArb <= `SARB1_WAIT_REQ; + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : SCTxArb_CurrentState + if (rst) + CurrState_SCTxArb <= `START_SARB; + else + CurrState_SCTxArb <= NextState_SCTxArb; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : SCTxArb_RegOutput + if (rst) + begin + muxDCEn <= 1'b0; + sendPacketGnt <= 1'b0; + directCntlGnt <= 1'b0; + end + else + begin + muxDCEn <= next_muxDCEn; + sendPacketGnt <= next_sendPacketGnt; + directCntlGnt <= next_directCntlGnt; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v (revision 40) @@ -0,0 +1,394 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbSerialInterfaceEngine.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module usbSerialInterfaceEngine( + clk, rst, + //readUSBWireData + USBWireDataIn, + USBWireDataInTick, + //writeUSBWireData + USBWireDataOut, + USBWireCtrlOut, + USBWireDataOutTick, + //SIEReceiver + connectState, + //processRxBit + resumeDetected, + //processRxByte + RxCtrlOut, + RxDataOutWEn, + RxDataOut, + //SIETransmitter + SIEPortCtrlIn, + SIEPortDataIn, + SIEPortTxRdy, + SIEPortWEn, + //lineControlUpdate + fullSpeedPolarity, + fullSpeedBitRate, + noActivityTimeOut, + noActivityTimeOutEnable +); + +input clk, rst; +//readUSBWireData +input [1:0] USBWireDataIn; +output USBWireDataInTick; +output noActivityTimeOut; +input noActivityTimeOutEnable; + +//writeUSBWireData +output [1:0] USBWireDataOut; +output USBWireCtrlOut; +output USBWireDataOutTick; + +//SIEReceiver +output [1:0] connectState; +//processRxBit +output resumeDetected; +//processRxByte +output [7:0] RxCtrlOut; +output RxDataOutWEn; +output [7:0] RxDataOut; +//SIETransmitter +input [7:0] SIEPortCtrlIn; +input [7:0] SIEPortDataIn; +output SIEPortTxRdy; +input SIEPortWEn; +//lineControlUpdate +input fullSpeedPolarity; +input fullSpeedBitRate; + +wire clk, rst; +//readUSBWireData +wire [1:0] USBWireDataIn; +wire USBWireDataInTick; +//writeUSBWireData +wire [1:0] USBWireDataOut; +wire USBWireCtrlOut; +wire noActivityTimeOut; +wire USBWireDataOutTick; +//SIEReceiver +wire [1:0] connectState; +//processRxBit +wire resumeDetected; +//processRxByte +wire [7:0] RxCtrlOut; +wire RxDataOutWEn; +wire [7:0] RxDataOut; +//SIETransmitter +wire [7:0] SIEPortCtrlIn; +wire [7:0] SIEPortDataIn; +wire SIEPortTxRdy; +wire SIEPortWEn; +//lineControlUpdate +wire fullSpeedPolarity; +wire fullSpeedBitRate; + +//internal wiring +wire processRxBitsWEn; +wire processRxBitRdy; +wire [1:0] RxWireDataFromWireRx; +wire RxWireDataWEn; +wire TxWireActiveDrive; +wire [1:0] TxBitsFromArbToWire; +wire TxCtrlFromArbToWire; +wire USBWireRdy; +wire USBWireWEn; +wire USBWireReadyFromTxArb; +wire prcTxByteCtrl; +wire [1:0] prcTxByteData; +wire prcTxByteGnt; +wire prcTxByteReq; +wire prcTxByteWEn; +wire SIETxCtrl; +wire [1:0] SIETxData; +wire SIETxGnt; +wire SIETxReq; +wire SIETxWEn; +wire [7:0] TxByteFromSIEToPrcTxByte; +wire [7:0] TxCtrlFromSIEToPrcTxByte; +wire [1:0] JBit; +wire [1:0] KBit; +wire processRxByteWEn; +wire [7:0] RxDataFromPrcRxBitToPrcRxByte; +wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte; +wire processRxByteRdy; +//Rx CRC +wire RxCRC16En; +wire [15:0] RxCRC16Result; +wire RxCRC16UpdateRdy; +wire RxCRC5En; +wire [4:0] RxCRC5Result; +wire RxCRC5_8Bit; +wire [7:0] RxCRCData; +wire RxRstCRC; +wire RxCRC5UpdateRdy; +//Tx CRC +wire TxCRC16En; +wire [15:0] TxCRC16Result; +wire TxCRC16UpdateRdy; +wire TxCRC5En; +wire [4:0] TxCRC5Result; +wire TxCRC5_8Bit; +wire [7:0] TxCRCData; +wire TxRstCRC; +wire TxCRC5UpdateRdy; + +wire processTxByteRdy; +wire processTxByteWEn; + +wire SIEFsRate; +wire TxFSRateFromSIETxToPrcTxByte; +wire prcTxByteFSRate; +wire FSRateFromArbiterToWire; + +wire RxWireActive; + +lineControlUpdate u_lineControlUpdate + (.fullSpeedPolarity(fullSpeedPolarity), + .fullSpeedBitRate(fullSpeedBitRate), + .JBit(JBit), + .KBit(KBit) ); + +SIEReceiver u_SIEReceiver + ( + .RxWireDataIn(RxWireDataFromWireRx), + .RxWireDataWEn(RxWireDataWEn), + .clk(clk), + .connectState(connectState), + .rst(rst) ); + + +processRxBit u_processRxBit + (.JBit(JBit), + .KBit(KBit), + .RxBitsIn(RxWireDataFromWireRx), + .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), + .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), + .clk(clk), + .processRxBitRdy(processRxBitRdy), + .processRxBitsWEn(RxWireDataWEn), + .processRxByteWEn(processRxByteWEn), + .resumeDetected(resumeDetected), + .rst(rst), + .processRxByteRdy(processRxByteRdy), + .RxWireActive(RxWireActive) + ); + +processRxByte u_processRxByte + (.CRC16En(RxCRC16En), + .CRC16Result(RxCRC16Result), + .CRC16UpdateRdy(RxCRC16UpdateRdy), + .CRC5En(RxCRC5En), + .CRC5Result(RxCRC5Result), + .CRC5_8Bit(RxCRC5_8Bit), + .CRC5UpdateRdy(RxCRC5UpdateRdy), + .CRCData(RxCRCData), + .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), + .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), + .RxCtrlOut(RxCtrlOut), + .RxDataOutWEn(RxDataOutWEn), + .RxDataOut(RxDataOut), + .clk(clk), + .processRxDataInWEn(processRxByteWEn), + .rst(rst), + .rstCRC(RxRstCRC), + .processRxByteRdy(processRxByteRdy) ); + + +updateCRC5 RxUpdateCRC5 + (.rstCRC(RxRstCRC), + .CRCResult(RxCRC5Result), + .CRCEn(RxCRC5En), + .CRC5_8BitIn(RxCRC5_8Bit), + .dataIn(RxCRCData), + .ready(RxCRC5UpdateRdy), + .clk(clk), + .rst(rst) ); + +updateCRC16 RxUpdateCRC16 + (.rstCRC(RxRstCRC), + .CRCResult(RxCRC16Result), + .CRCEn(RxCRC16En), + .dataIn(RxCRCData), + .ready(RxCRC16UpdateRdy), + .clk(clk), + .rst(rst) ); + +SIETransmitter u_SIETransmitter + (.CRC16En(TxCRC16En), + .CRC16Result(TxCRC16Result), + .CRC5En(TxCRC5En), + .CRC5Result(TxCRC5Result), + .CRC5_8Bit(TxCRC5_8Bit), + .CRCData(TxCRCData), + .CRC5UpdateRdy(TxCRC5UpdateRdy), + .CRC16UpdateRdy(TxCRC16UpdateRdy), + .JBit(JBit), + .KBit(KBit), + .SIEPortCtrlIn(SIEPortCtrlIn), + .SIEPortDataIn(SIEPortDataIn), + .SIEPortTxRdy(SIEPortTxRdy), + .SIEPortWEn(SIEPortWEn), + .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), + .TxByteOut(TxByteFromSIEToPrcTxByte), + .USBWireCtrl(SIETxCtrl), + .USBWireData(SIETxData), + .USBWireGnt(SIETxGnt), + .USBWireRdy(USBWireReadyFromTxArb), + .USBWireReq(SIETxReq), + .USBWireWEn(SIETxWEn), + .clk(clk), + .processTxByteRdy(processTxByteRdy), + .processTxByteWEn(processTxByteWEn), + .rst(rst), + .rstCRC(TxRstCRC), + .USBWireFullSpeedRate(SIEFsRate), + .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte), + .fullSpeedRateIn(fullSpeedBitRate) + ); + +updateCRC5 TxUpdateCRC5 + (.rstCRC(TxRstCRC), + .CRCResult(TxCRC5Result), + .CRCEn(TxCRC5En), + .CRC5_8BitIn(TxCRC5_8Bit), + .dataIn(TxCRCData), + .ready(TxCRC5UpdateRdy), + .clk(clk), + .rst(rst) ); + +updateCRC16 TxUpdateCRC16 + (.rstCRC(TxRstCRC), + .CRCResult(TxCRC16Result), + .CRCEn(TxCRC16En), + .dataIn(TxCRCData), + .ready(TxCRC16UpdateRdy), + .clk(clk), + .rst(rst) ); + +processTxByte u_processTxByte + (.JBit(JBit), + .KBit(KBit), + .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), + .TxByteIn(TxByteFromSIEToPrcTxByte), + .USBWireCtrl(prcTxByteCtrl), + .USBWireData(prcTxByteData), + .USBWireGnt(prcTxByteGnt), + .USBWireRdy(USBWireReadyFromTxArb), + .USBWireReq(prcTxByteReq), + .USBWireWEn(prcTxByteWEn), + .clk(clk), + .processTxByteRdy(processTxByteRdy), + .processTxByteWEn(processTxByteWEn), + .rst(rst), + .USBWireFullSpeedRate(prcTxByteFSRate), + .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte) + ); + +USBTxWireArbiter u_USBTxWireArbiter + (.SIETxCtrl(SIETxCtrl), + .SIETxData(SIETxData), + .SIETxGnt(SIETxGnt), + .SIETxReq(SIETxReq), + .SIETxWEn(SIETxWEn), + .TxBits(TxBitsFromArbToWire), + .TxCtl(TxCtrlFromArbToWire), + .USBWireRdyIn(USBWireRdy), + .USBWireRdyOut(USBWireReadyFromTxArb), + .USBWireWEn(USBWireWEn), + .clk(clk), + .prcTxByteCtrl(prcTxByteCtrl), + .prcTxByteData(prcTxByteData), + .prcTxByteGnt(prcTxByteGnt), + .prcTxByteReq(prcTxByteReq), + .prcTxByteWEn(prcTxByteWEn), + .rst(rst), + .SIETxFSRate(SIEFsRate), + .prcTxByteFSRate(prcTxByteFSRate), + .TxFSRate(FSRateFromArbiterToWire) + ); + +writeUSBWireData u_writeUSBWireData + (.TxBitsIn(TxBitsFromArbToWire), + .TxBitsOut(USBWireDataOut), + .TxDataOutTick(USBWireDataOutTick), + .TxCtrlIn(TxCtrlFromArbToWire), + .TxCtrlOut(USBWireCtrlOut), + .USBWireRdy(USBWireRdy), + .USBWireWEn(USBWireWEn), + .TxWireActiveDrive(TxWireActiveDrive), + .fullSpeedRate(FSRateFromArbiterToWire), + .clk(clk), + .rst(rst) + ); + + + +readUSBWireData u_readUSBWireData + (.RxBitsIn(USBWireDataIn), + .RxDataInTick(USBWireDataInTick), + .RxBitsOut(RxWireDataFromWireRx), + .SIERxRdyIn(processRxBitRdy), + .SIERxWEn(RxWireDataWEn), + .fullSpeedRate(fullSpeedBitRate), + .TxWireActiveDrive(TxWireActiveDrive), + .clk(clk), + .rst(rst), + .noActivityTimeOut(noActivityTimeOut), + .RxWireActive(RxWireActive), + .noActivityTimeOutEnable(noActivityTimeOutEnable) + ); + + +endmodule + + + + + + + Index: Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v =================================================================== --- Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v (revision 40) @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// slaveRxStatusMonitor.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst); + +input [1:0] connectStateIn; +input resumeDetectedIn; +input clk; +input rst; +output resetEventOut; +output [1:0] connectStateOut; +output resumeIntOut; + +wire [1:0] connectStateIn; +wire resumeDetectedIn; +reg resetEventOut; +reg [1:0] connectStateOut; +reg resumeIntOut; +wire clk; +wire rst; + +reg [1:0]oldConnectState; +reg oldResumeDetected; + +always @(connectStateIn) +begin + connectStateOut <= connectStateIn; +end + + +always @(posedge clk) +begin + if (rst == 1'b1) + begin + oldConnectState <= connectStateIn; + oldResumeDetected <= resumeDetectedIn; + end + else + begin + oldConnectState <= connectStateIn; + oldResumeDetected <= resumeDetectedIn; + if (oldConnectState != connectStateIn) + resetEventOut <= 1'b1; + else + resetEventOut <= 1'b0; + if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0) + resumeIntOut <= 1'b1; + else + resumeIntOut <= 1'b0; + end +end + +endmodule Index: Actel/usbDeviceActelTop/hdl/slaveGetpacket.v =================================================================== --- Actel/usbDeviceActelTop/hdl/slaveGetpacket.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/slaveGetpacket.v (revision 40) @@ -0,0 +1,357 @@ + +// File : ../RTL/slaveController/slaveGetpacket.v +// Generated : 11/10/06 05:37:25 +// From : ../RTL/slaveController/slaveGetpacket.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// slaveGetPacket +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + +module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst); +input [7:0] RXDataIn; +input RXDataValid; +input RXFifoFull; +input [7:0] RXStreamStatusIn; +input SIERxTimeOut; // Single cycle pulse +input clk; +input endPointReady; +input getPacketEn; +input rst; +output ACKRxed; +output CRCError; +output [7:0] RXFifoData; +output RXFifoWEn; +output RXOverflow; +output RXPacketRdy; +output RXTimeOut; +output [3:0] RxPID; +output SIERxTimeOutEn; +output bitStuffError; +output dataSequence; + +reg ACKRxed, next_ACKRxed; +reg CRCError, next_CRCError; +wire [7:0] RXDataIn; +wire RXDataValid; +reg [7:0] RXFifoData, next_RXFifoData; +wire RXFifoFull; +reg RXFifoWEn, next_RXFifoWEn; +reg RXOverflow, next_RXOverflow; +reg RXPacketRdy, next_RXPacketRdy; +wire [7:0] RXStreamStatusIn; +reg RXTimeOut, next_RXTimeOut; +reg [3:0] RxPID, next_RxPID; +wire SIERxTimeOut; +reg SIERxTimeOutEn, next_SIERxTimeOutEn; +reg bitStuffError, next_bitStuffError; +wire clk; +reg dataSequence, next_dataSequence; +wire endPointReady; +wire getPacketEn; +wire rst; + +// diagram signals declarations +reg [7:0]RXByteOld, next_RXByteOld; +reg [7:0]RXByteOldest, next_RXByteOldest; +reg [7:0]RXByte, next_RXByte; +reg [7:0]RXStreamStatus, next_RXStreamStatus; + +// BINARY ENCODED state machine: slvGetPkt +// State codes definitions: +`define PROC_PKT_CHK_PID 5'b00000 +`define PROC_PKT_HS 5'b00001 +`define PROC_PKT_DATA_W_D1 5'b00010 +`define PROC_PKT_DATA_CHK_D1 5'b00011 +`define PROC_PKT_DATA_W_D2 5'b00100 +`define PROC_PKT_DATA_FIN 5'b00101 +`define PROC_PKT_DATA_CHK_D2 5'b00110 +`define PROC_PKT_DATA_W_D3 5'b00111 +`define PROC_PKT_DATA_CHK_D3 5'b01000 +`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001 +`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010 +`define PROC_PKT_DATA_LOOP_W_D 5'b01011 +`define START_GP 5'b01100 +`define WAIT_PKT 5'b01101 +`define CHK_PKT_START 5'b01110 +`define WAIT_EN 5'b01111 +`define PKT_RDY 5'b10000 +`define PROC_PKT_DATA_LOOP_DELAY 5'b10001 +`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010 + +reg [4:0] CurrState_slvGetPkt; +reg [4:0] NextState_slvGetPkt; + + +//-------------------------------------------------------------------- +// Machine: slvGetPkt +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt) +begin : slvGetPkt_NextState + NextState_slvGetPkt <= CurrState_slvGetPkt; + // Set default values for outputs and signals + next_CRCError <= CRCError; + next_bitStuffError <= bitStuffError; + next_RXOverflow <= RXOverflow; + next_RXTimeOut <= RXTimeOut; + next_ACKRxed <= ACKRxed; + next_dataSequence <= dataSequence; + next_SIERxTimeOutEn <= SIERxTimeOutEn; + next_RXByte <= RXByte; + next_RXStreamStatus <= RXStreamStatus; + next_RxPID <= RxPID; + next_RXPacketRdy <= RXPacketRdy; + next_RXByteOldest <= RXByteOldest; + next_RXByteOld <= RXByteOld; + next_RXFifoWEn <= RXFifoWEn; + next_RXFifoData <= RXFifoData; + case (CurrState_slvGetPkt) + `START_GP: + NextState_slvGetPkt <= `WAIT_EN; + `WAIT_PKT: + begin + next_CRCError <= 1'b0; + next_bitStuffError <= 1'b0; + next_RXOverflow <= 1'b0; + next_RXTimeOut <= 1'b0; + next_ACKRxed <= 1'b0; + next_dataSequence <= 1'b0; + next_SIERxTimeOutEn <= 1'b1; + if (RXDataValid == 1'b1) + begin + NextState_slvGetPkt <= `CHK_PKT_START; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + else if (SIERxTimeOut == 1'b1) + begin + NextState_slvGetPkt <= `PKT_RDY; + next_RXTimeOut <= 1'b1; + end + end + `CHK_PKT_START: + if (RXStreamStatus == `RX_PACKET_START) + begin + NextState_slvGetPkt <= `PROC_PKT_CHK_PID; + next_RxPID <= RXByte[3:0]; + end + else + begin + NextState_slvGetPkt <= `PKT_RDY; + next_RXTimeOut <= 1'b1; + end + `WAIT_EN: + begin + next_RXPacketRdy <= 1'b0; + next_SIERxTimeOutEn <= 1'b0; + if (getPacketEn == 1'b1) + NextState_slvGetPkt <= `WAIT_PKT; + end + `PKT_RDY: + begin + next_RXPacketRdy <= 1'b1; + NextState_slvGetPkt <= `WAIT_EN; + end + `PROC_PKT_CHK_PID: + if (RXByte[1:0] == `HANDSHAKE) + NextState_slvGetPkt <= `PROC_PKT_HS; + else if (RXByte[1:0] == `DATA) + NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1; + else + NextState_slvGetPkt <= `PKT_RDY; + `PROC_PKT_HS: + if (RXDataValid == 1'b1) + begin + NextState_slvGetPkt <= `PKT_RDY; + next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT]; + next_ACKRxed <= RXDataIn[`ACK_RXED_BIT]; + end + `PROC_PKT_DATA_W_D1: + if (RXDataValid == 1'b1) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + `PROC_PKT_DATA_CHK_D1: + if (RXStreamStatus == `RX_PACKET_STREAM) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2; + next_RXByteOldest <= RXByte; + end + else + NextState_slvGetPkt <= `PROC_PKT_DATA_FIN; + `PROC_PKT_DATA_W_D2: + if (RXDataValid == 1'b1) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + `PROC_PKT_DATA_FIN: + begin + next_CRCError <= RXByte[`CRC_ERROR_BIT]; + next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT]; + next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT]; + NextState_slvGetPkt <= `PKT_RDY; + end + `PROC_PKT_DATA_CHK_D2: + if (RXStreamStatus == `RX_PACKET_STREAM) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3; + next_RXByteOld <= RXByte; + end + else + NextState_slvGetPkt <= `PROC_PKT_DATA_FIN; + `PROC_PKT_DATA_W_D3: + if (RXDataValid == 1'b1) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3; + next_RXByte <= RXDataIn; + next_RXStreamStatus <= RXStreamStatusIn; + end + `PROC_PKT_DATA_CHK_D3: + if (RXStreamStatus == `RX_PACKET_STREAM) + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO; + else + NextState_slvGetPkt <= `PROC_PKT_DATA_FIN; + `PROC_PKT_DATA_LOOP_CHK_FIFO: + if (endPointReady == 1'b0) + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY; + else if (RXFifoFull == 1'b1) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL; + next_RXOverflow <= 1'b1; + end + else + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D; + next_RXFifoWEn <= 1'b1; + next_RXFifoData <= RXByteOldest; + next_RXByteOldest <= RXByteOld; + next_RXByteOld <= RXByte; + end + `PROC_PKT_DATA_LOOP_FIFO_FULL: + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D; + `PROC_PKT_DATA_LOOP_W_D: + begin + next_RXFifoWEn <= 1'b0; + if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM)) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY; + next_RXByte <= RXDataIn; + end + else if (RXDataValid == 1'b1) + begin + NextState_slvGetPkt <= `PROC_PKT_DATA_FIN; + next_RXByte <= RXDataIn; + end + end + `PROC_PKT_DATA_LOOP_DELAY: + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO; + `PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data + NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D; + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : slvGetPkt_CurrentState + if (rst) + CurrState_slvGetPkt <= `START_GP; + else + CurrState_slvGetPkt <= NextState_slvGetPkt; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : slvGetPkt_RegOutput + if (rst) + begin + RXByteOld <= 8'h00; + RXByteOldest <= 8'h00; + RXByte <= 8'h00; + RXStreamStatus <= 8'h00; + RXPacketRdy <= 1'b0; + RXFifoWEn <= 1'b0; + RXFifoData <= 8'h00; + CRCError <= 1'b0; + bitStuffError <= 1'b0; + RXOverflow <= 1'b0; + RXTimeOut <= 1'b0; + ACKRxed <= 1'b0; + dataSequence <= 1'b0; + SIERxTimeOutEn <= 1'b0; + RxPID <= 4'h0; + end + else + begin + RXByteOld <= next_RXByteOld; + RXByteOldest <= next_RXByteOldest; + RXByte <= next_RXByte; + RXStreamStatus <= next_RXStreamStatus; + RXPacketRdy <= next_RXPacketRdy; + RXFifoWEn <= next_RXFifoWEn; + RXFifoData <= next_RXFifoData; + CRCError <= next_CRCError; + bitStuffError <= next_bitStuffError; + RXOverflow <= next_RXOverflow; + RXTimeOut <= next_RXTimeOut; + ACKRxed <= next_ACKRxed; + dataSequence <= next_dataSequence; + SIERxTimeOutEn <= next_SIERxTimeOutEn; + RxPID <= next_RxPID; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v (revision 40) @@ -0,0 +1,88 @@ + +module usbDeviceActelTop ( + + // + // Global signals + // + clk, + rst_n, + + // eval board features + ledOut, + + // + // USB + // + usbSlaveVP, + usbSlaveVM, + usbSlaveOE_n, + usbDPlusPullup + +); + + // + // Global signals + // + input clk; + input rst_n; + + output [9:0] ledOut; + + // + // USB + // + inout usbSlaveVP; + inout usbSlaveVM; + output usbSlaveOE_n; + output usbDPlusPullup; + +//local wires and regs +reg [1:0] rstReg; +wire rst; + +//generate sync reset +always @(posedge clk) begin + rstReg[1:0] <= {rstReg[0], ~rst_n}; +end +assign rst = rstReg[1]; + + +usbDevice u_usbDevice ( + .clk(clk), + .rst(rst), + .usbSlaveVP_in(usbSlaveVP_in), + .usbSlaveVM_in(usbSlaveVM_in), + .usbSlaveVP_out(usbSlaveVP_out), + .usbSlaveVM_out(usbSlaveVM_out), + .usbSlaveOE_n(usbSlaveOE_n), + .usbDPlusPullup(usbDPlusPullup), + .vBusDetect(1'b1) +); + + +assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM}; +assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz; + + +// comfort lights +reg [9:0] ledCntReg; +reg [21:0] cnt; + +assign ledOut = ledCntReg; + + +always @(posedge clk) begin + if (rst == 1'b1) begin + ledCntReg <= 10'b00_0000_0000; + cnt <= {22{1'b0}}; + end + else begin + cnt <= cnt + 1'b1; + if (cnt == {22{1'b0}}) + ledCntReg <= ledCntReg + 1'b1; + end +end + +endmodule + + Index: Actel/usbDeviceActelTop/hdl/readUSBWireData.v =================================================================== --- Actel/usbDeviceActelTop/hdl/readUSBWireData.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/readUSBWireData.v (revision 40) @@ -0,0 +1,274 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// readUSBWireData.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// This module reads data from the differential USB data lines +//// and writes into a 4 entry FIFO. The data is read from +//// the fifo and output from the module when the higher level +//// state machine is ready to receive the data. +//// This module must recover the clock phase from the incoming +//// USB data. 'sampleCnt' is reset to zero whenever a RX data +//// edge is detected. Note that due to metastability the data +//// at the edge may not be registered correctly, but this does +//// not matter. All that matters is that an edge was detected. The +//// data will be accurately sampled in the middle of the USB bit +//// period without metastability issues. +//// After the edge detect, 'sampleCnt' is incremented at every clock +//// tick, and when it indicates the middle of a USB bit period +//// the RX data is sampled and written to the input buffer. +//// Single clock tick adjustments to 'sampleCnt' can be made at +//// every RX data edge detect without double sampling the incoming +//// data. However, the first RX data bit in a packet may cause +//// 'sampleCnt' to be adjusted by a value greater than a single +//// clock tick, and this can result in double sampling of the +//// first data bit a RX packet. This +//// double sampled data must be rejected by the higher level module. +//// This is achieved by +//// qualifying the outgoing data with 'RxWireActive'. Thus +//// the first data bit in a RX packet may be double sampled +//// as the clock recovery mechanism synchronizes to 'RxBitsIn' +//// but the double sampled data will be rejected by the higher +//// level module. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + +module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable); +input [1:0] RxBitsIn; +output RxDataInTick; +input SIERxRdyIn; +input clk; +input fullSpeedRate; +input rst; +input TxWireActiveDrive; +output [1:0] RxBitsOut; +output SIERxWEn; +output noActivityTimeOut; +output RxWireActive; +input noActivityTimeOutEnable; + +wire [1:0] RxBitsIn; +reg RxDataInTick; +wire SIERxRdyIn; +wire clk; +wire fullSpeedRate; +wire rst; +reg [1:0] RxBitsOut; +reg SIERxWEn; +reg noActivityTimeOut; +reg RxWireActive; +wire noActivityTimeOutEnable; + +// local registers +reg [2:0]buffer0; +reg [2:0]buffer1; +reg [2:0]buffer2; +reg [2:0]buffer3; +reg [2:0]bufferCnt; +reg [1:0]bufferInIndex; +reg [1:0]bufferOutIndex; +reg decBufferCnt; +reg [4:0]sampleCnt; +reg incBufferCnt; +reg [1:0]oldRxBitsIn; +reg [1:0] RxBitsInReg; +reg [15:0] timeOutCnt; +reg [7:0] rxActiveCnt; +reg RxWireEdgeDetect; +reg RxWireActiveReg; +reg RxWireActiveReg2; +reg [1:0] RxBitsInSyncReg1; +reg [1:0] RxBitsInSyncReg2; + +// buffer output state machine state codes: +`define WAIT_BUFFER_NOT_EMPTY 2'b00 +`define WAIT_SIE_RX_READY 2'b01 +`define SIE_RX_WRITE 2'b10 + +// re-synchronize incoming bits +always @(posedge clk) begin + RxBitsInSyncReg1 <= RxBitsIn; + RxBitsInSyncReg2 <= RxBitsInSyncReg1; +end + +reg [1:0] bufferOutStMachCurrState; + + +always @(posedge clk) begin + if (rst == 1'b1) + begin + bufferCnt <= 3'b000; + end + else begin + if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0) + bufferCnt <= bufferCnt + 1'b1; + else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1) + bufferCnt <= bufferCnt - 1'b1; + end +end + + + +//Perform line rate clock recovery +//Recover the wire data, and store data to buffer +always @(posedge clk) begin + if (rst == 1'b1) + begin + sampleCnt <= 5'b00000; + incBufferCnt <= 1'b0; + bufferInIndex <= 2'b00; + buffer0 <= 3'b000; + buffer1 <= 3'b000; + buffer2 <= 3'b000; + buffer3 <= 3'b000; + RxDataInTick <= 1'b0; + RxWireEdgeDetect <= 1'b0; + RxWireActiveReg <= 1'b0; + RxWireActiveReg2 <= 1'b0; + end + else begin + RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset + RxBitsInReg <= RxBitsInSyncReg2; + oldRxBitsIn <= RxBitsInReg; + incBufferCnt <= 1'b0; //default value + if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then + sampleCnt <= 5'b00000; + RxWireEdgeDetect <= 1'b1; // flag receive activity + RxWireActiveReg <= 1'b1; + rxActiveCnt <= 8'h00; + end + else begin + sampleCnt <= sampleCnt + 1'b1; + RxWireEdgeDetect <= 1'b0; + rxActiveCnt <= rxActiveCnt + 1'b1; + //clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods + if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE) + || (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) ) + RxWireActiveReg <= 1'b0; + end + if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) ) + begin + RxDataInTick <= !RxDataInTick; + if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active + begin + incBufferCnt <= 1'b1; + bufferInIndex <= bufferInIndex + 1'b1; + case (bufferInIndex) + 2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn}; + 2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn}; + 2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn}; + 2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn}; + endcase + end + end + end +end + + + +//read from buffer, and output to SIEReceiver +always @(posedge clk) begin + if (rst == 1'b1) + begin + decBufferCnt <= 1'b0; + bufferOutIndex <= 2'b00; + RxBitsOut <= 2'b00; + SIERxWEn <= 1'b0; + bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY; + end + else begin + case (bufferOutStMachCurrState) + `WAIT_BUFFER_NOT_EMPTY: + begin + if (bufferCnt != 3'b000) + bufferOutStMachCurrState <= `WAIT_SIE_RX_READY; + end + `WAIT_SIE_RX_READY: + begin + if (SIERxRdyIn == 1'b1) + begin + SIERxWEn <= 1'b1; + bufferOutStMachCurrState <= `SIE_RX_WRITE; + decBufferCnt <= 1'b1; + bufferOutIndex <= bufferOutIndex + 1'b1; + case (bufferOutIndex) + 2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end + 2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end + 2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end + 2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end + endcase + end + end + `SIE_RX_WRITE: + begin + SIERxWEn <= 1'b0; + decBufferCnt <= 1'b0; + bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY; + end + endcase + end +end + +//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods +//'noActivityTimeOut' pulse can only be generated when the host or slave getPacket +//process enables via 'noActivityTimeOutEnable' signal +//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if +//there has been a response time out. +always @(posedge clk) begin + if (rst) begin + timeOutCnt <= 16'h0000; + noActivityTimeOut <= 1'b0; + end + else begin + if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0) + timeOutCnt <= 16'h0000; + else + timeOutCnt <= timeOutCnt + 1'b1; + if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE) + || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) ) + noActivityTimeOut <= 1'b1; + else + noActivityTimeOut <= 1'b0; + end +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbROM.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbROM.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbROM.v (revision 40) @@ -0,0 +1,254 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbROM.v //// +//// //// +//// This file is part of the usbHostSlave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// if you modify this file, be sure to modify usbDevice_define.v +//// Using RAM rather than logic resources might be a more efficient implememtation +//// but this has the advantage of working with FPGAs that do not provide a +//// mechanism for initialising RAM, eg Actel IGLOO +//// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "usbDevice_define.v" + + +module usbROM ( + clk, + addr, + data +); +input clk; +input [7:0] addr; +output [7:0] data; +reg [7:0] data; + +always @(posedge clk) begin + case (addr) +// ==================================== +// ===== DEVICE Descriptor ===== +// ==================================== + + 8'h00: data <= 8'h12; //BYTE bLength + 8'h01: data <= 8'h01; //BYTE bDescriptorType + 8'h02: data <= 8'h10; //WORD (Lo) bcdUSB version supported + 8'h03: data <= 8'h01; //WORD (Hi) bcdUSB version supported + 8'h04: data <= 8'h00; //BYTE bDeviceClass + 8'h05: data <= 8'h00; //BYTE bDeviceSubClass + 8'h06: data <= 8'h00; //BYTE bDeviceProtocol + 8'h07: data <= `MAX_RESP_SIZE; //BYTE bMaxPacketSize + 8'h08: data <= 8'hC7; //WORD (Lo) idVendor + 8'h09: data <= 8'h05; //WORD (Hi) idVendor + 8'h0a: data <= 8'h13; //WORD (Lo) idProduct; For Philips Hub mouse + 8'h0b: data <= 8'h01; //WORD (Hi) idProduct; For Philips Hub mouse + 8'h0c: data <= 8'h01; //WORD (Lo) bcdDevice + 8'h0d: data <= 8'h00; //WORD (Hi) bcdDevice + 8'h0e: data <= 8'h01; //BYTE iManufacturer + 8'h0f: data <= 8'h02; //BYTE iProduct + 8'h10: data <= 8'h03; //BYTE iSerialNumber + 8'h11: data <= 8'h01; //BYTE bNumConfigurations + + +// ==================================== +// ===== Configuration Descriptor ===== +// ==================================== + 8'h12: data <= 8'h09; //BYTE bLength (Configuration descriptor) + 8'h13: data <= 8'h02; //BYTE bDescriptorType //Assigned by USB + 8'h14: data <= 8'd34; //WORD (Lo) wTotalLength + 8'h15: data <= 8'h00; //WORD (Hi) wTotalLength + 8'h16: data <= 8'h01; //BYTE bNumInterfaces + 8'h17: data <= 8'h01; //BYTE bConfigurationValue + 8'h18: data <= 8'h00; //BYTE iConfiguration + 8'h19: data <= 8'ha0; //BYTE bmAttributes, Bus powered and remote wakeup + 8'h1a: data <= 8'h32; //BYTE MaxPower, 100mA + +// ==================================== +// ===== Interface Descriptor ===== +// ==================================== + 8'h1b: data <= 8'h09; //BYTE bLength (Interface descriptor) + 8'h1c: data <= 8'h04; //BYTE bDescriptionType; assigned by USB + 8'h1d: data <= 8'h00; //BYTE bInterfaceNumber + 8'h1e: data <= 8'h00; //BYTE bAlternateSetting + 8'h1f: data <= 8'h01; //BYTE bNumEndpoints; uses 1 endpoints + 8'h20: data <= 8'h03; //BYTE bInterfaceClass; HID Class - 0x03 + 8'h21: data <= 8'h01; //BYTE bInterfaceSubClass + 8'h22: data <= 8'h02; //BYTE bInterfaceProtocol + 8'h23: data <= 8'h00; //BYTE iInterface + +// ==================================== +// ===== HID Descriptor ===== +// ==================================== + 8'h24: data <= 8'h09; //BYTE bLength (HID Descriptor) + 8'h25: data <= 8'h21; //BYTE bDescriptorType + 8'h26: data <= 8'h10; //WORD (Lo) bcdHID + 8'h27: data <= 8'h01; //WORD (Hi) bcdHID + 8'h28: data <= 8'h00; //BYTE bCountryCode + 8'h29: data <= 8'h01; //BYTE bNumDescriptors + 8'h2a: data <= 8'h22; //BYTE bReportDescriptorType + 8'h2b: data <= 8'h32; //WORD (Lo) wItemLength + 8'h2c: data <= 8'h00; //WORD (Hi) wItemLength + +// ==================================== +// ===== Endpoint 1 Descriptor ===== +// ==================================== + 8'h2d: data <= 8'h07; //BYTE bLength (Endpoint Descriptor) + 8'h2e: data <= 8'h05; //BYTE bDescriptorType; assigned by USB + 8'h2f: data <= 8'h81; //BYTE bEndpointAddress; IN endpoint; endpoint 1 + 8'h30: data <= 8'h03; //BYTE bmAttributes; Interrupt endpoint + 8'h31: data <= 8'h10; //WORD (Lo) wMaxPacketSize + 8'h32: data <= 8'h00; //WORD (Hi) wMaxPacketSize + 8'h33: data <= 8'hFF; //BYTE bInterval + + +// ==================================== +// ===== Report Descriptor ===== +// ==================================== + + 8'h3a: data <= 8'h05; 8'h3b: data <= 8'h01; // USAGE_PAGE (Generic Desktop) + 8'h3c: data <= 8'h09; 8'h3d: data <= 8'h02; // USAGE (Mouse) + 8'h3e: data <= 8'ha1; 8'h3f: data <= 8'h01; // COLLECTION (Application) + 8'h40: data <= 8'h09; 8'h41: data <= 8'h01; // USAGE (Pointer) + 8'h42: data <= 8'ha1; 8'h43: data <= 8'h00; // COLLECTION (Physical) + 8'h44: data <= 8'h05; 8'h45: data <= 8'h09; // USAGE_PAGE (Button) + 8'h46: data <= 8'h19; 8'h47: data <= 8'h01; // USAGE_MINIMUM (Button 1) + 8'h48: data <= 8'h29; 8'h49: data <= 8'h03; // USAGE_MAXIMUM (Button 3) + 8'h4a: data <= 8'h15; 8'h4b: data <= 8'h00; // LOGICAL_MINIMUM (0) + 8'h4c: data <= 8'h25; 8'h4d: data <= 8'h01; // LOGICAL_MAXIMUM (1) + 8'h4e: data <= 8'h95; 8'h4f: data <= 8'h03; // REPORT_COUNT (3) + 8'h50: data <= 8'h75; 8'h51: data <= 8'h01; // REPORT_SIZE (1) + 8'h52: data <= 8'h81; 8'h53: data <= 8'h02; // INPUT (Data,Var,Abs) + 8'h54: data <= 8'h95; 8'h55: data <= 8'h01; // REPORT_COUNT (1) + 8'h56: data <= 8'h75; 8'h57: data <= 8'h05; // REPORT_SIZE (5) + 8'h58: data <= 8'h81; 8'h59: data <= 8'h01; // INPUT (Cnst,Var,Rel) + 8'h5a: data <= 8'h05; 8'h5b: data <= 8'h01; // USAGE_PAGE (Generic Desktop) + 8'h5c: data <= 8'h09; 8'h5d: data <= 8'h30; // USAGE (X) + 8'h5e: data <= 8'h09; 8'h5f: data <= 8'h31; // USAGE (Y) + 8'h60: data <= 8'h15; 8'h61: data <= 8'h81; // LOGICAL_MINIMUM (-127) + 8'h62: data <= 8'h25; 8'h63: data <= 8'h7f; // LOGICAL_MAXIMUM (127) + 8'h64: data <= 8'h75; 8'h65: data <= 8'h08; // REPORT_SIZE (8) + 8'h66: data <= 8'h95; 8'h67: data <= 8'h02; // REPORT_COUNT (2) + 8'h68: data <= 8'h81; 8'h69: data <= 8'h06; // INPUT (Data,Var,Rel) + 8'h6a: data <= 8'hc0; //END_COLLECTION + 8'h6b: data <= 8'hc0; // END_COLLECTION + +// ZERO_ZERO + 8'h6c: data <= 8'h00; + 8'h6d: data <= 8'h00; +// ONE_ZERO + 8'h6e: data <= 8'h01; + 8'h6f: data <= 8'h00; +// Vendor data + 8'h70: data <= 8'h00; + 8'h71: data <= 8'h00; + +// ============================================= +// ===== Language ID Descriptor(String0) ===== +// ============================================= + 8'h80: data <= 8'h04; // bLength + 8'h81: data <= 8'h03; // bDescriptorType = String Desc + 8'h82: data <= 8'h09; // wLangID (Lo) (Lang ID for English = 0x0409) + 8'h83: data <= 8'h04; // wLangID (Hi) (Lang ID for English = 0x0409) + +// ==================================== +// ===== string 1 Descriptor ===== +// ==================================== + 8'h90: data <= 8'd26; // bLength + 8'h91: data <= 8'h03; // bDescriptorType = String Desc + // Noting that text is always unicode, hence the 'padding' + 8'h92: data <= "B"; 8'h93: data <= 8'h00; + 8'h94: data <= "a"; 8'h95: data <= 8'h00; + 8'h96: data <= "s"; 8'h97: data <= 8'h00; + 8'h98: data <= "e"; 8'h99: data <= 8'h00; + 8'h9a: data <= "2"; 8'h9b: data <= 8'h00; + 8'h9c: data <= "D"; 8'h9d: data <= 8'h00; + 8'h9e: data <= "e"; 8'h9f: data <= 8'h00; + 8'ha0: data <= "s"; 8'ha1: data <= 8'h00; + 8'ha2: data <= "i"; 8'ha3: data <= 8'h00; + 8'ha4: data <= "g"; 8'ha5: data <= 8'h00; + 8'ha6: data <= "n"; 8'ha7: data <= 8'h00; + 8'ha8: data <= "s"; 8'ha9: data <= 8'h00; + + + +// ==================================== +// ===== string 2 Descriptor ===== +// ==================================== + 8'hb0: data <= 8'd20; // bLength + 8'hb1: data <= 8'h03; // bDescriptorType = String Desc + // Noting that text is always unicode, hence the 'padding' + 8'hb2: data <= "B"; 8'hb3: data <= 8'h00; + 8'hb4: data <= "2"; 8'hb5: data <= 8'h00; + 8'hb6: data <= "D"; 8'hb7: data <= 8'h00; + 8'hb8: data <= " "; 8'hb9: data <= 8'h00; + 8'hba: data <= "M"; 8'hbb: data <= 8'h00; + 8'hbc: data <= "o"; 8'hbd: data <= 8'h00; + 8'hbe: data <= "u"; 8'hbf: data <= 8'h00; + 8'hc0: data <= "s"; 8'hc1: data <= 8'h00; + 8'hc2: data <= "e"; 8'hc3: data <= 8'h00; + +// ==================================== +// ===== string 3 Descriptor ===== +// ==================================== + 8'hd0: data <= 8'd30; // bLength + 8'hd1: data <= 8'h03; // bDescriptorType = String Desc + // Noting that text is always unicode, hence the 'padding' + 8'hd2: data <= "L"; 8'hd3: data <= 8'h00; + 8'hd4: data <= "i"; 8'hd5: data <= 8'h00; + 8'hd6: data <= "m"; 8'hd7: data <= 8'h00; + 8'hd8: data <= "i"; 8'hd9: data <= 8'h00; + 8'hda: data <= "t"; 8'hdb: data <= 8'h00; + 8'hdc: data <= "e"; 8'hdd: data <= 8'h00; + 8'hde: data <= "d"; 8'hdf: data <= 8'h00; + 8'he0: data <= "E"; 8'he1: data <= 8'h00; + 8'he2: data <= "d"; 8'he3: data <= 8'h00; + 8'he4: data <= "i"; 8'he5: data <= 8'h00; + 8'he6: data <= "t"; 8'he7: data <= 8'h00; + 8'he8: data <= "i"; 8'he9: data <= 8'h00; + 8'hea: data <= "o"; 8'heb: data <= 8'h00; + 8'hec: data <= "n"; 8'hed: data <= 8'h00; + + + + default: data <= 8'h00; + endcase +end + +endmodule + + + Index: Actel/usbDeviceActelTop/hdl/slaveSendpacket.v =================================================================== --- Actel/usbDeviceActelTop/hdl/slaveSendpacket.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/slaveSendpacket.v (revision 40) @@ -0,0 +1,252 @@ + +// File : ../RTL/slaveController/slaveSendpacket.v +// Generated : 11/10/06 05:37:26 +// From : ../RTL/slaveController/slaveSendpacket.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// slaveSendPacket +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + +module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn); +input [3:0] PID; +input SCTxPortGnt; +input SCTxPortRdy; +input clk; +input [7:0] fifoData; +input fifoEmpty; +input rst; +input sendPacketWEn; +output [7:0] SCTxPortCntl; +output [7:0] SCTxPortData; +output SCTxPortReq; +output SCTxPortWEn; +output fifoReadEn; +output sendPacketRdy; + +wire [3:0] PID; +reg [7:0] SCTxPortCntl, next_SCTxPortCntl; +reg [7:0] SCTxPortData, next_SCTxPortData; +wire SCTxPortGnt; +wire SCTxPortRdy; +reg SCTxPortReq, next_SCTxPortReq; +reg SCTxPortWEn, next_SCTxPortWEn; +wire clk; +wire [7:0] fifoData; +wire fifoEmpty; +reg fifoReadEn, next_fifoReadEn; +wire rst; +reg sendPacketRdy, next_sendPacketRdy; +wire sendPacketWEn; + +// diagram signals declarations +reg [7:0]PIDNotPID; + +// BINARY ENCODED state machine: slvSndPkt +// State codes definitions: +`define START_SP1 4'b0000 +`define SP_WAIT_ENABLE 4'b0001 +`define SP1_WAIT_GNT 4'b0010 +`define SP_SEND_PID_WAIT_RDY 4'b0011 +`define SP_SEND_PID_FIN 4'b0100 +`define FIN_SP1 4'b0101 +`define SP_D0_D1_READ_FIFO 4'b0110 +`define SP_D0_D1_WAIT_READ_FIFO 4'b0111 +`define SP_D0_D1_FIFO_EMPTY 4'b1000 +`define SP_D0_D1_FIN 4'b1001 +`define SP_D0_D1_TERM_BYTE 4'b1010 +`define SP_NOT_DATA 4'b1011 +`define SP_D0_D1_CLR_WEN 4'b1100 +`define SP_D0_D1_CLR_REN 4'b1101 + +reg [3:0] CurrState_slvSndPkt; +reg [3:0] NextState_slvSndPkt; + +// Diagram actions (continuous assignments allowed only: assign ...) + +always @(PID) +begin + PIDNotPID <= { (PID ^ 4'hf), PID }; +end + +//-------------------------------------------------------------------- +// Machine: slvSndPkt +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt) +begin : slvSndPkt_NextState + NextState_slvSndPkt <= CurrState_slvSndPkt; + // Set default values for outputs and signals + next_sendPacketRdy <= sendPacketRdy; + next_SCTxPortReq <= SCTxPortReq; + next_SCTxPortWEn <= SCTxPortWEn; + next_SCTxPortData <= SCTxPortData; + next_SCTxPortCntl <= SCTxPortCntl; + next_fifoReadEn <= fifoReadEn; + case (CurrState_slvSndPkt) + `START_SP1: + NextState_slvSndPkt <= `SP_WAIT_ENABLE; + `SP_WAIT_ENABLE: + if (sendPacketWEn == 1'b1) + begin + NextState_slvSndPkt <= `SP1_WAIT_GNT; + next_sendPacketRdy <= 1'b0; + next_SCTxPortReq <= 1'b1; + end + `SP1_WAIT_GNT: + if (SCTxPortGnt == 1'b1) + NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY; + `FIN_SP1: + begin + NextState_slvSndPkt <= `SP_WAIT_ENABLE; + next_sendPacketRdy <= 1'b1; + next_SCTxPortReq <= 1'b0; + end + `SP_NOT_DATA: + NextState_slvSndPkt <= `FIN_SP1; + `SP_SEND_PID_WAIT_RDY: + if (SCTxPortRdy == 1'b1) + begin + NextState_slvSndPkt <= `SP_SEND_PID_FIN; + next_SCTxPortWEn <= 1'b1; + next_SCTxPortData <= PIDNotPID; + next_SCTxPortCntl <= `TX_PACKET_START; + end + `SP_SEND_PID_FIN: + begin + next_SCTxPortWEn <= 1'b0; + if (PID == `DATA0 || PID == `DATA1) + NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY; + else + NextState_slvSndPkt <= `SP_NOT_DATA; + end + `SP_D0_D1_READ_FIFO: + begin + next_SCTxPortWEn <= 1'b1; + next_SCTxPortData <= fifoData; + next_SCTxPortCntl <= `TX_PACKET_STREAM; + NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN; + end + `SP_D0_D1_WAIT_READ_FIFO: + if (SCTxPortRdy == 1'b1) + begin + NextState_slvSndPkt <= `SP_D0_D1_CLR_REN; + next_fifoReadEn <= 1'b1; + end + `SP_D0_D1_FIFO_EMPTY: + if (fifoEmpty == 1'b0) + NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO; + else + NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE; + `SP_D0_D1_FIN: + begin + next_SCTxPortWEn <= 1'b0; + NextState_slvSndPkt <= `FIN_SP1; + end + `SP_D0_D1_TERM_BYTE: + if (SCTxPortRdy == 1'b1) + begin + NextState_slvSndPkt <= `SP_D0_D1_FIN; + //Last byte is not valid data, + //but the 'TX_PACKET_STOP' flag is required + //by the SIE state machine to detect end of data packet + next_SCTxPortWEn <= 1'b1; + next_SCTxPortData <= 8'h00; + next_SCTxPortCntl <= `TX_PACKET_STOP; + end + `SP_D0_D1_CLR_WEN: + begin + next_SCTxPortWEn <= 1'b0; + NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY; + end + `SP_D0_D1_CLR_REN: + begin + next_fifoReadEn <= 1'b0; + NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : slvSndPkt_CurrentState + if (rst) + CurrState_slvSndPkt <= `START_SP1; + else + CurrState_slvSndPkt <= NextState_slvSndPkt; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : slvSndPkt_RegOutput + if (rst) + begin + sendPacketRdy <= 1'b1; + SCTxPortReq <= 1'b0; + SCTxPortWEn <= 1'b0; + SCTxPortData <= 8'h00; + SCTxPortCntl <= 8'h00; + fifoReadEn <= 1'b0; + end + else + begin + sendPacketRdy <= next_sendPacketRdy; + SCTxPortReq <= next_SCTxPortReq; + SCTxPortWEn <= next_SCTxPortWEn; + SCTxPortData <= next_SCTxPortData; + SCTxPortCntl <= next_SCTxPortCntl; + fifoReadEn <= next_fifoReadEn; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/fifoMux.v =================================================================== --- Actel/usbDeviceActelTop/hdl/fifoMux.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/fifoMux.v (revision 40) @@ -0,0 +1,212 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// fifoMux.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module fifoMux ( + currEndP, + //TxFifo + TxFifoREn, + TxFifoEP0REn, + TxFifoEP1REn, + TxFifoEP2REn, + TxFifoEP3REn, + TxFifoData, + TxFifoEP0Data, + TxFifoEP1Data, + TxFifoEP2Data, + TxFifoEP3Data, + TxFifoEmpty, + TxFifoEP0Empty, + TxFifoEP1Empty, + TxFifoEP2Empty, + TxFifoEP3Empty, + //RxFifo + RxFifoWEn, + RxFifoEP0WEn, + RxFifoEP1WEn, + RxFifoEP2WEn, + RxFifoEP3WEn, + RxFifoFull, + RxFifoEP0Full, + RxFifoEP1Full, + RxFifoEP2Full, + RxFifoEP3Full + ); + + +input [3:0] currEndP; +//TxFifo +input TxFifoREn; +output TxFifoEP0REn; +output TxFifoEP1REn; +output TxFifoEP2REn; +output TxFifoEP3REn; +output [7:0] TxFifoData; +input [7:0] TxFifoEP0Data; +input [7:0] TxFifoEP1Data; +input [7:0] TxFifoEP2Data; +input [7:0] TxFifoEP3Data; +output TxFifoEmpty; +input TxFifoEP0Empty; +input TxFifoEP1Empty; +input TxFifoEP2Empty; +input TxFifoEP3Empty; + //RxFifo +input RxFifoWEn; +output RxFifoEP0WEn; +output RxFifoEP1WEn; +output RxFifoEP2WEn; +output RxFifoEP3WEn; +output RxFifoFull; +input RxFifoEP0Full; +input RxFifoEP1Full; +input RxFifoEP2Full; +input RxFifoEP3Full; + +wire [3:0] currEndP; +//TxFifo +wire TxFifoREn; +reg TxFifoEP0REn; +reg TxFifoEP1REn; +reg TxFifoEP2REn; +reg TxFifoEP3REn; +reg [7:0] TxFifoData; +wire [7:0] TxFifoEP0Data; +wire [7:0] TxFifoEP1Data; +wire [7:0] TxFifoEP2Data; +wire [7:0] TxFifoEP3Data; +reg TxFifoEmpty; +wire TxFifoEP0Empty; +wire TxFifoEP1Empty; +wire TxFifoEP2Empty; +wire TxFifoEP3Empty; + //RxFifo +wire RxFifoWEn; +reg RxFifoEP0WEn; +reg RxFifoEP1WEn; +reg RxFifoEP2WEn; +reg RxFifoEP3WEn; +reg RxFifoFull; +wire RxFifoEP0Full; +wire RxFifoEP1Full; +wire RxFifoEP2Full; +wire RxFifoEP3Full; + +//internal wires and regs + +//combinatorially mux TX and RX fifos for end points 0 through 3 +always @(currEndP or + TxFifoREn or + RxFifoWEn or + TxFifoEP0Data or + TxFifoEP1Data or + TxFifoEP2Data or + TxFifoEP3Data or + TxFifoEP0Empty or + TxFifoEP1Empty or + TxFifoEP2Empty or + TxFifoEP3Empty or + RxFifoEP0Full or + RxFifoEP1Full or + RxFifoEP2Full or + RxFifoEP3Full) +begin + case (currEndP[1:0]) + 2'b00: begin + TxFifoEP0REn <= TxFifoREn; + TxFifoEP1REn <= 1'b0; + TxFifoEP2REn <= 1'b0; + TxFifoEP3REn <= 1'b0; + TxFifoData <= TxFifoEP0Data; + TxFifoEmpty <= TxFifoEP0Empty; + RxFifoEP0WEn <= RxFifoWEn; + RxFifoEP1WEn <= 1'b0; + RxFifoEP2WEn <= 1'b0; + RxFifoEP3WEn <= 1'b0; + RxFifoFull <= RxFifoEP0Full; + end + 2'b01: begin + TxFifoEP0REn <= 1'b0; + TxFifoEP1REn <= TxFifoREn; + TxFifoEP2REn <= 1'b0; + TxFifoEP3REn <= 1'b0; + TxFifoData <= TxFifoEP1Data; + TxFifoEmpty <= TxFifoEP1Empty; + RxFifoEP0WEn <= 1'b0; + RxFifoEP1WEn <= RxFifoWEn; + RxFifoEP2WEn <= 1'b0; + RxFifoEP3WEn <= 1'b0; + RxFifoFull <= RxFifoEP1Full; + end + 2'b10: begin + TxFifoEP0REn <= 1'b0; + TxFifoEP1REn <= 1'b0; + TxFifoEP2REn <= TxFifoREn; + TxFifoEP3REn <= 1'b0; + TxFifoData <= TxFifoEP2Data; + TxFifoEmpty <= TxFifoEP2Empty; + RxFifoEP0WEn <= 1'b0; + RxFifoEP1WEn <= 1'b0; + RxFifoEP2WEn <= RxFifoWEn; + RxFifoEP3WEn <= 1'b0; + RxFifoFull <= RxFifoEP2Full; + end + 2'b11: begin + TxFifoEP0REn <= 1'b0; + TxFifoEP1REn <= 1'b0; + TxFifoEP2REn <= 1'b0; + TxFifoEP3REn <= TxFifoREn; + TxFifoData <= TxFifoEP3Data; + TxFifoEmpty <= TxFifoEP3Empty; + RxFifoEP0WEn <= 1'b0; + RxFifoEP1WEn <= 1'b0; + RxFifoEP2WEn <= 1'b0; + RxFifoEP3WEn <= RxFifoWEn; + RxFifoFull <= RxFifoEP3Full; + end + endcase +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/SIETransmitter.v =================================================================== --- Actel/usbDeviceActelTop/hdl/SIETransmitter.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/SIETransmitter.v (revision 40) @@ -0,0 +1,714 @@ + +// File : ../RTL/serialInterfaceEngine/SIETransmitter.v +// Generated : 10/15/06 20:31:22 +// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// SIETransmitter +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" +`include "usbConstants_h.v" + + +module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC); +input [15:0] CRC16Result; +input CRC16UpdateRdy; +input [4:0] CRC5Result; +input CRC5UpdateRdy; +input [1:0] JBit; +input [1:0] KBit; +input [7:0] SIEPortCtrlIn; +input [7:0] SIEPortDataIn; +input SIEPortWEn; +input USBWireGnt; +input USBWireRdy; +input clk; +input fullSpeedRateIn; +input processTxByteRdy; +input rst; +output CRC16En; +output CRC5En; +output CRC5_8Bit; +output [7:0] CRCData; +output SIEPortTxRdy; +output [7:0] TxByteOutCtrl; +output TxByteOutFullSpeedRate; +output [7:0] TxByteOut; +output USBWireCtrl; +output [1:0] USBWireData; +output USBWireFullSpeedRate; +output USBWireReq; +output USBWireWEn; +output processTxByteWEn; +output rstCRC; + +reg CRC16En, next_CRC16En; +wire [15:0] CRC16Result; +wire CRC16UpdateRdy; +reg CRC5En, next_CRC5En; +wire [4:0] CRC5Result; +wire CRC5UpdateRdy; +reg CRC5_8Bit, next_CRC5_8Bit; +reg [7:0] CRCData, next_CRCData; +wire [1:0] JBit; +wire [1:0] KBit; +wire [7:0] SIEPortCtrlIn; +wire [7:0] SIEPortDataIn; +reg SIEPortTxRdy, next_SIEPortTxRdy; +wire SIEPortWEn; +reg [7:0] TxByteOutCtrl, next_TxByteOutCtrl; +reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate; +reg [7:0] TxByteOut, next_TxByteOut; +reg USBWireCtrl, next_USBWireCtrl; +reg [1:0] USBWireData, next_USBWireData; +reg USBWireFullSpeedRate, next_USBWireFullSpeedRate; +wire USBWireGnt; +wire USBWireRdy; +reg USBWireReq, next_USBWireReq; +reg USBWireWEn, next_USBWireWEn; +wire clk; +wire fullSpeedRateIn; +wire processTxByteRdy; +reg processTxByteWEn, next_processTxByteWEn; +wire rst; +reg rstCRC, next_rstCRC; + +// diagram signals declarations +reg [7:0]SIEPortCtrl, next_SIEPortCtrl; +reg [7:0]SIEPortData, next_SIEPortData; +reg [2:0]i, next_i; +reg [15:0]resumeCnt, next_resumeCnt; + +// BINARY ENCODED state machine: SIETx +// State codes definitions: +`define DIR_CTL_CHK_FIN 6'b000000 +`define RES_ST_CHK_FIN 6'b000001 +`define PKT_ST_CHK_PID 6'b000010 +`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011 +`define IDLE 6'b000100 +`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101 +`define PKT_ST_DATA_PID_PKT_SENT 6'b000110 +`define PKT_ST_HS_PKT_SENT 6'b000111 +`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000 +`define PKT_ST_TKN_PID_PKT_SENT 6'b001001 +`define PKT_ST_SPCL_PKT_SENT 6'b001010 +`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011 +`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100 +`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101 +`define RES_ST_SND_J_1 6'b001110 +`define RES_ST_SND_J_2 6'b001111 +`define RES_ST_SND_SE0_1 6'b010000 +`define RES_ST_SND_SE0_2 6'b010001 +`define START_SIETX 6'b010010 +`define STX_CHK_ST 6'b010011 +`define STX_WAIT_BYTE 6'b010100 +`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101 +`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110 +`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111 +`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000 +`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001 +`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010 +`define DIR_CTL_WAIT_GNT 6'b011011 +`define RES_ST_WAIT_GNT 6'b011100 +`define PKT_ST_HS_WAIT_RDY 6'b011101 +`define DIR_CTL_WAIT_RDY 6'b011110 +`define PKT_ST_SPCL_WAIT_RDY 6'b011111 +`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000 +`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001 +`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010 +`define RES_ST_WAIT_RDY 6'b100011 +`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100 +`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101 +`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110 +`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111 +`define PKT_ST_WAIT_RDY_PKT 6'b101000 +`define RES_ST_W_RDY1 6'b101001 +`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010 +`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011 +`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100 +`define TX_LS_EOP_WAIT_GNT1 6'b101101 +`define TX_LS_EOP_SND_SE0_2 6'b101110 +`define TX_LS_EOP_SND_SE0_1 6'b101111 +`define TX_LS_EOP_W_RDY1 6'b110000 +`define TX_LS_EOP_SND_J 6'b110001 +`define TX_LS_EOP_W_RDY2 6'b110010 +`define TX_LS_EOP_W_RDY3 6'b110011 +`define RES_ST_DELAY 6'b110100 +`define RES_ST_W_RDY2 6'b110101 +`define RES_ST_W_RDY3 6'b110110 +`define RES_ST_W_RDY4 6'b110111 +`define DIR_CTL_DELAY 6'b111000 + +reg [5:0] CurrState_SIETx; +reg [5:0] NextState_SIETx; + + +//-------------------------------------------------------------------- +// Machine: SIETx +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx) +begin : SIETx_NextState + NextState_SIETx <= CurrState_SIETx; + // Set default values for outputs and signals + next_processTxByteWEn <= processTxByteWEn; + next_TxByteOut <= TxByteOut; + next_TxByteOutCtrl <= TxByteOutCtrl; + next_USBWireData <= USBWireData; + next_USBWireCtrl <= USBWireCtrl; + next_USBWireReq <= USBWireReq; + next_USBWireWEn <= USBWireWEn; + next_rstCRC <= rstCRC; + next_CRCData <= CRCData; + next_CRC5En <= CRC5En; + next_CRC5_8Bit <= CRC5_8Bit; + next_CRC16En <= CRC16En; + next_SIEPortTxRdy <= SIEPortTxRdy; + next_SIEPortData <= SIEPortData; + next_SIEPortCtrl <= SIEPortCtrl; + next_i <= i; + next_resumeCnt <= resumeCnt; + next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate; + next_USBWireFullSpeedRate <= USBWireFullSpeedRate; + case (CurrState_SIETx) + `IDLE: + NextState_SIETx <= `STX_WAIT_BYTE; + `START_SIETX: + begin + next_processTxByteWEn <= 1'b0; + next_TxByteOut <= 8'h00; + next_TxByteOutCtrl <= 8'h00; + next_USBWireData <= 2'b00; + next_USBWireCtrl <= `TRI_STATE; + next_USBWireReq <= 1'b0; + next_USBWireWEn <= 1'b0; + next_rstCRC <= 1'b0; + next_CRCData <= 8'h00; + next_CRC5En <= 1'b0; + next_CRC5_8Bit <= 1'b0; + next_CRC16En <= 1'b0; + next_SIEPortTxRdy <= 1'b0; + next_SIEPortData <= 8'h00; + next_SIEPortCtrl <= 8'h00; + next_i <= 3'h0; + next_resumeCnt <= 16'h0000; + next_TxByteOutFullSpeedRate <= 1'b0; + next_USBWireFullSpeedRate <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + end + `STX_CHK_ST: + if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE)) + begin + NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT; + next_TxByteOutFullSpeedRate <= 1'b1; + //SOF and PRE always at full speed + end + else if (SIEPortCtrl == `TX_PACKET_START) + NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT; + else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE) + begin + NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1; + next_USBWireReq <= 1'b1; + end + else if (SIEPortCtrl == `TX_DIRECT_CONTROL) + begin + NextState_SIETx <= `DIR_CTL_WAIT_GNT; + next_USBWireReq <= 1'b1; + end + else if (SIEPortCtrl == `TX_IDLE) + NextState_SIETx <= `IDLE; + else if (SIEPortCtrl == `TX_RESUME_START) + begin + NextState_SIETx <= `RES_ST_WAIT_GNT; + next_USBWireReq <= 1'b1; + next_resumeCnt <= 16'h0000; + next_USBWireFullSpeedRate <= 1'b0; + //resume always uses low speed timing + end + `STX_WAIT_BYTE: + begin + next_SIEPortTxRdy <= 1'b1; + if (SIEPortWEn == 1'b1) + begin + NextState_SIETx <= `STX_CHK_ST; + next_SIEPortData <= SIEPortDataIn; + next_SIEPortCtrl <= SIEPortCtrlIn; + next_SIEPortTxRdy <= 1'b0; + next_TxByteOutFullSpeedRate <= fullSpeedRateIn; + next_USBWireFullSpeedRate <= fullSpeedRateIn; + end + end + `DIR_CTL_CHK_FIN: + begin + next_USBWireWEn <= 1'b0; + next_i <= i + 1'b1; + if (i == 3'h7) + begin + NextState_SIETx <= `STX_WAIT_BYTE; + next_USBWireReq <= 1'b0; + end + else + NextState_SIETx <= `DIR_CTL_DELAY; + end + `DIR_CTL_WAIT_GNT: + begin + next_i <= 3'h0; + if (USBWireGnt == 1'b1) + NextState_SIETx <= `DIR_CTL_WAIT_RDY; + end + `DIR_CTL_WAIT_RDY: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `DIR_CTL_CHK_FIN; + next_USBWireData <= SIEPortData[1:0]; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `DIR_CTL_DELAY: + NextState_SIETx <= `DIR_CTL_WAIT_RDY; + `PKT_ST_CHK_PID: + begin + next_processTxByteWEn <= 1'b0; + if (SIEPortData[1:0] == `TOKEN) + NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY; + else if (SIEPortData[1:0] == `HANDSHAKE) + NextState_SIETx <= `PKT_ST_HS_WAIT_RDY; + else if (SIEPortData[1:0] == `DATA) + NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY; + else if (SIEPortData[1:0] == `SPECIAL) + NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY; + end + `PKT_ST_WAIT_RDY_PKT: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_CHK_PID; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= `SYNC_BYTE; + next_TxByteOutCtrl <= `DATA_START; + end + `PKT_ST_DATA_CRC_PKT_SENT1: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2; + end + `PKT_ST_DATA_CRC_PKT_SENT2: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + end + `PKT_ST_DATA_CRC_WAIT_RDY1: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= ~CRC16Result[7:0]; + next_TxByteOutCtrl <= `DATA_STREAM; + end + `PKT_ST_DATA_CRC_WAIT_RDY2: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= ~CRC16Result[15:8]; + next_TxByteOutCtrl <= `DATA_STOP; + end + `PKT_ST_DATA_DATA_CHK_STOP: + if (SIEPortCtrl == `TX_PACKET_STOP) + NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1; + else + NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY; + `PKT_ST_DATA_DATA_PKT_SENT: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE; + end + `PKT_ST_DATA_DATA_UPD_CRC: + begin + next_CRCData <= SIEPortData; + next_CRC16En <= 1'b1; + NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY; + end + `PKT_ST_DATA_DATA_WAIT_BYTE: + begin + next_SIEPortTxRdy <= 1'b1; + if (SIEPortWEn == 1'b1) + begin + NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP; + next_SIEPortData <= SIEPortDataIn; + next_SIEPortCtrl <= SIEPortCtrlIn; + next_SIEPortTxRdy <= 1'b0; + end + end + `PKT_ST_DATA_DATA_WAIT_RDY: + begin + next_CRC16En <= 1'b0; + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= SIEPortData; + next_TxByteOutCtrl <= `DATA_STREAM; + end + end + `PKT_ST_DATA_DATA_WAIT_CRC_RDY: + if (CRC16UpdateRdy == 1'b1) + NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC; + `PKT_ST_DATA_PID_PKT_SENT: + begin + next_processTxByteWEn <= 1'b0; + next_rstCRC <= 1'b0; + NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE; + end + `PKT_ST_DATA_PID_WAIT_RDY: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= SIEPortData; + next_TxByteOutCtrl <= `DATA_STREAM; + next_rstCRC <= 1'b1; + end + `PKT_ST_HS_PKT_SENT: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + end + `PKT_ST_HS_WAIT_RDY: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_HS_PKT_SENT; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= SIEPortData; + next_TxByteOutCtrl <= `DATA_STOP; + end + `PKT_ST_SPCL_PKT_SENT: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + end + `PKT_ST_SPCL_WAIT_RDY: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= SIEPortData; + next_TxByteOutCtrl <= `DATA_STOP; + end + `PKT_ST_TKN_BYTE1_PKT_SENT1: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE; + end + `PKT_ST_TKN_BYTE1_UPD_CRC: + begin + next_CRCData <= SIEPortData; + next_CRC5_8Bit <= 1'b1; + next_CRC5En <= 1'b1; + NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY; + end + `PKT_ST_TKN_BYTE1_WAIT_BYTE: + begin + next_SIEPortTxRdy <= 1'b1; + if (SIEPortWEn == 1'b1) + begin + NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY; + next_SIEPortData <= SIEPortDataIn; + next_SIEPortCtrl <= SIEPortCtrlIn; + next_SIEPortTxRdy <= 1'b0; + end + end + `PKT_ST_TKN_BYTE1_WAIT_RDY: + begin + next_CRC5En <= 1'b0; + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= SIEPortData; + next_TxByteOutCtrl <= `DATA_STREAM; + end + end + `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY: + if (CRC5UpdateRdy == 1'b1) + NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC; + `PKT_ST_TKN_CRC_PKT_SENT: + begin + next_processTxByteWEn <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + end + `PKT_ST_TKN_CRC_UPD_CRC: + begin + next_CRCData <= SIEPortData; + next_CRC5_8Bit <= 1'b0; + next_CRC5En <= 1'b1; + NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY; + end + `PKT_ST_TKN_CRC_WAIT_BYTE: + begin + next_SIEPortTxRdy <= 1'b1; + if (SIEPortWEn == 1'b1) + begin + NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY; + next_SIEPortData <= SIEPortDataIn; + next_SIEPortCtrl <= SIEPortCtrlIn; + next_SIEPortTxRdy <= 1'b0; + end + end + `PKT_ST_TKN_CRC_WAIT_RDY: + begin + next_CRC5En <= 1'b0; + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] }; + next_TxByteOutCtrl <= `DATA_STOP; + end + end + `PKT_ST_TKN_CRC_WAIT_CRC_RDY: + if (CRC5UpdateRdy == 1'b1) + NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC; + `PKT_ST_TKN_PID_PKT_SENT: + begin + next_processTxByteWEn <= 1'b0; + next_rstCRC <= 1'b0; + NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE; + end + `PKT_ST_TKN_PID_WAIT_RDY: + if (processTxByteRdy == 1'b1) + begin + NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT; + next_processTxByteWEn <= 1'b1; + next_TxByteOut <= SIEPortData; + next_TxByteOutCtrl <= `DATA_STREAM; + next_rstCRC <= 1'b1; + end + `RES_ST_CHK_FIN: + begin + next_USBWireWEn <= 1'b0; + if (resumeCnt == `HOST_TX_RESUME_TIME) + NextState_SIETx <= `RES_ST_W_RDY1; + else + NextState_SIETx <= `RES_ST_DELAY; + end + `RES_ST_SND_J_1: + begin + next_USBWireWEn <= 1'b0; + NextState_SIETx <= `RES_ST_W_RDY4; + end + `RES_ST_SND_J_2: + begin + next_USBWireWEn <= 1'b0; + next_USBWireReq <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + next_USBWireFullSpeedRate <= fullSpeedRateIn; + end + `RES_ST_SND_SE0_1: + begin + next_USBWireWEn <= 1'b0; + NextState_SIETx <= `RES_ST_W_RDY2; + end + `RES_ST_SND_SE0_2: + begin + next_USBWireWEn <= 1'b0; + NextState_SIETx <= `RES_ST_W_RDY3; + end + `RES_ST_WAIT_GNT: + if (USBWireGnt == 1'b1) + NextState_SIETx <= `RES_ST_WAIT_RDY; + `RES_ST_WAIT_RDY: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `RES_ST_CHK_FIN; + next_USBWireData <= KBit; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + next_resumeCnt <= resumeCnt + 1'b1; + end + `RES_ST_W_RDY1: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `RES_ST_SND_SE0_1; + next_USBWireData <= `SE0; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `RES_ST_DELAY: + NextState_SIETx <= `RES_ST_WAIT_RDY; + `RES_ST_W_RDY2: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `RES_ST_SND_SE0_2; + next_USBWireData <= `SE0; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `RES_ST_W_RDY3: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `RES_ST_SND_J_1; + next_USBWireData <= JBit; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `RES_ST_W_RDY4: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `RES_ST_SND_J_2; + next_USBWireData <= JBit; + next_USBWireCtrl <= `TRI_STATE; + next_USBWireWEn <= 1'b1; + end + `TX_LS_EOP_WAIT_GNT1: + if (USBWireGnt == 1'b1) + NextState_SIETx <= `TX_LS_EOP_W_RDY1; + `TX_LS_EOP_SND_SE0_2: + begin + next_USBWireWEn <= 1'b0; + NextState_SIETx <= `TX_LS_EOP_W_RDY3; + end + `TX_LS_EOP_SND_SE0_1: + begin + next_USBWireWEn <= 1'b0; + NextState_SIETx <= `TX_LS_EOP_W_RDY2; + end + `TX_LS_EOP_W_RDY1: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `TX_LS_EOP_SND_SE0_1; + next_USBWireData <= `SE0; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `TX_LS_EOP_SND_J: + begin + next_USBWireWEn <= 1'b0; + next_USBWireReq <= 1'b0; + NextState_SIETx <= `STX_WAIT_BYTE; + end + `TX_LS_EOP_W_RDY2: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `TX_LS_EOP_SND_SE0_2; + next_USBWireData <= `SE0; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + `TX_LS_EOP_W_RDY3: + if (USBWireRdy == 1'b1) + begin + NextState_SIETx <= `TX_LS_EOP_SND_J; + next_USBWireData <= JBit; + next_USBWireCtrl <= `DRIVE; + next_USBWireWEn <= 1'b1; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : SIETx_CurrentState + if (rst) + CurrState_SIETx <= `START_SIETX; + else + CurrState_SIETx <= NextState_SIETx; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : SIETx_RegOutput + if (rst) + begin + SIEPortData <= 8'h00; + SIEPortCtrl <= 8'h00; + i <= 3'h0; + resumeCnt <= 16'h0000; + processTxByteWEn <= 1'b0; + TxByteOut <= 8'h00; + TxByteOutCtrl <= 8'h00; + USBWireData <= 2'b00; + USBWireCtrl <= `TRI_STATE; + USBWireReq <= 1'b0; + USBWireWEn <= 1'b0; + rstCRC <= 1'b0; + CRCData <= 8'h00; + CRC5En <= 1'b0; + CRC5_8Bit <= 1'b0; + CRC16En <= 1'b0; + SIEPortTxRdy <= 1'b0; + TxByteOutFullSpeedRate <= 1'b0; + USBWireFullSpeedRate <= 1'b0; + end + else + begin + SIEPortData <= next_SIEPortData; + SIEPortCtrl <= next_SIEPortCtrl; + i <= next_i; + resumeCnt <= next_resumeCnt; + processTxByteWEn <= next_processTxByteWEn; + TxByteOut <= next_TxByteOut; + TxByteOutCtrl <= next_TxByteOutCtrl; + USBWireData <= next_USBWireData; + USBWireCtrl <= next_USBWireCtrl; + USBWireReq <= next_USBWireReq; + USBWireWEn <= next_USBWireWEn; + rstCRC <= next_rstCRC; + CRCData <= next_CRCData; + CRC5En <= next_CRC5En; + CRC5_8Bit <= next_CRC5_8Bit; + CRC16En <= next_CRC16En; + SIEPortTxRdy <= next_SIEPortTxRdy; + TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate; + USBWireFullSpeedRate <= next_USBWireFullSpeedRate; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/endpMux.v =================================================================== --- Actel/usbDeviceActelTop/hdl/endpMux.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/endpMux.v (revision 40) @@ -0,0 +1,259 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// endpMux.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSlaveControl_h.v" + +module endpMux ( + clk, + rst, + currEndP, + NAKSent, + stallSent, + CRCError, + bitStuffError, + RxOverflow, + RxTimeOut, + dataSequence, + ACKRxed, + transType, + transTypeNAK, + endPControlReg, + clrEPRdy, + endPMuxErrorsWEn, + endP0ControlReg, + endP1ControlReg, + endP2ControlReg, + endP3ControlReg, + endP0StatusReg, + endP1StatusReg, + endP2StatusReg, + endP3StatusReg, + endP0TransTypeReg, + endP1TransTypeReg, + endP2TransTypeReg, + endP3TransTypeReg, + endP0NAKTransTypeReg, + endP1NAKTransTypeReg, + endP2NAKTransTypeReg, + endP3NAKTransTypeReg, + clrEP0Rdy, + clrEP1Rdy, + clrEP2Rdy, + clrEP3Rdy); + + +input clk; +input rst; +input [3:0] currEndP; +input NAKSent; +input stallSent; +input CRCError; +input bitStuffError; +input RxOverflow; +input RxTimeOut; +input dataSequence; +input ACKRxed; +input [1:0] transType; +input [1:0] transTypeNAK; +output [4:0] endPControlReg; +input clrEPRdy; +input endPMuxErrorsWEn; +input [4:0] endP0ControlReg; +input [4:0] endP1ControlReg; +input [4:0] endP2ControlReg; +input [4:0] endP3ControlReg; +output [7:0] endP0StatusReg; +output [7:0] endP1StatusReg; +output [7:0] endP2StatusReg; +output [7:0] endP3StatusReg; +output [1:0] endP0TransTypeReg; +output [1:0] endP1TransTypeReg; +output [1:0] endP2TransTypeReg; +output [1:0] endP3TransTypeReg; +output [1:0] endP0NAKTransTypeReg; +output [1:0] endP1NAKTransTypeReg; +output [1:0] endP2NAKTransTypeReg; +output [1:0] endP3NAKTransTypeReg; +output clrEP0Rdy; +output clrEP1Rdy; +output clrEP2Rdy; +output clrEP3Rdy; + +wire clk; +wire rst; +wire [3:0] currEndP; +wire NAKSent; +wire stallSent; +wire CRCError; +wire bitStuffError; +wire RxOverflow; +wire RxTimeOut; +wire dataSequence; +wire ACKRxed; +wire [1:0] transType; +wire [1:0] transTypeNAK; +reg [4:0] endPControlReg; +wire clrEPRdy; +wire endPMuxErrorsWEn; +wire [4:0] endP0ControlReg; +wire [4:0] endP1ControlReg; +wire [4:0] endP2ControlReg; +wire [4:0] endP3ControlReg; +reg [7:0] endP0StatusReg; +reg [7:0] endP1StatusReg; +reg [7:0] endP2StatusReg; +reg [7:0] endP3StatusReg; +reg [1:0] endP0TransTypeReg; +reg [1:0] endP1TransTypeReg; +reg [1:0] endP2TransTypeReg; +reg [1:0] endP3TransTypeReg; +reg [1:0] endP0NAKTransTypeReg; +reg [1:0] endP1NAKTransTypeReg; +reg [1:0] endP2NAKTransTypeReg; +reg [1:0] endP3NAKTransTypeReg; +reg clrEP0Rdy; +reg clrEP1Rdy; +reg clrEP2Rdy; +reg clrEP3Rdy; + +//internal wires and regs +reg [7:0] endPStatusCombine; + +//mux endPControlReg and clrEPRdy +always @(posedge clk) +begin + case (currEndP[1:0]) + 2'b00: begin + endPControlReg <= endP0ControlReg; + clrEP0Rdy <= clrEPRdy; + end + 2'b01: begin + endPControlReg <= endP1ControlReg; + clrEP1Rdy <= clrEPRdy; + end + 2'b10: begin + endPControlReg <= endP2ControlReg; + clrEP2Rdy <= clrEPRdy; + end + 2'b11: begin + endPControlReg <= endP3ControlReg; + clrEP3Rdy <= clrEPRdy; + end + endcase +end + +//mux endPNAKTransType, endPTransType, endPStatusReg +//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched. +//else update the entire status reg +always @(posedge clk) +begin + if (rst) begin + endP0NAKTransTypeReg <= 2'b00; + endP1NAKTransTypeReg <= 2'b00; + endP2NAKTransTypeReg <= 2'b00; + endP3NAKTransTypeReg <= 2'b00; + endP0TransTypeReg <= 2'b00; + endP1TransTypeReg <= 2'b00; + endP2TransTypeReg <= 2'b00; + endP3TransTypeReg <= 2'b00; + endP0StatusReg <= 4'h0; + endP1StatusReg <= 4'h0; + endP2StatusReg <= 4'h0; + endP3StatusReg <= 4'h0; + end + else begin + if (endPMuxErrorsWEn == 1'b1) begin + if (NAKSent == 1'b1) begin + case (currEndP[1:0]) + 2'b00: begin + endP0NAKTransTypeReg <= transTypeNAK; + endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; + end + 2'b01: begin + endP1NAKTransTypeReg <= transTypeNAK; + endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; + end + 2'b10: begin + endP2NAKTransTypeReg <= transTypeNAK; + endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; + end + 2'b11: begin + endP3NAKTransTypeReg <= transTypeNAK; + endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; + end + endcase + end + else begin + case (currEndP[1:0]) + 2'b00: begin + endP0TransTypeReg <= transType; + endP0StatusReg <= endPStatusCombine; + end + 2'b01: begin + endP1TransTypeReg <= transType; + endP1StatusReg <= endPStatusCombine; + end + 2'b10: begin + endP2TransTypeReg <= transType; + endP2StatusReg <= endPStatusCombine; + end + 2'b11: begin + endP3TransTypeReg <= transType; + endP3StatusReg <= endPStatusCombine; + end + endcase + end + end + end +end + + +//combine status bits into a single word +always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError) +begin + endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError}; +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/pll_48MHz.v =================================================================== --- Actel/usbDeviceActelTop/hdl/pll_48MHz.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/pll_48MHz.v (revision 40) @@ -0,0 +1,278 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_48MHz.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 7.2 Build 203 02/05/2008 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2007 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_48MHz ( + inclk0, + locked); + + input inclk0; + output locked; + + wire sub_wire0; + wire [0:0] sub_wire3 = 1'h0; + wire locked = sub_wire0; + wire sub_wire1 = inclk0; + wire [1:0] sub_wire2 = {sub_wire3, sub_wire1}; + + altpll altpll_component ( + .inclk (sub_wire2), + .locked (sub_wire0), + .activeclock (), + .areset (1'b0), + .clk (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.gate_lock_signal = "NO", + altpll_component.inclk0_input_frequency = 20833, + altpll_component.intended_device_family = "Cyclone II", + altpll_component.invalid_lock_multiplier = 5, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_48MHz", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NO_COMPENSATION", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_UNUSED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.valid_lock_multiplier = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_48MHz.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.ppf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_inst.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_bb.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_waveforms.html TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_wave*.jpg FALSE FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON Index: Actel/usbDeviceActelTop/hdl/EP0.v =================================================================== --- Actel/usbDeviceActelTop/hdl/EP0.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/EP0.v (revision 40) @@ -0,0 +1,869 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// EP0.v //// +//// //// +//// This file is part of the usbHostSlave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Implements EP0 control endpoint +//// Responds to 8-byte SETUP packets +//// of type GET_STATUS, GET_DESCRIPTOR and +//// SET_ADDRESS +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostSlaveReg_define.v" +`include "usbDevice_define.v" + + +module EP0 (clk, initComplete, memAddr, memData, memRdEn, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq); +input clk; +input [7:0]memData; +input rst; +input wb_ack; +input [7:0]wb_data_i; +input wbBusGnt; +output initComplete; +output [7:0]memAddr; +output memRdEn; +output [7:0]wb_addr; +output [7:0]wb_data_o; +output wb_stb; +output wb_we; +output wbBusReq; + +wire clk; +reg initComplete, next_initComplete; +reg [7:0]memAddr, next_memAddr; +wire [7:0]memData; +reg memRdEn, next_memRdEn; +wire rst; +wire wb_ack; +reg [7:0]wb_addr, next_wb_addr; +wire [7:0]wb_data_i; +reg [7:0]wb_data_o, next_wb_data_o; +reg wb_stb, next_wb_stb; +reg wb_we, next_wb_we; +wire wbBusGnt; +reg wbBusReq, next_wbBusReq; + +// diagram signals declarations +reg bm_req_dir, next_bm_req_dir; +reg [4:0]bm_req_recp, next_bm_req_recp; +reg [1:0]bm_req_type, next_bm_req_type; +reg [7:0]bRequest, next_bRequest; +reg [7:0]cnt, next_cnt; +reg dataSeq, next_dataSeq; +reg [7:0]epStatus, next_epStatus; +reg [7:0]epTransType, next_epTransType; +reg localRst, next_localRst; +reg [15:0]rxDataSize, next_rxDataSize; +reg transDone, next_transDone; +reg [7:0]txDataIndex, next_txDataIndex; +reg [7:0]txDataSize, next_txDataSize; +reg [7:0]txPacketRemSize, next_txPacketRemSize; +reg updateUSBAddress, next_updateUSBAddress; +reg [7:0]USBAddress, next_USBAddress; +reg [15:0]wIndex, next_wIndex; +reg [15:0]wLength, next_wLength; +reg [15:0]wValue, next_wValue; + +// BINARY ENCODED state machine: EP0St +// State codes definitions: +`define INIT_RST 6'b000000 +`define INIT_WT_GNT 6'b000001 +`define INIT_WT_RST 6'b000010 +`define INIT_WT_VBUS 6'b000011 +`define INIT_FIN 6'b000100 +`define DO_TRANS_WT_GNT 6'b000101 +`define DO_TRANS_TX_EMPTY 6'b000110 +`define DO_TRANS_WR_TX_FIFO 6'b000111 +`define DO_TRANS_RD_MEM 6'b001000 +`define DO_TRANS_CHK_TX_DONE 6'b001001 +`define DO_TRANS_TRANS_GO 6'b001010 +`define DO_TRANS_WT_TRANS_DONE_WT_GNT 6'b001011 +`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 6'b001100 +`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 6'b001101 +`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 6'b001110 +`define CHK_TRANS_RD_STAT 6'b001111 +`define CHK_TRANS_WT_GNT 6'b010000 +`define CHK_TRANS_RD_RX_SIZE1 6'b010001 +`define CHK_TRANS_RD_RX_SIZE2 6'b010010 +`define CHK_TRANS_RD_TRANS_TYPE 6'b010011 +`define CHK_TRANS_WT_UNGNT 6'b010100 +`define SETUP_CHK_ERR 6'b010101 +`define SETUP_GET_DATA_DAT1 6'b010110 +`define SETUP_GET_DATA_WT_GNT 6'b010111 +`define SETUP_GET_DATA_DAT2 6'b011000 +`define SETUP_GET_DATA_DAT3 6'b011001 +`define SETUP_GET_DATA_DAT4 6'b011010 +`define SETUP_GET_DATA_DAT6 6'b011011 +`define SETUP_GET_DATA_DAT5 6'b011100 +`define SETUP_GET_DATA_DAT8 6'b011101 +`define SETUP_GET_DATA_DAT7 6'b011110 +`define SETUP_GET_DATA_WT_UNGNT 6'b011111 +`define SETUP_GET_STAT 6'b100000 +`define SETUP_SET_ADDR 6'b100001 +`define SETUP_GET_DESC_S1 6'b100010 +`define SETUP_CHK_MAX_LEN 6'b100011 +`define OUT_CHK_SEQ 6'b100100 +`define IN_CHK_ACK 6'b100101 +`define IN_SET_PTR 6'b100110 +`define IN_SET_ADDR 6'b100111 +`define IN_WT_GNT 6'b101000 +`define IN_WT_UNGNT 6'b101001 +`define DO_TRANS_RX_EMPTY 6'b101010 +`define DO_TRANS_WT_TRANS_DONE_DEL 6'b101011 +`define START 6'b101100 +`define INIT_CONN 6'b101101 +`define INIT_WT_CONN 6'b101110 +`define DO_TRANS_DEL 6'b101111 +`define SETUP_PTR_SET 6'b110000 + +reg [5:0]CurrState_EP0St, NextState_EP0St; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: EP0St + +// NextState logic (combinatorial) +always @ (wb_ack or wbBusGnt or cnt or wb_data_i or memData or txDataIndex or txDataSize or transDone or epStatus or epTransType or rxDataSize or bRequest or wValue or wLength or dataSeq or updateUSBAddress or txPacketRemSize or USBAddress or wb_addr or wb_data_o or wb_stb or wb_we or wbBusReq or initComplete or memAddr or memRdEn or bm_req_dir or bm_req_type or bm_req_recp or wIndex or CurrState_EP0St) +begin + NextState_EP0St <= CurrState_EP0St; + // Set default values for outputs and signals + next_wb_addr <= wb_addr; + next_wb_data_o <= wb_data_o; + next_wb_stb <= wb_stb; + next_wb_we <= wb_we; + next_cnt <= cnt; + next_wbBusReq <= wbBusReq; + next_initComplete <= initComplete; + next_memAddr <= memAddr; + next_memRdEn <= memRdEn; + next_txDataSize <= txDataSize; + next_txDataIndex <= txDataIndex; + next_transDone <= transDone; + next_epStatus <= epStatus; + next_rxDataSize <= rxDataSize; + next_epTransType <= epTransType; + next_bm_req_dir <= bm_req_dir; + next_bm_req_type <= bm_req_type; + next_bm_req_recp <= bm_req_recp; + next_bRequest <= bRequest; + next_wValue <= wValue; + next_wIndex <= wIndex; + next_wLength <= wLength; + next_txPacketRemSize <= txPacketRemSize; + next_USBAddress <= USBAddress; + next_updateUSBAddress <= updateUSBAddress; + next_dataSeq <= dataSeq; + case (CurrState_EP0St) // synopsys parallel_case full_case + `START: + begin + next_initComplete <= 1'b0; + next_wbBusReq <= 1'b0; + next_wb_addr <= 8'h00; + next_wb_data_o <= 8'h00; + next_wb_stb <= 1'b0; + next_wb_we <= 1'b0; + next_txPacketRemSize <= 8'h00; + next_txDataSize <= 8'h00; + next_txDataIndex <= 8'h00; + next_epTransType <= 8'h00; + next_epStatus <= 8'h00; + next_rxDataSize <= 16'h0000; + next_cnt <= 8'h00; + next_memRdEn <= 1'b0; + next_memAddr <= 8'h00; + next_updateUSBAddress <= 1'b0; + next_transDone <= 1'b0; + next_bm_req_type <= 2'b00; + next_bm_req_dir <= 1'b0; + next_bm_req_recp <= 5'b00000; + next_bRequest <= 8'h00; + next_wLength <= 16'h0000; + next_wIndex <= 16'h0000; + next_wValue <= 16'h0000; + next_dataSeq <= 1'b0; + next_USBAddress <= 8'h00; + NextState_EP0St <= `INIT_WT_GNT; + end + `CHK_TRANS_RD_STAT: + begin + next_wb_addr <= `RA_EP0_STATUS_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE1; + next_wb_stb <= 1'b0; + next_epStatus <= wb_data_i; + end + end + `CHK_TRANS_WT_GNT: + begin + if (wbBusGnt == 1'b1) + begin + NextState_EP0St <= `CHK_TRANS_RD_STAT; + end + end + `CHK_TRANS_RD_RX_SIZE1: + begin + next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE2; + next_wb_stb <= 1'b0; + next_rxDataSize[15:8] <= wb_data_i; + end + end + `CHK_TRANS_RD_RX_SIZE2: + begin + next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `CHK_TRANS_RD_TRANS_TYPE; + next_wb_stb <= 1'b0; + next_rxDataSize[7:0] <= wb_data_i; + end + end + `CHK_TRANS_RD_TRANS_TYPE: + begin + next_wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `CHK_TRANS_WT_UNGNT; + next_wb_stb <= 1'b0; + next_epTransType <= wb_data_i; + end + end + `CHK_TRANS_WT_UNGNT: + begin + next_wbBusReq <= 1'b0; + if ((wbBusGnt == 1'b0) && ((epStatus & 8'h0f) != 8'h00)) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + else if ((wbBusGnt == 1'b0) && (epTransType == `SC_SETUP_TRANS)) + begin + NextState_EP0St <= `SETUP_CHK_ERR; + end + else if ((wbBusGnt == 1'b0) && (epTransType == `SC_IN_TRANS)) + begin + NextState_EP0St <= `IN_CHK_ACK; + end + else if ((wbBusGnt == 1'b0) && (epTransType == `SC_OUTDATA_TRANS)) + begin + NextState_EP0St <= `OUT_CHK_SEQ; + end + else if (wbBusGnt == 1'b0) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + end + `DO_TRANS_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_TX_EMPTY; + end + end + `DO_TRANS_TX_EMPTY: + begin + next_wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG; + next_wb_data_o <= 8'h01; + //force tx fifo empty + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_RX_EMPTY; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_WR_TX_FIFO: + begin + next_wb_data_o <= memData; + next_wb_addr <= `RA_EP0_TX_FIFO_DATA_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_CHK_TX_DONE; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_RD_MEM: + begin + next_memAddr <= txDataIndex; + next_memRdEn <= 1'b1; + next_txDataSize <= txDataSize - 1'b1; + next_txDataIndex <= txDataIndex + 1'b1; + NextState_EP0St <= `DO_TRANS_DEL; + end + `DO_TRANS_CHK_TX_DONE: + begin + if (txDataSize == 8'h00) + begin + NextState_EP0St <= `DO_TRANS_TRANS_GO; + end + else + begin + NextState_EP0St <= `DO_TRANS_RD_MEM; + end + end + `DO_TRANS_TRANS_GO: + begin + next_wb_addr <= `RA_EP0_CONTROL_REG; + if (dataSeq == 1'b1) + next_wb_data_o <= 8'h07; + else + next_wb_data_o <= 8'h03; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT; + next_wb_stb <= 1'b0; + next_transDone <= 1'b0; + end + end + `DO_TRANS_RX_EMPTY: + begin + next_wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG; + next_wb_data_o <= 8'h01; + //force rx fifo empty + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if ((wb_ack == 1'b1) && (txDataSize != 8'h00)) + begin + NextState_EP0St <= `DO_TRANS_RD_MEM; + next_wb_stb <= 1'b0; + end + else if (wb_ack == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_TRANS_GO; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_DEL: + begin + next_memRdEn <= 1'b0; + NextState_EP0St <= `DO_TRANS_WR_TX_FIFO; + end + `DO_TRANS_WT_TRANS_DONE_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS; + end + end + `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS: + begin + next_wb_addr <= `RA_EP0_CONTROL_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT; + next_wb_stb <= 1'b0; + next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT]; + end + end + `DO_TRANS_WT_TRANS_DONE_WT_UNGNT: + begin + next_wbBusReq <= 1'b0; + if (wbBusGnt == 1'b0) + begin + NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE; + end + end + `DO_TRANS_WT_TRANS_DONE_CHK_DONE: + begin + if (transDone == 1'b1) + begin + NextState_EP0St <= `CHK_TRANS_WT_GNT; + next_wbBusReq <= 1'b1; + end + else + begin + NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_DEL; + next_cnt <= 8'h00; + end + end + `DO_TRANS_WT_TRANS_DONE_DEL: + begin + next_cnt <= cnt + 1'b1; + if (cnt == `ONE_USEC_DEL) + begin + NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT; + end + end + `SETUP_CHK_ERR: + begin + if (rxDataSize != 16'h0008) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + else + begin + NextState_EP0St <= `SETUP_GET_DATA_WT_GNT; + next_wbBusReq <= 1'b1; + next_txDataSize <= 8'h00; + next_txPacketRemSize <= 8'h00; + //default tx packet size + next_dataSeq <= 1'b1; + next_wb_addr <= `RA_EP0_RX_FIFO_DATA_REG; + next_wb_we <= 1'b0; + end + end + `SETUP_GET_STAT: + begin + if (bm_req_type == 2'b00) begin + next_txPacketRemSize <= 8'h02; + if (bm_req_recp == 5'b00000) + next_txDataIndex <= `ONE_ZERO_STAT_INDEX; + else + next_txDataIndex <= `ZERO_ZERO_STAT_INDEX; + end + else if (bm_req_type == 2'b10) begin + next_txDataIndex <= `VENDOR_DATA_STAT_INDEX; + next_txPacketRemSize <= 8'h02; + end + NextState_EP0St <= `SETUP_CHK_MAX_LEN; + end + `SETUP_SET_ADDR: + begin + if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin + next_USBAddress <= wValue[7:0]; + next_updateUSBAddress <= 1'b1; + end + NextState_EP0St <= `SETUP_CHK_MAX_LEN; + end + `SETUP_CHK_MAX_LEN: + begin + if (txPacketRemSize > wLength) + next_txPacketRemSize <= wLength; + NextState_EP0St <= `SETUP_PTR_SET; + end + `SETUP_PTR_SET: + begin + if (txPacketRemSize > `MAX_RESP_SIZE) begin + next_txDataSize <= `MAX_RESP_SIZE; + next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE; + end + else begin + next_txDataSize <= txPacketRemSize; + next_txPacketRemSize <= 8'h00; + end + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + `SETUP_GET_DATA_DAT1: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT2; + next_wb_stb <= 1'b0; + next_bm_req_dir <= wb_data_i[7]; + next_bm_req_type <= wb_data_i[6:5]; + next_bm_req_recp <= wb_data_i[4:0]; + end + end + `SETUP_GET_DATA_WT_GNT: + begin + if (wbBusGnt == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT1; + end + end + `SETUP_GET_DATA_DAT2: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT3; + next_wb_stb <= 1'b0; + next_bRequest <= wb_data_i; + end + end + `SETUP_GET_DATA_DAT3: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT4; + next_wb_stb <= 1'b0; + next_wValue[7:0] <= wb_data_i; + end + end + `SETUP_GET_DATA_DAT4: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT5; + next_wb_stb <= 1'b0; + next_wValue[15:8] <= wb_data_i; + end + end + `SETUP_GET_DATA_DAT6: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT7; + next_wb_stb <= 1'b0; + next_wIndex[15:8] <= wb_data_i; + end + end + `SETUP_GET_DATA_DAT5: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT6; + next_wb_stb <= 1'b0; + next_wIndex[7:0] <= wb_data_i; + end + end + `SETUP_GET_DATA_DAT8: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_WT_UNGNT; + next_wb_stb <= 1'b0; + next_wLength[15:8] <= wb_data_i; + next_wbBusReq <= 1'b0; + end + end + `SETUP_GET_DATA_DAT7: + begin + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `SETUP_GET_DATA_DAT8; + next_wb_stb <= 1'b0; + next_wLength[7:0] <= wb_data_i; + end + end + `SETUP_GET_DATA_WT_UNGNT: + begin + if ((wbBusGnt == 1'b0) && (bRequest == `GET_STATUS)) + begin + NextState_EP0St <= `SETUP_GET_STAT; + end + else if ((wbBusGnt == 1'b0) && (bRequest == `GET_DESCRIPTOR)) + begin + NextState_EP0St <= `SETUP_GET_DESC_S1; + end + else if ((wbBusGnt == 1'b0) && (bRequest == `SET_ADDRESS)) + begin + NextState_EP0St <= `SETUP_SET_ADDR; + end + else if (wbBusGnt == 1'b0) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + end + `SETUP_GET_DESC_S1: + begin + case (wValue[15:8]) + `DEV_DESC: begin + next_txPacketRemSize <= `DEV_DESC_SIZE; + next_txDataIndex <= `DEV_DESC_INDEX; + end + `CFG_DESC: begin + next_txPacketRemSize <= `CFG_DESC_SIZE; + next_txDataIndex <= `CFG_DESC_INDEX; + end + `REP_DESC: begin + next_txPacketRemSize <= `REP_DESC_SIZE; + next_txDataIndex <= `REP_DESC_INDEX; + end + `STRING_DESC: begin + case (wValue[3:0]) + 4'h0: begin + next_txPacketRemSize <= `LANGID_DESC_SIZE; + next_txDataIndex <= `LANGID_DESC_INDEX; + end + 4'h1: begin + next_txPacketRemSize <= `STRING1_DESC_SIZE; + next_txDataIndex <= `STRING1_DESC_INDEX; + end + 4'h2: begin + next_txPacketRemSize <= `STRING2_DESC_SIZE; + next_txDataIndex <= `STRING2_DESC_INDEX; + end + 4'h3: begin + next_txPacketRemSize <= `STRING3_DESC_SIZE; + next_txDataIndex <= `STRING3_DESC_INDEX; + end + endcase + end + endcase + NextState_EP0St <= `SETUP_CHK_MAX_LEN; + end + `IN_CHK_ACK: + begin + if (epStatus[`SC_ACK_RXED_BIT] != 1'b1) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + else if (updateUSBAddress == 1'b1) + begin + NextState_EP0St <= `IN_WT_GNT; + end + else + begin + NextState_EP0St <= `IN_SET_PTR; + end + end + `IN_SET_PTR: + begin + if (txPacketRemSize > `MAX_RESP_SIZE) begin + next_txDataSize <= `MAX_RESP_SIZE; + next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE; + end + else begin + next_txDataSize <= txPacketRemSize; + next_txPacketRemSize <= 8'h00; + end + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + `IN_SET_ADDR: + begin + next_wb_addr <= `RA_SC_ADDRESS; + next_wb_data_o <= USBAddress; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `IN_WT_UNGNT; + next_wb_stb <= 1'b0; + next_wbBusReq <= 1'b0; + end + end + `IN_WT_GNT: + begin + next_wbBusReq <= 1'b1; + next_updateUSBAddress <= 1'b0; + if (wbBusGnt == 1'b1) + begin + NextState_EP0St <= `IN_SET_ADDR; + end + end + `IN_WT_UNGNT: + begin + if (wbBusGnt == 1'b0) + begin + NextState_EP0St <= `IN_SET_PTR; + end + end + `OUT_CHK_SEQ: + begin + if (epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + else + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + next_dataSeq <= ~dataSeq; + end + end + `INIT_RST: + begin + next_wb_addr <= `RA_HOST_SLAVE_MODE; + next_wb_data_o <= 8'h2; + //reset usbHostSlave + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `INIT_WT_RST; + next_wb_stb <= 1'b0; + next_cnt <= 8'h00; + end + end + `INIT_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP0St <= `INIT_RST; + end + end + `INIT_WT_RST: + begin + next_cnt <= cnt + 1'b1; + if (cnt == 8'hff) + begin + NextState_EP0St <= `INIT_WT_VBUS; + end + end + `INIT_WT_VBUS: + begin + next_wb_addr <= `RA_SC_LINE_STATUS_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if ((wb_ack == 1'b1) && (wb_data_i[`VBUS_PRES_BIT] == 1'b1)) + begin + NextState_EP0St <= `INIT_CONN; + next_wb_stb <= 1'b0; + end + end + `INIT_FIN: + begin + next_wbBusReq <= 1'b0; + next_initComplete <= 1'b1; + if (wbBusGnt == 1'b0) + begin + NextState_EP0St <= `DO_TRANS_WT_GNT; + end + end + `INIT_CONN: + begin + next_wb_addr <= `RA_SC_CONTROL_REG; + next_wb_data_o <= 8'h71; + //connect to host, full speed + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP0St <= `INIT_WT_CONN; + next_wb_stb <= 1'b0; + end + end + `INIT_WT_CONN: + begin + next_wb_addr <= `RA_SC_LINE_STATUS_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if ((wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT)) + begin + NextState_EP0St <= `INIT_FIN; + next_wb_stb <= 1'b0; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_EP0St <= `START; + else + CurrState_EP0St <= NextState_EP0St; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + wb_addr <= 8'h00; + wb_data_o <= 8'h00; + wb_stb <= 1'b0; + wb_we <= 1'b0; + wbBusReq <= 1'b0; + initComplete <= 1'b0; + memAddr <= 8'h00; + memRdEn <= 1'b0; + cnt <= 8'h00; + txDataSize <= 8'h00; + txDataIndex <= 8'h00; + transDone <= 1'b0; + epStatus <= 8'h00; + rxDataSize <= 16'h0000; + epTransType <= 8'h00; + bm_req_dir <= 1'b0; + bm_req_type <= 2'b00; + bm_req_recp <= 5'b00000; + bRequest <= 8'h00; + wValue <= 16'h0000; + wIndex <= 16'h0000; + wLength <= 16'h0000; + txPacketRemSize <= 8'h00; + USBAddress <= 8'h00; + updateUSBAddress <= 1'b0; + dataSeq <= 1'b0; + end + else + begin + wb_addr <= next_wb_addr; + wb_data_o <= next_wb_data_o; + wb_stb <= next_wb_stb; + wb_we <= next_wb_we; + wbBusReq <= next_wbBusReq; + initComplete <= next_initComplete; + memAddr <= next_memAddr; + memRdEn <= next_memRdEn; + cnt <= next_cnt; + txDataSize <= next_txDataSize; + txDataIndex <= next_txDataIndex; + transDone <= next_transDone; + epStatus <= next_epStatus; + rxDataSize <= next_rxDataSize; + epTransType <= next_epTransType; + bm_req_dir <= next_bm_req_dir; + bm_req_type <= next_bm_req_type; + bm_req_recp <= next_bm_req_recp; + bRequest <= next_bRequest; + wValue <= next_wValue; + wIndex <= next_wIndex; + wLength <= next_wLength; + txPacketRemSize <= next_txPacketRemSize; + USBAddress <= next_USBAddress; + updateUSBAddress <= next_updateUSBAddress; + dataSeq <= next_dataSeq; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/writeUSBWireData.v =================================================================== --- Actel/usbDeviceActelTop/hdl/writeUSBWireData.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/writeUSBWireData.v (revision 40) @@ -0,0 +1,281 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// writeUSBWireData.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + +`define BUFFER_FULL 3'b100 + +module writeUSBWireData ( + TxBitsIn, + TxBitsOut, + TxDataOutTick, + TxCtrlIn, + TxCtrlOut, + USBWireRdy, + USBWireWEn, + TxWireActiveDrive, + fullSpeedRate, + clk, + rst + ); + +input [1:0] TxBitsIn; +input TxCtrlIn; +input USBWireWEn; +input clk; +input fullSpeedRate; +input rst; +output [1:0] TxBitsOut; +output TxDataOutTick; +output TxCtrlOut; +output USBWireRdy; +output TxWireActiveDrive; + +wire [1:0] TxBitsIn; +reg [1:0] TxBitsOut; +reg TxDataOutTick; +wire TxCtrlIn; +reg TxCtrlOut; +reg USBWireRdy; +wire USBWireWEn; +wire clk; +wire fullSpeedRate; +wire rst; +reg TxWireActiveDrive; + +// local registers +reg [2:0]buffer0; +reg [2:0]buffer1; +reg [2:0]buffer2; +reg [2:0]buffer3; +reg [2:0]bufferCnt; +reg [1:0]bufferInIndex; +reg [1:0]bufferOutIndex; +reg decBufferCnt; +reg [4:0]i; +reg incBufferCnt; +reg fullSpeedTick; +reg lowSpeedTick; + +// buffer in state machine state codes: +`define WAIT_BUFFER_NOT_FULL 2'b00 +`define WAIT_WRITE_REQ 2'b01 +`define CLR_INC_BUFFER_CNT 2'b10 + +// buffer output state machine state codes: +`define WAIT_BUFFER_FULL 2'b00 +`define WAIT_LINE_WRITE 2'b01 +`define LINE_WRITE 2'b10 + +reg [1:0] bufferInStMachCurrState; +reg [1:0] bufferOutStMachCurrState; + +// buffer control +always @(posedge clk) +begin + if (rst == 1'b1) + begin + bufferCnt <= 3'b000; + end + else + begin + if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0) + bufferCnt <= bufferCnt + 1'b1; + else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1) + bufferCnt <= bufferCnt - 1'b1; + end +end + + +//buffer input state machine +always @(posedge clk) begin + if (rst == 1'b1) begin + incBufferCnt <= 1'b0; + bufferInIndex <= 2'b00; + buffer0 <= 3'b000; + buffer1 <= 3'b000; + buffer2 <= 3'b000; + buffer3 <= 3'b000; + USBWireRdy <= 1'b0; + bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL; + end + else begin + case (bufferInStMachCurrState) + `WAIT_BUFFER_NOT_FULL: + begin + if (bufferCnt != `BUFFER_FULL) + begin + bufferInStMachCurrState <= `WAIT_WRITE_REQ; + USBWireRdy <= 1'b1; + end + end + `WAIT_WRITE_REQ: + begin + if (USBWireWEn == 1'b1) + begin + incBufferCnt <= 1'b1; + USBWireRdy <= 1'b0; + bufferInIndex <= bufferInIndex + 1'b1; + case (bufferInIndex) + 2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn}; + 2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn}; + 2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn}; + 2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn}; + endcase + bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT; + end + end + `CLR_INC_BUFFER_CNT: + begin + incBufferCnt <= 1'b0; + if (bufferCnt != (`BUFFER_FULL - 1'b1) ) + begin + bufferInStMachCurrState <= `WAIT_WRITE_REQ; + USBWireRdy <= 1'b1; + end + else begin + bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL; + end + end + endcase + end +end + +//increment counter used to generate USB bit rate +always @(posedge clk) begin + if (rst == 1'b1) + begin + i <= 5'b00000; + fullSpeedTick <= 1'b0; + lowSpeedTick <= 1'b0; + end + else + begin + i <= i + 1'b1; + if (i[1:0] == 2'b00) + fullSpeedTick <= 1'b1; + else + fullSpeedTick <= 1'b0; + if (i == 5'b00000) + lowSpeedTick <= 1'b1; + else + lowSpeedTick <= 1'b0; + end +end + +//buffer output state machine +//buffer is constantly emptied at either +//the full or low speed rate +//if the buffer is empty, then the output is forced to tri-state +always @(posedge clk) begin + if (rst == 1'b1) + begin + bufferOutIndex <= 2'b00; + decBufferCnt <= 1'b0; + TxBitsOut <= 2'b00; + TxCtrlOut <= `TRI_STATE; + TxDataOutTick <= 1'b0; + bufferOutStMachCurrState <= `WAIT_LINE_WRITE; + end + else + begin + case (bufferOutStMachCurrState) + `WAIT_LINE_WRITE: + begin + if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) ) + begin + TxDataOutTick <= !TxDataOutTick; + if (bufferCnt == 0) begin + TxBitsOut <= 2'b00; + TxCtrlOut <= `TRI_STATE; + end + else begin + bufferOutStMachCurrState <= `LINE_WRITE; + decBufferCnt <= 1'b1; + bufferOutIndex <= bufferOutIndex + 1'b1; + case (bufferOutIndex) + 2'b00 : + begin + TxBitsOut <= buffer0[2:1]; + TxCtrlOut <= buffer0[0]; + end + 2'b01 : + begin + TxBitsOut <= buffer1[2:1]; + TxCtrlOut <= buffer1[0]; + end + 2'b10 : + begin + TxBitsOut <= buffer2[2:1]; + TxCtrlOut <= buffer2[0]; + end + 2'b11 : + begin + TxBitsOut <= buffer3[2:1]; + TxCtrlOut <= buffer3[0]; + end + endcase + end + end + end + `LINE_WRITE: + begin + decBufferCnt <= 1'b0; + bufferOutStMachCurrState <= `WAIT_LINE_WRITE; + end + endcase + end +end + +// control 'TxWireActiveDrive' +always @(TxCtrlOut) +begin + if (TxCtrlOut == `DRIVE) + TxWireActiveDrive <= 1'b1; + else + TxWireActiveDrive <= 1'b0; +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbDeviceAlteraTop.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbDeviceAlteraTop.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbDeviceAlteraTop.v (revision 40) @@ -0,0 +1,179 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbDeviceAlteraTop.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Top level module for Altera FPGA and NXP ISP1105 USB PHY. +//// Specifically it targets the Base2Designs Altera Development board. +//// Instantiates a PLL so that the lock signal can be used +//// to reset the logic, and ties unused control signals +//// to the off or disabled state +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// + +module usbDeviceAlteraTop ( + + // + // Global signals + // + clk, + + // + // SDRAM + // + mc_addr, + mc_ba, + mc_dqm, + mc_we_, + mc_cas_, + mc_ras_, + mc_cke_, + sdram_cs, + sdram_clk, + + // + // SPI bus + // + spiClk, + spiMasterDataOut, + spiCS_n, + + + // + // USB host + // + usbHostOE_n, + + // + // USB slave + // + usbSlaveVP, + usbSlaveVM, + usbSlaveOE_n, + usbDPlusPullup, + vBusDetect +); + // + // Global signals + // + input clk; + + // + // SDRAM + // + output [11:0] mc_addr; + output [1:0] mc_ba; + output [3:0] mc_dqm; + output mc_we_; + output mc_cas_; + output mc_ras_; + output mc_cke_; + output sdram_cs; + output sdram_clk; + + // + // SPI bus + // + output spiClk; + output spiMasterDataOut; + output spiCS_n; + + // + // USB host + // + output usbHostOE_n; + + // + // USB slave + // + inout usbSlaveVP; + inout usbSlaveVM; + output usbSlaveOE_n; + output usbDPlusPullup; + input vBusDetect; + +//local wires and regs +reg [1:0] rstReg; +wire rst; +wire pll_locked; + +assign mc_addr = {12{1'b0}}; +assign mc_ba = 2'b00; +assign mc_dqm = 4'h0; +assign mc_we_ = 1'b1; +assign mc_cas_ = 1'b1; +assign mc_ras_ = 1'b1; +assign mc_cke_ = 1'b1; +assign sdram_cs = 1'b1; +assign sdram_clk = 1'b1; +assign spiClk = 1'b0; +assign spiMasterDataOut = 1'b0; +assign spiCS_n = 1'b1; +assign usbHostOE_n = 1'b1; + +pll_48MHz pll_48MHz_inst ( + .inclk0 ( clk ), + .locked( pll_locked) + ); + +//generate sync reset from pll lock signal +always @(posedge clk) begin + rstReg[1:0] <= {rstReg[0], ~pll_locked}; +end +assign rst = rstReg[1]; + + +usbDevice u_usbDevice ( + .clk(clk), + .rst(rst), + .usbSlaveVP_in(usbSlaveVP_in), + .usbSlaveVM_in(usbSlaveVM_in), + .usbSlaveVP_out(usbSlaveVP_out), + .usbSlaveVM_out(usbSlaveVM_out), + .usbSlaveOE_n(usbSlaveOE_n), + .usbDPlusPullup(usbDPlusPullup), + .vBusDetect(vBusDetect) +); + + +assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM}; +assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz; + +endmodule + + Index: Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v (revision 40) @@ -0,0 +1,80 @@ +////////////////////////////////////////////////////////////////////// +// usbHostSlave_h.v +////////////////////////////////////////////////////////////////////// + +`ifdef usbHostSlave_h_vdefined +`else +`define usbHostSlave_h_vdefined + +// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports +// control reads and writes to USB flash dongle +// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect +// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by +// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full +// speed, and TX resume is always low speed. +// Fixed read clock recovery (readUSBWireData.v) issue which was resulting +// in missing receive packets. +// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission) +// by adding kludged delay to softranmit. This needs to be fixed properly. +// This version has undergone limited testing +// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes. +// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested +// with uClinux, and is known to work with a full speed USB flash stick. +// Moving Opencores project status from Beta to done. +// TODO: Test isochronous mode, and low speed mode using uClinux driver +// Create a seperate clock domain for the bus interface +// Add frame period adjustment capability +// Add compilation flags for slave only and host only versions +// Create data bus width options beyond 8-bit +// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock +// Removed TX and RX fifo status registers, and removed +// TX fifo data count register. +// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. +// Fixed slave mode bug which caused receive fifo to be filled with +// incoming data when the slave was responding with a NAK, and the +// data should have been discarded. +// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut' +// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever +// there was no detected activity on the USB data lines. This caused an infrequent +// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when +// the higher level state machines are actively looking for receive packets. +// Modified USB RX data clock recovery, so that data is sampled during the middle +// of a USB bit period. Fixed a bug which could result in double sampling +// of USB RX data if clock phase adjustments were required in the middle of a +// USB packet. +// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required +// during migration to ActiveHDL 7.1. Released SystemC test bench. +// Re-generated .v files using ActiveHDL 7.1 +// Replaced individual timescale directives with `include "timescale.v +// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to +// 'usbHostSlaveAvalonWrap' +// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added +// synchronizer to incoming USB wire data to avoid +// metastability, and delay hazards. Not entirely sure, but it appears that +// this bug caused more problems with some of the newer low power FPGAs +// Maybe because they are more prone to problems with metastable +// inputs that feed logic functions causing excessive high speed +// toggle activity, and disrupting nearby cicuits. +// Version 1.4 - June 16th 2008. Added two new top level modules which +// allow the instantiation of only host (usbHost.v), or only device +// features. Added double sync stages between usbClk, and busClk domains +// to fix possible metastability issues. Also modified synchronization to +// allow operation with busClk frequency less than usbClk frequency (down to +// 24MHz). Integrated full support for USB PHY. Prior to this modification +// the user would need to instantiate a GPIO module to control USB speed, +// D+ and D- pull-up control, and VBUS detect. Fixed bug in BI wb_ack. +// Modified cross-clock synchronisation of fifo resets +// Added usbDevice, a standalone usb device implementation of usbhostslave +// no additional hardware or software required + + +// Most significant nibble corresponds to major revision. +// Least significant nibble corresponds to minor revision. +`define USBHOSTSLAVE_VERSION_NUM 8'h14 + +//Host slave common registers +`define HOST_SLAVE_CONTROL_REG 1'b0 +`define HOST_SLAVE_VERSION_REG 1'b1 + +`endif //usbHostSlave_h_vdefined + Index: Actel/usbDeviceActelTop/hdl/wishBoneBI.v =================================================================== --- Actel/usbDeviceActelTop/hdl/wishBoneBI.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/wishBoneBI.v (revision 40) @@ -0,0 +1,245 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wishBoneBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "wishBoneBus_h.v" + + +module wishBoneBI ( + address, dataIn, dataOut, writeEn, + strobe_i, + ack_o, + clk, rst, + hostControlSel, + hostRxFifoSel, hostTxFifoSel, + slaveControlSel, + slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, + slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, + hostSlaveMuxSel, + dataFromHostControl, + dataFromHostRxFifo, + dataFromHostTxFifo, + dataFromSlaveControl, + dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo, + dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo, + dataFromHostSlaveMux + ); +input clk; +input rst; +input [7:0] address; +input [7:0] dataIn; +output [7:0] dataOut; +input strobe_i; +output ack_o; +input writeEn; +output hostControlSel; +output hostRxFifoSel; +output hostTxFifoSel; +output slaveControlSel; +output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; +output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; +output hostSlaveMuxSel; +input [7:0] dataFromHostControl; +input [7:0] dataFromHostRxFifo; +input [7:0] dataFromHostTxFifo; +input [7:0] dataFromSlaveControl; +input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo; +input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo; +input [7:0] dataFromHostSlaveMux; + + +wire clk; +wire rst; +wire [7:0] address; +wire [7:0] dataIn; +reg [7:0] dataOut; +wire writeEn; +wire strobe_i; +reg ack_o; +reg hostControlSel; +reg hostRxFifoSel; +reg hostTxFifoSel; +reg slaveControlSel; +reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; +reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; +reg hostSlaveMuxSel; +wire [7:0] dataFromHostControl; +wire [7:0] dataFromHostRxFifo; +wire [7:0] dataFromHostTxFifo; +wire [7:0] dataFromSlaveControl; +wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo; +wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo; +wire [7:0] dataFromHostSlaveMux; + +//internal wires and regs +reg ack_delayed; +reg ack_immediate; + +//address decode and data mux +always @(address or + dataFromHostControl or + dataFromHostRxFifo or + dataFromHostTxFifo or + dataFromSlaveControl or + dataFromEP0RxFifo or + dataFromEP1RxFifo or + dataFromEP2RxFifo or + dataFromEP3RxFifo or + dataFromHostSlaveMux or + dataFromEP0TxFifo or + dataFromEP1TxFifo or + dataFromEP2TxFifo or + dataFromEP3TxFifo) +begin + hostControlSel <= 1'b0; + hostRxFifoSel <= 1'b0; + hostTxFifoSel <= 1'b0; + slaveControlSel <= 1'b0; + slaveEP0RxFifoSel <= 1'b0; + slaveEP0TxFifoSel <= 1'b0; + slaveEP1RxFifoSel <= 1'b0; + slaveEP1TxFifoSel <= 1'b0; + slaveEP2RxFifoSel <= 1'b0; + slaveEP2TxFifoSel <= 1'b0; + slaveEP3RxFifoSel <= 1'b0; + slaveEP3TxFifoSel <= 1'b0; + hostSlaveMuxSel <= 1'b0; + case (address & `ADDRESS_DECODE_MASK) + `HCREG_BASE : begin + hostControlSel <= 1'b1; + dataOut <= dataFromHostControl; + end + `HCREG_BASE_PLUS_0X10 : begin + hostControlSel <= 1'b1; + dataOut <= dataFromHostControl; + end + `HOST_RX_FIFO_BASE : begin + hostRxFifoSel <= 1'b1; + dataOut <= dataFromHostRxFifo; + end + `HOST_TX_FIFO_BASE : begin + hostTxFifoSel <= 1'b1; + dataOut <= dataFromHostTxFifo; + end + `SCREG_BASE : begin + slaveControlSel <= 1'b1; + dataOut <= dataFromSlaveControl; + end + `SCREG_BASE_PLUS_0X10 : begin + slaveControlSel <= 1'b1; + dataOut <= dataFromSlaveControl; + end + `EP0_RX_FIFO_BASE : begin + slaveEP0RxFifoSel <= 1'b1; + dataOut <= dataFromEP0RxFifo; + end + `EP0_TX_FIFO_BASE : begin + slaveEP0TxFifoSel <= 1'b1; + dataOut <= dataFromEP0TxFifo; + end + `EP1_RX_FIFO_BASE : begin + slaveEP1RxFifoSel <= 1'b1; + dataOut <= dataFromEP1RxFifo; + end + `EP1_TX_FIFO_BASE : begin + slaveEP1TxFifoSel <= 1'b1; + dataOut <= dataFromEP1TxFifo; + end + `EP2_RX_FIFO_BASE : begin + slaveEP2RxFifoSel <= 1'b1; + dataOut <= dataFromEP2RxFifo; + end + `EP2_TX_FIFO_BASE : begin + slaveEP2TxFifoSel <= 1'b1; + dataOut <= dataFromEP2TxFifo; + end + `EP3_RX_FIFO_BASE : begin + slaveEP3RxFifoSel <= 1'b1; + dataOut <= dataFromEP3RxFifo; + end + `EP3_TX_FIFO_BASE : begin + slaveEP3TxFifoSel <= 1'b1; + dataOut <= dataFromEP3TxFifo; + end + `HOST_SLAVE_CONTROL_BASE : begin + hostSlaveMuxSel <= 1'b1; + dataOut <= dataFromHostSlaveMux; + end + default: + dataOut <= 8'h00; + endcase +end + +//delayed ack +always @(posedge clk) begin + ack_delayed <= strobe_i; +end + +//immediate ack +always @(strobe_i) begin + ack_immediate <= strobe_i; +end + +//select between immediate and delayed ack +always @(writeEn or address or ack_delayed or ack_immediate) begin + if (writeEn == 1'b0 && + (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG || + address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG || + address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) ) + begin + ack_o <= ack_delayed & ack_immediate; + end + else + begin + ack_o <= ack_immediate; + end +end + +endmodule Index: Actel/usbDeviceActelTop/hdl/lineControlUpdate.v =================================================================== --- Actel/usbDeviceActelTop/hdl/lineControlUpdate.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/lineControlUpdate.v (revision 40) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// lineControlUpdate.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + +module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit); +input fullSpeedPolarity; +input fullSpeedBitRate; +output [1:0] JBit; +output [1:0] KBit; + +wire fullSpeedPolarity; +wire fullSpeedBitRate; +reg [1:0] JBit; +reg [1:0] KBit; + + + +always @(fullSpeedPolarity) +begin + if (fullSpeedPolarity == 1'b1) + begin + JBit = `ONE_ZERO; + KBit = `ZERO_ONE; + end + else + begin + JBit = `ZERO_ONE; + KBit = `ONE_ZERO; + end +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v (revision 40) @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////// +// usbSlaveControl.v +////////////////////////////////////////////////////////////////////// + +`ifdef usbSlaveControl_h_vdefined +`else +`define usbSlaveControl_h_vdefined + +//endPointConstants +`define NUM_OF_ENDPOINTS 4 +`define NUM_OF_REGISTERS_PER_ENDPOINT 4 +`define BASE_INDEX_FOR_ENDPOINT_REGS 0 +`define ENDPOINT_CONTROL_REG 0 +`define ENDPOINT_STATUS_REG 1 +`define ENDPOINT_TRANSTYPE_STATUS_REG 2 +`define NAK_TRANSTYPE_STATUS_REG 3 +`define EP0_CTRL_REG 5'h0 +`define EP0_STS_REG 5'h1 +`define EP0_TRAN_TYPE_STS_REG 5'h2 +`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3 +`define EP1_CTRL_REG 5'h4 +`define EP1_STS_REG 5'h5 +`define EP1_TRAN_TYPE_STS_REG 5'h6 +`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7 +`define EP2_CTRL_REG 5'h8 +`define EP2_STS_REG 5'h9 +`define EP2_TRAN_TYPE_STS_REG 5'ha +`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb +`define EP3_CTRL_REG 5'hc +`define EP3_STS_REG 5'hd +`define EP3_TRAN_TYPE_STS_REG 5'he +`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf + + +//SCRegIndices +`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1 +`define SC_CONTROL_REG 5'h10 +`define SC_LINE_STATUS_REG 5'h11 +`define SC_INTERRUPT_STATUS_REG 5'h12 +`define SC_INTERRUPT_MASK_REG 5'h13 +`define SC_ADDRESS 5'h14 +`define SC_FRAME_NUM_MSP 5'h15 +`define SC_FRAME_NUM_LSP 5'h16 +`define SCREG_BUFFER_LEN 5'h17 +//SCRXStatusRegIndices +`define NAK_SET_MASK 8'h10 +`define SC_CRC_ERROR_BIT 0 +`define SC_BIT_STUFF_ERROR_BIT 1 +`define SC_RX_OVERFLOW_BIT 2 +`define SC_RX_TIME_OUT_BIT 3 +`define SC_NAK_SENT_BIT 4 +`define SC_STALL_SENT_BIT 5 +`define SC_ACK_RXED_BIT 6 +`define SC_DATA_SEQUENCE_BIT 7 +//SCEndPointControlRegIndices +`define ENDPOINT_ENABLE_BIT 0 +`define ENDPOINT_READY_BIT 1 +`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2 +`define ENDPOINT_SEND_STALL_BIT 3 +`define ENDPOINT_ISO_ENABLE_BIT 4 +//SCMasterControlegIndices +`define SC_GLOBAL_ENABLE_BIT 0 +`define SC_TX_LINE_STATE_LSBIT 1 +`define SC_TX_LINE_STATE_MSBIT 2 +`define SC_DIRECT_CONTROL_BIT 3 +`define SC_FULL_SPEED_LINE_POLARITY_BIT 4 +`define SC_FULL_SPEED_LINE_RATE_BIT 5 +`define SC_CONNECT_TO_HOST_BIT 6 +//SCinterruptRegIndices +`define TRANS_DONE_BIT 0 +`define RESUME_INT_BIT 1 +`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state +`define SOF_RECEIVED_BIT 3 +`define NAK_SENT_INT_BIT 4 +`define VBUS_DET_INT_BIT 5 +//TXTransactionTypes +`define SC_SETUP_TRANS 0 +`define SC_IN_TRANS 1 +`define SC_OUTDATA_TRANS 2 +//timeOuts +`define SC_RX_PACKET_TOUT 18 + +//line status reg +`define VBUS_PRES_BIT 2 + +`endif //usbSlaveControl_h_vdefined Index: Actel/usbDeviceActelTop/hdl/RxFifo.v =================================================================== --- Actel/usbDeviceActelTop/hdl/RxFifo.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/RxFifo.v (revision 40) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RxFifo.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo read access via bus interface, fifo write access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module RxFifo( + busClk, + usbClk, + rstSyncToBusClk, + rstSyncToUsbClk, + fifoWEn, + fifoFull, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataIn ); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input usbClk; +input rstSyncToBusClk; +input rstSyncToUsbClk; +input fifoWEn; +output fifoFull; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +input [7:0] fifoDataIn; + +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire rstSyncToUsbClk; +wire fifoWEn; +wire fifoFull; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataIn; + +//internal wires and regs +wire [7:0] dataFromFifoToBus; +wire fifoREn; +wire forceEmptySyncToBusClk; +wire forceEmptySyncToUsbClk; +wire [15:0] numElementsInFifo; +wire fifoEmpty; //not used + +fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo( + .wrClk(usbClk), + .rdClk(busClk), + .rstSyncToWrClk(rstSyncToUsbClk), + .rstSyncToRdClk(rstSyncToBusClk), + .dataIn(fifoDataIn), + .dataOut(dataFromFifoToBus), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToUsbClk), + .forceEmptySyncToRdClk(forceEmptySyncToBusClk), + .numElementsInFifo(numElementsInFifo) ); + +RxfifoBI u_RxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .usbClk(usbClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .fifoDataIn(dataFromFifoToBus), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoREn(fifoREn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbROM_logitech_mouse.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbROM_logitech_mouse.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbROM_logitech_mouse.v (revision 40) @@ -0,0 +1,213 @@ +// ----------------------------- usbROM --------------------------- +// if you modify this file, be sure to modify usbDevice_define.v +// Using RAM rather than logic resources might be a more efficient implememtation +// but this has the advantage of working with FPGAs that do not provide a +// mechanism for initialising RAM, eg Actel IGLOO +// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice +`include "usbDevice_define.v" + + +module usbROM ( + clk, + addr, + data +); +input clk; +input [7:0] addr; +output [7:0] data; +reg [7:0] data; + +always @(posedge clk) begin + case (addr) +// ==================================== +// ===== DEVICE Descriptor ===== +// ==================================== + + 8'h00: data <= 8'h12; //BYTE bLength + 8'h01: data <= 8'h01; //BYTE bDescriptorType + 8'h02: data <= 8'h10; //WORD (Lo) bcdUSB version supported + 8'h03: data <= 8'h01; //WORD (Hi) bcdUSB version supported + 8'h04: data <= 8'h00; //BYTE bDeviceClass + 8'h05: data <= 8'h00; //BYTE bDeviceSubClass + 8'h06: data <= 8'h00; //BYTE bDeviceProtocol + 8'h07: data <= `MAX_RESP_SIZE; //BYTE bMaxPacketSize + 8'h08: data <= 8'h6d; //WORD (Lo) idVendor + 8'h09: data <= 8'h04; //WORD (Hi) idVendor + 8'h0a: data <= 8'h3d; //WORD (Lo) idProduct; For Logitech mouse + 8'h0b: data <= 8'hc0; //WORD (Hi) idProduct; For Logitech Hub mouse + 8'h0c: data <= 8'h00; //WORD (Lo) bcdDevice + 8'h0d: data <= 8'h20; //WORD (Hi) bcdDevice + 8'h0e: data <= 8'h01; //BYTE iManufacturer + 8'h0f: data <= 8'h02; //BYTE iProduct + 8'h10: data <= 8'h00; //BYTE iSerialNumber + 8'h11: data <= 8'h01; //BYTE bNumConfigurations + + +// ==================================== +// ===== Configuration Descriptor ===== +// ==================================== + 8'h12: data <= 8'h09; //BYTE bLength (Configuration descriptor) + 8'h13: data <= 8'h02; //BYTE bDescriptorType //Assigned by USB + 8'h14: data <= 8'h22; //WORD (Lo) wTotalLength + 8'h15: data <= 8'h00; //WORD (Hi) wTotalLength + 8'h16: data <= 8'h01; //BYTE bNumInterfaces + 8'h17: data <= 8'h01; //BYTE bConfigurationValue + 8'h18: data <= 8'h00; //BYTE iConfiguration + 8'h19: data <= 8'ha0; //BYTE bmAttributes, Bus powered and remote wakeup + 8'h1a: data <= 8'h31; //BYTE MaxPower, 98mA + +// ==================================== +// ===== Interface Descriptor ===== +// ==================================== + 8'h1b: data <= 8'h09; //BYTE bLength (Interface descriptor) + 8'h1c: data <= 8'h04; //BYTE bDescriptionType; assigned by USB + 8'h1d: data <= 8'h00; //BYTE bInterfaceNumber + 8'h1e: data <= 8'h00; //BYTE bAlternateSetting + 8'h1f: data <= 8'h01; //BYTE bNumEndpoints; uses 1 endpoints + 8'h20: data <= 8'h03; //BYTE bInterfaceClass; HID Class - 0x03 + 8'h21: data <= 8'h01; //BYTE bInterfaceSubClass + 8'h22: data <= 8'h02; //BYTE bInterfaceProtocol + 8'h23: data <= 8'h00; //BYTE iInterface + +// ==================================== +// ===== HID Descriptor ===== +// ==================================== + 8'h24: data <= 8'h09; //BYTE bLength (HID Descriptor) + 8'h25: data <= 8'h21; //BYTE bDescriptorType + 8'h26: data <= 8'h10; //WORD (Lo) bcdHID + 8'h27: data <= 8'h01; //WORD (Hi) bcdHID + 8'h28: data <= 8'h00; //BYTE bCountryCode + 8'h29: data <= 8'h01; //BYTE bNumDescriptors + 8'h2a: data <= 8'h22; //BYTE bReportDescriptorType + 8'h2b: data <= 8'h32; //WORD (Lo) wItemLength + 8'h2c: data <= 8'h00; //WORD (Hi) wItemLength + +// ==================================== +// ===== Endpoint 1 Descriptor ===== +// ==================================== + 8'h2d: data <= 8'h07; //BYTE bLength (Endpoint Descriptor) + 8'h2e: data <= 8'h05; //BYTE bDescriptorType; assigned by USB + 8'h2f: data <= 8'h81; //BYTE bEndpointAddress; IN endpoint; endpoint 1 + 8'h30: data <= 8'h03; //BYTE bmAttributes; Interrupt endpoint + 8'h31: data <= 8'h04; //WORD (Lo) wMaxPacketSize + 8'h32: data <= 8'h00; //WORD (Hi) wMaxPacketSize + 8'h33: data <= 8'h0a; //BYTE bInterval + + +// ==================================== +// ===== Report Descriptor ===== +// ==================================== + + 8'h3a: data <= 8'h05; 8'h3b: data <= 8'h01; // USAGE_PAGE (Generic Desktop) + 8'h3c: data <= 8'h09; 8'h3d: data <= 8'h02; // USAGE (Mouse) + 8'h3e: data <= 8'ha1; 8'h3f: data <= 8'h01; // COLLECTION (Application) + 8'h40: data <= 8'h09; 8'h41: data <= 8'h01; // USAGE (Pointer) + 8'h42: data <= 8'ha1; 8'h43: data <= 8'h00; // COLLECTION (Physical) + 8'h44: data <= 8'h05; 8'h45: data <= 8'h09; // USAGE_PAGE (Button) + 8'h46: data <= 8'h19; 8'h47: data <= 8'h01; // USAGE_MINIMUM (Button 1) + 8'h48: data <= 8'h29; 8'h49: data <= 8'h03; // USAGE_MAXIMUM (Button 3) + 8'h4a: data <= 8'h15; 8'h4b: data <= 8'h00; // LOGICAL_MINIMUM (0) + 8'h4c: data <= 8'h25; 8'h4d: data <= 8'h01; // LOGICAL_MAXIMUM (1) + 8'h4e: data <= 8'h95; 8'h4f: data <= 8'h03; // REPORT_COUNT (3) + 8'h50: data <= 8'h75; 8'h51: data <= 8'h01; // REPORT_SIZE (1) + 8'h52: data <= 8'h81; 8'h53: data <= 8'h02; // INPUT (Data,Var,Abs) + 8'h54: data <= 8'h95; 8'h55: data <= 8'h05; // REPORT_COUNT (5) + 8'h56: data <= 8'h81; 8'h57: data <= 8'h03; // INPUT (Cnst,Var,Rel) + 8'h58: data <= 8'h05; 8'h59: data <= 8'h01; // USAGE_PAGE (Generic Desktop) + 8'h5a: data <= 8'h09; 8'h5b: data <= 8'h30; // USAGE (X) + 8'h5c: data <= 8'h09; 8'h5d: data <= 8'h31; // USAGE (Y) + 8'h5e: data <= 8'h09; 8'h5f: data <= 8'h38; // USAGE ? + 8'h60: data <= 8'h15; 8'h61: data <= 8'h81; // LOGICAL_MINIMUM (-127) + 8'h62: data <= 8'h25; 8'h63: data <= 8'h7f; // LOGICAL_MAXIMUM (127) + 8'h64: data <= 8'h75; 8'h65: data <= 8'h08; // REPORT_SIZE (8) + 8'h66: data <= 8'h95; 8'h67: data <= 8'h03; // REPORT_COUNT (3) + 8'h68: data <= 8'h81; 8'h69: data <= 8'h06; // INPUT (Data,Var,Rel) + 8'h6a: data <= 8'hc0; //END_COLLECTION + 8'h6b: data <= 8'hc0; // END_COLLECTION + +// ZERO_ZERO + 8'h6c: data <= 8'h00; + 8'h6d: data <= 8'h00; +// ONE_ZERO + 8'h6e: data <= 8'h01; + 8'h6f: data <= 8'h00; +// Vendor data + 8'h70: data <= 8'h00; + 8'h71: data <= 8'h00; + +// ============================================= +// ===== Language ID Descriptor(String0) ===== +// ============================================= + 8'h80: data <= 8'h04; // bLength + 8'h81: data <= 8'h03; // bDescriptorType = String Desc + 8'h82: data <= 8'h09; // wLangID (Lo) (Lang ID for English = 0x0409) + 8'h83: data <= 8'h04; // wLangID (Hi) (Lang ID for English = 0x0409) + +// ==================================== +// ===== string 1 Descriptor ===== +// ==================================== + 8'h90: data <= 8'd26; // bLength + 8'h91: data <= 8'h03; // bDescriptorType = String Desc + // Noting that text is always unicode, hence the 'padding' + 8'h92: data <= "B"; 8'h93: data <= 8'h00; + 8'h94: data <= "a"; 8'h95: data <= 8'h00; + 8'h96: data <= "s"; 8'h97: data <= 8'h00; + 8'h98: data <= "e"; 8'h99: data <= 8'h00; + 8'h9a: data <= "2"; 8'h9b: data <= 8'h00; + 8'h9c: data <= "D"; 8'h9d: data <= 8'h00; + 8'h9e: data <= "e"; 8'h9f: data <= 8'h00; + 8'ha0: data <= "s"; 8'ha1: data <= 8'h00; + 8'ha2: data <= "i"; 8'ha3: data <= 8'h00; + 8'ha4: data <= "g"; 8'ha5: data <= 8'h00; + 8'ha6: data <= "n"; 8'ha7: data <= 8'h00; + 8'ha8: data <= "s"; 8'ha9: data <= 8'h00; + + + +// ==================================== +// ===== string 2 Descriptor ===== +// ==================================== + 8'hb0: data <= 8'd20; // bLength + 8'hb1: data <= 8'h03; // bDescriptorType = String Desc + // Noting that text is always unicode, hence the 'padding' + 8'hb2: data <= "B"; 8'hb3: data <= 8'h00; + 8'hb4: data <= "2"; 8'hb5: data <= 8'h00; + 8'hb6: data <= "D"; 8'hb7: data <= 8'h00; + 8'hb8: data <= " "; 8'hb9: data <= 8'h00; + 8'hba: data <= "M"; 8'hbb: data <= 8'h00; + 8'hbc: data <= "o"; 8'hbd: data <= 8'h00; + 8'hbe: data <= "u"; 8'hbf: data <= 8'h00; + 8'hc0: data <= "s"; 8'hc1: data <= 8'h00; + 8'hc2: data <= "e"; 8'hc3: data <= 8'h00; + +// ==================================== +// ===== string 3 Descriptor ===== +// ==================================== + 8'hd0: data <= 8'd30; // bLength + 8'hd1: data <= 8'h03; // bDescriptorType = String Desc + // Noting that text is always unicode, hence the 'padding' + 8'hd2: data <= "L"; 8'hd3: data <= 8'h00; + 8'hd4: data <= "i"; 8'hd5: data <= 8'h00; + 8'hd6: data <= "m"; 8'hd7: data <= 8'h00; + 8'hd8: data <= "i"; 8'hd9: data <= 8'h00; + 8'hda: data <= "t"; 8'hdb: data <= 8'h00; + 8'hdc: data <= "e"; 8'hdd: data <= 8'h00; + 8'hde: data <= "d"; 8'hdf: data <= 8'h00; + 8'he0: data <= "E"; 8'he1: data <= 8'h00; + 8'he2: data <= "d"; 8'he3: data <= 8'h00; + 8'he4: data <= "i"; 8'he5: data <= 8'h00; + 8'he6: data <= "t"; 8'he7: data <= 8'h00; + 8'he8: data <= "i"; 8'he9: data <= 8'h00; + 8'hea: data <= "o"; 8'heb: data <= 8'h00; + 8'hec: data <= "n"; 8'hed: data <= 8'h00; + + + + default: data <= 8'h00; + endcase +end + +endmodule + + + Index: Actel/usbDeviceActelTop/hdl/EP1Mouse.v =================================================================== --- Actel/usbDeviceActelTop/hdl/EP1Mouse.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/EP1Mouse.v (revision 40) @@ -0,0 +1,295 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// EP1Mouse.v //// +//// //// +//// This file is part of the usbHostSlave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Implements EP1 as a IN endpoint +//// simulating a mouse (a broken one) by +//// responding to IN requests with a constant (x,y) <= (1,1) +//// which causes the mouse pointer to move from +//// top left to bottom right of the screen +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbHostSlaveReg_define.v" + +module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq); +input clk; +input initComplete; +input rst; +input wb_ack; +input [7:0]wb_data_i; +input wbBusGnt; +output [7:0]wb_addr; +output [7:0]wb_data_o; +output wb_stb; +output wb_we; +output wbBusReq; + +wire clk; +wire initComplete; +wire rst; +wire wb_ack; +reg [7:0]wb_addr, next_wb_addr; +wire [7:0]wb_data_i; +reg [7:0]wb_data_o, next_wb_data_o; +reg wb_stb, next_wb_stb; +reg wb_we, next_wb_we; +wire wbBusGnt; +reg wbBusReq, next_wbBusReq; + +// diagram signals declarations +reg [7:0]cnt, next_cnt; +reg dataSeq, next_dataSeq; +reg localRst, next_localRst; +reg transDone, next_transDone; + +// BINARY ENCODED state machine: EP1St +// State codes definitions: +`define DO_TRANS_WT_GNT 4'b0000 +`define DO_TRANS_TX_EMPTY 4'b0001 +`define DO_TRANS_WR_TX_FIFO1 4'b0010 +`define DO_TRANS_TRANS_GO 4'b0011 +`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100 +`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101 +`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110 +`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111 +`define START 4'b1000 +`define DO_TRANS_WR_TX_FIFO2 4'b1001 +`define DO_TRANS_WR_TX_FIFO3 4'b1010 +`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011 + +reg [3:0]CurrState_EP1St, NextState_EP1St; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: EP1St + +// NextState logic (combinatorial) +always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St) +begin + NextState_EP1St <= CurrState_EP1St; + // Set default values for outputs and signals + next_wbBusReq <= wbBusReq; + next_wb_addr <= wb_addr; + next_wb_data_o <= wb_data_o; + next_wb_stb <= wb_stb; + next_wb_we <= wb_we; + next_dataSeq <= dataSeq; + next_transDone <= transDone; + next_cnt <= cnt; + case (CurrState_EP1St) // synopsys parallel_case full_case + `START: + begin + next_wbBusReq <= 1'b0; + next_wb_addr <= 8'h00; + next_wb_data_o <= 8'h00; + next_wb_stb <= 1'b0; + next_wb_we <= 1'b0; + next_cnt <= 8'h00; + next_dataSeq <= 1'b0; + next_transDone <= 1'b0; + if (initComplete == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_GNT; + end + end + `DO_TRANS_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_TX_EMPTY; + end + end + `DO_TRANS_TX_EMPTY: + begin + next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG; + next_wb_data_o <= 8'h01; + //force tx fifo empty + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1; + next_wb_stb <= 1'b0; + next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG; + next_wb_we <= 1'b1; + end + end + `DO_TRANS_WR_TX_FIFO1: + begin + next_wb_data_o <= 8'h00; + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_TRANS_GO: + begin + next_wb_addr <= `RA_EP1_CONTROL_REG; + if (dataSeq == 1'b1) + next_wb_data_o <= 8'h07; + else + next_wb_data_o <= 8'h03; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT; + next_wb_stb <= 1'b0; + if (dataSeq == 1'b1) + next_dataSeq <= 1'b0; + else + next_dataSeq <= 1'b1; + next_transDone <= 1'b0; + end + end + `DO_TRANS_WR_TX_FIFO2: + begin + next_wb_data_o <= 8'h01; + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_WR_TX_FIFO3: + begin + next_wb_data_o <= 8'h01; + next_wb_stb <= 1'b1; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_TRANS_GO; + next_wb_stb <= 1'b0; + end + end + `DO_TRANS_WT_TRANS_DONE_WT_GNT: + begin + next_wbBusReq <= 1'b1; + if (wbBusGnt == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS; + end + end + `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS: + begin + next_wb_addr <= `RA_EP1_CONTROL_REG; + next_wb_stb <= 1'b1; + next_wb_we <= 1'b0; + if (wb_ack == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT; + next_wb_stb <= 1'b0; + next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT]; + end + end + `DO_TRANS_WT_TRANS_DONE_WT_UNGNT: + begin + next_wbBusReq <= 1'b0; + if (wbBusGnt == 1'b0) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE; + end + end + `DO_TRANS_WT_TRANS_DONE_CHK_DONE: + begin + if (transDone == 1'b1) + begin + NextState_EP1St <= `DO_TRANS_WT_GNT; + end + else + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL; + next_cnt <= 8'h00; + end + end + `DO_TRANS_WT_TRANS_DONE_DEL: + begin + next_cnt <= cnt + 1'b1; + if (cnt == `ONE_USEC_DEL) + begin + NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_EP1St <= `START; + else + CurrState_EP1St <= NextState_EP1St; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + wbBusReq <= 1'b0; + wb_addr <= 8'h00; + wb_data_o <= 8'h00; + wb_stb <= 1'b0; + wb_we <= 1'b0; + dataSeq <= 1'b0; + transDone <= 1'b0; + cnt <= 8'h00; + end + else + begin + wbBusReq <= next_wbBusReq; + wb_addr <= next_wb_addr; + wb_data_o <= next_wb_data_o; + wb_stb <= next_wb_stb; + wb_we <= next_wb_we; + dataSeq <= next_dataSeq; + transDone <= next_transDone; + cnt <= next_cnt; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/TxFifo.v =================================================================== --- Actel/usbDeviceActelTop/hdl/TxFifo.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/TxFifo.v (revision 40) @@ -0,0 +1,132 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TxFifo.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo write access via bus interface, fifo read access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module TxFifo( + busClk, + usbClk, + rstSyncToBusClk, + rstSyncToUsbClk, + fifoREn, + fifoEmpty, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataOut ); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input usbClk; +input rstSyncToBusClk; +input rstSyncToUsbClk; +input fifoREn; +output fifoEmpty; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +output [7:0] fifoDataOut; + +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire rstSyncToUsbClk; +wire fifoREn; +wire fifoEmpty; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataOut; + +//internal wires and regs +wire fifoWEn; +wire forceEmptySyncToUsbClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoFull; + +fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo( + .wrClk(busClk), + .rdClk(usbClk), + .rstSyncToWrClk(rstSyncToBusClk), + .rstSyncToRdClk(rstSyncToUsbClk), + .dataIn(busDataIn), + .dataOut(fifoDataOut), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToBusClk), + .forceEmptySyncToRdClk(forceEmptySyncToUsbClk), + .numElementsInFifo(numElementsInFifo) ); + +TxfifoBI u_TxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .usbClk(usbClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoWEn(fifoWEn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule Index: Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v =================================================================== --- Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v (revision 40) @@ -0,0 +1,35 @@ +////////////////////////////////////////////////////////////////////// +// wishBoneBus_h.v +////////////////////////////////////////////////////////////////////// + +`ifdef wishBoneBus_h_vdefined +`else +`define wishBoneBus_h_vdefined + +//memoryMap +`define HCREG_BASE 8'h00 +`define HCREG_BASE_PLUS_0X10 8'h10 +`define HOST_RX_FIFO_BASE 8'h20 +`define HOST_TX_FIFO_BASE 8'h30 +`define SCREG_BASE 8'h40 +`define SCREG_BASE_PLUS_0X10 8'h50 +`define EP0_RX_FIFO_BASE 8'h60 +`define EP0_TX_FIFO_BASE 8'h70 +`define EP1_RX_FIFO_BASE 8'h80 +`define EP1_TX_FIFO_BASE 8'h90 +`define EP2_RX_FIFO_BASE 8'ha0 +`define EP2_TX_FIFO_BASE 8'hb0 +`define EP3_RX_FIFO_BASE 8'hc0 +`define EP3_TX_FIFO_BASE 8'hd0 +`define HOST_SLAVE_CONTROL_BASE 8'he0 +`define ADDRESS_DECODE_MASK 8'hf0 + +//FifoAddresses +`define FIFO_DATA_REG 3'b000 +`define FIFO_STATUS_REG 3'b001 +`define FIFO_DATA_COUNT_MSB 3'b010 +`define FIFO_DATA_COUNT_LSB 3'b011 +`define FIFO_CONTROL_REG 3'b100 + +`endif //wishBoneBus_h_vdefined + Index: Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v =================================================================== --- Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v (revision 40) @@ -0,0 +1,714 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// USBSlaveControlBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSlaveControl_h.v" + +module USBSlaveControlBI (address, dataIn, dataOut, writeEn, + strobe_i, + busClk, + rstSyncToBusClk, + usbClk, + rstSyncToUsbClk, + SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut, vBusDetIntOut, + endP0TransTypeReg, endP0NAKTransTypeReg, + endP1TransTypeReg, endP1NAKTransTypeReg, + endP2TransTypeReg, endP2NAKTransTypeReg, + endP3TransTypeReg, endP3NAKTransTypeReg, + endP0ControlReg, + endP1ControlReg, + endP2ControlReg, + endP3ControlReg, + EP0StatusReg, + EP1StatusReg, + EP2StatusReg, + EP3StatusReg, + SCAddrReg, frameNum, + connectStateIn, + vBusDetectIn, + SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn, + slaveControlSelect, + clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready, + TxLineState, + LineDirectControlEn, + fullSpeedPol, + fullSpeedRate, + connectSlaveToHost, + SCGlobalEn + ); +input [4:0] address; +input [7:0] dataIn; +input writeEn; +input strobe_i; +input busClk; +input rstSyncToBusClk; +input usbClk; +input rstSyncToUsbClk; +output [7:0] dataOut; +output SOFRxedIntOut; +output resetEventIntOut; +output resumeIntOut; +output transDoneIntOut; +output NAKSentIntOut; +output vBusDetIntOut; + +input [1:0] endP0TransTypeReg; +input [1:0] endP0NAKTransTypeReg; +input [1:0] endP1TransTypeReg; +input [1:0] endP1NAKTransTypeReg; +input [1:0] endP2TransTypeReg; +input [1:0] endP2NAKTransTypeReg; +input [1:0] endP3TransTypeReg; +input [1:0] endP3NAKTransTypeReg; +output [4:0] endP0ControlReg; +output [4:0] endP1ControlReg; +output [4:0] endP2ControlReg; +output [4:0] endP3ControlReg; +input [7:0] EP0StatusReg; +input [7:0] EP1StatusReg; +input [7:0] EP2StatusReg; +input [7:0] EP3StatusReg; +output [6:0] SCAddrReg; +input [10:0] frameNum; +input [1:0] connectStateIn; +input vBusDetectIn; +input SOFRxedIn; +input resetEventIn; +input resumeIntIn; +input transDoneIn; +input NAKSentIn; +input slaveControlSelect; +input clrEP0Ready; +input clrEP1Ready; +input clrEP2Ready; +input clrEP3Ready; +output [1:0] TxLineState; +output LineDirectControlEn; +output fullSpeedPol; +output fullSpeedRate; +output connectSlaveToHost; +output SCGlobalEn; + +wire [4:0] address; +wire [7:0] dataIn; +wire writeEn; +wire strobe_i; +wire busClk; +wire rstSyncToBusClk; +wire usbClk; +wire rstSyncToUsbClk; +reg [7:0] dataOut; + +reg SOFRxedIntOut; +reg resetEventIntOut; +reg resumeIntOut; +reg transDoneIntOut; +reg NAKSentIntOut; +reg vBusDetIntOut; + +wire [1:0] endP0TransTypeReg; +wire [1:0] endP0NAKTransTypeReg; +wire [1:0] endP1TransTypeReg; +wire [1:0] endP1NAKTransTypeReg; +wire [1:0] endP2TransTypeReg; +wire [1:0] endP2NAKTransTypeReg; +wire [1:0] endP3TransTypeReg; +wire [1:0] endP3NAKTransTypeReg; +reg [4:0] endP0ControlReg; +reg [4:0] endP0ControlReg1; +reg [4:0] endP1ControlReg; +reg [4:0] endP1ControlReg1; +reg [4:0] endP2ControlReg; +reg [4:0] endP2ControlReg1; +reg [4:0] endP3ControlReg; +reg [4:0] endP3ControlReg1; +wire [7:0] EP0StatusReg; +wire [7:0] EP1StatusReg; +wire [7:0] EP2StatusReg; +wire [7:0] EP3StatusReg; +reg [6:0] SCAddrReg; +reg [3:0] TxEndPReg; +wire [10:0] frameNum; +wire [1:0] connectStateIn; + +wire SOFRxedIn; +wire resetEventIn; +wire resumeIntIn; +wire transDoneIn; +wire NAKSentIn; +wire slaveControlSelect; +wire clrEP0Ready; +wire clrEP1Ready; +wire clrEP2Ready; +wire clrEP3Ready; +reg [1:0] TxLineState; +reg [1:0] TxLineState_reg1; +reg LineDirectControlEn; +reg LineDirectControlEn_reg1; +reg fullSpeedPol; +reg fullSpeedPol_reg1; +reg fullSpeedRate; +reg fullSpeedRate_reg1; +reg connectSlaveToHost; +reg connectSlaveToHost_reg1; +reg SCGlobalEn; +reg SCGlobalEn_reg1; + +//internal wire and regs +reg [6:0] SCControlReg; +reg clrVBusDetReq; +reg clrNAKReq; +reg clrSOFReq; +reg clrResetReq; +reg clrResInReq; +reg clrTransDoneReq; +reg SOFRxedInt; +reg resetEventInt; +reg resumeInt; +reg transDoneInt; +reg vBusDetInt; +reg NAKSentInt; +reg [5:0] interruptMaskReg; +reg EP0SetReady; +reg EP1SetReady; +reg EP2SetReady; +reg EP3SetReady; +reg EP0SendStall; +reg EP1SendStall; +reg EP2SendStall; +reg EP3SendStall; +reg EP0IsoEn; +reg EP1IsoEn; +reg EP2IsoEn; +reg EP3IsoEn; +reg EP0DataSequence; +reg EP1DataSequence; +reg EP2DataSequence; +reg EP3DataSequence; +reg EP0Enable; +reg EP1Enable; +reg EP2Enable; +reg EP3Enable; +reg EP0Ready; +reg EP1Ready; +reg EP2Ready; +reg EP3Ready; +reg [2:0] SOFRxedInExtend; +reg [2:0] resetEventInExtend; +reg [2:0] resumeIntInExtend; +reg [2:0] transDoneInExtend; +reg [2:0] NAKSentInExtend; +reg [2:0] clrEP0ReadyExtend; +reg [2:0] clrEP1ReadyExtend; +reg [2:0] clrEP2ReadyExtend; +reg [2:0] clrEP3ReadyExtend; + + +//clock domain crossing sync registers +//STB = Sync To Busclk +reg [4:0] endP0ControlRegSTB; +reg [4:0] endP1ControlRegSTB; +reg [4:0] endP2ControlRegSTB; +reg [4:0] endP3ControlRegSTB; +reg [2:0] NAKSentInSTB; +reg [2:0] SOFRxedInSTB; +reg [2:0] resetEventInSTB; +reg [2:0] resumeIntInSTB; +reg [2:0] transDoneInSTB; +reg [2:0] clrEP0ReadySTB; +reg [2:0] clrEP1ReadySTB; +reg [2:0] clrEP2ReadySTB; +reg [2:0] clrEP3ReadySTB; +reg SCGlobalEnSTB; +reg [1:0] TxLineStateSTB; +reg LineDirectControlEnSTB; +reg fullSpeedPolSTB; +reg fullSpeedRateSTB; +reg connectSlaveToHostSTB; +reg [7:0] EP0StatusRegSTB; +reg [7:0] EP0StatusRegSTB_reg1; +reg [7:0] EP1StatusRegSTB; +reg [7:0] EP1StatusRegSTB_reg1; +reg [7:0] EP2StatusRegSTB; +reg [7:0] EP2StatusRegSTB_reg1; +reg [7:0] EP3StatusRegSTB; +reg [7:0] EP3StatusRegSTB_reg1; +reg [1:0] endP0TransTypeRegSTB; +reg [1:0] endP0TransTypeRegSTB_reg1; +reg [1:0] endP0NAKTransTypeRegSTB; +reg [1:0] endP0NAKTransTypeRegSTB_reg1; +reg [1:0] endP1TransTypeRegSTB; +reg [1:0] endP1TransTypeRegSTB_reg1; +reg [1:0] endP1NAKTransTypeRegSTB; +reg [1:0] endP1NAKTransTypeRegSTB_reg1; +reg [1:0] endP2TransTypeRegSTB; +reg [1:0] endP2TransTypeRegSTB_reg1; +reg [1:0] endP2NAKTransTypeRegSTB; +reg [1:0] endP2NAKTransTypeRegSTB_reg1; +reg [1:0] endP3TransTypeRegSTB; +reg [1:0] endP3TransTypeRegSTB_reg1; +reg [1:0] endP3NAKTransTypeRegSTB; +reg [1:0] endP3NAKTransTypeRegSTB_reg1; +reg [10:0] frameNumSTB; +reg [10:0] frameNumSTB_reg1; +reg [2:0] vBusDetectInSTB; +reg [1:0] connectStateInSTB; +reg [1:0] connectStateInSTB_reg1; + + +//sync write demux +always @(posedge busClk) +begin + if (rstSyncToBusClk == 1'b1) begin + EP0IsoEn <= 1'b0; + EP0SendStall <= 1'b0; + EP0DataSequence <= 1'b0; + EP0Enable <= 1'b0; + EP1IsoEn <= 1'b0; + EP1SendStall <= 1'b0; + EP1DataSequence <= 1'b0; + EP1Enable <= 1'b0; + EP2IsoEn <= 1'b0; + EP2SendStall <= 1'b0; + EP2DataSequence <= 1'b0; + EP2Enable <= 1'b0; + EP3IsoEn <= 1'b0; + EP3SendStall <= 1'b0; + EP3DataSequence <= 1'b0; + EP3Enable <= 1'b0; + SCControlReg <= 7'h00; + SCAddrReg <= 7'h00; + interruptMaskReg <= 6'h00; + end + else begin + clrVBusDetReq <= 1'b0; + clrNAKReq <= 1'b0; + clrSOFReq <= 1'b0; + clrResetReq <= 1'b0; + clrResInReq <= 1'b0; + clrTransDoneReq <= 1'b0; + EP0SetReady <= 1'b0; + EP1SetReady <= 1'b0; + EP2SetReady <= 1'b0; + EP3SetReady <= 1'b0; + if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1) + begin + case (address) + `EP0_CTRL_REG : begin + EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT]; + EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT]; + EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT]; + EP0SetReady <= dataIn[`ENDPOINT_READY_BIT]; + EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT]; + end + `EP1_CTRL_REG : begin + EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT]; + EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT]; + EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT]; + EP1SetReady <= dataIn[`ENDPOINT_READY_BIT]; + EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT]; + end + `EP2_CTRL_REG : begin + EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT]; + EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT]; + EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT]; + EP2SetReady <= dataIn[`ENDPOINT_READY_BIT]; + EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT]; + end + `EP3_CTRL_REG : begin + EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT]; + EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT]; + EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT]; + EP3SetReady <= dataIn[`ENDPOINT_READY_BIT]; + EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT]; + end + `SC_CONTROL_REG : SCControlReg <= dataIn[6:0]; + `SC_ADDRESS : SCAddrReg <= dataIn[6:0]; + `SC_INTERRUPT_STATUS_REG : begin + clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT]; + clrNAKReq <= dataIn[`NAK_SENT_INT_BIT]; + clrSOFReq <= dataIn[`SOF_RECEIVED_BIT]; + clrResetReq <= dataIn[`RESET_EVENT_BIT]; + clrResInReq <= dataIn[`RESUME_INT_BIT]; + clrTransDoneReq <= dataIn[`TRANS_DONE_BIT]; + end + `SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[5:0]; + endcase + end + end +end + +//interrupt control +always @(posedge busClk) +begin + if (rstSyncToBusClk == 1'b1) begin + vBusDetInt <= 1'b0; + NAKSentInt <= 1'b0; + SOFRxedInt <= 1'b0; + resetEventInt <= 1'b0; + resumeInt <= 1'b0; + transDoneInt <= 1'b0; + end + else begin + if (vBusDetectInSTB[0] != vBusDetectInSTB[1]) + vBusDetInt <= 1'b1; + else if (clrVBusDetReq == 1'b1) + vBusDetInt <= 1'b0; + + if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0) + NAKSentInt <= 1'b1; + else if (clrNAKReq == 1'b1) + NAKSentInt <= 1'b0; + + if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0) + SOFRxedInt <= 1'b1; + else if (clrSOFReq == 1'b1) + SOFRxedInt <= 1'b0; + + if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0) + resetEventInt <= 1'b1; + else if (clrResetReq == 1'b1) + resetEventInt <= 1'b0; + + if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0) + resumeInt <= 1'b1; + else if (clrResInReq == 1'b1) + resumeInt <= 1'b0; + + if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0) + transDoneInt <= 1'b1; + else if (clrTransDoneReq == 1'b1) + transDoneInt <= 1'b0; + end +end + +//mask interrupts +always @(*) begin + transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT]; + resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT]; + resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT]; + SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT]; + NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT]; + vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT]; +end + +//end point ready, set/clear +//Since 'busClk' can be a higher freq than 'usbClk', +//'EP0SetReady' etc must be delayed with respect to other control signals, thus +//ensuring that control signals have been clocked through to 'usbClk' clock +//domain before the ready is asserted. +//Not sure this is required because there is at least two 'usbClk' ticks between +//detection of 'EP0Ready' and sampling of related control signals. +always @(posedge busClk) +begin + if (rstSyncToBusClk == 1'b1) begin + EP0Ready <= 1'b0; + EP1Ready <= 1'b0; + EP2Ready <= 1'b0; + EP3Ready <= 1'b0; + end + else begin + if (EP0SetReady == 1'b1) + EP0Ready <= 1'b1; + else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0) + EP0Ready <= 1'b0; + + if (EP1SetReady == 1'b1) + EP1Ready <= 1'b1; + else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0) + EP1Ready <= 1'b0; + + if (EP2SetReady == 1'b1) + EP2Ready <= 1'b1; + else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0) + EP2Ready <= 1'b0; + + if (EP3SetReady == 1'b1) + EP3Ready <= 1'b1; + else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0) + EP3Ready <= 1'b0; + end +end + +//break out control signals +always @(SCControlReg) begin + SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT]; + TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT]; + LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT]; + fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; + fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT]; + connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT]; +end + +//combine endpoint control signals +always @(*) +begin + endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable}; + endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable}; + endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable}; + endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable}; +end + + +// async read mux +always @(*) +begin + case (address) + `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB; + `EP0_STS_REG : dataOut <= EP0StatusRegSTB; + `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB; + `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB; + `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB; + `EP1_STS_REG : dataOut <= EP1StatusRegSTB; + `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB; + `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB; + `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB; + `EP2_STS_REG : dataOut <= EP2StatusRegSTB; + `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB; + `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB; + `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB; + `EP3_STS_REG : dataOut <= EP3StatusRegSTB; + `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB; + `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB; + `SC_CONTROL_REG : dataOut <= SCControlReg; + `SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB}; + `SC_INTERRUPT_STATUS_REG : dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt}; + `SC_INTERRUPT_MASK_REG : dataOut <= {2'b00, interruptMaskReg}; + `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg}; + `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]}; + `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0]; + default: dataOut <= 8'h00; + endcase +end + + +//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick +//pulses to 3 tick pulses +always @(posedge usbClk) begin + if (rstSyncToUsbClk == 1'b1) begin + SOFRxedInExtend <= 3'b000; + resetEventInExtend <= 3'b000; + resumeIntInExtend <= 3'b000; + transDoneInExtend <= 3'b000; + NAKSentInExtend <= 3'b000; + clrEP0ReadyExtend <= 3'b000; + clrEP1ReadyExtend <= 3'b000; + clrEP2ReadyExtend <= 3'b000; + clrEP3ReadyExtend <= 3'b000; + end + else begin + if (SOFRxedIn == 1'b1) + SOFRxedInExtend <= 3'b111; + else + SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]}; + if (resetEventIn == 1'b1) + resetEventInExtend <= 3'b111; + else + resetEventInExtend <= {1'b0, resetEventInExtend[2:1]}; + if (resumeIntIn == 1'b1) + resumeIntInExtend <= 3'b111; + else + resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]}; + if (transDoneIn == 1'b1) + transDoneInExtend <= 3'b111; + else + transDoneInExtend <= {1'b0, transDoneInExtend[2:1]}; + if (NAKSentIn == 1'b1) + NAKSentInExtend <= 3'b111; + else + NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]}; + if (clrEP0Ready == 1'b1) + clrEP0ReadyExtend <= 3'b111; + else + clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]}; + if (clrEP1Ready == 1'b1) + clrEP1ReadyExtend <= 3'b111; + else + clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]}; + if (clrEP2Ready == 1'b1) + clrEP2ReadyExtend <= 3'b111; + else + clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]}; + if (clrEP3Ready == 1'b1) + clrEP3ReadyExtend <= 3'b111; + else + clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]}; + end +end + +//re-sync from busClk to usbClk. +always @(posedge usbClk) begin + if (rstSyncToUsbClk == 1'b1) begin + endP0ControlReg <= {5{1'b0}}; + endP0ControlReg1 <= {5{1'b0}}; + endP1ControlReg <= {5{1'b0}}; + endP1ControlReg1 <= {5{1'b0}}; + endP2ControlReg <= {5{1'b0}}; + endP2ControlReg1 <= {5{1'b0}}; + endP3ControlReg <= {5{1'b0}}; + endP3ControlReg1 <= {5{1'b0}}; + SCGlobalEn <= 1'b0; + SCGlobalEn_reg1 <= 1'b0; + TxLineState <= 2'b00; + TxLineState_reg1 <= 2'b00; + LineDirectControlEn <= 1'b0; + LineDirectControlEn_reg1 <= 1'b0; + fullSpeedPol <= 1'b0; + fullSpeedPol_reg1 <= 1'b0; + fullSpeedRate <= 1'b0; + fullSpeedRate_reg1 <= 1'b0; + connectSlaveToHost <= 1'b0; + connectSlaveToHost_reg1 <= 1'b0; + end + else begin + endP0ControlReg1 <= endP0ControlRegSTB; + endP0ControlReg <= endP0ControlReg1; + endP1ControlReg1 <= endP1ControlRegSTB; + endP1ControlReg <= endP1ControlReg1; + endP2ControlReg1 <= endP2ControlRegSTB; + endP2ControlReg <= endP2ControlReg1; + endP3ControlReg1 <= endP3ControlRegSTB; + endP3ControlReg <= endP3ControlReg1; + SCGlobalEn_reg1 <= SCGlobalEnSTB; + SCGlobalEn <= SCGlobalEn_reg1; + TxLineState_reg1 <= TxLineStateSTB; + TxLineState <= TxLineState_reg1; + LineDirectControlEn_reg1 <= LineDirectControlEnSTB; + LineDirectControlEn <= LineDirectControlEn_reg1; + fullSpeedPol_reg1 <= fullSpeedPolSTB; + fullSpeedPol <= fullSpeedPol_reg1; + fullSpeedRate_reg1 <= fullSpeedRateSTB; + fullSpeedRate <= fullSpeedRate_reg1; + connectSlaveToHost_reg1 <= connectSlaveToHostSTB; + connectSlaveToHost <= connectSlaveToHost_reg1; + end +end + +//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc +//are only asserted for 3 usbClk ticks +//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + vBusDetectInSTB <= 3'b000; + NAKSentInSTB <= 3'b000; + SOFRxedInSTB <= 3'b000; + resetEventInSTB <= 3'b000; + resumeIntInSTB <= 3'b000; + transDoneInSTB <= 3'b000; + clrEP0ReadySTB <= 3'b000; + clrEP1ReadySTB <= 3'b000; + clrEP2ReadySTB <= 3'b000; + clrEP3ReadySTB <= 3'b000; + EP0StatusRegSTB <= 8'h00; + EP0StatusRegSTB_reg1 <= 8'h00; + EP1StatusRegSTB <= 8'h00; + EP1StatusRegSTB_reg1 <= 8'h00; + EP2StatusRegSTB <= 8'h00; + EP2StatusRegSTB_reg1 <= 8'h00; + EP3StatusRegSTB <= 8'h00; + EP3StatusRegSTB_reg1 <= 8'h00; + endP0TransTypeRegSTB <= 2'b00; + endP0TransTypeRegSTB_reg1 <= 2'b00; + endP1TransTypeRegSTB <= 2'b00; + endP1TransTypeRegSTB_reg1 <= 2'b00; + endP2TransTypeRegSTB <= 2'b00; + endP2TransTypeRegSTB_reg1 <= 2'b00; + endP3TransTypeRegSTB <= 2'b00; + endP3TransTypeRegSTB_reg1 <= 2'b00; + endP0NAKTransTypeRegSTB <= 2'b00; + endP0NAKTransTypeRegSTB_reg1 <= 2'b00; + endP1NAKTransTypeRegSTB <= 2'b00; + endP1NAKTransTypeRegSTB_reg1 <= 2'b00; + endP2NAKTransTypeRegSTB <= 2'b00; + endP2NAKTransTypeRegSTB_reg1 <= 2'b00; + endP3NAKTransTypeRegSTB <= 2'b00; + endP3NAKTransTypeRegSTB_reg1 <= 2'b00; + frameNumSTB <= {11{1'b0}}; + frameNumSTB_reg1 <= {11{1'b0}}; + connectStateInSTB <= 2'b00; + connectStateInSTB_reg1 <= 2'b00; + end + else begin + vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]}; + NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]}; + SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]}; + resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]}; + resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]}; + transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]}; + clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]}; + clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]}; + clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]}; + clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]}; + EP0StatusRegSTB_reg1 <= EP0StatusReg; + EP0StatusRegSTB <= EP0StatusRegSTB_reg1; + EP1StatusRegSTB_reg1 <= EP1StatusReg; + EP1StatusRegSTB <= EP1StatusRegSTB_reg1; + EP2StatusRegSTB_reg1 <= EP2StatusReg; + EP2StatusRegSTB <= EP2StatusRegSTB_reg1; + EP3StatusRegSTB_reg1 <= EP3StatusReg; + EP3StatusRegSTB <= EP3StatusRegSTB_reg1; + endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg; + endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1; + endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg; + endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1; + endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg; + endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1; + endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg; + endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1; + endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg; + endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1; + endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg; + endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1; + endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg; + endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1; + endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg; + endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1; + frameNumSTB_reg1 <= frameNum; + frameNumSTB <= frameNumSTB_reg1; + connectStateInSTB_reg1 <= connectStateIn; + connectStateInSTB <= connectStateInSTB_reg1; + end +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/wishboneArb.v =================================================================== --- Actel/usbDeviceActelTop/hdl/wishboneArb.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/wishboneArb.v (revision 40) @@ -0,0 +1,218 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wishboneArb.v //// +//// //// +//// This file is part of the usbHostSlave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Arbitrate between 3 wishbone bus controllers +//// Uses Round Robin access controller +//// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +module wishboneArb ( + clk, + rst, + + addr0_i, + data0_i, + stb0_i, + we0_i, + req0, + gnt0, + + addr1_i, + data1_i, + stb1_i, + we1_i, + req1, + gnt1, + + addr2_i, + data2_i, + stb2_i, + we2_i, + req2, + gnt2, + + + addr_o, + data_o, + stb_o, + we_o +); + +input clk; +input rst; + +input [7:0] addr0_i; +input [7:0] data0_i; +input stb0_i; +input we0_i; +input req0; +output gnt0; +reg gnt0; + +input [7:0] addr1_i; +input [7:0] data1_i; +input stb1_i; +input we1_i; +input req1; +output gnt1; +reg gnt1; + +input [7:0] addr2_i; +input [7:0] data2_i; +input stb2_i; +input we2_i; +input req2; +output gnt2; +reg gnt2; + + +output [7:0] addr_o; +reg [7:0] addr_o; +output [7:0] data_o; +reg [7:0] data_o; +output stb_o; +reg stb_o; +output we_o; +reg we_o; + +//local wires and regs +reg [1:0] muxSel; +reg [2:0] arbSt; + +`define REQ_0 3'b000 +`define REQ_1 3'b001 +`define REQ_2 3'b010 +`define GNT_0 3'b011 +`define GNT_1 3'b100 +`define GNT_2 3'b101 + + +//arb +always @(posedge clk) begin + if (rst == 1'b1) begin + gnt0 <= 1'b0; + gnt1 <= 1'b0; + gnt2 <= 1'b0; + muxSel <= 2'b00; + arbSt <= `REQ_0; + end + else begin + case (arbSt) + `REQ_0: begin + if (req0 == 1'b1) + arbSt <= `GNT_0; + else + arbSt <= `REQ_1; + end + `REQ_1: begin + if (req1 == 1'b1) + arbSt <= `GNT_1; + else + arbSt <= `REQ_2; + end + `REQ_2: begin + if (req2 == 1'b1) + arbSt <= `GNT_2; + else + arbSt <= `REQ_0; + end + `GNT_0: begin + gnt0 <= 1'b1; + muxSel <= 2'b00; + if (req0 == 1'b0) begin + arbSt <= `REQ_1; + gnt0 <= 1'b0; + end + end + `GNT_1: begin + gnt1 <= 1'b1; + muxSel <= 2'b01; + if (req1 == 1'b0) begin + arbSt <= `REQ_2; + gnt1 <= 1'b0; + end + end + `GNT_2: begin + gnt2 <= 1'b1; + muxSel <= 2'b10; + if (req2 == 1'b0) begin + arbSt <= `REQ_0; + gnt2 <= 1'b0; + end + end + endcase + end +end + + +//mux +always @(*) begin + case (muxSel) + 2'b00: begin + addr_o <= addr0_i; + data_o <= data0_i; + stb_o <= stb0_i; + we_o <= we0_i; + end + 2'b01: begin + addr_o <= addr1_i; + data_o <= data1_i; + stb_o <= stb1_i; + we_o <= we1_i; + end + 2'b10: begin + addr_o <= addr2_i; + data_o <= data2_i; + stb_o <= stb2_i; + we_o <= we2_i; + end + default: begin + addr_o <= addr0_i; + data_o <= data0_i; + stb_o <= stb0_i; + we_o <= we0_i; + end + endcase +end + + +endmodule + Index: Actel/usbDeviceActelTop/hdl/siereceiver.v =================================================================== --- Actel/usbDeviceActelTop/hdl/siereceiver.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/siereceiver.v (revision 40) @@ -0,0 +1,283 @@ + +// File : ../RTL/serialInterfaceEngine/siereceiver.v +// Generated : 11/10/06 05:37:23 +// From : ../RTL/serialInterfaceEngine/siereceiver.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// SIEReceiver +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + + +module SIEReceiver (RxWireDataIn, RxWireDataWEn, clk, connectState, rst); +input [1:0] RxWireDataIn; +input RxWireDataWEn; +input clk; +input rst; +output [1:0] connectState; + +wire [1:0] RxWireDataIn; +wire RxWireDataWEn; +wire clk; +reg [1:0] connectState, next_connectState; +wire rst; + +// diagram signals declarations +reg [3:0]RXStMachCurrState, next_RXStMachCurrState; +reg [7:0]RXWaitCount, next_RXWaitCount; +reg [1:0]RxBits, next_RxBits; + +// BINARY ENCODED state machine: rcvr +// State codes definitions: +`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000 +`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001 +`define LS_CONN_CHK_RX_BITS 4'b0010 +`define DISCNCT_CHK_RXBITS 4'b0011 +`define WAIT_BIT 4'b0100 +`define START_SRX 4'b0101 +`define FS_CONN_CHK_RX_BITS1 4'b0110 +`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111 +`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000 + +reg [3:0] CurrState_rcvr; +reg [3:0] NextState_rcvr; + + +//-------------------------------------------------------------------- +// Machine: rcvr +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr) +begin : rcvr_NextState + NextState_rcvr <= CurrState_rcvr; + // Set default values for outputs and signals + next_RxBits <= RxBits; + next_RXStMachCurrState <= RXStMachCurrState; + next_RXWaitCount <= RXWaitCount; + next_connectState <= connectState; + case (CurrState_rcvr) + `WAIT_BIT: + if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST)) + begin + NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS; + next_RxBits <= RxWireDataIn; + end + else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST)) + begin + NextState_rcvr <= `LS_CONN_CHK_RX_BITS; + next_RxBits <= RxWireDataIn; + end + else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST)) + begin + NextState_rcvr <= `FS_CONN_CHK_RX_BITS1; + next_RxBits <= RxWireDataIn; + end + else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST)) + begin + NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS; + next_RxBits <= RxWireDataIn; + end + else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST)) + begin + NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2; + next_RxBits <= RxWireDataIn; + end + else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST)) + begin + NextState_rcvr <= `DISCNCT_CHK_RXBITS; + next_RxBits <= RxWireDataIn; + end + else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST)) + begin + NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS; + next_RxBits <= RxWireDataIn; + end + `START_SRX: + begin + next_RXStMachCurrState <= `DISCONNECT_ST; + next_RXWaitCount <= 8'h00; + next_connectState <= `DISCONNECT; + next_RxBits <= 2'b00; + NextState_rcvr <= `WAIT_BIT; + end + `DISCNCT_CHK_RXBITS: + if (RxBits == `ZERO_ONE) + begin + NextState_rcvr <= `WAIT_BIT; + next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST; + next_RXWaitCount <= 8'h00; + end + else if (RxBits == `ONE_ZERO) + begin + NextState_rcvr <= `WAIT_BIT; + next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST; + next_RXWaitCount <= 8'h00; + end + else + NextState_rcvr <= `WAIT_BIT; + `WAIT_FS_CONN_CHK_RX_BITS: + begin + if (RxBits == `ONE_ZERO) + begin + next_RXWaitCount <= RXWaitCount + 1'b1; + if (RXWaitCount == `CONNECT_WAIT_TIME) + begin + next_connectState <= `FULL_SPEED_CONNECT; + next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST; + end + end + else + begin + next_RXStMachCurrState <= `DISCONNECT_ST; + end + NextState_rcvr <= `WAIT_BIT; + end + `WAIT_LS_CONN_CHK_RX_BITS: + begin + if (RxBits == `ZERO_ONE) + begin + next_RXWaitCount <= RXWaitCount + 1'b1; + if (RXWaitCount == `CONNECT_WAIT_TIME) + begin + next_connectState <= `LOW_SPEED_CONNECT; + next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST; + end + end + else + begin + next_RXStMachCurrState <= `DISCONNECT_ST; + end + NextState_rcvr <= `WAIT_BIT; + end + `LS_CONN_CHK_RX_BITS: + begin + NextState_rcvr <= `WAIT_BIT; + if (RxBits == `SE0) + begin + next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST; + next_RXWaitCount <= 0; + end + end + `FS_CONN_CHK_RX_BITS1: + begin + NextState_rcvr <= `WAIT_BIT; + if (RxBits == `SE0) + begin + next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST; + next_RXWaitCount <= 0; + end + end + `WAIT_LS_DIS_CHK_RX_BITS: + begin + NextState_rcvr <= `WAIT_BIT; + if (RxBits == `SE0) + begin + next_RXWaitCount <= RXWaitCount + 1'b1; + if (RXWaitCount == `DISCONNECT_WAIT_TIME) + begin + next_RXStMachCurrState <= `DISCONNECT_ST; + next_connectState <= `DISCONNECT; + end + end + else + begin + next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST; + end + end + `WAIT_FS_DIS_CHK_RX_BITS2: + begin + NextState_rcvr <= `WAIT_BIT; + if (RxBits == `SE0) + begin + next_RXWaitCount <= RXWaitCount + 1'b1; + if (RXWaitCount == `DISCONNECT_WAIT_TIME) + begin + next_RXStMachCurrState <= `DISCONNECT_ST; + next_connectState <= `DISCONNECT; + end + end + else + begin + next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST; + end + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : rcvr_CurrentState + if (rst) + CurrState_rcvr <= `START_SRX; + else + CurrState_rcvr <= NextState_rcvr; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : rcvr_RegOutput + if (rst) + begin + RXStMachCurrState <= `DISCONNECT_ST; + RXWaitCount <= 8'h00; + RxBits <= 2'b00; + connectState <= `DISCONNECT; + end + else + begin + RXStMachCurrState <= next_RXStMachCurrState; + RXWaitCount <= next_RXWaitCount; + RxBits <= next_RxBits; + connectState <= next_connectState; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/fifoRTL.v =================================================================== --- Actel/usbDeviceActelTop/hdl/fifoRTL.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/fifoRTL.v (revision 40) @@ -0,0 +1,164 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// fifoRTL.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, + dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, + forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo); +//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +// Two clock domains within this module +// These ports are within 'wrClk' domain +input wrClk; +input rstSyncToWrClk; +input [FIFO_WIDTH-1:0] dataIn; +input fifoWEn; +input forceEmptySyncToWrClk; +output fifoFull; + +// These ports are within 'rdClk' domain +input rdClk; +input rstSyncToRdClk; +output [FIFO_WIDTH-1:0] dataOut; +input fifoREn; +input forceEmptySyncToRdClk; +output fifoEmpty; +output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536 + +wire wrClk; +wire rdClk; +wire rstSyncToWrClk; +wire rstSyncToRdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire fifoWEn; +wire fifoREn; +reg fifoFull; +reg fifoEmpty; +wire forceEmpty; +reg [15:0]numElementsInFifo; + + +// local registers +reg [ADDR_WIDTH:0]bufferInIndex; +reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk; +reg [ADDR_WIDTH:0]bufferOutIndex; +reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk; +reg [ADDR_WIDTH-1:0]bufferInIndexToMem; +reg [ADDR_WIDTH-1:0]bufferOutIndexToMem; +reg [ADDR_WIDTH:0]bufferCnt; +reg fifoREnDelayed; +wire [FIFO_WIDTH-1:0] dataFromMem; + +always @(posedge wrClk) +begin + bufferOutIndexSyncToWrClk <= bufferOutIndex; + if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1) + begin + fifoFull <= 1'b0; + bufferInIndex <= 0; + end + else + begin + if (fifoWEn == 1'b1) begin + bufferInIndex <= bufferInIndex + 1'b1; + end + if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) && + (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) ) + fifoFull <= 1'b1; + else + fifoFull <= 1'b0; + end +end + +always @(bufferInIndexSyncToRdClk or bufferOutIndex) + bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex; + +always @(posedge rdClk) +begin + numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes + bufferInIndexSyncToRdClk <= bufferInIndex; + if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1) + begin + fifoEmpty <= 1'b1; + bufferOutIndex <= 0; + fifoREnDelayed <= 1'b0; + end + else + begin + fifoREnDelayed <= fifoREn; + if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin + dataOut <= dataFromMem; + bufferOutIndex <= bufferOutIndex + 1'b1; + end + if (bufferInIndexSyncToRdClk == bufferOutIndex) + fifoEmpty <= 1'b1; + else + fifoEmpty <= 1'b0; + end +end + + +always @(bufferInIndex or bufferOutIndex) begin + bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0]; + bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0]; +end + +dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc ( + .addrIn(bufferInIndexToMem), + .addrOut(bufferOutIndexToMem), + .wrClk(wrClk), + .rdClk(rdClk), + .dataIn(dataIn), + .writeEn(fifoWEn), + .readEn(fifoREn), + .dataOut(dataFromMem)); + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v (revision 40) @@ -0,0 +1,213 @@ + +// File : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v +// Generated : 11/10/06 05:37:24 +// From : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// usbTxWireArbiter +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "usbConstants_h.v" +`include "usbSerialInterfaceEngine_h.v" + + + +module USBTxWireArbiter (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst); +input SIETxCtrl; +input [1:0] SIETxData; +input SIETxFSRate; +input SIETxReq; +input SIETxWEn; +input USBWireRdyIn; +input clk; +input prcTxByteCtrl; +input [1:0] prcTxByteData; +input prcTxByteFSRate; +input prcTxByteReq; +input prcTxByteWEn; +input rst; +output SIETxGnt; +output [1:0] TxBits; +output TxCtl; +output TxFSRate; +output USBWireRdyOut; +output USBWireWEn; +output prcTxByteGnt; + +wire SIETxCtrl; +wire [1:0] SIETxData; +wire SIETxFSRate; +reg SIETxGnt, next_SIETxGnt; +wire SIETxReq; +wire SIETxWEn; +reg [1:0] TxBits, next_TxBits; +reg TxCtl, next_TxCtl; +reg TxFSRate, next_TxFSRate; +wire USBWireRdyIn; +reg USBWireRdyOut, next_USBWireRdyOut; +reg USBWireWEn, next_USBWireWEn; +wire clk; +wire prcTxByteCtrl; +wire [1:0] prcTxByteData; +wire prcTxByteFSRate; +reg prcTxByteGnt, next_prcTxByteGnt; +wire prcTxByteReq; +wire prcTxByteWEn; +wire rst; + +// diagram signals declarations +reg muxSIENotPTXB, next_muxSIENotPTXB; + +// BINARY ENCODED state machine: txWireArb +// State codes definitions: +`define START_TARB 2'b00 +`define TARB_WAIT_REQ 2'b01 +`define PTXB_ACT 2'b10 +`define SIE_TX_ACT 2'b11 + +reg [1:0] CurrState_txWireArb; +reg [1:0] NextState_txWireArb; + +// Diagram actions (continuous assignments allowed only: assign ...) + +// processTxByte/SIETransmitter mux +always @(USBWireRdyIn) +begin + USBWireRdyOut <= USBWireRdyIn; +end +always @(muxSIENotPTXB or SIETxWEn or SIETxData or +SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or +SIETxFSRate or prcTxByteFSRate) +begin + if (muxSIENotPTXB == 1'b1) + begin + USBWireWEn <= SIETxWEn; + TxBits <= SIETxData; + TxCtl <= SIETxCtrl; + TxFSRate <= SIETxFSRate; + end + else + begin + USBWireWEn <= prcTxByteWEn; + TxBits <= prcTxByteData; + TxCtl <= prcTxByteCtrl; + TxFSRate <= prcTxByteFSRate; + end +end + +//-------------------------------------------------------------------- +// Machine: txWireArb +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb) +begin : txWireArb_NextState + NextState_txWireArb <= CurrState_txWireArb; + // Set default values for outputs and signals + next_prcTxByteGnt <= prcTxByteGnt; + next_muxSIENotPTXB <= muxSIENotPTXB; + next_SIETxGnt <= SIETxGnt; + case (CurrState_txWireArb) + `START_TARB: + NextState_txWireArb <= `TARB_WAIT_REQ; + `TARB_WAIT_REQ: + if (prcTxByteReq == 1'b1) + begin + NextState_txWireArb <= `PTXB_ACT; + next_prcTxByteGnt <= 1'b1; + next_muxSIENotPTXB <= 1'b0; + end + else if (SIETxReq == 1'b1) + begin + NextState_txWireArb <= `SIE_TX_ACT; + next_SIETxGnt <= 1'b1; + next_muxSIENotPTXB <= 1'b1; + end + `PTXB_ACT: + if (prcTxByteReq == 1'b0) + begin + NextState_txWireArb <= `TARB_WAIT_REQ; + next_prcTxByteGnt <= 1'b0; + end + `SIE_TX_ACT: + if (SIETxReq == 1'b0) + begin + NextState_txWireArb <= `TARB_WAIT_REQ; + next_SIETxGnt <= 1'b0; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : txWireArb_CurrentState + if (rst) + CurrState_txWireArb <= `START_TARB; + else + CurrState_txWireArb <= NextState_txWireArb; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : txWireArb_RegOutput + if (rst) + begin + muxSIENotPTXB <= 1'b0; + prcTxByteGnt <= 1'b0; + SIETxGnt <= 1'b0; + end + else + begin + muxSIENotPTXB <= next_muxSIENotPTXB; + prcTxByteGnt <= next_prcTxByteGnt; + SIETxGnt <= next_SIETxGnt; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/timescale.v =================================================================== --- Actel/usbDeviceActelTop/hdl/timescale.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/timescale.v (revision 40) @@ -0,0 +1,5 @@ +////////////////////////////////////////////////////////////////////// +// timescale.v +////////////////////////////////////////////////////////////////////// +`timescale 1ns / 1ps + Index: Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v =================================================================== --- Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v (revision 40) @@ -0,0 +1,197 @@ + +// File : ../RTL/slaveController/slaveDirectcontrol.v +// Generated : 11/10/06 05:37:25 +// From : ../RTL/slaveController/slaveDirectcontrol.asf +// By : FSM2VHDL ver. 5.0.0.9 + +////////////////////////////////////////////////////////////////////// +//// //// +//// slaveDirectControl +//// //// +//// This file is part of the usbhostslave opencores effort. +//// http://www.opencores.org/cores/usbhostslave/ //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// +`include "timescale.v" +`include "usbSerialInterfaceEngine_h.v" + +module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst); +input SCTxPortGnt; +input SCTxPortRdy; +input clk; +input directControlEn; +input [1:0] directControlLineState; +input rst; +output [7:0] SCTxPortCntl; +output [7:0] SCTxPortData; +output SCTxPortReq; +output SCTxPortWEn; + +reg [7:0] SCTxPortCntl, next_SCTxPortCntl; +reg [7:0] SCTxPortData, next_SCTxPortData; +wire SCTxPortGnt; +wire SCTxPortRdy; +reg SCTxPortReq, next_SCTxPortReq; +reg SCTxPortWEn, next_SCTxPortWEn; +wire clk; +wire directControlEn; +wire [1:0] directControlLineState; +wire rst; + +// BINARY ENCODED state machine: slvDrctCntl +// State codes definitions: +`define START_SDC 3'b000 +`define CHK_DRCT_CNTL 3'b001 +`define DRCT_CNTL_WAIT_GNT 3'b010 +`define DRCT_CNTL_CHK_LOOP 3'b011 +`define DRCT_CNTL_WAIT_RDY 3'b100 +`define IDLE_FIN 3'b101 +`define IDLE_WAIT_GNT 3'b110 +`define IDLE_WAIT_RDY 3'b111 + +reg [2:0] CurrState_slvDrctCntl; +reg [2:0] NextState_slvDrctCntl; + +// Diagram actions (continuous assignments allowed only: assign ...) + +// diagram ACTION + +//-------------------------------------------------------------------- +// Machine: slvDrctCntl +//-------------------------------------------------------------------- +//---------------------------------- +// Next State Logic (combinatorial) +//---------------------------------- +always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl) +begin : slvDrctCntl_NextState + NextState_slvDrctCntl <= CurrState_slvDrctCntl; + // Set default values for outputs and signals + next_SCTxPortReq <= SCTxPortReq; + next_SCTxPortWEn <= SCTxPortWEn; + next_SCTxPortData <= SCTxPortData; + next_SCTxPortCntl <= SCTxPortCntl; + case (CurrState_slvDrctCntl) + `START_SDC: + NextState_slvDrctCntl <= `CHK_DRCT_CNTL; + `CHK_DRCT_CNTL: + if (directControlEn == 1'b1) + begin + NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT; + next_SCTxPortReq <= 1'b1; + end + else + begin + NextState_slvDrctCntl <= `IDLE_WAIT_GNT; + next_SCTxPortReq <= 1'b1; + end + `DRCT_CNTL_WAIT_GNT: + if (SCTxPortGnt == 1'b1) + NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY; + `DRCT_CNTL_CHK_LOOP: + begin + next_SCTxPortWEn <= 1'b0; + if (directControlEn == 1'b0) + begin + NextState_slvDrctCntl <= `CHK_DRCT_CNTL; + next_SCTxPortReq <= 1'b0; + end + else + NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY; + end + `DRCT_CNTL_WAIT_RDY: + if (SCTxPortRdy == 1'b1) + begin + NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP; + next_SCTxPortWEn <= 1'b1; + next_SCTxPortData <= {6'b000000, directControlLineState}; + next_SCTxPortCntl <= `TX_DIRECT_CONTROL; + end + `IDLE_FIN: + begin + next_SCTxPortWEn <= 1'b0; + next_SCTxPortReq <= 1'b0; + NextState_slvDrctCntl <= `CHK_DRCT_CNTL; + end + `IDLE_WAIT_GNT: + if (SCTxPortGnt == 1'b1) + NextState_slvDrctCntl <= `IDLE_WAIT_RDY; + `IDLE_WAIT_RDY: + if (SCTxPortRdy == 1'b1) + begin + NextState_slvDrctCntl <= `IDLE_FIN; + next_SCTxPortWEn <= 1'b1; + next_SCTxPortData <= 8'h00; + next_SCTxPortCntl <= `TX_IDLE; + end + endcase +end + +//---------------------------------- +// Current State Logic (sequential) +//---------------------------------- +always @ (posedge clk) +begin : slvDrctCntl_CurrentState + if (rst) + CurrState_slvDrctCntl <= `START_SDC; + else + CurrState_slvDrctCntl <= NextState_slvDrctCntl; +end + +//---------------------------------- +// Registered outputs logic +//---------------------------------- +always @ (posedge clk) +begin : slvDrctCntl_RegOutput + if (rst) + begin + SCTxPortCntl <= 8'h00; + SCTxPortData <= 8'h00; + SCTxPortWEn <= 1'b0; + SCTxPortReq <= 1'b0; + end + else + begin + SCTxPortCntl <= next_SCTxPortCntl; + SCTxPortData <= next_SCTxPortData; + SCTxPortWEn <= next_SCTxPortWEn; + SCTxPortReq <= next_SCTxPortReq; + end +end + +endmodule \ No newline at end of file Index: Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v (revision 40) @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////// +// usbSerialInterfaceEngine_h.v +////////////////////////////////////////////////////////////////////// + +`ifdef usbSerialInterfaceEngine_h_vdefined +`else +`define usbSerialInterfaceEngine_h_vdefined + + // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate +`define FS_OVER_SAMPLE_RATE 4 +`define LS_OVER_SAMPLE_RATE 32 + +//timeOuts +`define RX_PACKET_TOUT 18 +`define RX_EDGE_DET_TOUT 7 + +//TXStreamControlTypes +`define TX_DIRECT_CONTROL 8'h00 +`define TX_RESUME_START 8'h01 +`define TX_PACKET_START 8'h02 +`define TX_PACKET_STREAM 8'h03 +`define TX_PACKET_STOP 8'h04 +`define TX_IDLE 8'h05 +`define TX_LS_KEEP_ALIVE 8'h06 + +//RXStreamControlTypes +`define RX_PACKET_START 0 +`define RX_PACKET_STREAM 1 +`define RX_PACKET_STOP 2 + +//USBLineStates +// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo +`define ONE_ZERO 2'b10 +`define ZERO_ONE 2'b01 +`define SE0 2'b00 +`define SE1 2'b11 + +//RXStatusIndices +`define CRC_ERROR_BIT 0 +`define BIT_STUFF_ERROR_BIT 1 +`define RX_OVERFLOW_BIT 2 +`define NAK_RXED_BIT 3 +`define STALL_RXED_BIT 4 +`define ACK_RXED_BIT 5 +`define DATA_SEQUENCE_BIT 6 + +//usbWireControlStates +`define TRI_STATE 1'b0 +`define DRIVE 1'b1 + +//limits +`define MAX_CONSEC_SAME_BITS 4'h6 +`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7 +// RESUME_RX_WAIT_TIME defines the time period for resume detection +// The resume counter is incremented at the bit rate, so +// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed +// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of +// 2.5uS <= resumeDetectTime <= 100uS +`define RESUME_RX_WAIT_TIME 5'd29 +//`define RESUME_WAIT_TIME_MINUS1 9 +// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate +`ifdef SIM_COMPILE +`define HOST_TX_RESUME_TIME 16'd10 +`else +`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS +`endif +//`define CONNECT_WAIT_TIME 8'd20 +`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS +//`define DISCONNECT_WAIT_TIME 8'd20 +`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS + +//RXConnectStates +`define DISCONNECT 2'b00 +`define LOW_SPEED_CONNECT 2'b01 +`define FULL_SPEED_CONNECT 2'b10 + +//TX_RX_InternalStreamTypes +`define DATA_START 8'h00 +`define DATA_STOP 8'h01 +`define DATA_STREAM 8'h02 +`define DATA_BIT_STUFF_ERROR 8'h03 + +//RXStMach states +`define DISCONNECT_ST 4'h0 +`define WAIT_FULL_SPEED_CONN_ST 4'h1 +`define WAIT_LOW_SPEED_CONN_ST 4'h2 +`define CONNECT_LOW_SPEED_ST 4'h3 +`define CONNECT_FULL_SPEED_ST 4'h4 +`define WAIT_LOW_SP_DISCONNECT_ST 4'h5 +`define WAIT_FULL_SP_DISCONNECT_ST 4'h6 + +//RXBitStateMachStates +`define IDLE_BIT_ST 2'b00 +`define DATA_RECEIVE_BIT_ST 2'b01 +`define WAIT_RESUME_ST 2'b10 +`define RESUME_END_WAIT_ST 2'b11 + +//RXByteStateMachStates +`define IDLE_BYTE_ST 3'b000 +`define CHECK_SYNC_ST 3'b001 +`define CHECK_PID_ST 3'b010 +`define HS_BYTE_ST 3'b011 +`define TOKEN_BYTE_ST 3'b100 +`define DATA_BYTE_ST 3'b101 + +`endif //usbSerialInterfaceEngine_h_vdefined + + Index: Actel/usbDeviceActelTop/hdl/RxFifoBI.v =================================================================== --- Actel/usbDeviceActelTop/hdl/RxFifoBI.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/RxFifoBI.v (revision 40) @@ -0,0 +1,154 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RxfifoBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "wishBoneBus_h.v" + +module RxfifoBI ( + address, + writeEn, + strobe_i, + busClk, + usbClk, + rstSyncToBusClk, + fifoSelect, + fifoDataIn, + busDataIn, + busDataOut, + fifoREn, + forceEmptySyncToUsbClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input usbClk; +input rstSyncToBusClk; +input [7:0] fifoDataIn; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoREn; +output forceEmptySyncToUsbClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire [7:0] fifoDataIn; +wire [7:0] busDataIn; +reg [7:0] busDataOut; +reg fifoREn; +wire forceEmptySyncToUsbClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg forceEmptyReg; +reg forceEmpty; +reg forceEmptyToggle; +reg [2:0] forceEmptyToggleSyncToUsbClk; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//detect rising edge of 'forceEmpty', and generate toggle signal +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + forceEmptyReg <= 1'b0; + forceEmptyToggle <= 1'b0; + end + else begin + if (forceEmpty == 1'b1) + forceEmptyReg <= 1'b1; + else + forceEmptyReg <= 1'b0; + if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) + forceEmptyToggle <= ~forceEmptyToggle; + end +end +assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0; + + +// double sync across clock domains to generate 'forceEmptySyncToUsbClk' +always @(posedge usbClk) begin + forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle}; +end +assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1]; + +// async read mux +always @(address or fifoDataIn or numElementsInFifo) +begin + case (address) + `FIFO_DATA_REG : busDataOut <= fifoDataIn; + `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8]; + `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0]; + default: busDataOut <= 8'h00; + endcase +end + +//generate fifo read strobe +always @(address or writeEn or strobe_i or fifoSelect) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b0 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoREn <= 1'b1; + else + fifoREn <= 1'b0; +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/dpMem_dc.v =================================================================== --- Actel/usbDeviceActelTop/hdl/dpMem_dc.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/dpMem_dc.v (revision 40) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dpMem_dc.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Synchronous dual port memory with dual clocks +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input wrClk; +input rdClk; +input [FIFO_WIDTH-1:0] dataIn; +output [FIFO_WIDTH-1:0] dataOut; +input writeEn; +input readEn; +input [ADDR_WIDTH-1:0] addrIn; +input [ADDR_WIDTH-1:0] addrOut; + +wire wrClk; +wire rdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire writeEn; +wire readEn; +wire [ADDR_WIDTH-1:0] addrIn; +wire [ADDR_WIDTH-1:0] addrOut; + +reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1]; + +// synchronous read. Introduces one clock cycle delay +always @(posedge rdClk) begin + dataOut <= buffer[addrOut]; +end + +// synchronous write +always @(posedge wrClk) begin + if (writeEn == 1'b1) + buffer[addrIn] <= dataIn; +end + + +endmodule Index: Actel/usbDeviceActelTop/hdl/usbDevice.v =================================================================== --- Actel/usbDeviceActelTop/hdl/usbDevice.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/usbDevice.v (revision 40) @@ -0,0 +1,231 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// usbDevice.v //// +//// //// +//// This file is part of the usbHostSlave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Top level module for usbDevice +//// Instantiates a usbSlave, and controllers for EP0 and EP1 +//// If you wish to implement another type of HID, then you will +//// need to modify usbROM.v, and EP1Mouse.v +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// + +module usbDevice ( + clk, + rst, + usbSlaveVP_in, + usbSlaveVM_in, + usbSlaveVP_out, + usbSlaveVM_out, + usbSlaveOE_n, + usbDPlusPullup, + vBusDetect +); + +input clk; +input rst; +input usbSlaveVP_in; +input usbSlaveVM_in; +output usbSlaveVP_out; +output usbSlaveVM_out; +output usbSlaveOE_n; +output usbDPlusPullup; +input vBusDetect; + +//local wires and regs +wire [7:0] wb_addr0; +wire wb_stb0; +wire wb_we0; +wire wbBusReq0; +wire wbBusGnt0; +wire [7:0] wb_addr1; +wire [7:0] wb_data_o1; +wire wb_stb1; +wire wb_we1; +wire wbBusReq1; +wire wbBusGnt1; +wire [7:0] wb_addr2; +wire [7:0] wb_data_o2; +wire wb_stb2; +wire wb_we2; +wire wbBusReq2; +wire wbBusGnt2; +wire [7:0] wb_adr; +wire [7:0] wb_dat_to_usb; +wire [7:0] wb_dat_from_usb; +wire wb_we; +wire wb_stb; +wire wb_ack; +reg [1:0] resetReg; +wire initComplete; +wire usbRstDet; +wire [7:0] memAddr; +wire [7:0] memData; +wire USBWireCtrlOut; +wire [1:0] USBWireDataIn; +wire [1:0] USBWireDataOut; + + +//Parameters declaration: +defparam usbSlaveInst.EP0_FIFO_DEPTH = 64; +defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6; +defparam usbSlaveInst.EP1_FIFO_DEPTH = 64; +defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6; +defparam usbSlaveInst.EP2_FIFO_DEPTH = 64; +defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6; +defparam usbSlaveInst.EP3_FIFO_DEPTH = 64; +defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6; +usbSlave usbSlaveInst ( + .clk_i(clk), + .rst_i(rst), + .address_i(wb_adr), + .data_i(wb_dat_to_usb), + .data_o(wb_dat_from_usb), + .we_i(wb_we), + .strobe_i(wb_stb), + .ack_o(wb_ack), + .usbClk(clk), + .slaveSOFRxedIntOut(), + .slaveResetEventIntOut(), + .slaveResumeIntOut(), + .slaveTransDoneIntOut(), + .slaveNAKSentIntOut(), + .slaveVBusDetIntOut(), + .USBWireDataIn(USBWireDataIn), + .USBWireDataInTick(), + .USBWireDataOut(USBWireDataOut), + .USBWireDataOutTick(), + .USBWireCtrlOut(USBWireCtrlOut), + .USBFullSpeed(), + .USBDPlusPullup(usbDPlusPullup), + .USBDMinusPullup(), + .vBusDetect(vBusDetect) +); + +assign USBWireDataIn = {usbSlaveVP_in, usbSlaveVM_in}; +assign {usbSlaveVP_out, usbSlaveVM_out} = USBWireDataOut; +assign usbSlaveOE_n = ~USBWireCtrlOut; + +checkLineState u_checkLineState ( + .clk(clk), + .rst(rst), + .initComplete(initComplete), + .usbRstDet(usbRstDet), + .wb_ack(wb_ack), + .wb_addr(wb_addr0), + .wb_data_i(wb_dat_from_usb), + .wb_stb(wb_stb0), + .wb_we(wb_we0), + .wbBusGnt(wbBusGnt0), + .wbBusReq(wbBusReq0) +); + + +EP0 u_EP0 ( + .clk(clk), + .rst(rst | usbRstDet), + .initComplete(initComplete), + .wb_ack(wb_ack), + .wb_addr(wb_addr1), + .wb_data_i(wb_dat_from_usb), + .wb_data_o(wb_data_o1), + .wb_stb(wb_stb1), + .wb_we(wb_we1), + .wbBusGnt(wbBusGnt1), + .wbBusReq(wbBusReq1), + .memAddr(memAddr), + .memData(memData), + .memRdEn() +); + +usbROM u_usbROM ( + .clk(clk), + .addr(memAddr), + .data(memData) +); + + +EP1Mouse u_EP1Mouse ( + .clk(clk), + .rst(rst | usbRstDet), + .initComplete(initComplete), + .wb_ack(wb_ack), + .wb_addr(wb_addr2), + .wb_data_i(wb_dat_from_usb), + .wb_data_o(wb_data_o2), + .wb_stb(wb_stb2), + .wb_we(wb_we2), + .wbBusGnt(wbBusGnt2), + .wbBusReq(wbBusReq2) +); + +wishboneArb u_wishboneArb ( + .clk(clk), + .rst(rst), + + .addr0_i(wb_addr0), + .data0_i(8'h00), + .stb0_i(wb_stb0), + .we0_i(wb_we0), + .req0(wbBusReq0), + .gnt0(wbBusGnt0), + + .addr1_i(wb_addr1), + .data1_i(wb_data_o1), + .stb1_i(wb_stb1), + .we1_i(wb_we1), + .req1(wbBusReq1), + .gnt1(wbBusGnt1), + + .addr2_i(wb_addr2), + .data2_i(wb_data_o2), + .stb2_i(wb_stb2), + .we2_i(wb_we2), + .req2(wbBusReq2), + .gnt2(wbBusGnt2), + + + .addr_o(wb_adr), + .data_o(wb_dat_to_usb), + .stb_o(wb_stb), + .we_o(wb_we) +); + + +endmodule + Index: Actel/usbDeviceActelTop/hdl/TxFifoBI.v =================================================================== --- Actel/usbDeviceActelTop/hdl/TxFifoBI.v (nonexistent) +++ Actel/usbDeviceActelTop/hdl/TxFifoBI.v (revision 40) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TxfifoBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "wishBoneBus_h.v" + +module TxfifoBI ( + address, writeEn, strobe_i, + busClk, + usbClk, + rstSyncToBusClk, + fifoSelect, + busDataIn, + busDataOut, + fifoWEn, + forceEmptySyncToUsbClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input usbClk; +input rstSyncToBusClk; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoWEn; +output forceEmptySyncToUsbClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire usbClk; +wire rstSyncToBusClk; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +reg fifoWEn; +wire forceEmptySyncToUsbClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg forceEmptyReg; +reg forceEmpty; +reg forceEmptyToggle; +reg [2:0] forceEmptyToggleSyncToUsbClk; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//detect rising edge of 'forceEmpty', and generate toggle signal +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + forceEmptyReg <= 1'b0; + forceEmptyToggle <= 1'b0; + end + else begin + if (forceEmpty == 1'b1) + forceEmptyReg <= 1'b1; + else + forceEmptyReg <= 1'b0; + if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) + forceEmptyToggle <= ~forceEmptyToggle; + end +end +assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0; + +// double sync across clock domains to generate 'forceEmptySyncToUsbClk' +always @(posedge usbClk) begin + forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle}; +end +assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1]; + +// async read mux +assign busDataOut = 8'h00; +//always @(address or fifoFull or numElementsInFifo) +//begin +// case (address) +// `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull}; +// `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8]; +// `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0]; +// default: busDataOut <= 8'h00; +// endcase +//end + +//generate fifo write strobe +always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b1 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoWEn <= 1'b1; + else + fifoWEn <= 1'b0; +end + + +endmodule Index: Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop_syn.prj =================================================================== --- Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop_syn.prj (nonexistent) +++ Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop_syn.prj (revision 40) @@ -0,0 +1,62 @@ +#add_file options +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/timescale.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbConstants_h.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v" +add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice_define.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slavecontroller.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/endpMux.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveSendpacket.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/sctxportarbiter.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveGetpacket.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoMux.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBI.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/lineControlUpdate.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/siereceiver.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxBit.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxByte.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC5.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC16.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/SIETransmitter.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processTxByte.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/writeUSBWireData.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/readUSBWireData.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/dpMem_dc.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoRTL.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifoBI.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifo.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifoBI.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifo.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlave.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/checkLineState.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP0.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP1Mouse.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishboneArb.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice.v" +add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v" +set_option -top_module usbDeviceActelTop + +#device options +set_option -technology IGLOO +set_option -part AGL600V5 + +#compilation/mapping options +set_option -symbolic_fsm_compiler true + +#compilation/mapping options +set_option -frequency 100.000 + +#simulation options +impl -active "synthesis" +project -result_file "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop.edn" Index: xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v =================================================================== --- xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v (nonexistent) +++ xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v (revision 40) @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 9.2.03i +// \ \ Application : xaw2verilog +// / / Filename : pll_48MHz_xilinx.v +// /___/ /\ Timestamp : 08/20/2008 15:22:39 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle F:/version_ctrl/usbhostslave/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw -st pll_48MHz_xilinx.v +//Design Name: pll_48MHz_xilinx +//Device: xc3s700a-5fg484 +// +// Module pll_48MHz_xilinx +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +`timescale 1ns / 1ps + +module pll_48MHz_xilinx(CLKIN_IN, + CLKIN_IBUFG_OUT, + CLK0_OUT, + LOCKED_OUT); + + input CLKIN_IN; + output CLKIN_IBUFG_OUT; + output CLK0_OUT; + output LOCKED_OUT; + + wire CLKFB_IN; + wire CLKIN_IBUFG; + wire CLK0_BUF; + wire GND_BIT; + + assign GND_BIT = 0; + assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; + assign CLK0_OUT = CLKFB_IN; + IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), + .O(CLKIN_IBUFG)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IBUFG), + .DSSEN(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(GND_BIT), + .CLKDV(), + .CLKFX(), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_SP_INST.CLK_FEEDBACK = "1X"; + defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_SP_INST.CLKFX_DIVIDE = 1; + defparam DCM_SP_INST.CLKFX_MULTIPLY = 4; + defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_SP_INST.CLKIN_PERIOD = 20.833; + defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_SP_INST.FACTORY_JF = 16'hC080; + defparam DCM_SP_INST.PHASE_SHIFT = 0; + defparam DCM_SP_INST.STARTUP_WAIT = "FALSE"; +endmodule Index: xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.prj =================================================================== --- xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.prj (nonexistent) +++ xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.prj (revision 40) @@ -0,0 +1,39 @@ +verilog work "../../../../RTL/buffers/dpMem_dc.v" +verilog work "../../../../RTL/slaveController/slavecontroller.v" +verilog work "../../../../RTL/slaveController/slaveSendpacket.v" +verilog work "../../../../RTL/slaveController/slaveRxStatusMonitor.v" +verilog work "../../../../RTL/slaveController/slaveGetpacket.v" +verilog work "../../../../RTL/slaveController/slaveDirectcontrol.v" +verilog work "../../../../RTL/slaveController/sctxportarbiter.v" +verilog work "../../../../RTL/slaveController/fifoMux.v" +verilog work "../../../../RTL/slaveController/endpMux.v" +verilog work "../../../../RTL/slaveController/USBSlaveControlBI.v" +verilog work "../../../../RTL/serialInterfaceEngine/writeUSBWireData.v" +verilog work "../../../../RTL/serialInterfaceEngine/usbTxWireArbiter.v" +verilog work "../../../../RTL/serialInterfaceEngine/updateCRC5.v" +verilog work "../../../../RTL/serialInterfaceEngine/updateCRC16.v" +verilog work "../../../../RTL/serialInterfaceEngine/siereceiver.v" +verilog work "../../../../RTL/serialInterfaceEngine/readUSBWireData.v" +verilog work "../../../../RTL/serialInterfaceEngine/processTxByte.v" +verilog work "../../../../RTL/serialInterfaceEngine/processRxByte.v" +verilog work "../../../../RTL/serialInterfaceEngine/processRxBit.v" +verilog work "../../../../RTL/serialInterfaceEngine/lineControlUpdate.v" +verilog work "../../../../RTL/serialInterfaceEngine/SIETransmitter.v" +verilog work "../../../../RTL/buffers/fifoRTL.v" +verilog work "../../../../RTL/buffers/TxFifoBI.v" +verilog work "../../../../RTL/buffers/RxFifoBI.v" +verilog work "../../../../RTL/slaveController/usbSlaveControl.v" +verilog work "../../../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v" +verilog work "../../../../RTL/hostSlaveMux/hostSlaveMuxBI.v" +verilog work "../../../../RTL/busInterface/wishBoneBI.v" +verilog work "../../../../RTL/buffers/TxFifo.v" +verilog work "../../../../RTL/buffers/RxFifo.v" +verilog work "../../../RTL/wishboneArb.v" +verilog work "../../../RTL/usbROM.v" +verilog work "../../../RTL/checkLineState.v" +verilog work "../../../RTL/EP1Mouse.v" +verilog work "../../../RTL/EP0.v" +verilog work "../../../../RTL/wrapper/usbSlave.v" +verilog work "pll_48MHz_xilinx.v" +verilog work "../../../RTL/usbDevice.v" +verilog work "../../../RTL/usbDeviceXilinxTop.v" Index: xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ucf =================================================================== --- xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ucf (nonexistent) +++ xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ucf (revision 40) @@ -0,0 +1,144 @@ +############################################################################## +## Copyright (c) 2006, 2007 Xilinx, Inc. +## This design is confidential and proprietary of Xilinx, All Rights Reserved. +############################################################################## +## ____ ____ +## / /\/ / +## /___/ \ / Vendor: Xilinx +## \ \ \/ Version: 1.0.1 +## \ \ Filename: starter_kit_constraints.ucf +## / / Date Created: December 25, 2006 +## /___/ /\ Last Modified: April 1, 2007 +## \ \ / \ +## \___\/\___\ +## +## Devices: Spartan-3 Generation FPGA +## Purpose: Complete constraint file for Spartan-3A(N) Starter Kit +## Contact: crabill@xilinx.com +## Reference: None +## +## Revision History: +## Rev 1.0.0 - (crabill) Created December 25, 2006 for PCB revision C. +## Rev 1.0.1 - (crabill) Modified April 1, 2007 to mention revision D +## of the PCB and applicability to Spartan-3AN. +## +############################################################################## +## +## LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is". +## Xilinx and its licensors make and you receive no warranties or conditions, +## express, implied, statutory or otherwise, and Xilinx specifically disclaims +## any implied warranties of merchantability, non-infringement, or fitness for +## a particular purpose. Xilinx does not warrant that the functions contained +## in these designs will meet your requirements, or that the operation of +## these designs will be uninterrupted or error free, or that defects in the +## designs will be corrected. Furthermore, Xilinx does not warrant or make any +## representations regarding use or the results of the use of the designs in +## terms of correctness, accuracy, reliability, or otherwise. +## +## LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable +## for any loss of data, lost profits, cost or procurement of substitute goods +## or services, or for any special, incidental, consequential, or indirect +## damages arising from the use or operation of the designs or accompanying +## documentation, however caused and on any theory of liability. This +## limitation will apply even if Xilinx has been advised of the possibility +## of such damage. This limitation shall apply not-withstanding the failure +## of the essential purpose of any limited remedies herein. +## +############################################################################## +## Copyright (c) 2006, 2007 Xilinx, Inc. +## This design is confidential and proprietary of Xilinx, All Rights Reserved. +############################################################################## + +# On this board, VCCAUX is 3.3 volts. + +CONFIG VCCAUX = "3.3" ; + +# Configure SUSPEND mode options. + +CONFIG ENABLE_SUSPEND = "FILTERED" ; + +# FILTERED is appropriate for use with the switch on this board. Other allowed +# settings are NO or UNFILTERED. If set NO, the AWAKE pin becomes general I/O. +# Please read the FPGA User Guide for more information. + +# Configure POST_CRC options. + +CONFIG POST_CRC = "DISABLE" ; + +# DISABLE the post-configuration CRC checking so INIT_B is available for +# general I/O after configuration is done. On this board, INIT_B is used +# after configuration to control the Platform Flash device. Other allowed +# settings are ENABLE. Please read the FPGA User Guide for more information. + +############################################################################## +# These are sample constraints for the three clock inputs. You will need +# to change these constraints to suit your application. Please read the +# FPGA Development System Reference Guide for more information on expressing +# timing constraints for your design. +############################################################################## + + +NET "clk" LOC = "V12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.830 ; +OFFSET = IN 10.410 VALID 20.830 BEFORE "clk" ; +OFFSET = OUT 20.830 AFTER "clk" ; + + + + + + +############################################################################## +# Accessory Headers (J18, J19, J20) +############################################################################## + +#NET "J18_IO<1>" LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J18_IO<2>" LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J18_IO<3>" LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J18_IO<4>" LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "usbSlaveVP" LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "usbSlaveVM" LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "usbSlaveOE_n" LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "usbDPlusPullup" LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; + +#NET "J19_IO<1>" LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J19_IO<2>" LOC = "W18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J19_IO<3>" LOC = "V17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J19_IO<4>" LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; + +#NET "J20_IO<1>" LOC = "V14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J20_IO<2>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J20_IO<3>" LOC = "W16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "J20_IO<4>" LOC = "V16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; + + + + + +############################################################################## +# 10/100 Ethernet (E) +############################################################################## + + +NET "E_NRST" LOC = "D15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; + +############################################################################## +# Serial Peripheral System +############################################################################## + +NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; + +############################################################################## +# Parallel Flash (NF) +############################################################################## + +NET "NF_CE" LOC = "W20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; + + +############################################################################## +# DDR2 SDRAM Device (SD) +############################################################################## + +NET "SD_CS" LOC = "M5" | IOSTANDARD = SSTL18_I ; + + +############################################################################## Index: xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise =================================================================== --- xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise (nonexistent) +++ xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise (revision 40)
xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw =================================================================== --- xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw (nonexistent) +++ xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw (revision 40)
xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx_arwz.ucf =================================================================== --- xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx_arwz.ucf (nonexistent) +++ xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx_arwz.ucf (revision 40) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 4; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.833; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE;

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