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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

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/trunk/RTL/wrapper/usbHostSlave.v
1,576 → 1,583
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostSlave.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbHostSlave(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
hostSOFSentIntOut,
hostConnEventIntOut,
hostResumeIntOut,
hostTransDoneIntOut,
slaveVBusDetIntOut,
slaveNAKSentIntOut,
slaveSOFRxedIntOut,
slaveResetEventIntOut,
slaveResumeIntOut,
slaveTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
parameter HOST_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_ADDR_WIDTH = 6;
 
input clk_i; //Wishbone bus clock. Min = usbClk/2 = 24MHz. Max 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output hostSOFSentIntOut;
output hostConnEventIntOut;
output hostResumeIntOut;
output hostTransDoneIntOut;
output slaveSOFRxedIntOut;
output slaveResetEventIntOut;
output slaveResumeIntOut;
output slaveTransDoneIntOut;
output slaveNAKSentIntOut;
output slaveVBusDetIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
 
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
wire USBDPlusPullup;
wire USBDMinusPullup;
wire vBusDetect;
 
//internal wiring
wire hostControlSel;
wire slaveControlSel;
wire hostRxFifoSel;
wire hostTxFifoSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromHostControl;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostRxFifo;
wire [7:0] dataFromHostTxFifo;
wire [7:0] dataFromHostSlaveMux;
wire hostTxFifoRE;
wire [7:0] hostTxFifoData;
wire hostTxFifoEmpty;
wire hostRxFifoWE;
wire [7:0] hostRxFifoData;
wire hostRxFifoFull;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromHost;
wire fullSpeedBitRateFromSlave;
wire fullSpeedPolarityFromHost;
wire fullSpeedPolarityFromSlave;
wire SIEPortWEnFromHost;
wire SIEPortWEnFromSlave;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromHost;
wire [7:0] SIEPortDataInFromSlave;
wire [7:0] SIEPortCtrlInFromHost;
wire [7:0] SIEPortCtrlInFromSlave;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire noActivityTimeOut;
wire TxFifoEP0REn;
wire TxFifoEP1REn;
wire TxFifoEP2REn;
wire TxFifoEP3REn;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
wire RxFifoEP0WEn;
wire RxFifoEP1WEn;
wire RxFifoEP2WEn;
wire RxFifoEP3WEn;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
wire [7:0] slaveRxFifoData;
wire [7:0] dataFromEP0RxFifo;
wire [7:0] dataFromEP1RxFifo;
wire [7:0] dataFromEP2RxFifo;
wire [7:0] dataFromEP3RxFifo;
wire [7:0] dataFromEP0TxFifo;
wire [7:0] dataFromEP1TxFifo;
wire [7:0] dataFromEP2TxFifo;
wire [7:0] dataFromEP3TxFifo;
wire slaveEP0RxFifoSel;
wire slaveEP1RxFifoSel;
wire slaveEP2RxFifoSel;
wire slaveEP3RxFifoSel;
wire slaveEP0TxFifoSel;
wire slaveEP1TxFifoSel;
wire slaveEP2TxFifoSel;
wire slaveEP3TxFifoSel;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
wire noActivityTimeOutEnableFromSlave;
wire connectSlaveToHost;
 
assign USBFullSpeed = fullSpeedBitRateToSIE;
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
 
usbHostControl u_usbHostControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.TxFifoRE(hostTxFifoRE),
.TxFifoData(hostTxFifoData),
.TxFifoEmpty(hostTxFifoEmpty),
.RxFifoWE(hostRxFifoWE),
.RxFifoData(hostRxFifoData),
.RxFifoFull(hostRxFifoFull),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
.fullSpeedRate(fullSpeedBitRateFromHost),
.fullSpeedPol(fullSpeedPolarityFromHost),
.HCTxPortEn(SIEPortWEnFromHost),
.HCTxPortRdy(SIEPortTxRdy),
.HCTxPortData(SIEPortDataInFromHost),
.HCTxPortCtrl(SIEPortCtrlInFromHost),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[3:0]),
.busDataIn(data_i),
.busDataOut(dataFromHostControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFSentIntOut(hostSOFSentIntOut),
.connEventIntOut(hostConnEventIntOut),
.resumeIntOut(hostResumeIntOut),
.transDoneIntOut(hostTransDoneIntOut),
.hostControlSelect(hostControlSel) );
 
usbSlaveControl u_usbSlaveControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
.RxFifoData(slaveRxFifoData),
.connectSlaveToHost(connectSlaveToHost),
.fullSpeedRate(fullSpeedBitRateFromSlave),
.fullSpeedPol(fullSpeedPolarityFromSlave),
.SCTxPortEn(SIEPortWEnFromSlave),
.SCTxPortRdy(SIEPortTxRdy),
.SCTxPortData(SIEPortDataInFromSlave),
.SCTxPortCtrl(SIEPortCtrlInFromSlave),
.vBusDetect(vBusDetect),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[4:0]),
.busDataIn(data_i),
.busDataOut(dataFromSlaveControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFRxedIntOut(slaveSOFRxedIntOut),
.resetEventIntOut(slaveResetEventIntOut),
.resumeIntOut(slaveResumeIntOut),
.transDoneIntOut(slaveTransDoneIntOut),
.NAKSentIntOut(slaveNAKSentIntOut),
.vBusDetIntOut(slaveVBusDetIntOut),
.slaveControlSelect(slaveControlSel),
.TxFifoEP0REn(TxFifoEP0REn),
.TxFifoEP1REn(TxFifoEP1REn),
.TxFifoEP2REn(TxFifoEP2REn),
.TxFifoEP3REn(TxFifoEP3REn),
.TxFifoEP0Data(TxFifoEP0Data),
.TxFifoEP1Data(TxFifoEP1Data),
.TxFifoEP2Data(TxFifoEP2Data),
.TxFifoEP3Data(TxFifoEP3Data),
.TxFifoEP0Empty(TxFifoEP0Empty),
.TxFifoEP1Empty(TxFifoEP1Empty),
.TxFifoEP2Empty(TxFifoEP2Empty),
.TxFifoEP3Empty(TxFifoEP3Empty),
.RxFifoEP0WEn(RxFifoEP0WEn),
.RxFifoEP1WEn(RxFifoEP1WEn),
.RxFifoEP2WEn(RxFifoEP2WEn),
.RxFifoEP3WEn(RxFifoEP3WEn),
.RxFifoEP0Full(RxFifoEP0Full),
.RxFifoEP1Full(RxFifoEP1Full),
.RxFifoEP2Full(RxFifoEP2Full),
.RxFifoEP3Full(RxFifoEP3Full)
);
 
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(hostControlSel),
.hostRxFifoSel(hostRxFifoSel),
.hostTxFifoSel(hostTxFifoSel),
.slaveControlSel(slaveControlSel),
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(dataFromHostControl),
.dataFromHostRxFifo(dataFromHostRxFifo),
.dataFromHostTxFifo(dataFromHostTxFifo),
.dataFromSlaveControl(dataFromSlaveControl),
.dataFromEP0RxFifo(dataFromEP0RxFifo),
.dataFromEP1RxFifo(dataFromEP1RxFifo),
.dataFromEP2RxFifo(dataFromEP2RxFifo),
.dataFromEP3RxFifo(dataFromEP3RxFifo),
.dataFromEP0TxFifo(dataFromEP0TxFifo),
.dataFromEP1TxFifo(dataFromEP1TxFifo),
.dataFromEP2TxFifo(dataFromEP2TxFifo),
.dataFromEP3TxFifo(dataFromEP3TxFifo),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
 
hostSlaveMux u_hostSlaveMux(
.SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
.SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
.SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
.SIEPortDataInToSIE(SIEPortDataInToSIE),
.SIEPortDataInFromHost(SIEPortDataInFromHost),
.SIEPortDataInFromSlave(SIEPortDataInFromSlave),
.SIEPortWEnToSIE(SIEPortWEnToSIE),
.SIEPortWEnFromHost(SIEPortWEnFromHost),
.SIEPortWEnFromSlave(SIEPortWEnFromSlave),
.fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
.fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
.fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
.fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
.noActivityTimeOutEnableToSIE(noActivityTimeOutEnableToSIE),
.noActivityTimeOutEnableFromHost(noActivityTimeOutEnableFromHost),
.noActivityTimeOutEnableFromSlave(noActivityTimeOutEnableFromSlave),
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostSlaveMuxSel(hostSlaveMuxSel),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
 
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
 
//---Host fifos
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(hostTxFifoRE),
.fifoEmpty(hostTxFifoEmpty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostTxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostTxFifo),
.fifoDataOut(hostTxFifoData) );
 
 
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(hostRxFifoWE),
.fifoFull(hostRxFifoFull),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostRxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostRxFifo),
.fifoDataIn(hostRxFifoData) );
 
//---Slave fifos
 
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP0REn),
.fifoEmpty(TxFifoEP0Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0TxFifo),
.fifoDataOut(TxFifoEP0Data) );
 
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP1REn),
.fifoEmpty(TxFifoEP1Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1TxFifo),
.fifoDataOut(TxFifoEP1Data) );
 
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP2REn),
.fifoEmpty(TxFifoEP2Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2TxFifo),
.fifoDataOut(TxFifoEP2Data) );
 
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP3REn),
.fifoEmpty(TxFifoEP3Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3TxFifo),
.fifoDataOut(TxFifoEP3Data) );
 
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP0WEn),
.fifoFull(RxFifoEP0Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP1WEn),
.fifoFull(RxFifoEP1Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP2WEn),
.fifoFull(RxFifoEP2Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP3WEn),
.fifoFull(RxFifoEP3Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
endmodule
 
 
 
 
 
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostSlave.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbHostSlave(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
hostSOFSentIntOut,
hostConnEventIntOut,
hostResumeIntOut,
hostTransDoneIntOut,
slaveVBusDetIntOut,
slaveNAKSentIntOut,
slaveSOFRxedIntOut,
slaveResetEventIntOut,
slaveResumeIntOut,
slaveTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
parameter HOST_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_ADDR_WIDTH = 6;
 
input clk_i; //Wishbone bus clock. Min = usbClk/2 = 24MHz. Max 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output hostSOFSentIntOut;
output hostConnEventIntOut;
output hostResumeIntOut;
output hostTransDoneIntOut;
output slaveSOFRxedIntOut;
output slaveResetEventIntOut;
output slaveResumeIntOut;
output slaveTransDoneIntOut;
output slaveNAKSentIntOut;
output slaveVBusDetIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
 
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
wire USBDPlusPullup;
wire USBDMinusPullup;
wire vBusDetect;
 
//internal wiring
wire hostControlSel;
wire slaveControlSel;
wire hostRxFifoSel;
wire hostTxFifoSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromHostControl;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostRxFifo;
wire [7:0] dataFromHostTxFifo;
wire [7:0] dataFromHostSlaveMux;
wire hostTxFifoRE;
wire [7:0] hostTxFifoData;
wire hostTxFifoEmpty;
wire hostRxFifoWE;
wire [7:0] hostRxFifoData;
wire hostRxFifoFull;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromHost;
wire fullSpeedBitRateFromSlave;
wire fullSpeedPolarityFromHost;
wire fullSpeedPolarityFromSlave;
wire SIEPortWEnFromHost;
wire SIEPortWEnFromSlave;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromHost;
wire [7:0] SIEPortDataInFromSlave;
wire [7:0] SIEPortCtrlInFromHost;
wire [7:0] SIEPortCtrlInFromSlave;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire noActivityTimeOut;
wire TxFifoEP0REn;
wire TxFifoEP1REn;
wire TxFifoEP2REn;
wire TxFifoEP3REn;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
wire RxFifoEP0WEn;
wire RxFifoEP1WEn;
wire RxFifoEP2WEn;
wire RxFifoEP3WEn;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
wire [7:0] slaveRxFifoData;
wire [7:0] dataFromEP0RxFifo;
wire [7:0] dataFromEP1RxFifo;
wire [7:0] dataFromEP2RxFifo;
wire [7:0] dataFromEP3RxFifo;
wire [7:0] dataFromEP0TxFifo;
wire [7:0] dataFromEP1TxFifo;
wire [7:0] dataFromEP2TxFifo;
wire [7:0] dataFromEP3TxFifo;
wire slaveEP0RxFifoSel;
wire slaveEP1RxFifoSel;
wire slaveEP2RxFifoSel;
wire slaveEP3RxFifoSel;
wire slaveEP0TxFifoSel;
wire slaveEP1TxFifoSel;
wire slaveEP2TxFifoSel;
wire slaveEP3TxFifoSel;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
wire noActivityTimeOutEnableFromSlave;
wire connectSlaveToHost;
 
// This is not a bug.
// USBFullSpeed controls the PHY edge speed.
// The only time that the PHY needs to operate with low speed edge rate is
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
// but according to spec edge speed must be full rate edge speed.
assign USBFullSpeed = fullSpeedPolarityToSIE;
//assign USBFullSpeed = fullSpeedBitRateToSIE;
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
 
usbHostControl u_usbHostControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.TxFifoRE(hostTxFifoRE),
.TxFifoData(hostTxFifoData),
.TxFifoEmpty(hostTxFifoEmpty),
.RxFifoWE(hostRxFifoWE),
.RxFifoData(hostRxFifoData),
.RxFifoFull(hostRxFifoFull),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
.fullSpeedRate(fullSpeedBitRateFromHost),
.fullSpeedPol(fullSpeedPolarityFromHost),
.HCTxPortEn(SIEPortWEnFromHost),
.HCTxPortRdy(SIEPortTxRdy),
.HCTxPortData(SIEPortDataInFromHost),
.HCTxPortCtrl(SIEPortCtrlInFromHost),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[3:0]),
.busDataIn(data_i),
.busDataOut(dataFromHostControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFSentIntOut(hostSOFSentIntOut),
.connEventIntOut(hostConnEventIntOut),
.resumeIntOut(hostResumeIntOut),
.transDoneIntOut(hostTransDoneIntOut),
.hostControlSelect(hostControlSel) );
 
usbSlaveControl u_usbSlaveControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
.RxFifoData(slaveRxFifoData),
.connectSlaveToHost(connectSlaveToHost),
.fullSpeedRate(fullSpeedBitRateFromSlave),
.fullSpeedPol(fullSpeedPolarityFromSlave),
.SCTxPortEn(SIEPortWEnFromSlave),
.SCTxPortRdy(SIEPortTxRdy),
.SCTxPortData(SIEPortDataInFromSlave),
.SCTxPortCtrl(SIEPortCtrlInFromSlave),
.vBusDetect(vBusDetect),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[4:0]),
.busDataIn(data_i),
.busDataOut(dataFromSlaveControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFRxedIntOut(slaveSOFRxedIntOut),
.resetEventIntOut(slaveResetEventIntOut),
.resumeIntOut(slaveResumeIntOut),
.transDoneIntOut(slaveTransDoneIntOut),
.NAKSentIntOut(slaveNAKSentIntOut),
.vBusDetIntOut(slaveVBusDetIntOut),
.slaveControlSelect(slaveControlSel),
.TxFifoEP0REn(TxFifoEP0REn),
.TxFifoEP1REn(TxFifoEP1REn),
.TxFifoEP2REn(TxFifoEP2REn),
.TxFifoEP3REn(TxFifoEP3REn),
.TxFifoEP0Data(TxFifoEP0Data),
.TxFifoEP1Data(TxFifoEP1Data),
.TxFifoEP2Data(TxFifoEP2Data),
.TxFifoEP3Data(TxFifoEP3Data),
.TxFifoEP0Empty(TxFifoEP0Empty),
.TxFifoEP1Empty(TxFifoEP1Empty),
.TxFifoEP2Empty(TxFifoEP2Empty),
.TxFifoEP3Empty(TxFifoEP3Empty),
.RxFifoEP0WEn(RxFifoEP0WEn),
.RxFifoEP1WEn(RxFifoEP1WEn),
.RxFifoEP2WEn(RxFifoEP2WEn),
.RxFifoEP3WEn(RxFifoEP3WEn),
.RxFifoEP0Full(RxFifoEP0Full),
.RxFifoEP1Full(RxFifoEP1Full),
.RxFifoEP2Full(RxFifoEP2Full),
.RxFifoEP3Full(RxFifoEP3Full)
);
 
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(hostControlSel),
.hostRxFifoSel(hostRxFifoSel),
.hostTxFifoSel(hostTxFifoSel),
.slaveControlSel(slaveControlSel),
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(dataFromHostControl),
.dataFromHostRxFifo(dataFromHostRxFifo),
.dataFromHostTxFifo(dataFromHostTxFifo),
.dataFromSlaveControl(dataFromSlaveControl),
.dataFromEP0RxFifo(dataFromEP0RxFifo),
.dataFromEP1RxFifo(dataFromEP1RxFifo),
.dataFromEP2RxFifo(dataFromEP2RxFifo),
.dataFromEP3RxFifo(dataFromEP3RxFifo),
.dataFromEP0TxFifo(dataFromEP0TxFifo),
.dataFromEP1TxFifo(dataFromEP1TxFifo),
.dataFromEP2TxFifo(dataFromEP2TxFifo),
.dataFromEP3TxFifo(dataFromEP3TxFifo),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
 
hostSlaveMux u_hostSlaveMux(
.SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
.SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
.SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
.SIEPortDataInToSIE(SIEPortDataInToSIE),
.SIEPortDataInFromHost(SIEPortDataInFromHost),
.SIEPortDataInFromSlave(SIEPortDataInFromSlave),
.SIEPortWEnToSIE(SIEPortWEnToSIE),
.SIEPortWEnFromHost(SIEPortWEnFromHost),
.SIEPortWEnFromSlave(SIEPortWEnFromSlave),
.fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
.fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
.fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
.fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
.noActivityTimeOutEnableToSIE(noActivityTimeOutEnableToSIE),
.noActivityTimeOutEnableFromHost(noActivityTimeOutEnableFromHost),
.noActivityTimeOutEnableFromSlave(noActivityTimeOutEnableFromSlave),
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostSlaveMuxSel(hostSlaveMuxSel),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
 
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
 
//---Host fifos
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(hostTxFifoRE),
.fifoEmpty(hostTxFifoEmpty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostTxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostTxFifo),
.fifoDataOut(hostTxFifoData) );
 
 
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(hostRxFifoWE),
.fifoFull(hostRxFifoFull),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostRxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostRxFifo),
.fifoDataIn(hostRxFifoData) );
 
//---Slave fifos
 
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP0REn),
.fifoEmpty(TxFifoEP0Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0TxFifo),
.fifoDataOut(TxFifoEP0Data) );
 
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP1REn),
.fifoEmpty(TxFifoEP1Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1TxFifo),
.fifoDataOut(TxFifoEP1Data) );
 
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP2REn),
.fifoEmpty(TxFifoEP2Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2TxFifo),
.fifoDataOut(TxFifoEP2Data) );
 
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP3REn),
.fifoEmpty(TxFifoEP3Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3TxFifo),
.fifoDataOut(TxFifoEP3Data) );
 
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP0WEn),
.fifoFull(RxFifoEP0Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP1WEn),
.fifoFull(RxFifoEP1Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP2WEn),
.fifoFull(RxFifoEP2Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP3WEn),
.fifoFull(RxFifoEP3Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
endmodule
 
 
 
 
 
/trunk/RTL/wrapper/usbSlave.v
1,474 → 1,481
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSlave.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbSlave(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
slaveVBusDetIntOut,
slaveNAKSentIntOut,
slaveSOFRxedIntOut,
slaveResetEventIntOut,
slaveResumeIntOut,
slaveTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
parameter EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_ADDR_WIDTH = 6;
 
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output slaveSOFRxedIntOut;
output slaveResetEventIntOut;
output slaveResumeIntOut;
output slaveTransDoneIntOut;
output slaveNAKSentIntOut;
output slaveVBusDetIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
 
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
wire USBDPlusPullup;
wire USBDMinusPullup;
wire vBusDetect;
 
//internal wiring
wire slaveControlSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostSlaveMux;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromSlave;
wire fullSpeedPolarityFromSlave;
wire SIEPortWEnFromSlave;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromSlave;
wire [7:0] SIEPortCtrlInFromSlave;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire connectSlaveToHost;
wire noActivityTimeOut;
wire TxFifoEP0REn;
wire TxFifoEP1REn;
wire TxFifoEP2REn;
wire TxFifoEP3REn;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
wire RxFifoEP0WEn;
wire RxFifoEP1WEn;
wire RxFifoEP2WEn;
wire RxFifoEP3WEn;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
wire [7:0] slaveRxFifoData;
wire [7:0] dataFromEP0RxFifo;
wire [7:0] dataFromEP1RxFifo;
wire [7:0] dataFromEP2RxFifo;
wire [7:0] dataFromEP3RxFifo;
wire [7:0] dataFromEP0TxFifo;
wire [7:0] dataFromEP1TxFifo;
wire [7:0] dataFromEP2TxFifo;
wire [7:0] dataFromEP3TxFifo;
wire slaveEP0RxFifoSel;
wire slaveEP1RxFifoSel;
wire slaveEP2RxFifoSel;
wire slaveEP3RxFifoSel;
wire slaveEP0TxFifoSel;
wire slaveEP1TxFifoSel;
wire slaveEP2TxFifoSel;
wire slaveEP3TxFifoSel;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
wire noActivityTimeOutEnableFromSlave;
 
assign USBFullSpeed = fullSpeedBitRateToSIE;
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
 
usbSlaveControl u_usbSlaveControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
.RxFifoData(slaveRxFifoData),
.connectSlaveToHost(connectSlaveToHost),
.fullSpeedRate(fullSpeedBitRateFromSlave),
.fullSpeedPol(fullSpeedPolarityFromSlave),
.SCTxPortEn(SIEPortWEnFromSlave),
.SCTxPortRdy(SIEPortTxRdy),
.SCTxPortData(SIEPortDataInFromSlave),
.SCTxPortCtrl(SIEPortCtrlInFromSlave),
.vBusDetect(vBusDetect),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[4:0]),
.busDataIn(data_i),
.busDataOut(dataFromSlaveControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFRxedIntOut(slaveSOFRxedIntOut),
.resetEventIntOut(slaveResetEventIntOut),
.resumeIntOut(slaveResumeIntOut),
.transDoneIntOut(slaveTransDoneIntOut),
.NAKSentIntOut(slaveNAKSentIntOut),
.vBusDetIntOut(slaveVBusDetIntOut),
.slaveControlSelect(slaveControlSel),
.TxFifoEP0REn(TxFifoEP0REn),
.TxFifoEP1REn(TxFifoEP1REn),
.TxFifoEP2REn(TxFifoEP2REn),
.TxFifoEP3REn(TxFifoEP3REn),
.TxFifoEP0Data(TxFifoEP0Data),
.TxFifoEP1Data(TxFifoEP1Data),
.TxFifoEP2Data(TxFifoEP2Data),
.TxFifoEP3Data(TxFifoEP3Data),
.TxFifoEP0Empty(TxFifoEP0Empty),
.TxFifoEP1Empty(TxFifoEP1Empty),
.TxFifoEP2Empty(TxFifoEP2Empty),
.TxFifoEP3Empty(TxFifoEP3Empty),
.RxFifoEP0WEn(RxFifoEP0WEn),
.RxFifoEP1WEn(RxFifoEP1WEn),
.RxFifoEP2WEn(RxFifoEP2WEn),
.RxFifoEP3WEn(RxFifoEP3WEn),
.RxFifoEP0Full(RxFifoEP0Full),
.RxFifoEP1Full(RxFifoEP1Full),
.RxFifoEP2Full(RxFifoEP2Full),
.RxFifoEP3Full(RxFifoEP3Full)
);
 
 
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(),
.hostRxFifoSel(),
.hostTxFifoSel(),
.slaveControlSel(slaveControlSel),
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(8'h00),
.dataFromHostRxFifo(8'h00),
.dataFromHostTxFifo(8'h00),
.dataFromSlaveControl(dataFromSlaveControl),
.dataFromEP0RxFifo(dataFromEP0RxFifo),
.dataFromEP1RxFifo(dataFromEP1RxFifo),
.dataFromEP2RxFifo(dataFromEP2RxFifo),
.dataFromEP3RxFifo(dataFromEP3RxFifo),
.dataFromEP0TxFifo(dataFromEP0TxFifo),
.dataFromEP1TxFifo(dataFromEP1TxFifo),
.dataFromEP2TxFifo(dataFromEP2TxFifo),
.dataFromEP3TxFifo(dataFromEP3TxFifo),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
 
 
 
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
 
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostSlaveMuxSel(hostSlaveMuxSel),
.hostMode(),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
 
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
 
 
 
//---Slave fifos
 
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP0REn),
.fifoEmpty(TxFifoEP0Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0TxFifo),
.fifoDataOut(TxFifoEP0Data) );
 
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP1REn),
.fifoEmpty(TxFifoEP1Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1TxFifo),
.fifoDataOut(TxFifoEP1Data) );
 
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP2REn),
.fifoEmpty(TxFifoEP2Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2TxFifo),
.fifoDataOut(TxFifoEP2Data) );
 
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP3REn),
.fifoEmpty(TxFifoEP3Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3TxFifo),
.fifoDataOut(TxFifoEP3Data) );
 
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP0WEn),
.fifoFull(RxFifoEP0Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP1WEn),
.fifoFull(RxFifoEP1Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP2WEn),
.fifoFull(RxFifoEP2Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP3WEn),
.fifoFull(RxFifoEP3Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
 
 
endmodule
 
 
 
 
 
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSlave.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbSlave(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
slaveVBusDetIntOut,
slaveNAKSentIntOut,
slaveSOFRxedIntOut,
slaveResetEventIntOut,
slaveResumeIntOut,
slaveTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
parameter EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_ADDR_WIDTH = 6;
 
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output slaveSOFRxedIntOut;
output slaveResetEventIntOut;
output slaveResumeIntOut;
output slaveTransDoneIntOut;
output slaveNAKSentIntOut;
output slaveVBusDetIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
 
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
wire USBDPlusPullup;
wire USBDMinusPullup;
wire vBusDetect;
 
//internal wiring
wire slaveControlSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostSlaveMux;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromSlave;
wire fullSpeedPolarityFromSlave;
wire SIEPortWEnFromSlave;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromSlave;
wire [7:0] SIEPortCtrlInFromSlave;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire connectSlaveToHost;
wire noActivityTimeOut;
wire TxFifoEP0REn;
wire TxFifoEP1REn;
wire TxFifoEP2REn;
wire TxFifoEP3REn;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
wire RxFifoEP0WEn;
wire RxFifoEP1WEn;
wire RxFifoEP2WEn;
wire RxFifoEP3WEn;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
wire [7:0] slaveRxFifoData;
wire [7:0] dataFromEP0RxFifo;
wire [7:0] dataFromEP1RxFifo;
wire [7:0] dataFromEP2RxFifo;
wire [7:0] dataFromEP3RxFifo;
wire [7:0] dataFromEP0TxFifo;
wire [7:0] dataFromEP1TxFifo;
wire [7:0] dataFromEP2TxFifo;
wire [7:0] dataFromEP3TxFifo;
wire slaveEP0RxFifoSel;
wire slaveEP1RxFifoSel;
wire slaveEP2RxFifoSel;
wire slaveEP3RxFifoSel;
wire slaveEP0TxFifoSel;
wire slaveEP1TxFifoSel;
wire slaveEP2TxFifoSel;
wire slaveEP3TxFifoSel;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
wire noActivityTimeOutEnableFromSlave;
 
// This is not a bug.
// USBFullSpeed controls the PHY edge speed.
// The only time that the PHY needs to operate with low speed edge rate is
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
// but according to spec edge speed must be full rate edge speed.
assign USBFullSpeed = fullSpeedPolarityToSIE;
//assign USBFullSpeed = fullSpeedBitRateToSIE;
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
 
usbSlaveControl u_usbSlaveControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
.RxFifoData(slaveRxFifoData),
.connectSlaveToHost(connectSlaveToHost),
.fullSpeedRate(fullSpeedBitRateFromSlave),
.fullSpeedPol(fullSpeedPolarityFromSlave),
.SCTxPortEn(SIEPortWEnFromSlave),
.SCTxPortRdy(SIEPortTxRdy),
.SCTxPortData(SIEPortDataInFromSlave),
.SCTxPortCtrl(SIEPortCtrlInFromSlave),
.vBusDetect(vBusDetect),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[4:0]),
.busDataIn(data_i),
.busDataOut(dataFromSlaveControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFRxedIntOut(slaveSOFRxedIntOut),
.resetEventIntOut(slaveResetEventIntOut),
.resumeIntOut(slaveResumeIntOut),
.transDoneIntOut(slaveTransDoneIntOut),
.NAKSentIntOut(slaveNAKSentIntOut),
.vBusDetIntOut(slaveVBusDetIntOut),
.slaveControlSelect(slaveControlSel),
.TxFifoEP0REn(TxFifoEP0REn),
.TxFifoEP1REn(TxFifoEP1REn),
.TxFifoEP2REn(TxFifoEP2REn),
.TxFifoEP3REn(TxFifoEP3REn),
.TxFifoEP0Data(TxFifoEP0Data),
.TxFifoEP1Data(TxFifoEP1Data),
.TxFifoEP2Data(TxFifoEP2Data),
.TxFifoEP3Data(TxFifoEP3Data),
.TxFifoEP0Empty(TxFifoEP0Empty),
.TxFifoEP1Empty(TxFifoEP1Empty),
.TxFifoEP2Empty(TxFifoEP2Empty),
.TxFifoEP3Empty(TxFifoEP3Empty),
.RxFifoEP0WEn(RxFifoEP0WEn),
.RxFifoEP1WEn(RxFifoEP1WEn),
.RxFifoEP2WEn(RxFifoEP2WEn),
.RxFifoEP3WEn(RxFifoEP3WEn),
.RxFifoEP0Full(RxFifoEP0Full),
.RxFifoEP1Full(RxFifoEP1Full),
.RxFifoEP2Full(RxFifoEP2Full),
.RxFifoEP3Full(RxFifoEP3Full)
);
 
 
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(),
.hostRxFifoSel(),
.hostTxFifoSel(),
.slaveControlSel(slaveControlSel),
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(8'h00),
.dataFromHostRxFifo(8'h00),
.dataFromHostTxFifo(8'h00),
.dataFromSlaveControl(dataFromSlaveControl),
.dataFromEP0RxFifo(dataFromEP0RxFifo),
.dataFromEP1RxFifo(dataFromEP1RxFifo),
.dataFromEP2RxFifo(dataFromEP2RxFifo),
.dataFromEP3RxFifo(dataFromEP3RxFifo),
.dataFromEP0TxFifo(dataFromEP0TxFifo),
.dataFromEP1TxFifo(dataFromEP1TxFifo),
.dataFromEP2TxFifo(dataFromEP2TxFifo),
.dataFromEP3TxFifo(dataFromEP3TxFifo),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
 
 
 
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
 
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostSlaveMuxSel(hostSlaveMuxSel),
.hostMode(),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
 
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
 
 
 
//---Slave fifos
 
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP0REn),
.fifoEmpty(TxFifoEP0Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0TxFifo),
.fifoDataOut(TxFifoEP0Data) );
 
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP1REn),
.fifoEmpty(TxFifoEP1Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1TxFifo),
.fifoDataOut(TxFifoEP1Data) );
 
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP2REn),
.fifoEmpty(TxFifoEP2Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2TxFifo),
.fifoDataOut(TxFifoEP2Data) );
 
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP3REn),
.fifoEmpty(TxFifoEP3Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3TxFifo),
.fifoDataOut(TxFifoEP3Data) );
 
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP0WEn),
.fifoFull(RxFifoEP0Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP1WEn),
.fifoFull(RxFifoEP1Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP2WEn),
.fifoFull(RxFifoEP2Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP3WEn),
.fifoFull(RxFifoEP3Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3RxFifo),
.fifoDataIn(slaveRxFifoData) );
 
 
 
endmodule
 
 
 
 
 
/trunk/RTL/wrapper/usbHost.v
1,314 → 1,320
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHost.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbHost(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
hostSOFSentIntOut,
hostConnEventIntOut,
hostResumeIntOut,
hostTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed
);
parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = 2^HOST_ADDR_WIDTH
parameter HOST_FIFO_ADDR_WIDTH = 6;
 
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output hostSOFSentIntOut;
output hostConnEventIntOut;
output hostResumeIntOut;
output hostTransDoneIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
 
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
 
//internal wiring
wire hostControlSel;
wire slaveControlSel;
wire hostRxFifoSel;
wire hostTxFifoSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromHostControl;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostRxFifo;
wire [7:0] dataFromHostTxFifo;
wire [7:0] dataFromHostSlaveMux;
wire hostTxFifoRE;
wire [7:0] hostTxFifoData;
wire hostTxFifoEmpty;
wire hostRxFifoWE;
wire [7:0] hostRxFifoData;
wire hostRxFifoFull;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromHost;
wire fullSpeedPolarityFromHost;
wire SIEPortWEnFromHost;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromHost;
wire [7:0] SIEPortCtrlInFromHost;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire noActivityTimeOut;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
 
assign USBFullSpeed = fullSpeedBitRateToSIE;
 
 
usbHostControl u_usbHostControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.TxFifoRE(hostTxFifoRE),
.TxFifoData(hostTxFifoData),
.TxFifoEmpty(hostTxFifoEmpty),
.RxFifoWE(hostRxFifoWE),
.RxFifoData(hostRxFifoData),
.RxFifoFull(hostRxFifoFull),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
.fullSpeedRate(fullSpeedBitRateFromHost),
.fullSpeedPol(fullSpeedPolarityFromHost),
.HCTxPortEn(SIEPortWEnFromHost),
.HCTxPortRdy(SIEPortTxRdy),
.HCTxPortData(SIEPortDataInFromHost),
.HCTxPortCtrl(SIEPortCtrlInFromHost),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[3:0]),
.busDataIn(data_i),
.busDataOut(dataFromHostControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFSentIntOut(hostSOFSentIntOut),
.connEventIntOut(hostConnEventIntOut),
.resumeIntOut(hostResumeIntOut),
.transDoneIntOut(hostTransDoneIntOut),
.hostControlSelect(hostControlSel) );
 
 
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(hostControlSel),
.hostRxFifoSel(hostRxFifoSel),
.hostTxFifoSel(hostTxFifoSel),
.slaveControlSel(),
.slaveEP0RxFifoSel(),
.slaveEP1RxFifoSel(),
.slaveEP2RxFifoSel(),
.slaveEP3RxFifoSel(),
.slaveEP0TxFifoSel(),
.slaveEP1TxFifoSel(),
.slaveEP2TxFifoSel(),
.slaveEP3TxFifoSel(),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(dataFromHostControl),
.dataFromHostRxFifo(dataFromHostRxFifo),
.dataFromHostTxFifo(dataFromHostTxFifo),
.dataFromSlaveControl(8'h00),
.dataFromEP0RxFifo(8'h00),
.dataFromEP1RxFifo(8'h00),
.dataFromEP2RxFifo(8'h00),
.dataFromEP3RxFifo(8'h00),
.dataFromEP0TxFifo(8'h00),
.dataFromEP1TxFifo(8'h00),
.dataFromEP2TxFifo(8'h00),
.dataFromEP3TxFifo(8'h00),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
 
 
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromHost;
assign SIEPortDataInToSIE = SIEPortDataInFromHost;
assign SIEPortWEnToSIE = SIEPortWEnFromHost;
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromHost;
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromHost;
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromHost;
 
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostMode(hostMode),
.hostSlaveMuxSel(hostSlaveMuxSel),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
 
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
 
 
 
//---Host fifos
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(hostTxFifoRE),
.fifoEmpty(hostTxFifoEmpty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostTxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostTxFifo),
.fifoDataOut(hostTxFifoData) );
 
 
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(hostRxFifoWE),
.fifoFull(hostRxFifoFull),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostRxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostRxFifo),
.fifoDataIn(hostRxFifoData) );
 
 
endmodule
 
 
 
 
 
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHost.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbHost(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
hostSOFSentIntOut,
hostConnEventIntOut,
hostResumeIntOut,
hostTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed
);
parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = 2^HOST_ADDR_WIDTH
parameter HOST_FIFO_ADDR_WIDTH = 6;
 
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output hostSOFSentIntOut;
output hostConnEventIntOut;
output hostResumeIntOut;
output hostTransDoneIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
 
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
 
//internal wiring
wire hostControlSel;
wire slaveControlSel;
wire hostRxFifoSel;
wire hostTxFifoSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromHostControl;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostRxFifo;
wire [7:0] dataFromHostTxFifo;
wire [7:0] dataFromHostSlaveMux;
wire hostTxFifoRE;
wire [7:0] hostTxFifoData;
wire hostTxFifoEmpty;
wire hostRxFifoWE;
wire [7:0] hostRxFifoData;
wire hostRxFifoFull;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromHost;
wire fullSpeedPolarityFromHost;
wire SIEPortWEnFromHost;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromHost;
wire [7:0] SIEPortCtrlInFromHost;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire noActivityTimeOut;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
 
// This is not a bug.
// USBFullSpeed controls the PHY edge speed.
// The only time that the PHY needs to operate with low speed edge rate is
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
// but according to spec edge speed must be full rate edge speed.
assign USBFullSpeed = fullSpeedPolarityToSIE;
//assign USBFullSpeed = fullSpeedBitRateToSIE;
 
usbHostControl u_usbHostControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.TxFifoRE(hostTxFifoRE),
.TxFifoData(hostTxFifoData),
.TxFifoEmpty(hostTxFifoEmpty),
.RxFifoWE(hostRxFifoWE),
.RxFifoData(hostRxFifoData),
.RxFifoFull(hostRxFifoFull),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
.fullSpeedRate(fullSpeedBitRateFromHost),
.fullSpeedPol(fullSpeedPolarityFromHost),
.HCTxPortEn(SIEPortWEnFromHost),
.HCTxPortRdy(SIEPortTxRdy),
.HCTxPortData(SIEPortDataInFromHost),
.HCTxPortCtrl(SIEPortCtrlInFromHost),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[3:0]),
.busDataIn(data_i),
.busDataOut(dataFromHostControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFSentIntOut(hostSOFSentIntOut),
.connEventIntOut(hostConnEventIntOut),
.resumeIntOut(hostResumeIntOut),
.transDoneIntOut(hostTransDoneIntOut),
.hostControlSelect(hostControlSel) );
 
 
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(hostControlSel),
.hostRxFifoSel(hostRxFifoSel),
.hostTxFifoSel(hostTxFifoSel),
.slaveControlSel(),
.slaveEP0RxFifoSel(),
.slaveEP1RxFifoSel(),
.slaveEP2RxFifoSel(),
.slaveEP3RxFifoSel(),
.slaveEP0TxFifoSel(),
.slaveEP1TxFifoSel(),
.slaveEP2TxFifoSel(),
.slaveEP3TxFifoSel(),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(dataFromHostControl),
.dataFromHostRxFifo(dataFromHostRxFifo),
.dataFromHostTxFifo(dataFromHostTxFifo),
.dataFromSlaveControl(8'h00),
.dataFromEP0RxFifo(8'h00),
.dataFromEP1RxFifo(8'h00),
.dataFromEP2RxFifo(8'h00),
.dataFromEP3RxFifo(8'h00),
.dataFromEP0TxFifo(8'h00),
.dataFromEP1TxFifo(8'h00),
.dataFromEP2TxFifo(8'h00),
.dataFromEP3TxFifo(8'h00),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
 
 
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromHost;
assign SIEPortDataInToSIE = SIEPortDataInFromHost;
assign SIEPortWEnToSIE = SIEPortWEnFromHost;
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromHost;
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromHost;
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromHost;
 
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostMode(hostMode),
.hostSlaveMuxSel(hostSlaveMuxSel),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
 
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
 
 
 
//---Host fifos
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(hostTxFifoRE),
.fifoEmpty(hostTxFifoEmpty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostTxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostTxFifo),
.fifoDataOut(hostTxFifoData) );
 
 
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(hostRxFifoWE),
.fifoFull(hostRxFifoFull),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(hostRxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromHostRxFifo),
.fifoDataIn(hostRxFifoData) );
 
 
endmodule
 
 
 
 
 
/trunk/RTL/hostController/sendpacketcheckpreamble.v
1,205 → 1,205
 
// File : ../RTL/hostController/sendpacketcheckpreamble.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/sendpacketcheckpreamble.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// sendpacketcheckpreamble
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbConstants_h.v"
 
module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input clk;
input preAmbleEnable;
input rst;
input [3:0] sendPacketCPPID;
input sendPacketCPWEn;
input sendPacketRdy;
output sendPacketCPReady;
output [3:0] sendPacketPID;
output sendPacketWEn;
 
wire clk;
wire preAmbleEnable;
wire rst;
wire [3:0] sendPacketCPPID;
reg sendPacketCPReady, next_sendPacketCPReady;
wire sendPacketCPWEn;
reg [3:0] sendPacketPID, next_sendPacketPID;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
 
// BINARY ENCODED state machine: sendPktCP
// State codes definitions:
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_PREAM_SENT 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_PID_SENT 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
`define PREAM_PKT_WAIT_RDY2 4'b1100
`define PREAM_PKT_WAIT_RDY3 4'b1101
 
reg [3:0] CurrState_sendPktCP;
reg [3:0] NextState_sendPktCP;
 
 
//--------------------------------------------------------------------
// Machine: sendPktCP
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
begin : sendPktCP_NextState
NextState_sendPktCP <= CurrState_sendPktCP;
// Set default values for outputs and signals
next_sendPacketCPReady <= sendPacketCPReady;
next_sendPacketWEn <= sendPacketWEn;
next_sendPacketPID <= sendPacketPID;
case (CurrState_sendPktCP)
`SPC_WAIT_EN:
if (sendPacketCPWEn == 1'b1)
begin
NextState_sendPktCP <= `CHK_PREAM;
next_sendPacketCPReady <= 1'b0;
end
`START_SPC:
NextState_sendPktCP <= `SPC_WAIT_EN;
`CHK_PREAM:
if (preAmbleEnable == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
else
NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
`READY:
begin
next_sendPacketCPReady <= 1'b1;
NextState_sendPktCP <= `SPC_WAIT_EN;
end
`PREAM_PKT_SND_PREAM:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= `PREAMBLE;
NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
end
`PREAM_PKT_WAIT_RDY1:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
`PREAM_PKT_PREAM_SENT:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
end
`PREAM_PKT_SND_PID:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= sendPacketCPPID;
NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
end
`PREAM_PKT_PID_SENT:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
end
`PREAM_PKT_WAIT_RDY2:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_SND_PID;
`PREAM_PKT_WAIT_RDY3:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `READY;
`REG_PKT_SEND_PID:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= sendPacketCPPID;
NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
end
`REG_PKT_WAIT_RDY1:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `REG_PKT_SEND_PID;
`REG_PKT_WAIT_RDY:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `READY;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_CurrentState
if (rst)
CurrState_sendPktCP <= `START_SPC;
else
CurrState_sendPktCP <= NextState_sendPktCP;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_RegOutput
if (rst)
begin
sendPacketWEn <= 1'b0;
sendPacketPID <= 4'b0;
sendPacketCPReady <= 1'b1;
end
else
begin
sendPacketWEn <= next_sendPacketWEn;
sendPacketPID <= next_sendPacketPID;
sendPacketCPReady <= next_sendPacketCPReady;
end
end
 
endmodule
 
// File : ../RTL/hostController/sendpacketcheckpreamble.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/sendpacketcheckpreamble.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// sendpacketcheckpreamble
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbConstants_h.v"
 
module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input clk;
input preAmbleEnable;
input rst;
input [3:0] sendPacketCPPID;
input sendPacketCPWEn;
input sendPacketRdy;
output sendPacketCPReady;
output [3:0] sendPacketPID;
output sendPacketWEn;
 
wire clk;
wire preAmbleEnable;
wire rst;
wire [3:0] sendPacketCPPID;
reg sendPacketCPReady, next_sendPacketCPReady;
wire sendPacketCPWEn;
reg [3:0] sendPacketPID, next_sendPacketPID;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
 
// BINARY ENCODED state machine: sendPktCP
// State codes definitions:
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_PREAM_SENT 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_PID_SENT 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
`define PREAM_PKT_WAIT_RDY2 4'b1100
`define PREAM_PKT_WAIT_RDY3 4'b1101
 
reg [3:0] CurrState_sendPktCP;
reg [3:0] NextState_sendPktCP;
 
 
//--------------------------------------------------------------------
// Machine: sendPktCP
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
begin : sendPktCP_NextState
NextState_sendPktCP <= CurrState_sendPktCP;
// Set default values for outputs and signals
next_sendPacketCPReady <= sendPacketCPReady;
next_sendPacketWEn <= sendPacketWEn;
next_sendPacketPID <= sendPacketPID;
case (CurrState_sendPktCP)
`SPC_WAIT_EN:
if (sendPacketCPWEn == 1'b1)
begin
NextState_sendPktCP <= `CHK_PREAM;
next_sendPacketCPReady <= 1'b0;
end
`START_SPC:
NextState_sendPktCP <= `SPC_WAIT_EN;
`CHK_PREAM:
if (preAmbleEnable == 1'b1 && sendPacketCPPID != `SOF)
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
else
NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
`READY:
begin
next_sendPacketCPReady <= 1'b1;
NextState_sendPktCP <= `SPC_WAIT_EN;
end
`PREAM_PKT_SND_PREAM:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= `PREAMBLE;
NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
end
`PREAM_PKT_WAIT_RDY1:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
`PREAM_PKT_PREAM_SENT:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
end
`PREAM_PKT_SND_PID:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= sendPacketCPPID;
NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
end
`PREAM_PKT_PID_SENT:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
end
`PREAM_PKT_WAIT_RDY2:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_SND_PID;
`PREAM_PKT_WAIT_RDY3:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `READY;
`REG_PKT_SEND_PID:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= sendPacketCPPID;
NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
end
`REG_PKT_WAIT_RDY1:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `REG_PKT_SEND_PID;
`REG_PKT_WAIT_RDY:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `READY;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_CurrentState
if (rst)
CurrState_sendPktCP <= `START_SPC;
else
CurrState_sendPktCP <= NextState_sendPktCP;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_RegOutput
if (rst)
begin
sendPacketWEn <= 1'b0;
sendPacketPID <= 4'b0;
sendPacketCPReady <= 1'b1;
end
else
begin
sendPacketWEn <= next_sendPacketWEn;
sendPacketPID <= next_sendPacketPID;
sendPacketCPReady <= next_sendPacketCPReady;
end
end
 
endmodule
/trunk/RTL/include/usbSerialInterfaceEngine_h.v
1,108 → 1,109
//////////////////////////////////////////////////////////////////////
// usbSerialInterfaceEngine_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSerialInterfaceEngine_h_vdefined
`else
`define usbSerialInterfaceEngine_h_vdefined
 
// Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
`define FS_OVER_SAMPLE_RATE 4
`define LS_OVER_SAMPLE_RATE 32
 
//timeOuts
`define RX_PACKET_TOUT 18
`define RX_EDGE_DET_TOUT 7
 
//TXStreamControlTypes
`define TX_DIRECT_CONTROL 8'h00
`define TX_RESUME_START 8'h01
`define TX_PACKET_START 8'h02
`define TX_PACKET_STREAM 8'h03
`define TX_PACKET_STOP 8'h04
`define TX_IDLE 8'h05
`define TX_LS_KEEP_ALIVE 8'h06
 
//RXStreamControlTypes
`define RX_PACKET_START 0
`define RX_PACKET_STREAM 1
`define RX_PACKET_STOP 2
 
//USBLineStates
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
`define ONE_ZERO 2'b10
`define ZERO_ONE 2'b01
`define SE0 2'b00
`define SE1 2'b11
 
//RXStatusIndices
`define CRC_ERROR_BIT 0
`define BIT_STUFF_ERROR_BIT 1
`define RX_OVERFLOW_BIT 2
`define NAK_RXED_BIT 3
`define STALL_RXED_BIT 4
`define ACK_RXED_BIT 5
`define DATA_SEQUENCE_BIT 6
 
//usbWireControlStates
`define TRI_STATE 1'b0
`define DRIVE 1'b1
 
//limits
`define MAX_CONSEC_SAME_BITS 4'h6
`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
// RESUME_RX_WAIT_TIME defines the time period for resume detection
// The resume counter is incremented at the bit rate, so
// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of
// 2.5uS <= resumeDetectTime <= 100uS
`define RESUME_RX_WAIT_TIME 5'd29
//`define RESUME_WAIT_TIME_MINUS1 9
// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate
`ifdef SIM_COMPILE
`define HOST_TX_RESUME_TIME 16'd10
`else
`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS
`endif
//`define CONNECT_WAIT_TIME 8'd20
`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS
//`define DISCONNECT_WAIT_TIME 8'd20
`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS
 
//RXConnectStates
`define DISCONNECT 2'b00
`define LOW_SPEED_CONNECT 2'b01
`define FULL_SPEED_CONNECT 2'b10
 
//TX_RX_InternalStreamTypes
`define DATA_START 8'h00
`define DATA_STOP 8'h01
`define DATA_STREAM 8'h02
`define DATA_BIT_STUFF_ERROR 8'h03
 
//RXStMach states
`define DISCONNECT_ST 4'h0
`define WAIT_FULL_SPEED_CONN_ST 4'h1
`define WAIT_LOW_SPEED_CONN_ST 4'h2
`define CONNECT_LOW_SPEED_ST 4'h3
`define CONNECT_FULL_SPEED_ST 4'h4
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
 
//RXBitStateMachStates
`define IDLE_BIT_ST 2'b00
`define DATA_RECEIVE_BIT_ST 2'b01
`define WAIT_RESUME_ST 2'b10
`define RESUME_END_WAIT_ST 2'b11
 
//RXByteStateMachStates
`define IDLE_BYTE_ST 3'b000
`define CHECK_SYNC_ST 3'b001
`define CHECK_PID_ST 3'b010
`define HS_BYTE_ST 3'b011
`define TOKEN_BYTE_ST 3'b100
`define DATA_BYTE_ST 3'b101
 
`endif //usbSerialInterfaceEngine_h_vdefined
 
 
//////////////////////////////////////////////////////////////////////
// usbSerialInterfaceEngine_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSerialInterfaceEngine_h_vdefined
`else
`define usbSerialInterfaceEngine_h_vdefined
 
// Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
`define FS_OVER_SAMPLE_RATE 4
`define LS_OVER_SAMPLE_RATE 32
 
//timeOuts
`define RX_PACKET_TOUT 18
`define RX_EDGE_DET_TOUT 7
 
//TXStreamControlTypes
`define TX_DIRECT_CONTROL 8'h00
`define TX_RESUME_START 8'h01
`define TX_PACKET_START 8'h02
`define TX_PACKET_STREAM 8'h03
`define TX_PACKET_STOP 8'h04
`define TX_IDLE 8'h05
`define TX_LS_KEEP_ALIVE 8'h06
 
//RXStreamControlTypes
`define RX_PACKET_START 0
`define RX_PACKET_STREAM 1
`define RX_PACKET_STOP 2
 
//USBLineStates
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
`define ONE_ZERO 2'b10
`define ZERO_ONE 2'b01
`define SE0 2'b00
`define SE1 2'b11
 
//RXStatusIndices
`define CRC_ERROR_BIT 0
`define BIT_STUFF_ERROR_BIT 1
`define RX_OVERFLOW_BIT 2
`define NAK_RXED_BIT 3
`define STALL_RXED_BIT 4
`define ACK_RXED_BIT 5
`define DATA_SEQUENCE_BIT 6
 
//usbWireControlStates
`define TRI_STATE 1'b0
`define DRIVE 1'b1
 
//limits
`define MAX_CONSEC_SAME_BITS 4'h6
`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
// RESUME_RX_WAIT_TIME defines the time period for resume detection
// The resume counter is incremented at the bit rate, so
// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of
// 2.5uS <= resumeDetectTime <= 100uS
`define RESUME_RX_WAIT_TIME 5'd29
//`define RESUME_WAIT_TIME_MINUS1 9
// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate
`ifdef SIM_COMPILE
`define HOST_TX_RESUME_TIME 16'd10
`else
`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS
`endif
//`define CONNECT_WAIT_TIME 8'd20
`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS
//`define DISCONNECT_WAIT_TIME 8'd20
`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS
 
//RXConnectStates
`define DISCONNECT 2'b00
`define LOW_SPEED_CONNECT 2'b01
`define FULL_SPEED_CONNECT 2'b10
 
//TX_RX_InternalStreamTypes
`define DATA_START 8'h00
`define DATA_STOP 8'h01
`define DATA_STREAM 8'h02
`define DATA_BIT_STUFF_ERROR 8'h03
`define DATA_STOP_PRE 8'h04
 
//RXStMach states
`define DISCONNECT_ST 4'h0
`define WAIT_FULL_SPEED_CONN_ST 4'h1
`define WAIT_LOW_SPEED_CONN_ST 4'h2
`define CONNECT_LOW_SPEED_ST 4'h3
`define CONNECT_FULL_SPEED_ST 4'h4
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
 
//RXBitStateMachStates
`define IDLE_BIT_ST 2'b00
`define DATA_RECEIVE_BIT_ST 2'b01
`define WAIT_RESUME_ST 2'b10
`define RESUME_END_WAIT_ST 2'b11
 
//RXByteStateMachStates
`define IDLE_BYTE_ST 3'b000
`define CHECK_SYNC_ST 3'b001
`define CHECK_PID_ST 3'b010
`define HS_BYTE_ST 3'b011
`define TOKEN_BYTE_ST 3'b100
`define DATA_BYTE_ST 3'b101
 
`endif //usbSerialInterfaceEngine_h_vdefined
 
 
/trunk/RTL/include/usbHostSlave_h.v
1,53 → 1,53
//////////////////////////////////////////////////////////////////////
// usbHostSlave_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostSlave_h_vdefined
`else
`define usbHostSlave_h_vdefined
 
// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
// control reads and writes to USB flash dongle
// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
// speed, and TX resume is always low speed.
// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
// in missing receive packets.
// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
// by adding kludged delay to softranmit. This needs to be fixed properly.
// This version has undergone limited testing
// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
// with uClinux, and is known to work with a full speed USB flash stick.
// Moving Opencores project status from Beta to done.
// TODO: Test isochronous mode, and low speed mode using uClinux driver
// Create a seperate clock domain for the bus interface
// Add frame period adjustment capability
// Add compilation flags for slave only and host only versions
// Create data bus width options beyond 8-bit
// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
// Removed TX and RX fifo status registers, and removed
// TX fifo data count register.
// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
// Fixed slave mode bug which caused receive fifo to be filled with
// incoming data when the slave was responding with a NAK, and the
// data should have been discarded.
// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
// there was no detected activity on the USB data lines. This caused an infrequent
// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
// the higher level state machines are actively looking for receive packets.
// Modified USB RX data clock recovery, so that data is sampled during the middle
// of a USB bit period. Fixed a bug which could result in double sampling
// of USB RX data if clock phase adjustments were required in the middle of a
// USB packet.
// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
// during migration to ActiveHDL 7.1. Released SystemC test bench.
// Re-generated .v files using ActiveHDL 7.1
// Replaced individual timescale directives with `include "timescale.v
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
// 'usbHostSlaveAvalonWrap'
//////////////////////////////////////////////////////////////////////
// usbHostSlave_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostSlave_h_vdefined
`else
`define usbHostSlave_h_vdefined
 
// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
// control reads and writes to USB flash dongle
// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
// speed, and TX resume is always low speed.
// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
// in missing receive packets.
// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
// by adding kludged delay to softranmit. This needs to be fixed properly.
// This version has undergone limited testing
// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
// with uClinux, and is known to work with a full speed USB flash stick.
// Moving Opencores project status from Beta to done.
// TODO: Test isochronous mode, and low speed mode using uClinux driver
// Create a seperate clock domain for the bus interface
// Add frame period adjustment capability
// Add compilation flags for slave only and host only versions
// Create data bus width options beyond 8-bit
// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
// Removed TX and RX fifo status registers, and removed
// TX fifo data count register.
// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
// Fixed slave mode bug which caused receive fifo to be filled with
// incoming data when the slave was responding with a NAK, and the
// data should have been discarded.
// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
// there was no detected activity on the USB data lines. This caused an infrequent
// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
// the higher level state machines are actively looking for receive packets.
// Modified USB RX data clock recovery, so that data is sampled during the middle
// of a USB bit period. Fixed a bug which could result in double sampling
// of USB RX data if clock phase adjustments were required in the middle of a
// USB packet.
// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
// during migration to ActiveHDL 7.1. Released SystemC test bench.
// Re-generated .v files using ActiveHDL 7.1
// Replaced individual timescale directives with `include "timescale.v
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
// 'usbHostSlaveAvalonWrap'
// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
// synchronizer to incoming USB wire data to avoid
// metastability, and delay hazards. Not entirely sure, but it appears that
66,15 → 66,22
// Modified cross-clock synchronisation of fifo resets
// Added usbDevice, a standalone usb device implementation of usbhostslave
// no additional hardware or software required
 
 
// Most significant nibble corresponds to major revision.
// Least significant nibble corresponds to minor revision.
`define USBHOSTSLAVE_VERSION_NUM 8'h20
 
//Host slave common registers
`define HOST_SLAVE_CONTROL_REG 1'b0
`define HOST_SLAVE_VERSION_REG 1'b1
 
`endif //usbHostSlave_h_vdefined
 
// Version 2.1 - October 8th 2010. Fixed issues related to accessing low speed device via hub.
// Changed USB PHY 'USBFullSpeed' edge rate control pin so that it is wired to
// 'fullSpeedPolarityToSIE', rather than 'fullSpeedBitRateToSIE'.
// Introduced delay into 'fullSpeedRate' in module writeUSBWireData.v. Thus matching
// data delay with control delay.
// Created new control flow constant DATA_STOP_PRE. This allows PREAMBLE PID to completed
// without SEO (EOP), and ensures line state is left at state J.
// Prevented PREAMBLE PID from preceding SOF when PREAMBLE is enabled.
 
// Most significant nibble corresponds to major revision.
// Least significant nibble corresponds to minor revision.
`define USBHOSTSLAVE_VERSION_NUM 8'h21
 
//Host slave common registers
`define HOST_SLAVE_CONTROL_REG 1'b0
`define HOST_SLAVE_VERSION_REG 1'b1
 
`endif //usbHostSlave_h_vdefined
 
/trunk/RTL/serialInterfaceEngine/SIETransmitter.v
1,153 → 1,153
 
// File : ../RTL/serialInterfaceEngine/SIETransmitter.v
 
// File : ../RTL/serialInterfaceEngine/SIETransmitter.v
// Generated : 10/15/06 20:31:22
// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// SIETransmitter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
input [15:0] CRC16Result;
input CRC16UpdateRdy;
input [4:0] CRC5Result;
input CRC5UpdateRdy;
input [1:0] JBit;
input [1:0] KBit;
input [7:0] SIEPortCtrlIn;
input [7:0] SIEPortDataIn;
input SIEPortWEn;
input USBWireGnt;
input USBWireRdy;
input clk;
input fullSpeedRateIn;
input processTxByteRdy;
input rst;
output CRC16En;
output CRC5En;
output CRC5_8Bit;
output [7:0] CRCData;
output SIEPortTxRdy;
output [7:0] TxByteOutCtrl;
output TxByteOutFullSpeedRate;
output [7:0] TxByteOut;
output USBWireCtrl;
output [1:0] USBWireData;
output USBWireFullSpeedRate;
output USBWireReq;
output USBWireWEn;
output processTxByteWEn;
output rstCRC;
 
reg CRC16En, next_CRC16En;
wire [15:0] CRC16Result;
wire CRC16UpdateRdy;
reg CRC5En, next_CRC5En;
wire [4:0] CRC5Result;
wire CRC5UpdateRdy;
reg CRC5_8Bit, next_CRC5_8Bit;
reg [7:0] CRCData, next_CRCData;
wire [1:0] JBit;
wire [1:0] KBit;
wire [7:0] SIEPortCtrlIn;
wire [7:0] SIEPortDataIn;
reg SIEPortTxRdy, next_SIEPortTxRdy;
wire SIEPortWEn;
reg [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
reg [7:0] TxByteOut, next_TxByteOut;
reg USBWireCtrl, next_USBWireCtrl;
reg [1:0] USBWireData, next_USBWireData;
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire USBWireGnt;
wire USBWireRdy;
reg USBWireReq, next_USBWireReq;
reg USBWireWEn, next_USBWireWEn;
wire clk;
wire fullSpeedRateIn;
wire processTxByteRdy;
reg processTxByteWEn, next_processTxByteWEn;
wire rst;
reg rstCRC, next_rstCRC;
 
// diagram signals declarations
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
reg [7:0]SIEPortData, next_SIEPortData;
reg [2:0]i, next_i;
reg [15:0]resumeCnt, next_resumeCnt;
 
// BINARY ENCODED state machine: SIETx
// State codes definitions:
`define DIR_CTL_CHK_FIN 6'b000000
`define RES_ST_CHK_FIN 6'b000001
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define IDLE 6'b000100
// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// SIETransmitter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
input [15:0] CRC16Result;
input CRC16UpdateRdy;
input [4:0] CRC5Result;
input CRC5UpdateRdy;
input [1:0] JBit;
input [1:0] KBit;
input [7:0] SIEPortCtrlIn;
input [7:0] SIEPortDataIn;
input SIEPortWEn;
input USBWireGnt;
input USBWireRdy;
input clk;
input fullSpeedRateIn;
input processTxByteRdy;
input rst;
output CRC16En;
output CRC5En;
output CRC5_8Bit;
output [7:0] CRCData;
output SIEPortTxRdy;
output [7:0] TxByteOutCtrl;
output TxByteOutFullSpeedRate;
output [7:0] TxByteOut;
output USBWireCtrl;
output [1:0] USBWireData;
output USBWireFullSpeedRate;
output USBWireReq;
output USBWireWEn;
output processTxByteWEn;
output rstCRC;
 
reg CRC16En, next_CRC16En;
wire [15:0] CRC16Result;
wire CRC16UpdateRdy;
reg CRC5En, next_CRC5En;
wire [4:0] CRC5Result;
wire CRC5UpdateRdy;
reg CRC5_8Bit, next_CRC5_8Bit;
reg [7:0] CRCData, next_CRCData;
wire [1:0] JBit;
wire [1:0] KBit;
wire [7:0] SIEPortCtrlIn;
wire [7:0] SIEPortDataIn;
reg SIEPortTxRdy, next_SIEPortTxRdy;
wire SIEPortWEn;
reg [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
reg [7:0] TxByteOut, next_TxByteOut;
reg USBWireCtrl, next_USBWireCtrl;
reg [1:0] USBWireData, next_USBWireData;
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire USBWireGnt;
wire USBWireRdy;
reg USBWireReq, next_USBWireReq;
reg USBWireWEn, next_USBWireWEn;
wire clk;
wire fullSpeedRateIn;
wire processTxByteRdy;
reg processTxByteWEn, next_processTxByteWEn;
wire rst;
reg rstCRC, next_rstCRC;
 
// diagram signals declarations
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
reg [7:0]SIEPortData, next_SIEPortData;
reg [2:0]i, next_i;
reg [15:0]resumeCnt, next_resumeCnt;
 
// BINARY ENCODED state machine: SIETx
// State codes definitions:
`define DIR_CTL_CHK_FIN 6'b000000
`define RES_ST_CHK_FIN 6'b000001
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define IDLE 6'b000100
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
`define PKT_ST_HS_PKT_SENT 6'b000111
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
`define PKT_ST_SPCL_PKT_SENT 6'b001010
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_SND_J_1 6'b001110
`define RES_ST_SND_J_2 6'b001111
`define RES_ST_SND_SE0_1 6'b010000
`define RES_ST_SND_SE0_2 6'b010001
`define START_SIETX 6'b010010
`define STX_CHK_ST 6'b010011
`define STX_WAIT_BYTE 6'b010100
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_SND_J_1 6'b001110
`define RES_ST_SND_J_2 6'b001111
`define RES_ST_SND_SE0_1 6'b010000
`define RES_ST_SND_SE0_2 6'b010001
`define START_SIETX 6'b010010
`define STX_CHK_ST 6'b010011
`define STX_WAIT_BYTE 6'b010100
`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
`define DIR_CTL_WAIT_GNT 6'b011011
161,554 → 161,557
`define RES_ST_WAIT_RDY 6'b100011
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
`define PKT_ST_WAIT_RDY_PKT 6'b101000
`define RES_ST_W_RDY1 6'b101001
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
`define TX_LS_EOP_WAIT_GNT1 6'b101101
`define TX_LS_EOP_SND_SE0_2 6'b101110
`define TX_LS_EOP_SND_SE0_1 6'b101111
`define TX_LS_EOP_W_RDY1 6'b110000
`define TX_LS_EOP_SND_J 6'b110001
`define TX_LS_EOP_W_RDY2 6'b110010
`define TX_LS_EOP_W_RDY3 6'b110011
`define RES_ST_DELAY 6'b110100
`define RES_ST_W_RDY2 6'b110101
`define RES_ST_W_RDY3 6'b110110
`define RES_ST_W_RDY4 6'b110111
`define DIR_CTL_DELAY 6'b111000
 
reg [5:0] CurrState_SIETx;
reg [5:0] NextState_SIETx;
 
 
//--------------------------------------------------------------------
// Machine: SIETx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
begin : SIETx_NextState
NextState_SIETx <= CurrState_SIETx;
// Set default values for outputs and signals
next_processTxByteWEn <= processTxByteWEn;
next_TxByteOut <= TxByteOut;
next_TxByteOutCtrl <= TxByteOutCtrl;
next_USBWireData <= USBWireData;
next_USBWireCtrl <= USBWireCtrl;
next_USBWireReq <= USBWireReq;
next_USBWireWEn <= USBWireWEn;
next_rstCRC <= rstCRC;
next_CRCData <= CRCData;
next_CRC5En <= CRC5En;
next_CRC5_8Bit <= CRC5_8Bit;
next_CRC16En <= CRC16En;
next_SIEPortTxRdy <= SIEPortTxRdy;
next_SIEPortData <= SIEPortData;
next_SIEPortCtrl <= SIEPortCtrl;
next_i <= i;
next_resumeCnt <= resumeCnt;
next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
case (CurrState_SIETx)
`IDLE:
NextState_SIETx <= `STX_WAIT_BYTE;
`START_SIETX:
begin
next_processTxByteWEn <= 1'b0;
next_TxByteOut <= 8'h00;
next_TxByteOutCtrl <= 8'h00;
next_USBWireData <= 2'b00;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireReq <= 1'b0;
next_USBWireWEn <= 1'b0;
next_rstCRC <= 1'b0;
next_CRCData <= 8'h00;
next_CRC5En <= 1'b0;
next_CRC5_8Bit <= 1'b0;
next_CRC16En <= 1'b0;
next_SIEPortTxRdy <= 1'b0;
next_SIEPortData <= 8'h00;
next_SIEPortCtrl <= 8'h00;
next_i <= 3'h0;
next_resumeCnt <= 16'h0000;
next_TxByteOutFullSpeedRate <= 1'b0;
next_USBWireFullSpeedRate <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`STX_CHK_ST:
if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
begin
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
next_TxByteOutFullSpeedRate <= 1'b1;
//SOF and PRE always at full speed
end
else if (SIEPortCtrl == `TX_PACKET_START)
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
begin
NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
next_USBWireReq <= 1'b1;
end
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
begin
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
next_USBWireReq <= 1'b1;
end
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
`define PKT_ST_WAIT_RDY_PKT 6'b101000
`define RES_ST_W_RDY1 6'b101001
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
`define TX_LS_EOP_WAIT_GNT1 6'b101101
`define TX_LS_EOP_SND_SE0_2 6'b101110
`define TX_LS_EOP_SND_SE0_1 6'b101111
`define TX_LS_EOP_W_RDY1 6'b110000
`define TX_LS_EOP_SND_J 6'b110001
`define TX_LS_EOP_W_RDY2 6'b110010
`define TX_LS_EOP_W_RDY3 6'b110011
`define RES_ST_DELAY 6'b110100
`define RES_ST_W_RDY2 6'b110101
`define RES_ST_W_RDY3 6'b110110
`define RES_ST_W_RDY4 6'b110111
`define DIR_CTL_DELAY 6'b111000
 
reg [5:0] CurrState_SIETx;
reg [5:0] NextState_SIETx;
 
 
//--------------------------------------------------------------------
// Machine: SIETx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
begin : SIETx_NextState
NextState_SIETx <= CurrState_SIETx;
// Set default values for outputs and signals
next_processTxByteWEn <= processTxByteWEn;
next_TxByteOut <= TxByteOut;
next_TxByteOutCtrl <= TxByteOutCtrl;
next_USBWireData <= USBWireData;
next_USBWireCtrl <= USBWireCtrl;
next_USBWireReq <= USBWireReq;
next_USBWireWEn <= USBWireWEn;
next_rstCRC <= rstCRC;
next_CRCData <= CRCData;
next_CRC5En <= CRC5En;
next_CRC5_8Bit <= CRC5_8Bit;
next_CRC16En <= CRC16En;
next_SIEPortTxRdy <= SIEPortTxRdy;
next_SIEPortData <= SIEPortData;
next_SIEPortCtrl <= SIEPortCtrl;
next_i <= i;
next_resumeCnt <= resumeCnt;
next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
case (CurrState_SIETx)
`IDLE:
NextState_SIETx <= `STX_WAIT_BYTE;
`START_SIETX:
begin
next_processTxByteWEn <= 1'b0;
next_TxByteOut <= 8'h00;
next_TxByteOutCtrl <= 8'h00;
next_USBWireData <= 2'b00;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireReq <= 1'b0;
next_USBWireWEn <= 1'b0;
next_rstCRC <= 1'b0;
next_CRCData <= 8'h00;
next_CRC5En <= 1'b0;
next_CRC5_8Bit <= 1'b0;
next_CRC16En <= 1'b0;
next_SIEPortTxRdy <= 1'b0;
next_SIEPortData <= 8'h00;
next_SIEPortCtrl <= 8'h00;
next_i <= 3'h0;
next_resumeCnt <= 16'h0000;
next_TxByteOutFullSpeedRate <= 1'b0;
next_USBWireFullSpeedRate <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`STX_CHK_ST:
if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
begin
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
next_TxByteOutFullSpeedRate <= 1'b1;
//SOF and PRE always at full speed
end
else if (SIEPortCtrl == `TX_PACKET_START)
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
begin
NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
next_USBWireReq <= 1'b1;
end
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
begin
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
next_USBWireReq <= 1'b1;
end
else if (SIEPortCtrl == `TX_IDLE)
NextState_SIETx <= `IDLE;
else if (SIEPortCtrl == `TX_RESUME_START)
begin
NextState_SIETx <= `RES_ST_WAIT_GNT;
next_USBWireReq <= 1'b1;
next_resumeCnt <= 16'h0000;
next_USBWireFullSpeedRate <= 1'b0;
//resume always uses low speed timing
end
`STX_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `STX_CHK_ST;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
next_USBWireFullSpeedRate <= fullSpeedRateIn;
end
end
`DIR_CTL_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
next_i <= i + 1'b1;
if (i == 3'h7)
begin
NextState_SIETx <= `STX_WAIT_BYTE;
next_USBWireReq <= 1'b0;
end
else
NextState_SIETx <= `DIR_CTL_DELAY;
end
`DIR_CTL_WAIT_GNT:
begin
next_i <= 3'h0;
if (USBWireGnt == 1'b1)
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
end
`DIR_CTL_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `DIR_CTL_CHK_FIN;
next_USBWireData <= SIEPortData[1:0];
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`DIR_CTL_DELAY:
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
`PKT_ST_CHK_PID:
begin
next_processTxByteWEn <= 1'b0;
else if (SIEPortCtrl == `TX_RESUME_START)
begin
NextState_SIETx <= `RES_ST_WAIT_GNT;
next_USBWireReq <= 1'b1;
next_resumeCnt <= 16'h0000;
next_USBWireFullSpeedRate <= 1'b0;
//resume always uses low speed timing
end
`STX_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `STX_CHK_ST;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
next_USBWireFullSpeedRate <= fullSpeedRateIn;
end
end
`DIR_CTL_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
next_i <= i + 1'b1;
if (i == 3'h7)
begin
NextState_SIETx <= `STX_WAIT_BYTE;
next_USBWireReq <= 1'b0;
end
else
NextState_SIETx <= `DIR_CTL_DELAY;
end
`DIR_CTL_WAIT_GNT:
begin
next_i <= 3'h0;
if (USBWireGnt == 1'b1)
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
end
`DIR_CTL_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `DIR_CTL_CHK_FIN;
next_USBWireData <= SIEPortData[1:0];
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`DIR_CTL_DELAY:
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
`PKT_ST_CHK_PID:
begin
next_processTxByteWEn <= 1'b0;
if (SIEPortData[1:0] == `TOKEN)
NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
else if (SIEPortData[1:0] == `HANDSHAKE)
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
else if (SIEPortData[1:0] == `DATA)
NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
else if (SIEPortData[1:0] == `SPECIAL)
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
end
`PKT_ST_WAIT_RDY_PKT:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_CHK_PID;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= `SYNC_BYTE;
next_TxByteOutCtrl <= `DATA_START;
end
`PKT_ST_DATA_CRC_PKT_SENT1:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
end
`PKT_ST_DATA_CRC_PKT_SENT2:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_DATA_CRC_WAIT_RDY1:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= ~CRC16Result[7:0];
next_TxByteOutCtrl <= `DATA_STREAM;
end
`PKT_ST_DATA_CRC_WAIT_RDY2:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= ~CRC16Result[15:8];
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_DATA_DATA_CHK_STOP:
if (SIEPortCtrl == `TX_PACKET_STOP)
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
else
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
`PKT_ST_DATA_DATA_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
end
`PKT_ST_DATA_DATA_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC16En <= 1'b1;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
end
`PKT_ST_DATA_DATA_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_DATA_DATA_WAIT_RDY:
begin
next_CRC16En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
end
end
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
if (CRC16UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
`PKT_ST_DATA_PID_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
next_rstCRC <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
end
`PKT_ST_DATA_PID_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
next_rstCRC <= 1'b1;
end
`PKT_ST_HS_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_HS_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_SPCL_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_SPCL_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_TKN_BYTE1_PKT_SENT1:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
end
`PKT_ST_TKN_BYTE1_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC5_8Bit <= 1'b1;
next_CRC5En <= 1'b1;
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
end
`PKT_ST_TKN_BYTE1_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_TKN_BYTE1_WAIT_RDY:
begin
next_CRC5En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
end
end
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
if (CRC5UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
`PKT_ST_TKN_CRC_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_TKN_CRC_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC5_8Bit <= 1'b0;
next_CRC5En <= 1'b1;
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
end
`PKT_ST_TKN_CRC_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_TKN_CRC_WAIT_RDY:
begin
next_CRC5En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
next_TxByteOutCtrl <= `DATA_STOP;
end
end
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
if (CRC5UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
`PKT_ST_TKN_PID_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
next_rstCRC <= 1'b0;
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
end
`PKT_ST_TKN_PID_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
next_rstCRC <= 1'b1;
end
`RES_ST_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
if (resumeCnt == `HOST_TX_RESUME_TIME)
NextState_SIETx <= `RES_ST_W_RDY1;
else
NextState_SIETx <= `RES_ST_DELAY;
end
`RES_ST_SND_J_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY4;
end
`RES_ST_SND_J_2:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
next_USBWireFullSpeedRate <= fullSpeedRateIn;
end
`RES_ST_SND_SE0_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY2;
end
`RES_ST_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY3;
end
`RES_ST_WAIT_GNT:
if (USBWireGnt == 1'b1)
NextState_SIETx <= `RES_ST_WAIT_RDY;
`RES_ST_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_CHK_FIN;
next_USBWireData <= KBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
next_resumeCnt <= resumeCnt + 1'b1;
end
`RES_ST_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_SE0_1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_DELAY:
NextState_SIETx <= `RES_ST_WAIT_RDY;
`RES_ST_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_SE0_2;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_J_1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_W_RDY4:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_J_2;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_WAIT_GNT1:
if (USBWireGnt == 1'b1)
NextState_SIETx <= `TX_LS_EOP_W_RDY1;
`TX_LS_EOP_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `TX_LS_EOP_W_RDY3;
end
`TX_LS_EOP_SND_SE0_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `TX_LS_EOP_W_RDY2;
end
`TX_LS_EOP_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_SND_J:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`TX_LS_EOP_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_J;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SIETx_CurrentState
if (rst)
CurrState_SIETx <= `START_SIETX;
else
CurrState_SIETx <= NextState_SIETx;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SIETx_RegOutput
if (rst)
begin
SIEPortData <= 8'h00;
SIEPortCtrl <= 8'h00;
i <= 3'h0;
resumeCnt <= 16'h0000;
processTxByteWEn <= 1'b0;
TxByteOut <= 8'h00;
TxByteOutCtrl <= 8'h00;
USBWireData <= 2'b00;
USBWireCtrl <= `TRI_STATE;
USBWireReq <= 1'b0;
USBWireWEn <= 1'b0;
rstCRC <= 1'b0;
CRCData <= 8'h00;
CRC5En <= 1'b0;
CRC5_8Bit <= 1'b0;
CRC16En <= 1'b0;
SIEPortTxRdy <= 1'b0;
TxByteOutFullSpeedRate <= 1'b0;
USBWireFullSpeedRate <= 1'b0;
end
else
begin
SIEPortData <= next_SIEPortData;
SIEPortCtrl <= next_SIEPortCtrl;
i <= next_i;
resumeCnt <= next_resumeCnt;
processTxByteWEn <= next_processTxByteWEn;
TxByteOut <= next_TxByteOut;
TxByteOutCtrl <= next_TxByteOutCtrl;
USBWireData <= next_USBWireData;
USBWireCtrl <= next_USBWireCtrl;
USBWireReq <= next_USBWireReq;
USBWireWEn <= next_USBWireWEn;
rstCRC <= next_rstCRC;
CRCData <= next_CRCData;
CRC5En <= next_CRC5En;
CRC5_8Bit <= next_CRC5_8Bit;
CRC16En <= next_CRC16En;
SIEPortTxRdy <= next_SIEPortTxRdy;
TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
end
end
 
endmodule
else if (SIEPortData[1:0] == `SPECIAL)
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
end
`PKT_ST_WAIT_RDY_PKT:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_CHK_PID;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= `SYNC_BYTE;
next_TxByteOutCtrl <= `DATA_START;
end
`PKT_ST_DATA_CRC_PKT_SENT1:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
end
`PKT_ST_DATA_CRC_PKT_SENT2:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_DATA_CRC_WAIT_RDY1:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= ~CRC16Result[7:0];
next_TxByteOutCtrl <= `DATA_STREAM;
end
`PKT_ST_DATA_CRC_WAIT_RDY2:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= ~CRC16Result[15:8];
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_DATA_DATA_CHK_STOP:
if (SIEPortCtrl == `TX_PACKET_STOP)
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
else
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
`PKT_ST_DATA_DATA_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
end
`PKT_ST_DATA_DATA_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC16En <= 1'b1;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
end
`PKT_ST_DATA_DATA_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_DATA_DATA_WAIT_RDY:
begin
next_CRC16En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
end
end
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
if (CRC16UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
`PKT_ST_DATA_PID_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
next_rstCRC <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
end
`PKT_ST_DATA_PID_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
next_rstCRC <= 1'b1;
end
`PKT_ST_HS_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_HS_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_SPCL_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_SPCL_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
if (SIEPortData[3:0] == `PREAMBLE)
next_TxByteOutCtrl <= `DATA_STOP_PRE;
else
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_TKN_BYTE1_PKT_SENT1:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
end
`PKT_ST_TKN_BYTE1_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC5_8Bit <= 1'b1;
next_CRC5En <= 1'b1;
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
end
`PKT_ST_TKN_BYTE1_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_TKN_BYTE1_WAIT_RDY:
begin
next_CRC5En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
end
end
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
if (CRC5UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
`PKT_ST_TKN_CRC_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_TKN_CRC_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC5_8Bit <= 1'b0;
next_CRC5En <= 1'b1;
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
end
`PKT_ST_TKN_CRC_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_TKN_CRC_WAIT_RDY:
begin
next_CRC5En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
next_TxByteOutCtrl <= `DATA_STOP;
end
end
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
if (CRC5UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
`PKT_ST_TKN_PID_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
next_rstCRC <= 1'b0;
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
end
`PKT_ST_TKN_PID_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
next_rstCRC <= 1'b1;
end
`RES_ST_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
if (resumeCnt == `HOST_TX_RESUME_TIME)
NextState_SIETx <= `RES_ST_W_RDY1;
else
NextState_SIETx <= `RES_ST_DELAY;
end
`RES_ST_SND_J_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY4;
end
`RES_ST_SND_J_2:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
next_USBWireFullSpeedRate <= fullSpeedRateIn;
end
`RES_ST_SND_SE0_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY2;
end
`RES_ST_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY3;
end
`RES_ST_WAIT_GNT:
if (USBWireGnt == 1'b1)
NextState_SIETx <= `RES_ST_WAIT_RDY;
`RES_ST_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_CHK_FIN;
next_USBWireData <= KBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
next_resumeCnt <= resumeCnt + 1'b1;
end
`RES_ST_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_SE0_1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_DELAY:
NextState_SIETx <= `RES_ST_WAIT_RDY;
`RES_ST_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_SE0_2;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_J_1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_W_RDY4:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_J_2;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_WAIT_GNT1:
if (USBWireGnt == 1'b1)
NextState_SIETx <= `TX_LS_EOP_W_RDY1;
`TX_LS_EOP_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `TX_LS_EOP_W_RDY3;
end
`TX_LS_EOP_SND_SE0_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `TX_LS_EOP_W_RDY2;
end
`TX_LS_EOP_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_SND_J:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`TX_LS_EOP_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_J;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SIETx_CurrentState
if (rst)
CurrState_SIETx <= `START_SIETX;
else
CurrState_SIETx <= NextState_SIETx;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SIETx_RegOutput
if (rst)
begin
SIEPortData <= 8'h00;
SIEPortCtrl <= 8'h00;
i <= 3'h0;
resumeCnt <= 16'h0000;
processTxByteWEn <= 1'b0;
TxByteOut <= 8'h00;
TxByteOutCtrl <= 8'h00;
USBWireData <= 2'b00;
USBWireCtrl <= `TRI_STATE;
USBWireReq <= 1'b0;
USBWireWEn <= 1'b0;
rstCRC <= 1'b0;
CRCData <= 8'h00;
CRC5En <= 1'b0;
CRC5_8Bit <= 1'b0;
CRC16En <= 1'b0;
SIEPortTxRdy <= 1'b0;
TxByteOutFullSpeedRate <= 1'b0;
USBWireFullSpeedRate <= 1'b0;
end
else
begin
SIEPortData <= next_SIEPortData;
SIEPortCtrl <= next_SIEPortCtrl;
i <= next_i;
resumeCnt <= next_resumeCnt;
processTxByteWEn <= next_processTxByteWEn;
TxByteOut <= next_TxByteOut;
TxByteOutCtrl <= next_TxByteOutCtrl;
USBWireData <= next_USBWireData;
USBWireCtrl <= next_USBWireCtrl;
USBWireReq <= next_USBWireReq;
USBWireWEn <= next_USBWireWEn;
rstCRC <= next_rstCRC;
CRCData <= next_CRCData;
CRC5En <= next_CRC5En;
CRC5_8Bit <= next_CRC5_8Bit;
CRC16En <= next_CRC16En;
SIEPortTxRdy <= next_SIEPortTxRdy;
TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
end
end
 
endmodule
/trunk/RTL/serialInterfaceEngine/processTxByte.v
1,448 → 1,450
 
// File : ../RTL/serialInterfaceEngine/processTxByte.v
// Generated : 11/10/06 05:37:23
// From : ../RTL/serialInterfaceEngine/processTxByte.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// processTxByte
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
input [1:0] JBit;
input [1:0] KBit;
input [7:0] TxByteCtrlIn;
input TxByteFullSpeedRateIn;
input [7:0] TxByteIn;
input USBWireGnt;
input USBWireRdy;
input clk;
input processTxByteWEn;
input rst;
output USBWireCtrl;
output [1:0] USBWireData;
output USBWireFullSpeedRate;
output USBWireReq;
output USBWireWEn;
output processTxByteRdy;
 
wire [1:0] JBit;
wire [1:0] KBit;
wire [7:0] TxByteCtrlIn;
wire TxByteFullSpeedRateIn;
wire [7:0] TxByteIn;
reg USBWireCtrl, next_USBWireCtrl;
reg [1:0] USBWireData, next_USBWireData;
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire USBWireGnt;
wire USBWireRdy;
reg USBWireReq, next_USBWireReq;
reg USBWireWEn, next_USBWireWEn;
wire clk;
reg processTxByteRdy, next_processTxByteRdy;
wire processTxByteWEn;
wire rst;
 
// diagram signals declarations
reg [1:0]TXLineState, next_TXLineState;
reg [3:0]TXOneCount, next_TXOneCount;
reg [7:0]TxByteCtrl, next_TxByteCtrl;
reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
reg [7:0]TxByte, next_TxByte;
reg [3:0]i, next_i;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 5'b00000
`define PTBY_WAIT_EN 5'b00001
`define SEND_BYTE_UPDATE_BYTE 5'b00010
`define SEND_BYTE_WAIT_RDY 5'b00011
`define SEND_BYTE_CHK 5'b00100
`define SEND_BYTE_BIT_STUFF 5'b00101
`define SEND_BYTE_WAIT_RDY2 5'b00110
`define SEND_BYTE_CHK_FIN 5'b00111
`define PTBY_WAIT_GNT 5'b01000
`define STOP_SND_SE0_2 5'b01001
`define STOP_SND_SE0_1 5'b01010
`define STOP_CHK 5'b01011
`define STOP_SND_J 5'b01100
`define STOP_SND_IDLE 5'b01101
`define STOP_FIN 5'b01110
`define WAIT_RDY_WIRE 5'b01111
`define WAIT_RDY_PKT 5'b10000
`define LS_START_SND_IDLE3 5'b10001
`define LS_START_SND_J1 5'b10010
`define LS_START_SND_IDLE1 5'b10011
`define LS_START_SND_IDLE2 5'b10100
`define LS_START_FIN 5'b10101
`define LS_START_W_RDY1 5'b10110
`define LS_START_W_RDY2 5'b10111
`define LS_START_W_RDY3 5'b11000
`define STOP_W_RDY1 5'b11001
`define STOP_W_RDY2 5'b11010
`define STOP_W_RDY3 5'b11011
`define STOP_W_RDY4 5'b11100
 
reg [4:0] CurrState_prcTxB;
reg [4:0] NextState_prcTxB;
 
 
//--------------------------------------------------------------------
// Machine: prcTxB
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
begin : prcTxB_NextState
NextState_prcTxB <= CurrState_prcTxB;
// Set default values for outputs and signals
next_processTxByteRdy <= processTxByteRdy;
next_USBWireData <= USBWireData;
next_USBWireCtrl <= USBWireCtrl;
next_USBWireReq <= USBWireReq;
next_USBWireWEn <= USBWireWEn;
next_i <= i;
next_TxByte <= TxByte;
next_TxByteCtrl <= TxByteCtrl;
next_TXLineState <= TXLineState;
next_TXOneCount <= TXOneCount;
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
case (CurrState_prcTxB)
`START_PTBY:
begin
next_processTxByteRdy <= 1'b0;
next_USBWireData <= 2'b00;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireReq <= 1'b0;
next_USBWireWEn <= 1'b0;
next_i <= 4'h0;
next_TxByte <= 8'h00;
next_TxByteCtrl <= 8'h00;
next_TXLineState <= 2'b0;
next_TXOneCount <= 4'h0;
next_USBWireFullSpeedRate <= 1'b0;
next_TxByteFullSpeedRate <= 1'b0;
NextState_prcTxB <= `PTBY_WAIT_EN;
end
`PTBY_WAIT_EN:
begin
next_processTxByteRdy <= 1'b1;
if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
begin
NextState_prcTxB <= `PTBY_WAIT_GNT;
next_processTxByteRdy <= 1'b0;
next_TxByte <= TxByteIn;
next_TxByteCtrl <= TxByteCtrlIn;
next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
next_TXOneCount <= 4'h0;
next_TXLineState <= JBit;
next_USBWireReq <= 1'b1;
end
else if (processTxByteWEn == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_processTxByteRdy <= 1'b0;
next_TxByte <= TxByteIn;
next_TxByteCtrl <= TxByteCtrlIn;
next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
next_i <= 4'h0;
end
end
`PTBY_WAIT_GNT:
if (USBWireGnt == 1'b1)
NextState_prcTxB <= `WAIT_RDY_WIRE;
`WAIT_RDY_WIRE:
if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
NextState_prcTxB <= `LS_START_SND_IDLE1;
else if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `WAIT_RDY_PKT;
//actively drive the first J bit
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`WAIT_RDY_PKT:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_i <= 4'h0;
end
`SEND_BYTE_UPDATE_BYTE:
begin
next_i <= i + 1'b1;
next_TxByte <= {1'b0, TxByte[7:1] };
if (TxByte[0] == 1'b1) //If this bit is 1, then
next_TXOneCount <= TXOneCount + 1'b1;
//increment 'TXOneCount'
else //else this is a zero bit
begin
next_TXOneCount <= 4'h0;
//reset 'TXOneCount'
if (TXLineState == JBit)
next_TXLineState <= KBit;
//toggle the line state
else
next_TXLineState <= JBit;
end
NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
end
`SEND_BYTE_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_CHK;
next_USBWireWEn <= 1'b1;
next_USBWireData <= TXLineState;
next_USBWireCtrl <= `DRIVE;
end
`SEND_BYTE_CHK:
begin
next_USBWireWEn <= 1'b0;
if (TXOneCount == `MAX_CONSEC_SAME_BITS)
NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
else if (i != 4'h8)
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
else
NextState_prcTxB <= `STOP_CHK;
end
`SEND_BYTE_BIT_STUFF:
begin
next_TXOneCount <= 4'h0;
//reset 'TXOneCount'
if (TXLineState == JBit)
next_TXLineState <= KBit;
//toggle the line state
else
next_TXLineState <= JBit;
NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
end
`SEND_BYTE_WAIT_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
next_USBWireWEn <= 1'b1;
next_USBWireData <= TXLineState;
next_USBWireCtrl <= `DRIVE;
end
`SEND_BYTE_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
if (i == 4'h8)
NextState_prcTxB <= `STOP_CHK;
else
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
end
`STOP_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY2;
end
`STOP_SND_SE0_1:
NextState_prcTxB <= `STOP_W_RDY1;
`STOP_CHK:
if (TxByteCtrl == `DATA_STOP)
NextState_prcTxB <= `STOP_SND_SE0_1;
else
NextState_prcTxB <= `PTBY_WAIT_EN;
`STOP_SND_J:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY3;
end
`STOP_SND_IDLE:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY4;
end
`STOP_FIN:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
//release the wire
NextState_prcTxB <= `PTBY_WAIT_EN;
end
`STOP_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_SE0_2;
next_USBWireWEn <= 1'b1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_J;
next_USBWireWEn <= 1'b1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_IDLE;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY4:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_FIN;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_SND_IDLE3:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY2;
end
`LS_START_SND_J1:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY3;
end
`LS_START_SND_IDLE1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_IDLE2;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_SND_IDLE2:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY1;
end
`LS_START_FIN:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_i <= 4'h0;
end
`LS_START_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_IDLE3;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_J1;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_FIN;
//Drive the first JBit
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prcTxB_CurrentState
if (rst)
CurrState_prcTxB <= `START_PTBY;
else
CurrState_prcTxB <= NextState_prcTxB;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prcTxB_RegOutput
if (rst)
begin
i <= 4'h0;
TxByte <= 8'h00;
TxByteCtrl <= 8'h00;
TXLineState <= 2'b0;
TXOneCount <= 4'h0;
TxByteFullSpeedRate <= 1'b0;
processTxByteRdy <= 1'b0;
USBWireData <= 2'b00;
USBWireCtrl <= `TRI_STATE;
USBWireReq <= 1'b0;
USBWireWEn <= 1'b0;
USBWireFullSpeedRate <= 1'b0;
end
else
begin
i <= next_i;
TxByte <= next_TxByte;
TxByteCtrl <= next_TxByteCtrl;
TXLineState <= next_TXLineState;
TXOneCount <= next_TXOneCount;
TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
processTxByteRdy <= next_processTxByteRdy;
USBWireData <= next_USBWireData;
USBWireCtrl <= next_USBWireCtrl;
USBWireReq <= next_USBWireReq;
USBWireWEn <= next_USBWireWEn;
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
end
end
 
endmodule
 
// File : ../RTL/serialInterfaceEngine/processTxByte.v
// Generated : 11/10/06 05:37:23
// From : ../RTL/serialInterfaceEngine/processTxByte.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// processTxByte
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
input [1:0] JBit;
input [1:0] KBit;
input [7:0] TxByteCtrlIn;
input TxByteFullSpeedRateIn;
input [7:0] TxByteIn;
input USBWireGnt;
input USBWireRdy;
input clk;
input processTxByteWEn;
input rst;
output USBWireCtrl;
output [1:0] USBWireData;
output USBWireFullSpeedRate;
output USBWireReq;
output USBWireWEn;
output processTxByteRdy;
 
wire [1:0] JBit;
wire [1:0] KBit;
wire [7:0] TxByteCtrlIn;
wire TxByteFullSpeedRateIn;
wire [7:0] TxByteIn;
reg USBWireCtrl, next_USBWireCtrl;
reg [1:0] USBWireData, next_USBWireData;
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire USBWireGnt;
wire USBWireRdy;
reg USBWireReq, next_USBWireReq;
reg USBWireWEn, next_USBWireWEn;
wire clk;
reg processTxByteRdy, next_processTxByteRdy;
wire processTxByteWEn;
wire rst;
 
// diagram signals declarations
reg [1:0]TXLineState, next_TXLineState;
reg [3:0]TXOneCount, next_TXOneCount;
reg [7:0]TxByteCtrl, next_TxByteCtrl;
reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
reg [7:0]TxByte, next_TxByte;
reg [3:0]i, next_i;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 5'b00000
`define PTBY_WAIT_EN 5'b00001
`define SEND_BYTE_UPDATE_BYTE 5'b00010
`define SEND_BYTE_WAIT_RDY 5'b00011
`define SEND_BYTE_CHK 5'b00100
`define SEND_BYTE_BIT_STUFF 5'b00101
`define SEND_BYTE_WAIT_RDY2 5'b00110
`define SEND_BYTE_CHK_FIN 5'b00111
`define PTBY_WAIT_GNT 5'b01000
`define STOP_SND_SE0_2 5'b01001
`define STOP_SND_SE0_1 5'b01010
`define STOP_CHK 5'b01011
`define STOP_SND_J 5'b01100
`define STOP_SND_IDLE 5'b01101
`define STOP_FIN 5'b01110
`define WAIT_RDY_WIRE 5'b01111
`define WAIT_RDY_PKT 5'b10000
`define LS_START_SND_IDLE3 5'b10001
`define LS_START_SND_J1 5'b10010
`define LS_START_SND_IDLE1 5'b10011
`define LS_START_SND_IDLE2 5'b10100
`define LS_START_FIN 5'b10101
`define LS_START_W_RDY1 5'b10110
`define LS_START_W_RDY2 5'b10111
`define LS_START_W_RDY3 5'b11000
`define STOP_W_RDY1 5'b11001
`define STOP_W_RDY2 5'b11010
`define STOP_W_RDY3 5'b11011
`define STOP_W_RDY4 5'b11100
 
reg [4:0] CurrState_prcTxB;
reg [4:0] NextState_prcTxB;
 
 
//--------------------------------------------------------------------
// Machine: prcTxB
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
begin : prcTxB_NextState
NextState_prcTxB <= CurrState_prcTxB;
// Set default values for outputs and signals
next_processTxByteRdy <= processTxByteRdy;
next_USBWireData <= USBWireData;
next_USBWireCtrl <= USBWireCtrl;
next_USBWireReq <= USBWireReq;
next_USBWireWEn <= USBWireWEn;
next_i <= i;
next_TxByte <= TxByte;
next_TxByteCtrl <= TxByteCtrl;
next_TXLineState <= TXLineState;
next_TXOneCount <= TXOneCount;
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
case (CurrState_prcTxB)
`START_PTBY:
begin
next_processTxByteRdy <= 1'b0;
next_USBWireData <= 2'b00;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireReq <= 1'b0;
next_USBWireWEn <= 1'b0;
next_i <= 4'h0;
next_TxByte <= 8'h00;
next_TxByteCtrl <= 8'h00;
next_TXLineState <= 2'b0;
next_TXOneCount <= 4'h0;
next_USBWireFullSpeedRate <= 1'b0;
next_TxByteFullSpeedRate <= 1'b0;
NextState_prcTxB <= `PTBY_WAIT_EN;
end
`PTBY_WAIT_EN:
begin
next_processTxByteRdy <= 1'b1;
if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
begin
NextState_prcTxB <= `PTBY_WAIT_GNT;
next_processTxByteRdy <= 1'b0;
next_TxByte <= TxByteIn;
next_TxByteCtrl <= TxByteCtrlIn;
next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
next_TXOneCount <= 4'h0;
next_TXLineState <= JBit;
next_USBWireReq <= 1'b1;
end
else if (processTxByteWEn == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_processTxByteRdy <= 1'b0;
next_TxByte <= TxByteIn;
next_TxByteCtrl <= TxByteCtrlIn;
next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
next_i <= 4'h0;
end
end
`PTBY_WAIT_GNT:
if (USBWireGnt == 1'b1)
NextState_prcTxB <= `WAIT_RDY_WIRE;
`WAIT_RDY_WIRE:
if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
NextState_prcTxB <= `LS_START_SND_IDLE1;
else if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `WAIT_RDY_PKT;
//actively drive the first J bit
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`WAIT_RDY_PKT:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_i <= 4'h0;
end
`SEND_BYTE_UPDATE_BYTE:
begin
next_i <= i + 1'b1;
next_TxByte <= {1'b0, TxByte[7:1] };
if (TxByte[0] == 1'b1) //If this bit is 1, then
next_TXOneCount <= TXOneCount + 1'b1;
//increment 'TXOneCount'
else //else this is a zero bit
begin
next_TXOneCount <= 4'h0;
//reset 'TXOneCount'
if (TXLineState == JBit)
next_TXLineState <= KBit;
//toggle the line state
else
next_TXLineState <= JBit;
end
NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
end
`SEND_BYTE_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_CHK;
next_USBWireWEn <= 1'b1;
next_USBWireData <= TXLineState;
next_USBWireCtrl <= `DRIVE;
end
`SEND_BYTE_CHK:
begin
next_USBWireWEn <= 1'b0;
if (TXOneCount == `MAX_CONSEC_SAME_BITS)
NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
else if (i != 4'h8)
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
else
NextState_prcTxB <= `STOP_CHK;
end
`SEND_BYTE_BIT_STUFF:
begin
next_TXOneCount <= 4'h0;
//reset 'TXOneCount'
if (TXLineState == JBit)
next_TXLineState <= KBit;
//toggle the line state
else
next_TXLineState <= JBit;
NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
end
`SEND_BYTE_WAIT_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
next_USBWireWEn <= 1'b1;
next_USBWireData <= TXLineState;
next_USBWireCtrl <= `DRIVE;
end
`SEND_BYTE_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
if (i == 4'h8)
NextState_prcTxB <= `STOP_CHK;
else
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
end
`STOP_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY2;
end
`STOP_SND_SE0_1:
NextState_prcTxB <= `STOP_W_RDY1;
`STOP_CHK:
if (TxByteCtrl == `DATA_STOP)
NextState_prcTxB <= `STOP_SND_SE0_1;
else if (TxByteCtrl == `DATA_STOP_PRE)
NextState_prcTxB <= `STOP_SND_J;
else
NextState_prcTxB <= `PTBY_WAIT_EN;
`STOP_SND_J:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY3;
end
`STOP_SND_IDLE:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `STOP_W_RDY4;
end
`STOP_FIN:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
//release the wire
NextState_prcTxB <= `PTBY_WAIT_EN;
end
`STOP_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_SE0_2;
next_USBWireWEn <= 1'b1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_J;
next_USBWireWEn <= 1'b1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_SND_IDLE;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
end
`STOP_W_RDY4:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `STOP_FIN;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_SND_IDLE3:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY2;
end
`LS_START_SND_J1:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY3;
end
`LS_START_SND_IDLE1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_IDLE2;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_SND_IDLE2:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `LS_START_W_RDY1;
end
`LS_START_FIN:
begin
next_USBWireWEn <= 1'b0;
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
next_i <= 4'h0;
end
`LS_START_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_IDLE3;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_SND_J1;
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
end
`LS_START_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_prcTxB <= `LS_START_FIN;
//Drive the first JBit
next_USBWireWEn <= 1'b1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prcTxB_CurrentState
if (rst)
CurrState_prcTxB <= `START_PTBY;
else
CurrState_prcTxB <= NextState_prcTxB;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prcTxB_RegOutput
if (rst)
begin
i <= 4'h0;
TxByte <= 8'h00;
TxByteCtrl <= 8'h00;
TXLineState <= 2'b0;
TXOneCount <= 4'h0;
TxByteFullSpeedRate <= 1'b0;
processTxByteRdy <= 1'b0;
USBWireData <= 2'b00;
USBWireCtrl <= `TRI_STATE;
USBWireReq <= 1'b0;
USBWireWEn <= 1'b0;
USBWireFullSpeedRate <= 1'b0;
end
else
begin
i <= next_i;
TxByte <= next_TxByte;
TxByteCtrl <= next_TxByteCtrl;
TXLineState <= next_TXLineState;
TXOneCount <= next_TXOneCount;
TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
processTxByteRdy <= next_processTxByteRdy;
USBWireData <= next_USBWireData;
USBWireCtrl <= next_USBWireCtrl;
USBWireReq <= next_USBWireReq;
USBWireWEn <= next_USBWireWEn;
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
end
end
 
endmodule
/trunk/RTL/serialInterfaceEngine/writeUSBWireData.v
1,281 → 1,289
//////////////////////////////////////////////////////////////////////
//// ////
//// writeUSBWireData.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
`define BUFFER_FULL 3'b100
 
module writeUSBWireData (
TxBitsIn,
TxBitsOut,
TxDataOutTick,
TxCtrlIn,
TxCtrlOut,
USBWireRdy,
USBWireWEn,
TxWireActiveDrive,
fullSpeedRate,
clk,
rst
);
input [1:0] TxBitsIn;
input TxCtrlIn;
input USBWireWEn;
input clk;
input fullSpeedRate;
input rst;
output [1:0] TxBitsOut;
output TxDataOutTick;
output TxCtrlOut;
output USBWireRdy;
output TxWireActiveDrive;
 
wire [1:0] TxBitsIn;
reg [1:0] TxBitsOut;
reg TxDataOutTick;
wire TxCtrlIn;
reg TxCtrlOut;
reg USBWireRdy;
wire USBWireWEn;
wire clk;
wire fullSpeedRate;
wire rst;
reg TxWireActiveDrive;
 
// local registers
reg [2:0]buffer0;
reg [2:0]buffer1;
reg [2:0]buffer2;
reg [2:0]buffer3;
reg [2:0]bufferCnt;
reg [1:0]bufferInIndex;
reg [1:0]bufferOutIndex;
reg decBufferCnt;
reg [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
 
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
 
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
 
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
 
// buffer control
always @(posedge clk)
begin
if (rst == 1'b1)
begin
bufferCnt <= 3'b000;
end
else
begin
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
bufferCnt <= bufferCnt + 1'b1;
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
bufferCnt <= bufferCnt - 1'b1;
end
end
 
 
//buffer input state machine
always @(posedge clk) begin
if (rst == 1'b1) begin
incBufferCnt <= 1'b0;
bufferInIndex <= 2'b00;
buffer0 <= 3'b000;
buffer1 <= 3'b000;
buffer2 <= 3'b000;
buffer3 <= 3'b000;
USBWireRdy <= 1'b0;
bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
end
else begin
case (bufferInStMachCurrState)
`WAIT_BUFFER_NOT_FULL:
begin
if (bufferCnt != `BUFFER_FULL)
begin
bufferInStMachCurrState <= `WAIT_WRITE_REQ;
USBWireRdy <= 1'b1;
end
end
`WAIT_WRITE_REQ:
begin
if (USBWireWEn == 1'b1)
begin
incBufferCnt <= 1'b1;
USBWireRdy <= 1'b0;
bufferInIndex <= bufferInIndex + 1'b1;
case (bufferInIndex)
2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
endcase
bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
end
end
`CLR_INC_BUFFER_CNT:
begin
incBufferCnt <= 1'b0;
if (bufferCnt != (`BUFFER_FULL - 1'b1) )
begin
bufferInStMachCurrState <= `WAIT_WRITE_REQ;
USBWireRdy <= 1'b1;
end
else begin
bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
end
end
endcase
end
end
//increment counter used to generate USB bit rate
always @(posedge clk) begin
if (rst == 1'b1)
begin
i <= 5'b00000;
fullSpeedTick <= 1'b0;
lowSpeedTick <= 1'b0;
end
else
begin
i <= i + 1'b1;
if (i[1:0] == 2'b00)
fullSpeedTick <= 1'b1;
else
fullSpeedTick <= 1'b0;
if (i == 5'b00000)
lowSpeedTick <= 1'b1;
else
lowSpeedTick <= 1'b0;
end
end
 
//buffer output state machine
//buffer is constantly emptied at either
//the full or low speed rate
//if the buffer is empty, then the output is forced to tri-state
always @(posedge clk) begin
if (rst == 1'b1)
begin
bufferOutIndex <= 2'b00;
decBufferCnt <= 1'b0;
TxBitsOut <= 2'b00;
TxCtrlOut <= `TRI_STATE;
TxDataOutTick <= 1'b0;
bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
end
else
begin
case (bufferOutStMachCurrState)
`WAIT_LINE_WRITE:
begin
if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
begin
TxDataOutTick <= !TxDataOutTick;
if (bufferCnt == 0) begin
TxBitsOut <= 2'b00;
TxCtrlOut <= `TRI_STATE;
end
else begin
bufferOutStMachCurrState <= `LINE_WRITE;
decBufferCnt <= 1'b1;
bufferOutIndex <= bufferOutIndex + 1'b1;
case (bufferOutIndex)
2'b00 :
begin
TxBitsOut <= buffer0[2:1];
TxCtrlOut <= buffer0[0];
end
2'b01 :
begin
TxBitsOut <= buffer1[2:1];
TxCtrlOut <= buffer1[0];
end
2'b10 :
begin
TxBitsOut <= buffer2[2:1];
TxCtrlOut <= buffer2[0];
end
2'b11 :
begin
TxBitsOut <= buffer3[2:1];
TxCtrlOut <= buffer3[0];
end
endcase
end
end
end
`LINE_WRITE:
begin
decBufferCnt <= 1'b0;
bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
end
endcase
end
end
 
// control 'TxWireActiveDrive'
always @(TxCtrlOut)
begin
if (TxCtrlOut == `DRIVE)
TxWireActiveDrive <= 1'b1;
else
TxWireActiveDrive <= 1'b0;
end
 
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// writeUSBWireData.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
`define BUFFER_FULL 3'b100
 
module writeUSBWireData (
TxBitsIn,
TxBitsOut,
TxDataOutTick,
TxCtrlIn,
TxCtrlOut,
USBWireRdy,
USBWireWEn,
TxWireActiveDrive,
fullSpeedRate,
clk,
rst
);
input [1:0] TxBitsIn;
input TxCtrlIn;
input USBWireWEn;
input clk;
input fullSpeedRate;
input rst;
output [1:0] TxBitsOut;
output TxDataOutTick;
output TxCtrlOut;
output USBWireRdy;
output TxWireActiveDrive;
 
wire [1:0] TxBitsIn;
reg [1:0] TxBitsOut;
reg TxDataOutTick;
wire TxCtrlIn;
reg TxCtrlOut;
reg USBWireRdy;
wire USBWireWEn;
wire clk;
wire fullSpeedRate;
wire rst;
reg TxWireActiveDrive;
 
// local registers
reg [3:0]buffer0;
reg [3:0]buffer1;
reg [3:0]buffer2;
reg [3:0]buffer3;
reg [2:0]bufferCnt;
reg [1:0]bufferInIndex;
reg [1:0]bufferOutIndex;
reg decBufferCnt;
reg [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
reg fullSpeedRate_reg;
 
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
 
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
 
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
 
// buffer control
always @(posedge clk)
begin
if (rst == 1'b1)
begin
bufferCnt <= 3'b000;
end
else
begin
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
bufferCnt <= bufferCnt + 1'b1;
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
bufferCnt <= bufferCnt - 1'b1;
end
end
 
 
//buffer input state machine
always @(posedge clk) begin
if (rst == 1'b1) begin
incBufferCnt <= 1'b0;
bufferInIndex <= 2'b00;
buffer0 <= 4'b0000;
buffer1 <= 4'b0000;
buffer2 <= 4'b0000;
buffer3 <= 4'b0000;
USBWireRdy <= 1'b0;
bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
end
else begin
case (bufferInStMachCurrState)
`WAIT_BUFFER_NOT_FULL:
begin
if (bufferCnt != `BUFFER_FULL)
begin
bufferInStMachCurrState <= `WAIT_WRITE_REQ;
USBWireRdy <= 1'b1;
end
end
`WAIT_WRITE_REQ:
begin
if (USBWireWEn == 1'b1)
begin
incBufferCnt <= 1'b1;
USBWireRdy <= 1'b0;
bufferInIndex <= bufferInIndex + 1'b1;
case (bufferInIndex)
2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
endcase
bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
end
end
`CLR_INC_BUFFER_CNT:
begin
incBufferCnt <= 1'b0;
if (bufferCnt != (`BUFFER_FULL - 1'b1) )
begin
bufferInStMachCurrState <= `WAIT_WRITE_REQ;
USBWireRdy <= 1'b1;
end
else begin
bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
end
end
endcase
end
end
//increment counter used to generate USB bit rate
always @(posedge clk) begin
if (rst == 1'b1)
begin
i <= 5'b00000;
fullSpeedTick <= 1'b0;
lowSpeedTick <= 1'b0;
end
else
begin
i <= i + 1'b1;
if (i[1:0] == 2'b00)
fullSpeedTick <= 1'b1;
else
fullSpeedTick <= 1'b0;
if (i == 5'b00000)
lowSpeedTick <= 1'b1;
else
lowSpeedTick <= 1'b0;
end
end
 
//buffer output state machine
//buffer is constantly emptied at either
//the full or low speed rate
//if the buffer is empty, then the output is forced to tri-state
always @(posedge clk) begin
if (rst == 1'b1)
begin
bufferOutIndex <= 2'b00;
decBufferCnt <= 1'b0;
TxBitsOut <= 2'b00;
TxCtrlOut <= `TRI_STATE;
TxDataOutTick <= 1'b0;
bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
fullSpeedRate_reg <= 1'b0;
end
else
begin
case (bufferOutIndex)
2'b00: fullSpeedRate_reg <= buffer0[3];
2'b01: fullSpeedRate_reg <= buffer1[3];
2'b10: fullSpeedRate_reg <= buffer2[3];
2'b11: fullSpeedRate_reg <= buffer3[3];
endcase
case (bufferOutStMachCurrState)
`WAIT_LINE_WRITE:
begin
if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )
begin
TxDataOutTick <= !TxDataOutTick;
if (bufferCnt == 0) begin
TxBitsOut <= 2'b00;
TxCtrlOut <= `TRI_STATE;
end
else begin
bufferOutStMachCurrState <= `LINE_WRITE;
decBufferCnt <= 1'b1;
bufferOutIndex <= bufferOutIndex + 1'b1;
case (bufferOutIndex)
2'b00 :
begin
TxBitsOut <= buffer0[2:1];
TxCtrlOut <= buffer0[0];
end
2'b01 :
begin
TxBitsOut <= buffer1[2:1];
TxCtrlOut <= buffer1[0];
end
2'b10 :
begin
TxBitsOut <= buffer2[2:1];
TxCtrlOut <= buffer2[0];
end
2'b11 :
begin
TxBitsOut <= buffer3[2:1];
TxCtrlOut <= buffer3[0];
end
endcase
end
end
end
`LINE_WRITE:
begin
decBufferCnt <= 1'b0;
bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
end
endcase
end
end
 
// control 'TxWireActiveDrive'
always @(TxCtrlOut)
begin
if (TxCtrlOut == `DRIVE)
TxWireActiveDrive <= 1'b1;
else
TxWireActiveDrive <= 1'b0;
end
 
 
endmodule

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