URL
https://opencores.org/ocsvn/utosnet/utosnet/trunk
Subversion Repositories utosnet
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Rev 8 → Rev 10
/readme_ip_xc3s50an_tqg144.txt
0,0 → 1,25
The .xco files are created by CoreGen for the following FPGA device: |
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Xilinx xc3s50an tqg144 |
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To generate an ip-core for other devices, use the following cores and settings: |
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data_register: |
- Core: Block Memory Generator |
- Memory Type: True Dual Port RAM |
- Use Byte Write Enable: No |
- Algorithm: Minimum Area |
- Port A: |
- Write Width: 32 |
- Write Depth: 64 |
- Operating Mode: Write First |
- Enable: Always Enabled |
- Port B: |
- Write Width: 32 |
- Operating Mode: Write First |
- Enable: Always Enabled |
- Optional Output Registers: No |
- Memory Initialization: Fill with 0 |
- Output Reset Pins: No |