URL
https://opencores.org/ocsvn/utosnet/utosnet/trunk
Subversion Repositories utosnet
Compare Revisions
- This comparison shows the changes necessary to convert path
/utosnet/trunk/gateware/uTosNet_uart
- from Rev 2 to Rev 4
- ↔ Reverse comparison
Rev 2 → Rev 4
/transcript
0,0 → 1,12
# Reading C:/Xilinx/modeltech_6.6/tcl/vsim/pref.tcl |
# // ModelSim SE 6.6 Jan 5 2010 |
# // |
# // Copyright 1991-2010 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND |
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY |
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS |
# // AND IS SUBJECT TO LICENSE TERMS. |
# // |
# OpenFile D:/openCores/utosnet/trunk/gateware/uTosNet_uart/uTosNet_uart.vhd |
/uTosNet_uart.vhd
5,6 → 5,7
-- Create Date: 19/03/2010 |
-- Design Name: uTosNet |
-- Module Name: uTosNet_usb - Behavioral |
-- File Name: uTosNet_uart.vhd |
-- Project Name: uTosNet |
-- Target Devices: SDU XC3S50AN Board |
-- Tool versions: Xilinx ISE 11.4 |
38,7 → 39,22
-- Revision: |
-- Revision 0.10 - Initial release |
-- |
-- Copyright 2010 |
-- |
-- This module is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This module is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with this module. If not, see <http://www.gnu.org/licenses/>. |
---------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |