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/uTosNet_example/uTosNet_controller/UTNX_top.vhd
0,0 → 1,215
----------------------------------------------------------------------------------
-- Company: University of Southern Denmark
 
--
-- Create Date: 30/11/2009
-- Design Name: uTosNet
-- Module Name: uTosNet_top - Behavioral
-- File Name: uTosNet_top.vhd
-- Project Name: uTosNet
-- Target Devices: SDU XC3S50AN Board
-- Tool versions: Xilinx ISE 11.4
-- Description: SDU/TEK/Embedix Spartan-3 50AN experimentation board +
-- Expansion board with: USB + Ethernet + VGA.
-- Example uTosNet application (over USB UART)
-- Use serial port setting: 115200 bps 8N1
--
-- Revision:
-- Revision 0.10 - Initial release
--
-- Copyright 2010
--
-- This module is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This module is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this module. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Here we define the I/O connections from the example
-- Since this is the top level, the connections all go to the outside world
entity UTNX_top is
Port ( CLK_50M_I : in STD_LOGIC; -- 50 MHz from onboard oscillator
LEDS_O : out STD_LOGIC_VECTOR(1 downto 0); -- Two onboard LED's
XB_SERIAL_O : out STD_LOGIC; -- Serial stream to PC
XB_SERIAL_I : in STD_LOGIC; -- Serial stream from PC
XB_LEDS_O : out STD_LOGIC_VECTOR(2 downto 0); -- 3 LED's on expansion board
XB_DIPSW_I : in STD_LOGIC_VECTOR(3 downto 0); -- 4 dip switches
BB_OUT_O : out STD_LOGIC_VECTOR(2 downto 0); -- 3 outputs on breadboard
BB_LEDS_O : out STD_LOGIC_VECTOR(7 downto 0)); -- 8 LED's on breadboard
end UTNX_top;
 
architecture Behavioral of UTNX_top is
 
-- Here we define the components we want to include in our design (there is only one)
-- The Port description is just copied from the components own source file
COMPONENT uTosNet_ctrl is
Port ( T_clk_50M : in STD_LOGIC;
T_serial_out : out STD_LOGIC;
T_serial_in : in STD_LOGIC;
T_reg_ptr : out std_logic_vector(2 downto 0);
T_word_ptr : out std_logic_vector(1 downto 0);
T_data_to_mem : in std_logic_vector(31 downto 0);
T_data_from_mem : out std_logic_vector(31 downto 0);
T_data_from_mem_latch : out std_logic);
END COMPONENT;
 
-- Here we define the signals used by the top level design
signal clk_50M : std_logic;
signal sys_cnt : std_logic_vector(31 downto 0) := (others => '0');
signal freq_gen : std_logic_vector(31 downto 0) := (others => '0');
signal freq_out : std_logic := '0';
signal bb_leds : std_logic_vector(7 downto 0); -- register for 8 leds
signal dipsw : std_logic_vector(3 downto 0);
signal frq,flsh,pwm : std_logic;
 
-- The signals below is used to hold data for our I/O application
signal pwm_value : std_logic_vector(15 downto 0); -- 16 bit register for pwm value
signal period : std_logic_vector(31 downto 0); -- 32 bit register for freq generator
signal flash : std_logic_vector(7 downto 0); -- 8 bit register for flash duration
signal v_leds : std_logic_vector(31 downto 0); -- 32 bit register to hold status for variable leds
 
-- Signals below is used to connect to the uTosNet Controller component
signal T_reg_ptr : std_logic_vector(2 downto 0);
signal T_word_ptr : std_logic_vector(1 downto 0);
signal T_data_to_mem : std_logic_vector(31 downto 0);
signal T_data_from_mem : std_logic_vector(31 downto 0);
signal T_data_from_mem_latch : std_logic;
 
begin
 
-- Here we instantiate the uTosNet Controller component, and connect its ports to signals
uTosNet_ctrlInst : uTosNet_ctrl
Port map ( T_clk_50M => clk_50M,
T_serial_out => XB_SERIAL_O,
T_serial_in => XB_SERIAL_I,
T_reg_ptr => T_reg_ptr,
T_word_ptr => T_word_ptr,
T_data_to_mem => T_data_to_mem,
T_data_from_mem => T_data_from_mem,
T_data_from_mem_latch => T_data_from_mem_latch);
 
-- It's not necessary to transfer these ports to signals, we just think it makes the syntax nicer
-- to avoid referring to ports in the body of the code. The compiler will optimize identical signals away
clk_50M <= CLK_50M_I;
BB_LEDS_O <= bb_leds;
dipsw <= XB_DIPSW_I;
-- here we define 3 signals used for output
frq <= freq_out;
pwm <= '1' when pwm_value > sys_cnt(15 downto 0) else '0';
flsh <= '1' when (sys_cnt(25 downto 24) = 0) and (sys_cnt(23 downto 16) < flash) else '0';
-- here we map the above 3 sigals to both breadboard outputs, and expansion board LED's
BB_OUT_O(0) <= frq;
BB_OUT_O(1) <= pwm;
BB_OUT_O(2) <= flsh;
XB_LEDS_O(0) <= frq;
XB_LEDS_O(1) <= pwm;
XB_LEDS_O(2) <= flsh;
 
-- Here we map some bits from the system counter to onboard LED's, as an 'alive' marker
LEDS_O <= sys_cnt(25 downto 24);
---------------------------------------------------------
-- Clocked process, to take data off the controller bus
----------------------------------------------------------
DatFromTosNet:
process(clk_50M)
begin -- process
if (clk_50M'event and clk_50M='1' and T_data_from_mem_latch='1') then
case (T_reg_ptr & T_word_ptr) is -- The addresses are concatenated for compact code
when "00000" => period <= T_data_from_mem; -- Register 0, word 0 - all 32 bits
when "00001" => pwm_value <= T_data_from_mem(15 downto 0); -- Register 0, word 1 - low 16 bits
flash <= T_data_from_mem(31 downto 24); -- high 8 bits
when "00100" => v_leds <= T_data_from_mem; -- Register 1, word 0 - all 32 bits
when others =>
end case;
end if;
end process;
 
----------------------------------------------------------
-- Unclocked process, to place data on the controller bus
----------------------------------------------------------
DatToTosNet:
process(T_reg_ptr,T_word_ptr)
begin
T_data_to_mem<="00000000000000000000000000000000"; -- default data
case (T_reg_ptr & T_word_ptr) is -- The addresses are concatenated for compact code
-- Register 0, word 0-3 are hard coded to these values for test/demo purposes
when "00000" => T_data_to_mem <= "00000000000000000000000000000001"; -- 1
when "00001" => T_data_to_mem <= "00000000000000000000000000000010"; -- 2
when "00010" => T_data_to_mem <= "00000000000000000000000000000100"; -- 3
when "00011" => T_data_to_mem <= "00000000000000000000000000001000"; -- 4
-- Register 1
when "00100" => T_data_to_mem <= sys_cnt; -- Word 0 gives the value of the system counter
when "00101" => T_data_to_mem <= freq_gen; -- Word 1 gives the value of the frequency generator
-- register 2
when "01000" => T_data_to_mem <= "0000000000000000000000000000" & dipsw;
-- Etc. etc. etc.
when others =>
end case;
end process;
 
---------------------------------------------------------------------
-- Clocked process, that counts clk_50M edges
---------------------------------------------------------------------
SystemCounter:
process(clk_50M)
begin -- process
if(clk_50M'event and clk_50M='1') then
sys_cnt<=sys_cnt+1;
end if;
end process;
 
-----------------------------------------------------------------
-- Clocked process to generate a square wave with variable period
-----------------------------------------------------------------
FreqGen:
process(clk_50M)
begin -- process
if (clk_50M'event and clk_50M='1') then
if period = 0 then
freq_gen <= (others => '0');
freq_out <= '0';
elsif freq_gen > period then
freq_gen <= (others => '0');
freq_out <= not freq_out;
else
freq_gen <= freq_gen +1;
end if;
end if;
end process;
 
-------------------------------------------------------
-- Unclocked proces to generate 8 pwm outputs for LEDS
-------------------------------------------------------
process(sys_cnt)
variable i : integer range 1 to 8;
begin -- process
for i in 1 to 8 loop
if(v_leds((i*4)-1 downto (i-1)*4) > sys_cnt(13 downto 10)) then
bb_leds(i-1) <= '1';
else
bb_leds(i-1) <='0';
end if;
end loop;
end process;
 
end Behavioral;
 
/uTosNet_example/uTosNet_controller/UTN_CTRL/ip_xc3s50an_tqg144/dataRegister.xco
0,0 → 1,89
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Mon Nov 02 14:50:24 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dataRegister
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=true
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=32
CSET read_width_b=32
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=64
CSET write_width_a=32
CSET write_width_b=32
# END Parameters
GENERATE
# CRC: af90b416
/uTosNet_example/uTosNet_controller/UTN_CTRL/ip_xc3s50an_tqg144/readme_ip_xc3s50an_tqg144.txt
0,0 → 1,25
The .xco files are created by CoreGen for the following FPGA device:
 
Xilinx xc3s50an tqg144
 
 
To generate an ip-core for other devices, use the following cores and settings:
 
 
data_register:
- Core: Block Memory Generator
- Memory Type: True Dual Port RAM
- Use Byte Write Enable: No
- Algorithm: Minimum Area
- Port A:
- Write Width: 32
- Write Depth: 64
- Operating Mode: Write First
- Enable: Always Enabled
- Port B:
- Write Width: 32
- Operating Mode: Write First
- Enable: Always Enabled
- Optional Output Registers: No
- Memory Initialization: Fill with 0
- Output Reset Pins: No
/uTosNet_example/uTosNet_controller/UTN_CTRL/uTosNet_ctrl.vhd
0,0 → 1,147
----------------------------------------------------------------------------------
-- Company: University of Southern Denmark
 
--
-- Create Date: 30/11/2009
-- Design Name: uTosNet
-- Module Name: uTosNet_ctrl - Behavioral
-- File Name: uTosNet_ctrl.vhd
-- Project Name: uTosNet
-- Target Devices: SDU XC3S50AN Board
-- Tool versions: Xilinx ISE 11.4
-- Description: This module implements a state machine for accessing the
-- uTosNet BlockRAM.
--
-- Revision:
-- Revision 0.10 - Initial release
--
-- Copyright 2010
--
-- This module is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This module is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this module. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity uTosNet_ctrl is
Port ( T_clk_50M : in STD_LOGIC;
T_serial_out : out STD_LOGIC;
T_serial_in : in STD_LOGIC;
T_reg_ptr : out std_logic_vector(2 downto 0);
T_word_ptr : out std_logic_vector(1 downto 0);
T_data_to_mem : in std_logic_vector(31 downto 0);
T_data_from_mem : out std_logic_vector(31 downto 0);
T_data_from_mem_latch : out std_logic);
end uTosNet_ctrl;
 
-------------------------------------------------
 
architecture Behavioral of uTosNet_ctrl is
 
component uTosNet_uart is
Port ( clk_50M : in STD_LOGIC;
serial_out : out STD_LOGIC;
serial_in : in STD_LOGIC;
dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
dataReg_clk : in STD_LOGIC;
dataReg_writeEnable : in STD_LOGIC);
end component;
 
type STATES is (IDLE, SETUP_1, CLK_1, DONE_1);
signal state : STATES := IDLE;
signal nextState : STATES := IDLE;
signal dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
signal dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
signal dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
signal dataReg_clk : STD_LOGIC;
signal dataReg_we : STD_LOGIC;
signal word_cnt : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
 
begin
uTosNet_uartInst : uTosNet_uart
Port map ( clk_50M => T_clk_50M,
serial_out => T_serial_out,
serial_in => T_serial_in,
dataReg_addr => dataReg_addr,
dataReg_dataIn => dataReg_dataIn,
dataReg_dataOut => dataReg_dataOut,
dataReg_clk => dataReg_clk,
dataReg_writeEnable => dataReg_we);
 
 
T_data_from_mem <= dataReg_dataOut;
dataReg_dataIn <= T_data_to_mem;
T_reg_ptr <= dataReg_addr(5 downto 3);
T_word_ptr <= dataReg_addr(1 downto 0);
 
process(T_clk_50M)
begin
if(T_clk_50M = '1' and T_clk_50M'event) then
state <= nextState;
case state is
when IDLE =>
when SETUP_1 =>
dataReg_addr <= word_cnt(5 downto 3) & word_cnt(0) & word_cnt(2 downto 1);
-- < register > | in/out area | word index
dataReg_clk <= '0';
T_data_from_mem_latch <= '0';
word_cnt <= word_cnt;
if word_cnt(0) = '0' then -- If we are looking at a slave output register
dataReg_we <= '1'; -- Prepare to copy data from bus to RAM block
else
dataReg_we <= '0';
end if;
when CLK_1 =>
dataReg_clk <= '1';
if word_cnt(0) = '1' then -- If we are looking at a slave_input register
T_data_from_mem_latch <= '1'; -- Signal bus-slave, that data can be copied from the bus
dataReg_we <= '0';
else
dataReg_we <= '1';
T_data_from_mem_latch <= '0';
end if;
word_cnt <= word_cnt;
when DONE_1 =>
dataReg_we <='0';
T_data_from_mem_latch <= '0';
word_cnt <= word_cnt + 1;
end case;
end if;
end process;
process(state)
begin
case state is
when IDLE =>
nextState <= SETUP_1;
when SETUP_1 =>
nextState <= CLK_1;
when CLK_1 =>
nextState <= DONE_1;
when DONE_1 =>
nextState <= IDLE;
end case;
end process;
 
 
end architecture;
/uTosNet_example/uTosNet_controller/UTN_CTRL/uTosNet_uart.vhd
0,0 → 1,513
----------------------------------------------------------------------------------
-- Company: University of Southern Denmark
-- Engineer: Simon Falsig
--
-- Create Date: 19/03/2010
-- Design Name: uTosNet
-- Module Name: uTosNet_usb - Behavioral
-- File Name: uTosNet_uart.vhd
-- Project Name: uTosNet
-- Target Devices: SDU XC3S50AN Board
-- Tool versions: Xilinx ISE 11.4
-- Description: This module implements a very simple ASCII based protocol over
-- a uart. Data can be read and written from and to one port of a
-- dual-port blockRAM, where the other blockRAM port is available
-- to the user application. Communication takes place at the fol-
-- lowing settings:
-- Baudrate: 115200 kbps
-- Parity: none
-- Bits: 8 data bits, 1 stop bit
-- Flowcontrol: none
-- The protocol format can be seen in the documentation files.
--
-- Focus has mostly been on a simple implementation, as the
-- module is to be used during courses at the university.
--
-- Dependencies: The module uses the uart implementation from Ken Chapmans
-- PicoBlaze. More specifically the following files:
-- uart_rx.vhd
-- kcuart_rx.vhd
-- bbfifo_16x8.vhd
-- uart_tx.vhd
-- kcuart_tx.vhd
-- These files can be downloaded from Xilinx:
-- https://secure.xilinx.com/webreg/register.do?group=picoblaze
--
-- It should not be hard to implement the module using another
-- uart implementation though.
--
-- Revision:
-- Revision 0.10 - Initial release
--
-- Copyright 2010
--
-- This module is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This module is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this module. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uTosNet_uart is
Port ( clk_50M : in STD_LOGIC;
serial_out : out STD_LOGIC;
serial_in : in STD_LOGIC;
dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
dataReg_clk : in STD_LOGIC;
dataReg_writeEnable : in STD_LOGIC);
end uTosNet_uart;
 
architecture Behavioral of uTosNet_uart is
 
component dataRegister
Port ( clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR(0 downto 0);
addra : in STD_LOGIC_VECTOR(5 downto 0);
dina : in STD_LOGIC_VECTOR(31 downto 0);
douta : out STD_LOGIC_VECTOR(31 downto 0);
clkb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR(0 downto 0);
addrb : in STD_LOGIC_VECTOR(5 downto 0);
dinb : in STD_LOGIC_VECTOR(31 downto 0);
doutb : out STD_LOGIC_VECTOR(31 downto 0));
end component;
 
component uart_rx
Port ( serial_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
read_buffer : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
buffer_data_present : out STD_LOGIC;
buffer_full : out STD_LOGIC;
buffer_half_full : out STD_LOGIC;
clk : in STD_LOGIC);
end component;
 
component uart_tx
Port ( serial_out : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
write_buffer : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
buffer_full : out STD_LOGIC;
buffer_half_full : out STD_LOGIC;
clk : in STD_LOGIC);
end component;
signal baudCount : integer range 0 to 36 :=0;
signal en_16_x_baud : STD_LOGIC;
signal readFromUart : STD_LOGIC;
signal rxData : STD_LOGIC_VECTOR(7 downto 0);
signal rxDataPresent : STD_LOGIC;
signal rxFull : STD_LOGIC;
signal rxHalfFull : STD_LOGIC;
 
signal txData : STD_LOGIC_VECTOR(7 downto 0);
signal writeToUart : STD_LOGIC;
signal txFull : STD_LOGIC;
signal txHalfFull : STD_LOGIC;
 
constant UARTDIV : STD_LOGIC_VECTOR(5 downto 0) := "011010";
 
type STATES is (IDLE, COMMAND_IN, WAIT1, REG_IN, WAIT2, INDEX_IN, WAIT3, SPACE_IN, WAIT4, DATA_IN, WAIT_DATA_IN, DATA_OUT, PERFORM_READ_SETUP, PERFORM_READ_CLK, PERFORM_READ_DONE, PERFORM_WRITE_SETUP, PERFORM_WRITE_CLK, PERFORM_WRITE_DONE);
signal state : STATES := IDLE;
signal nextState : STATES := IDLE;
 
type COMMANDS is (CMD_NONE, CMD_READ, CMD_WRITE, CMD_COMMIT_READ, CMD_COMMIT_WRITE);
 
signal currentCommand : COMMANDS := CMD_NONE;
 
signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0);
signal int_dataReg_clk : STD_LOGIC;
signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0);
signal inputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal outputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
signal readCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal writeCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal currentReg : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal currentIndex : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal commitRead : STD_LOGIC := '0';
signal commitWrite : STD_LOGIC := '0';
 
begin
 
dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:)
 
dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister
Port map ( clka => dataReg_clk, --PortA is used for the user application
wea => dataReg_writeEnable_V, --
addra => dataReg_addr, --
dina => dataReg_dataIn, --
douta => dataReg_dataOut, --
clkb => int_dataReg_clk, --PortB is used for the SPI interface
web => int_dataReg_we, --
addrb => int_dataReg_addr, --
dinb => int_dataReg_dataIn, --
doutb => int_dataReg_dataOut); --
 
rx_inst: uart_rx
Port map ( serial_in => serial_in,
data_out => rxData,
read_buffer => readFromUart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rxDataPresent,
buffer_full => rxFull,
buffer_half_full => rxHalfFull,
clk => clk_50M );
 
tx_inst : uart_tx
Port map ( serial_out => serial_out,
data_in => txData,
write_buffer => writeToUart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_full => txFull,
buffer_half_full => txHalfFull,
clk => clk_50M);
 
baudTimer_inst: process(clk_50M)
begin
if(clk_50M'event and clk_50M='1')then
if(baudCount = UARTDIV)then
baudCount <= 0;
en_16_x_baud <= '1';
else
baudCount <= baudCount + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baudTimer_inst;
 
process(clk_50M)
begin
if(clk_50M = '1' and clk_50M'event) then
state <= nextState;
readFromUart <= '0';
writeToUart <= '0';
case state is
when IDLE =>
currentCommand <= CMD_NONE;
readCounter <= (others => '0');
writeCounter <= (others => '0');
commitRead <= '0';
commitWrite <= '0';
when COMMAND_IN =>
commitRead <= '0';
commitWrite <= '0';
if(rxDataPresent = '1') then
case rxData is
when "01110010" => --'r'
currentCommand <= CMD_READ;
when "01110111" => --'w'
currentCommand <= CMD_WRITE;
when "01110100" => --'t'
commitRead <= '1'; --Might need to switch with write
currentCommand <= CMD_NONE;
when "01100011" => --'c'
commitWrite <= '1'; --Might need to switch with read
currentCommand <= CMD_NONE;
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
end if;
when WAIT1 =>
when REG_IN =>
if(rxDataPresent = '1') then
case rxData is
when "00110000" =>
currentReg <= "000";
when "00110001" =>
currentReg <= "001";
when "00110010" =>
currentReg <= "010";
when "00110011" =>
currentReg <= "011";
when "00110100" =>
currentReg <= "100";
when "00110101" =>
currentReg <= "101";
when "00110110" =>
currentReg <= "110";
when "00110111" =>
currentReg <= "111";
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
end if;
when WAIT2 =>
when INDEX_IN =>
if(rxDataPresent = '1') then
case rxData is
when "00110000" =>
currentIndex <= "000";
when "00110001" =>
currentIndex <= "001";
when "00110010" =>
currentIndex <= "010";
when "00110011" =>
currentIndex <= "011";
when "00110100" =>
currentIndex <= "100";
when "00110101" =>
currentIndex <= "101";
when "00110110" =>
currentIndex <= "110";
when "00110111" =>
currentIndex <= "111";
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
end if;
when WAIT3 =>
when SPACE_IN =>
if(rxDataPresent = '1') then
if(not(rxData = "00100000")) then
currentCommand <= CMD_NONE;
end if;
readFromUart <= '1';
end if;
when WAIT4 =>
when DATA_IN =>
if(rxDataPresent = '1') then
case rxData is
when "00110000" => --'0'
inputBuffer <= inputBuffer(27 downto 0) & "0000";
when "00110001" => --'1'
inputBuffer <= inputBuffer(27 downto 0) & "0001";
when "00110010" => --'2'
inputBuffer <= inputBuffer(27 downto 0) & "0010";
when "00110011" => --'3'
inputBuffer <= inputBuffer(27 downto 0) & "0011";
when "00110100" => --'4'
inputBuffer <= inputBuffer(27 downto 0) & "0100";
when "00110101" => --'5'
inputBuffer <= inputBuffer(27 downto 0) & "0101";
when "00110110" => --'6'
inputBuffer <= inputBuffer(27 downto 0) & "0110";
when "00110111" => --'7'
inputBuffer <= inputBuffer(27 downto 0) & "0111";
when "00111000" => --'8'
inputBuffer <= inputBuffer(27 downto 0) & "1000";
when "00111001" => --'9'
inputBuffer <= inputBuffer(27 downto 0) & "1001";
when "01100001" => --'a'
inputBuffer <= inputBuffer(27 downto 0) & "1010";
when "01100010" => --'b'
inputBuffer <= inputBuffer(27 downto 0) & "1011";
when "01100011" => --'c'
inputBuffer <= inputBuffer(27 downto 0) & "1100";
when "01100100" => --'d'
inputBuffer <= inputBuffer(27 downto 0) & "1101";
when "01100101" => --'e'
inputBuffer <= inputBuffer(27 downto 0) & "1110";
when "01100110" => --'f'
inputBuffer <= inputBuffer(27 downto 0) & "1111";
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
readCounter <= readCounter + 1;
end if;
when WAIT_DATA_IN =>
when DATA_OUT =>
writeToUart <= '1';
if(writeCounter = 8) then
txData <= "00100000"; --Transmit a space to make thinks look nicer...:)
else
case outputBuffer(31 downto 28) is
when "0000" => --'0'
txData <= "00110000";
when "0001" => --'1'
txData <= "00110001";
when "0010" => --'2'
txData <= "00110010";
when "0011" => --'3'
txData <= "00110011";
when "0100" => --'4'
txData <= "00110100";
when "0101" => --'5'
txData <= "00110101";
when "0110" => --'6'
txData <= "00110110";
when "0111" => --'7'
txData <= "00110111";
when "1000" => --'8'
txData <= "00111000";
when "1001" => --'9'
txData <= "00111001";
when "1010" => --'a'
txData <= "01100001";
when "1011" => --'b'
txData <= "01100010";
when "1100" => --'c'
txData <= "01100011";
when "1101" => --'d'
txData <= "01100100";
when "1110" => --'e'
txData <= "01100101";
when "1111" => --'f'
txData <= "01100110";
when others =>
end case;
end if;
outputBuffer <= outputBuffer(27 downto 0) & "0000";
writeCounter <= writeCounter + 1;
when PERFORM_READ_SETUP =>
int_dataReg_addr <= currentReg & currentIndex;
int_dataReg_we <= "0";
int_dataReg_clk <= '0';
when PERFORM_READ_CLK =>
int_dataReg_clk <= '1';
when PERFORM_READ_DONE =>
outputBuffer <= int_dataReg_dataOut;
int_dataReg_clk <= '0';
when PERFORM_WRITE_SETUP =>
int_dataReg_addr <= currentReg & currentIndex;
int_dataReg_dataIn <= inputBuffer;
int_dataReg_we <= "1";
int_dataReg_clk <= '0';
when PERFORM_WRITE_CLK =>
int_dataReg_clk <= '1';
when PERFORM_WRITE_DONE =>
int_dataReg_we <= "0";
int_dataReg_clk <= '0';
end case;
end if;
end process;
process(state, rxDataPresent, currentCommand, readCounter, writeCounter)
begin
if((currentCommand = CMD_NONE) and not ((state = COMMAND_IN) or (state = IDLE))) then
nextState <= IDLE;
else
case state is
when IDLE =>
nextState <= COMMAND_IN;
when COMMAND_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT1;
else
nextState <= COMMAND_IN;
end if;
when WAIT1 =>
if(rxDataPresent = '0') then
nextState <= REG_IN;
else
nextState <= WAIT1;
end if;
when REG_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT2;
else
nextState <= REG_IN;
end if;
when WAIT2 =>
if(rxDataPresent = '0') then
nextState <= INDEX_IN;
else
nextState <= WAIT2;
end if;
when INDEX_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT3;
else
nextState <= INDEX_IN;
end if;
when WAIT3 =>
if(rxDataPresent = '0') then
if(currentCommand = CMD_READ) then
nextState <= PERFORM_READ_SETUP;
else
nextState <= SPACE_IN;
end if;
else
nextState <= WAIT3;
end if;
when SPACE_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT4;
else
nextState <= SPACE_IN;
end if;
when WAIT4 =>
if(rxDataPresent = '0') then
nextState <= DATA_IN;
else
nextState <= WAIT4;
end if;
when DATA_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT_DATA_IN;
else
nextState <= DATA_IN;
end if;
when WAIT_DATA_IN =>
if(rxDataPresent = '0') then
if(readCounter = 8) then
nextState <= PERFORM_WRITE_SETUP;
else
nextState <= DATA_IN;
end if;
else
nextState <= WAIT_DATA_IN;
end if;
when DATA_OUT =>
if(writeCounter = 8) then
nextState <= IDLE;
else
nextState <= DATA_OUT;
end if;
when PERFORM_READ_SETUP =>
nextState <= PERFORM_READ_CLK;
when PERFORM_READ_CLK =>
nextState <= PERFORM_READ_DONE;
when PERFORM_READ_DONE =>
nextState <= DATA_OUT;
when PERFORM_WRITE_SETUP =>
nextState <= PERFORM_WRITE_CLK;
when PERFORM_WRITE_CLK =>
nextState <= PERFORM_WRITE_DONE;
when PERFORM_WRITE_DONE =>
nextState <= IDLE;
end case;
end if;
end process;
end Behavioral;
 
/uTosNet_example/uTosNet_controller/UTNX_top.ucf
0,0 → 1,29
NET "CLK_50M_I" LOC = P124; # On board oscillator
NET "LEDS_O<0>" LOC = P31; # On board LED
NET "LEDS_O<1>" LOC = P32; # On board LED
 
NET "XB_SERIAL_I" LOC = P125; # Expansion board USB <-> UART
NET "XB_SERIAL_O" LOC = P127; # Expansion board USB <-> UART
 
NET "XB_LEDS_O[0]" LOC = P10; # Expansion board LED
NET "XB_LEDS_O[1]" LOC = P12; # Expansion board LED
NET "XB_LEDS_O[2]" LOC = P13; # Expansion board LED
 
NET "XB_DIPSW_I<0>" LOC = P20 | PULLUP; # Expansion board Dip switch
NET "XB_DIPSW_I<1>" LOC = P21 | PULLUP; # Expansion board Dip switch
NET "XB_DIPSW_I<2>" LOC = P24 | PULLUP; # Expansion board Dip switch
NET "XB_DIPSW_I<3>" LOC = P25 | PULLUP; # Expansion board Dip switch
 
 
NET "BB_LEDS_O<0>" LOC = P48; # Bottom connector pin 12
NET "BB_LEDS_O<1>" LOC = P47; # Bottom connector pin 13
NET "BB_LEDS_O<2>" LOC = P55; # Bottom connector pin 14
NET "BB_LEDS_O<3>" LOC = P45; # Bottom connector pin 15
NET "BB_LEDS_O<4>" LOC = P44; # Bottom connector pin 16
NET "BB_LEDS_O<5>" LOC = P43; # Bottom connector pin 17
NET "BB_LEDS_O<6>" LOC = P42; # Bottom connector pin 18
NET "BB_LEDS_O<7>" LOC = P30; # Bottom connector pin 19
 
NET "BB_OUT_O<0>" LOC = P60; # Bottom connector pin 1
NET "BB_OUT_O<1>" LOC = P59; # Bottom connector pin 2
NET "BB_OUT_O<2>" LOC = P58; # Bottom connector pin 3
/uTosNet_spi/readme_ip_xc3s50an_tqg144.txt
0,0 → 1,25
The .xco files are created by CoreGen for the following FPGA device:
 
Xilinx xc3s50an tqg144
 
 
To generate an ip-core for other devices, use the following cores and settings:
 
 
data_register:
- Core: Block Memory Generator
- Memory Type: True Dual Port RAM
- Use Byte Write Enable: No
- Algorithm: Minimum Area
- Port A:
- Write Width: 32
- Write Depth: 64
- Operating Mode: Write First
- Enable: Always Enabled
- Port B:
- Write Width: 32
- Operating Mode: Write First
- Enable: Always Enabled
- Optional Output Registers: No
- Memory Initialization: Fill with 0
- Output Reset Pins: No
/uTosNet_uart/readme_ip_xc3s50an_tqg144.txt
0,0 → 1,25
The .xco files are created by CoreGen for the following FPGA device:
 
Xilinx xc3s50an tqg144
 
 
To generate an ip-core for other devices, use the following cores and settings:
 
 
data_register:
- Core: Block Memory Generator
- Memory Type: True Dual Port RAM
- Use Byte Write Enable: No
- Algorithm: Minimum Area
- Port A:
- Write Width: 32
- Write Depth: 64
- Operating Mode: Write First
- Enable: Always Enabled
- Port B:
- Write Width: 32
- Operating Mode: Write First
- Enable: Always Enabled
- Optional Output Registers: No
- Memory Initialization: Fill with 0
- Output Reset Pins: No

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