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https://opencores.org/ocsvn/v586/v586/trunk
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/v586/trunk
- from Rev 103 to Rev 104
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Rev 103 → Rev 104
/rtl/clk_wiz_0.v
0,0 → 1,202
// file: clk_wiz_0.v |
// |
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. |
// |
// This file contains confidential and proprietary information |
// of Xilinx, Inc. and is protected under U.S. and |
// international copyright and other intellectual property |
// laws. |
// |
// DISCLAIMER |
// This disclaimer is not a license and does not grant any |
// rights to the materials distributed herewith. Except as |
// otherwise provided in a valid license issued to you by |
// Xilinx, and to the maximum extent permitted by applicable |
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
// (2) Xilinx shall not be liable (whether in contract or tort, |
// including negligence, or under any other theory of |
// liability) for any loss or damage of any kind or nature |
// related to, arising under or in connection with these |
// materials, including for any direct, or any indirect, |
// special, incidental, or consequential loss or damage |
// (including loss of data, profits, goodwill, or any type of |
// loss or damage suffered as a result of any action brought |
// by a third party) even if such damage or loss was |
// reasonably foreseeable or Xilinx had been advised of the |
// possibility of the same. |
// |
// CRITICAL APPLICATIONS |
// Xilinx products are not designed or intended to be fail- |
// safe, or for use in any application requiring fail-safe |
// performance, such as life-support or safety devices or |
// systems, Class III medical devices, nuclear facilities, |
// applications related to the deployment of airbags, or any |
// other applications that could lead to death, personal |
// injury, or severe property or environmental damage |
// (individually and collectively, "Critical |
// Applications"). Customer assumes the sole risk and |
// liability of any use of Xilinx products in Critical |
// Applications, subject only to applicable laws and |
// regulations governing limitations on product liability. |
// |
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
// PART OF THIS FILE AT ALL TIMES. |
// |
//---------------------------------------------------------------------------- |
// User entered comments |
//---------------------------------------------------------------------------- |
// None |
// |
//---------------------------------------------------------------------------- |
// Output Output Phase Duty Cycle Pk-to-Pk Phase |
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) |
//---------------------------------------------------------------------------- |
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575 |
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575 |
// CLK_OUT3___200.000______0.000______50.0______114.829_____98.575 |
// |
//---------------------------------------------------------------------------- |
// Input Clock Freq (MHz) Input Jitter (UI) |
//---------------------------------------------------------------------------- |
// __primary_________100.000____________0.010 |
|
`timescale 1ps/1ps |
|
module clk_wiz_0 |
(// Clock in ports |
input clk_in1, |
// Clock out ports |
output clk_out1, |
output clk_out2, |
output clk_out3, |
// Status and control signals |
output locked |
); |
|
// Input buffering |
//------------------------------------ |
IBUF clkin1_ibufg |
(.O (clk_in1_clk_wiz_0), |
.I (clk_in1)); |
|
|
|
// Clocking PRIMITIVE |
//------------------------------------ |
// Instantiation of the MMCM PRIMITIVE |
// * Unused inputs are tied off |
// * Unused outputs are labeled unused |
wire [15:0] do_unused; |
wire drdy_unused; |
wire psdone_unused; |
wire locked_int; |
wire clkfbout_clk_wiz_0; |
wire clkfbout_buf_clk_wiz_0; |
wire clkfboutb_unused; |
wire clkout0b_unused; |
wire clkout1b_unused; |
wire clkout2b_unused; |
wire clkout3_unused; |
wire clkout3b_unused; |
wire clkout4_unused; |
wire clkout5_unused; |
wire clkout6_unused; |
wire clkfbstopped_unused; |
wire clkinstopped_unused; |
|
MMCME2_ADV |
#(.BANDWIDTH ("OPTIMIZED"), |
.CLKOUT4_CASCADE ("FALSE"), |
.COMPENSATION ("ZHOLD"), |
.STARTUP_WAIT ("FALSE"), |
.DIVCLK_DIVIDE (1), |
.CLKFBOUT_MULT_F (10.000), |
.CLKFBOUT_PHASE (0.000), |
.CLKFBOUT_USE_FINE_PS ("FALSE"), |
.CLKOUT0_DIVIDE_F (10.000), |
.CLKOUT0_PHASE (0.000), |
.CLKOUT0_DUTY_CYCLE (0.500), |
.CLKOUT0_USE_FINE_PS ("FALSE"), |
.CLKOUT1_DIVIDE (40), |
.CLKOUT1_PHASE (0.000), |
.CLKOUT1_DUTY_CYCLE (0.500), |
.CLKOUT1_USE_FINE_PS ("FALSE"), |
.CLKOUT2_DIVIDE (5), |
.CLKOUT2_PHASE (0.000), |
.CLKOUT2_DUTY_CYCLE (0.500), |
.CLKOUT2_USE_FINE_PS ("FALSE"), |
.CLKIN1_PERIOD (10.0)) |
mmcm_adv_inst |
// Output clocks |
( |
.CLKFBOUT (clkfbout_clk_wiz_0), |
.CLKFBOUTB (clkfboutb_unused), |
.CLKOUT0 (clk_out1_clk_wiz_0), |
.CLKOUT0B (clkout0b_unused), |
.CLKOUT1 (clk_out2_clk_wiz_0), |
.CLKOUT1B (clkout1b_unused), |
.CLKOUT2 (clk_out3_clk_wiz_0), |
.CLKOUT2B (clkout2b_unused), |
.CLKOUT3 (clkout3_unused), |
.CLKOUT3B (clkout3b_unused), |
.CLKOUT4 (clkout4_unused), |
.CLKOUT5 (clkout5_unused), |
.CLKOUT6 (clkout6_unused), |
// Input clock control |
.CLKFBIN (clkfbout_buf_clk_wiz_0), |
.CLKIN1 (clk_in1_clk_wiz_0), |
.CLKIN2 (1'b0), |
// Tied to always select the primary input clock |
.CLKINSEL (1'b1), |
// Ports for dynamic reconfiguration |
.DADDR (7'h0), |
.DCLK (1'b0), |
.DEN (1'b0), |
.DI (16'h0), |
.DO (do_unused), |
.DRDY (drdy_unused), |
.DWE (1'b0), |
// Ports for dynamic phase shift |
.PSCLK (1'b0), |
.PSEN (1'b0), |
.PSINCDEC (1'b0), |
.PSDONE (psdone_unused), |
// Other control and status signals |
.LOCKED (locked_int), |
.CLKINSTOPPED (clkinstopped_unused), |
.CLKFBSTOPPED (clkfbstopped_unused), |
.PWRDWN (1'b0), |
.RST (1'b0)); |
|
|
assign locked = locked_int; |
|
// Output buffering |
//----------------------------------- |
|
BUFG clkf_buf |
(.O (clkfbout_buf_clk_wiz_0), |
.I (clkfbout_clk_wiz_0)); |
|
|
|
BUFG clkout1_buf |
(.O (clk_out1), |
.I (clk_out1_clk_wiz_0)); |
|
|
BUFG clkout2_buf |
(.O (clk_out2), |
.I (clk_out2_clk_wiz_0)); |
|
BUFG clkout3_buf |
(.O (clk_out3), |
.I (clk_out3_clk_wiz_0)); |
|
|
|
endmodule |
/rtl/rstgen.v
0,0 → 1,38
/* |
* Copyright (c) 2015, Arch Labolatory |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions are met: |
* |
* 1. Redistributions of source code must retain the above copyright notice, |
* this list of conditions and the following disclaimer. |
* 2. Redistributions in binary form must reproduce the above copyright notice, |
* this list of conditions and the following disclaimer in the documentation |
* and/or other materials provided with the distribution. |
* |
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
* |
*/ |
|
module RSTGEN(CLK, RST_X_I, RST_X_O); |
input CLK, RST_X_I; |
output RST_X_O; |
|
reg [7:0] cnt; |
assign RST_X_O = cnt[7]; |
|
always @(posedge CLK or negedge RST_X_I) begin |
if (!RST_X_I) cnt <= 0; |
else if (~RST_X_O) cnt <= (cnt + 1'b1); |
end |
endmodule |