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    /v586/trunk
    from Rev 89 to Rev 90
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Rev 89 → Rev 90

/rtl/periph.v
1,12 → 1,6
 
// Generated by ac_shell v5.17-s013 on Tue May 24 12:38:58 CET 2016.
module BIZWDP_DEC_023767(O0, bit_bang);
 
// Restrictions concerning the use of Ambit BuildGates are covered in the
// license agreement. Distribution to third party EDA vendors is
// strictly prohibited.
 
module AWDP_DEC_023767(O0, bit_bang);
 
output [8:0] O0;
input [8:0] bit_bang;
 
9230,7 → 9224,7
notech_reg \iDIN_reg[7] (.CP(n_8408), .D(DIN[7]), .CD(n416), .Q(iDIN[7])
);
endmodule
module AWDP_DEC_36_0(O0, counter);
module BIZWDP_DEC_36_0(O0, counter);
 
output [15:0] O0;
input [15:0] counter;
9284,7 → 9278,7
notech_inv i_284034(.A(n_6039), .Z(O0[1]));
notech_or2 i_264035(.A(counter[1]), .B(counter[0]), .Z(n_100));
endmodule
module AWDP_SUB_39_0(O0, counter);
module BIZWDP_SUB_39_0(O0, counter);
 
output [15:0] O0;
input [15:0] counter;
10049,14 → 10043,14
notech_inv i_4390(.A(n_1444), .Z(n_3308));
notech_inv i_4391(.A(n_1445), .Z(n_3309));
notech_inv i_4392(.A(read), .Z(n_3310));
AWDP_DEC_36_0 i_1338(.O0({n_1329, n_1328, n_1327, n_1326, n_1325, n_1324
BIZWDP_DEC_36_0 i_1338(.O0({n_1329, n_1328, n_1327, n_1326, n_1325, n_1324
, n_1323, n_1322, n_1321, n_1319, n_1317, n_1315, n_1313, n_1311
, n_1309, n_1307}), .counter(counter));
AWDP_SUB_39_0 i_1332(.O0({n_1445, n_1444, n_1443, n_1442, n_1441, n_1440
BIZWDP_SUB_39_0 i_1332(.O0({n_1445, n_1444, n_1443, n_1442, n_1441, n_1440
, n_1439, n_1438, n_1437, n_1436, n_1435, n_1434, n_1433, n_1431
, n_1429, n_1427}), .counter(counter));
endmodule
module AWDP_DEC_36_1(O0, counter);
module BIZWDP_DEC_36_1(O0, counter);
 
output [15:0] O0;
input [15:0] counter;
10110,7 → 10104,7
notech_inv i_284094(.A(n_6770), .Z(O0[1]));
notech_or2 i_264095(.A(counter[1]), .B(counter[0]), .Z(n_100));
endmodule
module AWDP_SUB_39_1(O0, counter);
module BIZWDP_SUB_39_1(O0, counter);
 
output [15:0] O0;
input [15:0] counter;
10876,14 → 10870,14
notech_inv i_3350(.A(n_1444), .Z(n_2789));
notech_inv i_3351(.A(n_1445), .Z(n_2790));
notech_inv i_3352(.A(read), .Z(n_2791));
AWDP_DEC_36_1 i_1338(.O0({n_1329, n_1328, n_1327, n_1326, n_1325, n_1324
BIZWDP_DEC_36_1 i_1338(.O0({n_1329, n_1328, n_1327, n_1326, n_1325, n_1324
, n_1323, n_1322, n_1321, n_1319, n_1317, n_1315, n_1313, n_1311
, n_1309, n_1307}), .counter(counter));
AWDP_SUB_39_1 i_1332(.O0({n_1445, n_1444, n_1443, n_1442, n_1441, n_1440
BIZWDP_SUB_39_1 i_1332(.O0({n_1445, n_1444, n_1443, n_1442, n_1441, n_1440
, n_1439, n_1438, n_1437, n_1436, n_1435, n_1434, n_1433, n_1431
, n_1429, n_1427}), .counter(counter));
endmodule
module AWDP_DEC_36_2(O0, counter);
module BIZWDP_DEC_36_2(O0, counter);
 
output [15:0] O0;
input [15:0] counter;
10937,7 → 10931,7
notech_inv i_284154(.A(n_7501), .Z(O0[1]));
notech_or2 i_264155(.A(counter[1]), .B(counter[0]), .Z(n_100));
endmodule
module AWDP_SUB_39_2(O0, counter);
module BIZWDP_SUB_39_2(O0, counter);
 
output [15:0] O0;
input [15:0] counter;
11718,10 → 11712,10
notech_inv i_2310(.A(n_1307), .Z(n_2266));
notech_inv i_2311(.A(n_1313), .Z(n_2267));
notech_inv i_2312(.A(n_1433), .Z(n_2268));
AWDP_DEC_36_2 i_1338(.O0({n_1329, n_1328, n_1327, n_1326, n_1325, n_1324
BIZWDP_DEC_36_2 i_1338(.O0({n_1329, n_1328, n_1327, n_1326, n_1325, n_1324
, n_1323, n_1322, n_1321, n_1319, n_1317, n_1315, n_1313, n_1311
, n_1309, n_1307}), .counter(counter));
AWDP_SUB_39_2 i_1332(.O0({n_1445, n_1444, n_1443, n_1442, n_1441, n_1440
BIZWDP_SUB_39_2 i_1332(.O0({n_1445, n_1444, n_1443, n_1442, n_1441, n_1440
, n_1439, n_1438, n_1437, n_1436, n_1435, n_1434, n_1433, n_1431
, n_1429, n_1427}), .counter(counter));
endmodule
13685,8 → 13679,8
notech_inv i_6695(.A(ms_write), .Z(n_4374));
endmodule
module periph(s00_AXI_RSTN, s00_AXI_CLK, cfg, spi_mosi, spi_miso, spi_clk, spi_cs
, mosi, miso, sclk, s00_AXI_AWADDR, s00_AXI_AWVALID, s00_AXI_AWREADY
, s00_AXI_AWBURST, s00_AXI_AWLEN, s00_AXI_AWSIZE, s00_AXI_ARADDR
, mosi, miso, sclk, s00_AXI_BIZWADDR, s00_AXI_BIZWVALID, s00_AXI_BIZWREADY
, s00_AXI_BIZWBURST, s00_AXI_BIZWLEN, s00_AXI_BIZWSIZE, s00_AXI_ARADDR
, s00_AXI_ARVALID, s00_AXI_ARREADY, s00_AXI_ARBURST, s00_AXI_ARLEN
, s00_AXI_ARSIZE, s00_AXI_WDATA, s00_AXI_WVALID, s00_AXI_WREADY,
s00_AXI_WSTRB, s00_AXI_WLAST, s00_AXI_RDATA, s00_AXI_RVALID, s00_AXI_RREADY
13704,12 → 13698,12
output mosi;
input miso;
output sclk;
input [31:0] s00_AXI_AWADDR;
input s00_AXI_AWVALID;
output s00_AXI_AWREADY;
input [1:0] s00_AXI_AWBURST;
input [3:0] s00_AXI_AWLEN;
input [2:0] s00_AXI_AWSIZE;
input [31:0] s00_AXI_BIZWADDR;
input s00_AXI_BIZWVALID;
output s00_AXI_BIZWREADY;
input [1:0] s00_AXI_BIZWBURST;
input [3:0] s00_AXI_BIZWLEN;
input [2:0] s00_AXI_BIZWSIZE;
input [31:0] s00_AXI_ARADDR;
input s00_AXI_ARVALID;
output s00_AXI_ARREADY;
14402,9 → 14396,9
));
notech_ao4 i_332(.A(n_629), .B(n_5435), .C(n_5335), .D(n_5479), .Z(n_822
));
notech_reg s00_AXI_AWREADY_reg(.CP(n_8489), .D(n_4673), .CD(n_8183), .Q(s00_AXI_AWREADY
notech_reg s00_AXI_BIZWREADY_reg(.CP(n_8489), .D(n_4673), .CD(n_8183), .Q(s00_AXI_BIZWREADY
));
notech_mux2 i_7095(.S(n_7569), .A(s00_AXI_AWREADY), .B(n_5339), .Z(n_4673
notech_mux2 i_7095(.S(n_7569), .A(s00_AXI_BIZWREADY), .B(n_5339), .Z(n_4673
));
notech_reg superIO_idx_reg_0(.CP(n_8489), .D(n_4679), .CD(n_8183), .Q(superIO_idx
[0]));
14443,7 → 14437,7
[7]));
notech_mux2 i_7159(.S(n_5383), .A(writeio_data[7]), .B(superIO_idx[7]),
.Z(n_4721));
notech_nand2 i_2(.A(s00_AXI_AWVALID), .B(n_5481), .Z(n_6223));
notech_nand2 i_2(.A(s00_AXI_BIZWVALID), .B(n_5481), .Z(n_6223));
notech_reg div_clke_reg_0(.CP(n_8477), .D(n_5345), .CD(n_8183), .Q(div_clke
[0]));
notech_reg div_clke_reg_1(.CP(n_8477), .D(n_5348), .CD(n_8183), .Q(div_clke
14479,97 → 14473,97
notech_reg bit_bang_reg_2(.CP(n_8477), .D(n_4759), .CD(n_8184), .Q(bit_bang
[2]));
notech_mux2 i_7223(.S(n_5352), .A(bit_bang[2]), .B(n_554), .Z(n_4759));
notech_mux2 i_161430(.S(n_6223), .A(s00_AXI_AWADDR[17]), .B(s00_AXI_ARADDR
notech_mux2 i_161430(.S(n_6223), .A(s00_AXI_BIZWADDR[17]), .B(s00_AXI_ARADDR
[17]), .Z(n_6320));
notech_reg bit_bang_reg_3(.CP(n_8477), .D(n_4765), .CD(n_8184), .Q(bit_bang
[3]));
notech_mux2 i_7231(.S(n_5352), .A(bit_bang[3]), .B(n_7202), .Z(n_4765)
);
notech_mux2 i_151429(.S(n_6223), .A(s00_AXI_AWADDR[16]), .B(s00_AXI_ARADDR
notech_mux2 i_151429(.S(n_6223), .A(s00_AXI_BIZWADDR[16]), .B(s00_AXI_ARADDR
[16]), .Z(n_6314));
notech_reg bit_bang_reg_4(.CP(n_8495), .D(n_4771), .CD(n_8184), .Q(bit_bang
[4]));
notech_mux2 i_7239(.S(n_5352), .A(bit_bang[4]), .B(n_7208), .Z(n_4771)
);
notech_mux2 i_141428(.S(n_6223), .A(s00_AXI_AWADDR[15]), .B(s00_AXI_ARADDR
notech_mux2 i_141428(.S(n_6223), .A(s00_AXI_BIZWADDR[15]), .B(s00_AXI_ARADDR
[15]), .Z(n_6308));
notech_reg bit_bang_reg_5(.CP(n_8495), .D(n_4777), .CD(n_8183), .Q(bit_bang
[5]));
notech_mux2 i_7247(.S(n_5352), .A(bit_bang[5]), .B(n_7214), .Z(n_4777)
);
notech_mux2 i_131427(.S(n_6223), .A(s00_AXI_AWADDR[14]), .B(s00_AXI_ARADDR
notech_mux2 i_131427(.S(n_6223), .A(s00_AXI_BIZWADDR[14]), .B(s00_AXI_ARADDR
[14]), .Z(n_6302));
notech_reg bit_bang_reg_6(.CP(n_8495), .D(n_4783), .CD(n_8182), .Q(bit_bang
[6]));
notech_mux2 i_7255(.S(n_5352), .A(bit_bang[6]), .B(n_7220), .Z(n_4783)
);
notech_mux2 i_121426(.S(n_6223), .A(s00_AXI_AWADDR[13]), .B(s00_AXI_ARADDR
notech_mux2 i_121426(.S(n_6223), .A(s00_AXI_BIZWADDR[13]), .B(s00_AXI_ARADDR
[13]), .Z(n_6296));
notech_reg bit_bang_reg_7(.CP(n_8495), .D(n_4789), .CD(n_8182), .Q(bit_bang
[7]));
notech_mux2 i_7263(.S(n_5352), .A(bit_bang[7]), .B(n_7226), .Z(n_4789)
);
notech_mux2 i_111425(.S(n_6223), .A(s00_AXI_AWADDR[12]), .B(s00_AXI_ARADDR
notech_mux2 i_111425(.S(n_6223), .A(s00_AXI_BIZWADDR[12]), .B(s00_AXI_ARADDR
[12]), .Z(n_6290));
notech_reg bit_bang_reg_8(.CP(n_8495), .D(n_4795), .CD(n_8182), .Q(bit_bang
[8]));
notech_mux2 i_7271(.S(n_5352), .A(bit_bang[8]), .B(n_7232), .Z(n_4795)
);
notech_mux2 i_101424(.S(n_6223), .A(s00_AXI_AWADDR[11]), .B(s00_AXI_ARADDR
notech_mux2 i_101424(.S(n_6223), .A(s00_AXI_BIZWADDR[11]), .B(s00_AXI_ARADDR
[11]), .Z(n_6284));
notech_reg bit_bang_shift_reg_0(.CP(n_8495), .D(n_4801), .CD(n_8182), .Q
(bit_bang_shift[0]));
notech_mux2 i_7279(.S(n_546), .A(spi_miso), .B(bit_bang_shift[0]), .Z(n_4801
));
notech_mux2 i_91423(.S(n_6223), .A(s00_AXI_AWADDR[10]), .B(s00_AXI_ARADDR
notech_mux2 i_91423(.S(n_6223), .A(s00_AXI_BIZWADDR[10]), .B(s00_AXI_ARADDR
[10]), .Z(n_6278));
notech_reg bit_bang_shift_reg_1(.CP(n_8495), .D(n_4807), .CD(n_8182), .Q
(bit_bang_shift[1]));
notech_mux2 i_7287(.S(n_546), .A(bit_bang_shift[0]), .B(bit_bang_shift[1
]), .Z(n_4807));
notech_mux2 i_81422(.S(n_6223), .A(s00_AXI_AWADDR[9]), .B(s00_AXI_ARADDR
notech_mux2 i_81422(.S(n_6223), .A(s00_AXI_BIZWADDR[9]), .B(s00_AXI_ARADDR
[9]), .Z(n_6272));
notech_reg bit_bang_shift_reg_2(.CP(n_8495), .D(n_4813), .CD(n_8182), .Q
(bit_bang_shift[2]));
notech_mux2 i_7295(.S(n_546), .A(bit_bang_shift[1]), .B(bit_bang_shift[2
]), .Z(n_4813));
notech_mux2 i_71421(.S(n_6223), .A(s00_AXI_AWADDR[8]), .B(s00_AXI_ARADDR
notech_mux2 i_71421(.S(n_6223), .A(s00_AXI_BIZWADDR[8]), .B(s00_AXI_ARADDR
[8]), .Z(n_6266));
notech_reg bit_bang_shift_reg_3(.CP(n_8495), .D(n_4819), .CD(n_8180), .Q
(bit_bang_shift[3]));
notech_mux2 i_7303(.S(n_546), .A(bit_bang_shift[2]), .B(bit_bang_shift[3
]), .Z(n_4819));
notech_mux2 i_61420(.S(n_6223), .A(s00_AXI_AWADDR[7]), .B(s00_AXI_ARADDR
notech_mux2 i_61420(.S(n_6223), .A(s00_AXI_BIZWADDR[7]), .B(s00_AXI_ARADDR
[7]), .Z(n_6260));
notech_reg bit_bang_shift_reg_4(.CP(n_8495), .D(n_4825), .CD(n_8180), .Q
(bit_bang_shift[4]));
notech_mux2 i_7311(.S(n_546), .A(bit_bang_shift[3]), .B(bit_bang_shift[4
]), .Z(n_4825));
notech_mux2 i_5(.S(n_6223), .A(s00_AXI_AWADDR[6]), .B(s00_AXI_ARADDR[6])
notech_mux2 i_5(.S(n_6223), .A(s00_AXI_BIZWADDR[6]), .B(s00_AXI_ARADDR[6])
, .Z(n_6254));
notech_reg bit_bang_shift_reg_5(.CP(n_8495), .D(n_4831), .CD(n_8180), .Q
(bit_bang_shift[5]));
notech_mux2 i_7319(.S(n_546), .A(bit_bang_shift[4]), .B(bit_bang_shift[5
]), .Z(n_4831));
notech_mux2 i_4(.S(n_6223), .A(s00_AXI_AWADDR[5]), .B(s00_AXI_ARADDR[5])
notech_mux2 i_4(.S(n_6223), .A(s00_AXI_BIZWADDR[5]), .B(s00_AXI_ARADDR[5])
, .Z(n_6248));
notech_reg bit_bang_shift_reg_6(.CP(n_8495), .D(n_4837), .CD(n_8180), .Q
(bit_bang_shift[6]));
notech_mux2 i_7327(.S(n_546), .A(bit_bang_shift[5]), .B(bit_bang_shift[6
]), .Z(n_4837));
notech_mux2 i_3(.S(n_6223), .A(s00_AXI_AWADDR[4]), .B(s00_AXI_ARADDR[4])
notech_mux2 i_3(.S(n_6223), .A(s00_AXI_BIZWADDR[4]), .B(s00_AXI_ARADDR[4])
, .Z(n_6242));
notech_reg bit_bang_shift_reg_7(.CP(n_8495), .D(n_4843), .CD(n_8180), .Q
(bit_bang_shift[7]));
notech_mux2 i_7335(.S(n_546), .A(bit_bang_shift[6]), .B(bit_bang_shift[7
]), .Z(n_4843));
notech_mux2 i_21419(.S(n_6223), .A(s00_AXI_AWADDR[3]), .B(s00_AXI_ARADDR
notech_mux2 i_21419(.S(n_6223), .A(s00_AXI_BIZWADDR[3]), .B(s00_AXI_ARADDR
[3]), .Z(n_6236));
notech_reg bit_bang_shift_reg_8(.CP(n_8495), .D(n_4849), .CD(n_8180), .Q
(bit_bang_shift[8]));
notech_mux2 i_7343(.S(n_546), .A(bit_bang_shift[7]), .B(bit_bang_shift[8
]), .Z(n_4849));
notech_mux2 i_1(.S(n_6223), .A(s00_AXI_AWADDR[2]), .B(s00_AXI_ARADDR[2])
notech_mux2 i_1(.S(n_6223), .A(s00_AXI_BIZWADDR[2]), .B(s00_AXI_ARADDR[2])
, .Z(n_6230));
notech_reg bit_bang_shift_reg_9(.CP(n_8495), .D(n_4855), .CD(n_8183), .Q
(bit_bang_shift[9]));
15153,7 → 15147,7
notech_inv i_8821(.A(\rdio_spk[0] ), .Z(n_5478));
notech_inv i_8822(.A(n_5293), .Z(n_5479));
notech_inv i_8823(.A(s00_AXI_ARREADY), .Z(n_5480));
notech_inv i_8824(.A(s00_AXI_AWREADY), .Z(n_5481));
notech_inv i_8824(.A(s00_AXI_BIZWREADY), .Z(n_5481));
tiny_spi uspi_0(.rst_i(n_4956), .clk_i(s00_AXI_CLK), .stb_i(n_7233), .we_i
(we_spi_0), .dat_o(dat_o_spi_0), .dat_i(writeio_data), .adr_i({\io_add[5]
, \io_add[4] , \io_add[3] , \io_add[2] }), .MOSI(mosi), .SCLK(sclk
15181,5 → 15175,5
\nbus_108[4] , UNCONNECTED_011, UNCONNECTED_012,
UNCONNECTED_013, \nbus_108[0] }), .inter_do(int_pic), .inter_vector
(ivect), .inter_done(iack));
AWDP_DEC_023767 i_3513(.O0(bit_bang_0), .bit_bang(bit_bang));
BIZWDP_DEC_023767 i_3513(.O0(bit_bang_0), .bit_bang(bit_bang));
endmodule

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