OpenCores
URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

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    /v586
    from Rev 68 to Rev 69
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Rev 68 → Rev 69

/trunk/ucf/TOP_SYS.ucf
1,6 → 1,6
NET "clk100" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
NET "clk100" TNM_NET = clk100_pin;
TIMESPEC TS_clk100_pin = PERIOD clk100_pin 150 MHz HIGH 50%;
TIMESPEC TS_clk100_pin = PERIOD clk100_pin 100 MHz HIGH 50%;
 
NET "RXD" LOC = "C4" | IOSTANDARD = "LVCMOS33" ;
NET "TXD" LOC = "D4" | IOSTANDARD = "LVCMOS33" ;
60,7 → 60,7
NET "gpioB<6>" LOC = "R2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14
NET "gpioB<7>" LOC = "P2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15
 
NET "extA<0>" LOC = "K5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
#NET "extA<0>" LOC = "K5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
#NET "RGB1_Green" LOC = "F13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G
#NET "RGB1_Blue" LOC = "F6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B
#NET "RGB2_Red" LOC = "K6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
246,7 → 246,7
NET "extWEN" LOC = "R11" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN
NET "extLB" LOC = "J15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN
NET "extUB" LOC = "J13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN
#NET "extWAIT" LOC = "T14" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
NET "extWAIT" LOC = "T14" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
 
NET "extDB<0>" LOC = "R12" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0
NET "extDB<1>" LOC = "T11" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1
/trunk/xdc/TOP_SYS.xdc
0,0 → 1,623
 
####################################################################################
# Generated by PlanAhead 14.7 built on 'Fri Sep 27 19:24:36 MDT 2013' by 'xbuild'
####################################################################################
 
 
####################################################################################
# Constraints from file : 'TOP_SYS.ucf'
####################################################################################
 
#Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
set_property PACKAGE_PIN E3 [get_ports clk100]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:1
# The conversion of 'IOSTANDARD' constraint on 'net' object 'clk100' has been applied to the port object 'clk100'.
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
 
# All timing constraint translations are rough conversions, intended to act as a template for further manual refinement. The translations should not be expected to produce semantically identical results to the original ucf. Each xdc timing constraint must be manually inspected and verified to ensure it captures the desired intent
 
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:3
create_clock -name clk100 -period 10.000 [get_ports clk100]
 
set_property PACKAGE_PIN C4 [get_ports RXD]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:5
# The conversion of 'IOSTANDARD' constraint on 'net' object 'RXD' has been applied to the port object 'RXD'.
set_property IOSTANDARD LVCMOS33 [get_ports RXD]
set_property PACKAGE_PIN D4 [get_ports TXD]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:6
# The conversion of 'IOSTANDARD' constraint on 'net' object 'TXD' has been applied to the port object 'TXD'.
set_property IOSTANDARD LVCMOS33 [get_ports TXD]
 
#NET "RXD_B" LOC = "V11" | IOSTANDARD = "LVCMOS33" ;
#NET "TXD_B" LOC = "V15" | IOSTANDARD = "LVCMOS33" ;
 
 
set_property PACKAGE_PIN U9 [get_ports rstn]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:12
# The conversion of 'IOSTANDARD' constraint on 'net' object 'rstn' has been applied to the port object 'rstn'.
set_property IOSTANDARD LVCMOS33 [get_ports rstn]
 
#NET "RTS" LOC = "D3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS
#NET "CTS" LOC = "E5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS
 
## This file is a general .ucf for the Nexys4 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used signals according to the project
 
## Clock signal
#NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
#NET "clk" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%;
## Switches
#NET "sw<0>" LOC = "U9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
#Bank = 34, Pin name = IO_25_34, Sch name = SW1
set_property PACKAGE_PIN U8 [get_ports {gpio_in[0]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:29
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[0]' has been applied to the port object 'gpio_in[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[0]}]
#Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2
set_property PACKAGE_PIN R7 [get_ports {gpio_in[1]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:30
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[1]' has been applied to the port object 'gpio_in[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[1]}]
#Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3
set_property PACKAGE_PIN R6 [get_ports {gpio_in[2]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:31
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[2]' has been applied to the port object 'gpio_in[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[2]}]
#Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4
set_property PACKAGE_PIN R5 [get_ports {gpio_in[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:32
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[3]' has been applied to the port object 'gpio_in[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[3]}]
#Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5
set_property PACKAGE_PIN V7 [get_ports {gpio_in[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:33
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[4]' has been applied to the port object 'gpio_in[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[4]}]
#Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6
set_property PACKAGE_PIN V6 [get_ports {gpio_in[5]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:34
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[5]' has been applied to the port object 'gpio_in[5]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[5]}]
#Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7
set_property PACKAGE_PIN V5 [get_ports {gpio_in[6]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:35
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpio_in[6]' has been applied to the port object 'gpio_in[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_in[6]}]
#NET "gpio_in<7>" LOC = "U4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8
#NET "sw<9>" LOC = "V2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9
#NET "sw<10>" LOC = "U2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10
#NET "sw<11>" LOC = "T3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11
#NET "sw<12>" LOC = "T1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12
#NET "sw<13>" LOC = "R3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13
#NET "sw<14>" LOC = "P3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14
#Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
set_property PACKAGE_PIN P4 [get_ports {gpioA[0]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:43
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[0]' has been applied to the port object 'gpioA[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[0]}]
## LEDs
#NET "dbg1" LOC = "T8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
#NET "dbg2" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
#NET "gpioA<2>" LOC = "R8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
#Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
set_property PACKAGE_PIN T6 [get_ports {gpioA[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:49
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[3]' has been applied to the port object 'gpioA[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[3]}]
#NET "gpioA<4>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4
#Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5
set_property PACKAGE_PIN T4 [get_ports {gpioA[5]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:51
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[5]' has been applied to the port object 'gpioA[5]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[5]}]
#NET "gpioA<6>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
#NET "gpioA<7>" LOC = "U6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
#Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8
set_property PACKAGE_PIN V4 [get_ports {gpioB[0]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:54
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[0]' has been applied to the port object 'gpioB[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[0]}]
#Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
set_property PACKAGE_PIN U3 [get_ports {gpioB[1]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:55
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[1]' has been applied to the port object 'gpioB[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[1]}]
#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10#NET "debug<4>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
set_property PACKAGE_PIN V1 [get_ports {gpioB[2]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:56
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[2]' has been applied to the port object 'gpioB[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[2]}]
#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10#NET "debug<4>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
set_property PACKAGE_PIN R1 [get_ports {gpioB[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:57
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[3]' has been applied to the port object 'gpioB[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[3]}]
#Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12
set_property PACKAGE_PIN P5 [get_ports {gpioB[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:58
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[4]' has been applied to the port object 'gpioB[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[4]}]
#Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13
set_property PACKAGE_PIN U1 [get_ports {gpioB[5]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:59
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[5]' has been applied to the port object 'gpioB[5]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[5]}]
#Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14
set_property PACKAGE_PIN R2 [get_ports {gpioB[6]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:60
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[6]' has been applied to the port object 'gpioB[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[6]}]
#Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15
set_property PACKAGE_PIN P2 [get_ports {gpioB[7]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:61
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioB[7]' has been applied to the port object 'gpioB[7]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioB[7]}]
 
#NET "extA<0>" LOC = "K5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
#NET "RGB1_Green" LOC = "F13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G
#NET "RGB1_Blue" LOC = "F6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B
#NET "RGB2_Red" LOC = "K6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
#NET "RGB2_Green" LOC = "H6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
#NET "RGB2_Blue" LOC = "L16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B
 
## 7 segment display
#NET "seg<0>" LOC = "L3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
#NET "seg<1>" LOC = "N1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
#NET "seg<2>" LOC = "L5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
#NET "seg<3>" LOC = "L4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
#NET "seg<4>" LOC = "K3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
#NET "seg<5>" LOC = "M2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
#NET "seg<6>" LOC = "L6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
 
#NET "dp" LOC = "M4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
 
#NET "an<0>" LOC = "N6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
#NET "an<1>" LOC = "M6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
#NET "an<2>" LOC = "M3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
#NET "an<3>" LOC = "N5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
#NET "an<4>" LOC = "N2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
#NET "an<5>" LOC = "N4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
#NET "an<6>" LOC = "L1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
#NET "an<7>" LOC = "M1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
 
## Buttons
#NET "btnCpuReset" LOC = "C12" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET
#NET "btnC" LOC = "E16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
#NET "btnU" LOC = "F15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU
#NET "btnL" LOC = "T16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL
#NET "btnR" LOC = "R10" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_25_14, Sch name = BTNR
#NET "btnD" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
## Pmod Header JA
#Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1
set_property PACKAGE_PIN B13 [get_ports {gpioA[6]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:99
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[6]' has been applied to the port object 'gpioA[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[6]}]
#Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2
set_property PACKAGE_PIN F14 [get_ports {gpioA[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:100
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[4]' has been applied to the port object 'gpioA[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[4]}]
#Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3
set_property PACKAGE_PIN D17 [get_ports {gpioA[1]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:101
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[1]' has been applied to the port object 'gpioA[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[1]}]
#Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4
set_property PACKAGE_PIN E17 [get_ports {gpioA[2]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:102
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[2]' has been applied to the port object 'gpioA[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[2]}]
#NET "JA<4>" LOC = "G13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_0_15, Sch name = JA7
#NET "JA<5>" LOC = "C17" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8
#NET "JA<6>" LOC = "D18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9
#NET "JA<7>" LOC = "E18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10
 
## Pmod Header JB
#NET "JB<0>" LOC = "G14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1
#NET "JB<1>" LOC = "P15" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2
#NET "JB<2>" LOC = "V11" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3
#NET "JB<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4
#NET "JB<4>" LOC = "K16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_25_15, Sch name = JB7
#NET "JB<5>" LOC = "R16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8
#NET "JB<6>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9
#NET "JB<7>" LOC = "U11" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10
## Pmod Header JC
#NET "JC<0>" LOC = "K2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1
#NET "JC<1>" LOC = "E7" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2
#NET "JC<2>" LOC = "J3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3
#NET "JC<3>" LOC = "J4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4
#NET "JC<4>" LOC = "K1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7
#NET "JC<5>" LOC = "E6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8
#NET "JC<6>" LOC = "J2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9
#NET "JC<7>" LOC = "G6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10
## Pmod Header JD
#NET "JD<0>" LOC = "H4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1
#NET "JD<1>" LOC = "H1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2
#NET "JD<2>" LOC = "G1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3
#NET "JD<3>" LOC = "G3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4
#NET "JD<4>" LOC = "H2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7
#NET "JD<5>" LOC = "G4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8
#NET "JD<6>" LOC = "G2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9
#NET "JD<7>" LOC = "F3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10
## Pmod Header JXADC
#NET "JXADC<0>" LOC = "A13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P
#NET "JXADC<1>" LOC = "A15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P
#NET "JXADC<2>" LOC = "B16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P
#NET "JXADC<3>" LOC = "B18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P
#NET "JXADC<4>" LOC = "A14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N
#NET "JXADC<5>" LOC = "A16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N
#NET "JXADC<6>" LOC = "B17" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N
#NET "JXADC<7>" LOC = "A18" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N
 
## VGA Connector
#NET "vgaRed<0>" LOC = "A3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0
#NET "vgaRed<1>" LOC = "B4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1
#NET "vgaRed<2>" LOC = "C5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2
#NET "vgaRed<3>" LOC = "A4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3
#NET "vgaBlue<0>" LOC = "B7" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0
#NET "vgaBlue<1>" LOC = "C7" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1
#NET "vgaBlue<2>" LOC = "D7" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2
#NET "vgaBlue<3>" LOC = "D8" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3
#NET "vgaGreen<0>" LOC = "C6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0
#NET "vgaGreen<1>" LOC = "A5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1
#NET "vgaGreen<2>" LOC = "B6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2
#NET "vgaGreen<3>" LOC = "A6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3
#NET "Hsync" LOC = "B11" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS
#NET "Vsync" LOC = "B12" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_BVS
 
## Micro SD Connector
#NET "sdReset" LOC = "E2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET
#NET "sdCD" LOC = "A1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
#NET "sdSCK" LOC = "B1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK
#NET "sdCmd" LOC = "C1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD
#NET "sdData<0>" LOC = "C2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
#NET "sdData<1>" LOC = "E1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1
#NET "sdData<2>" LOC = "F1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2
#NET "sdData<3>" LOC = "D2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
 
#NET "sdReset" LOC = "E2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET
#NET "gpioA<1>" LOC = "F1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2
#NET "gpioA<2>" LOC = "E1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1
#NET "sdVdd" LOC = "C1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD
#NET "gpioA<4>" LOC = "B1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK
#NET "sdVss" LOC = "D2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
#NET "gpioA<6>" LOC = "C2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
#Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
set_property PACKAGE_PIN A1 [get_ports {gpioA[7]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:181
# The conversion of 'IOSTANDARD' constraint on 'net' object 'gpioA[7]' has been applied to the port object 'gpioA[7]'.
set_property IOSTANDARD LVCMOS33 [get_ports {gpioA[7]}]
 
 
 
## Accelerometer
#NET "aclMISO" LOC = "D13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO
#NET "aclMOSI" LOC = "B14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI
#NET "aclSCK" LOC = "D15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK
#NET "aclSS" LOC = "C15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN
#NET "aclInt1" LOC = "C16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1
#NET "aclInt2" LOC = "E15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2
 
## Temperature Sensor
#NET "tmpSCL" LOC = "F16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL
#NET "tmpSDA" LOC = "G16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA
#NET "tmpInt" LOC = "D14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT
#NET "tmpCT" LOC = "C14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT
 
## Omnidirectional Microphone
#NET "micClk" LOC = "J5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_25_35, Sch name = M_CLK
#NET "micData" LOC = "H5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA
#NET "micLRSel" LOC = "F5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL
 
## PWM Audio Amplifier
#NET "ampPWM" LOC = "A11" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM
#NET "ampSD" LOC = "D12" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD
 
## USB-RS232 Interface
#NET "RsRx" LOC = "C4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN
#NET "RsTx" LOC = "D4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT
#NET "RsCts" LOC = "D3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS
#NET "RsRts" LOC = "E5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS
 
## USB HID (PS/2)
#NET "PS2Clk" LOC = "F4" | PULLUP | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK
#NET "PS2Data" LOC = "B2" | PULLUP | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA
 
## SMSC Ethernet PHY
#NET "PhyMdc" LOC = "C9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC
#NET "PhyMdio" LOC = "A9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO
#NET "PhyRstn" LOC = "B3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN
#NET "PhyCrs" LOC = "D9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV
#NET "PhyRxErr" LOC = "C10" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR
#NET "PhyRxd<0>" LOC = "D10" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0
#NET "PhyRxd<1>" LOC = "C11" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1
#NET "PhyTxEn" LOC = "B9" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN
#NET "PhyTxd<0>" LOC = "A10" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0
#NET "PhyTxd<1>" LOC = "A8" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1
#NET "PhyClk50Mhz" LOC = "D5" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK
#NET "PhyIntn" LOC = "B8" | IOSTANDARD = "LVCMOS33"; #Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN
 
## Quad SPI Flash
#NET "sdclk" LOC = "E9" ; #Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK
#Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0
set_property PACKAGE_PIN K17 [get_ports sdout]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:234
# The conversion of 'IOSTANDARD' constraint on 'net' object 'sdout' has been applied to the port object 'sdout'.
set_property IOSTANDARD LVCMOS33 [get_ports sdout]
#Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1
set_property PACKAGE_PIN K18 [get_ports sdin]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:235
# The conversion of 'IOSTANDARD' constraint on 'net' object 'sdin' has been applied to the port object 'sdin'.
set_property IOSTANDARD LVCMOS33 [get_ports sdin]
#Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2
set_property PACKAGE_PIN L14 [get_ports sdwp]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:236
# The conversion of 'IOSTANDARD' constraint on 'net' object 'sdwp' has been applied to the port object 'sdwp'.
set_property IOSTANDARD LVCMOS33 [get_ports sdwp]
#Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3
set_property PACKAGE_PIN M14 [get_ports sdhld]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:237
# The conversion of 'IOSTANDARD' constraint on 'net' object 'sdhld' has been applied to the port object 'sdhld'.
set_property IOSTANDARD LVCMOS33 [get_ports sdhld]
#Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN
set_property PACKAGE_PIN L13 [get_ports sdcs]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:238
# The conversion of 'IOSTANDARD' constraint on 'net' object 'sdcs' has been applied to the port object 'sdcs'.
set_property IOSTANDARD LVCMOS33 [get_ports sdcs]
 
## Cellular RAM
#Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:241
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extCLK' has been applied to the port object 'extCLK'.
set_property IOSTANDARD LVCMOS33 [get_ports extCLK]
#Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN
set_property PACKAGE_PIN T13 [get_ports extADV]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:242
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extADV' has been applied to the port object 'extADV'.
set_property IOSTANDARD LVCMOS33 [get_ports extADV]
#Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN
set_property PACKAGE_PIN L18 [get_ports extCSN]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:243
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extCSN' has been applied to the port object 'extCSN'.
set_property IOSTANDARD LVCMOS33 [get_ports extCSN]
#Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE
set_property PACKAGE_PIN J14 [get_ports extCRE]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:244
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extCRE' has been applied to the port object 'extCRE'.
set_property IOSTANDARD LVCMOS33 [get_ports extCRE]
#Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN
set_property PACKAGE_PIN H14 [get_ports extOE]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:245
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extOE' has been applied to the port object 'extOE'.
set_property IOSTANDARD LVCMOS33 [get_ports extOE]
#Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN
set_property PACKAGE_PIN R11 [get_ports extWEN]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:246
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extWEN' has been applied to the port object 'extWEN'.
set_property IOSTANDARD LVCMOS33 [get_ports extWEN]
#Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN
set_property PACKAGE_PIN J15 [get_ports extLB]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:247
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extLB' has been applied to the port object 'extLB'.
set_property IOSTANDARD LVCMOS33 [get_ports extLB]
#Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN
set_property PACKAGE_PIN J13 [get_ports extUB]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:248
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extUB' has been applied to the port object 'extUB'.
set_property IOSTANDARD LVCMOS33 [get_ports extUB]
#Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
set_property PACKAGE_PIN T14 [get_ports extWAIT]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:249
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extWAIT' has been applied to the port object 'extWAIT'.
set_property IOSTANDARD LVCMOS33 [get_ports extWAIT]
 
#Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0
set_property PACKAGE_PIN R12 [get_ports {extDB[0]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:251
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[0]' has been applied to the port object 'extDB[0]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[0]}]
#Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1
set_property PACKAGE_PIN T11 [get_ports {extDB[1]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:252
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[1]' has been applied to the port object 'extDB[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[1]}]
#Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2
set_property PACKAGE_PIN U12 [get_ports {extDB[2]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:253
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[2]' has been applied to the port object 'extDB[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[2]}]
#Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3
set_property PACKAGE_PIN R13 [get_ports {extDB[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:254
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[3]' has been applied to the port object 'extDB[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[3]}]
#Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4
set_property PACKAGE_PIN U18 [get_ports {extDB[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:255
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[4]' has been applied to the port object 'extDB[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[4]}]
#Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5
set_property PACKAGE_PIN R17 [get_ports {extDB[5]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:256
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[5]' has been applied to the port object 'extDB[5]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[5]}]
#Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6
set_property PACKAGE_PIN T18 [get_ports {extDB[6]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:257
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[6]' has been applied to the port object 'extDB[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[6]}]
#Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7
set_property PACKAGE_PIN R18 [get_ports {extDB[7]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:258
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[7]' has been applied to the port object 'extDB[7]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[7]}]
#Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8
set_property PACKAGE_PIN F18 [get_ports {extDB[8]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:259
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[8]' has been applied to the port object 'extDB[8]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[8]}]
#Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9
set_property PACKAGE_PIN G18 [get_ports {extDB[9]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:260
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[9]' has been applied to the port object 'extDB[9]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[9]}]
#Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10
set_property PACKAGE_PIN G17 [get_ports {extDB[10]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:261
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[10]' has been applied to the port object 'extDB[10]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[10]}]
#Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11
set_property PACKAGE_PIN M18 [get_ports {extDB[11]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:262
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[11]' has been applied to the port object 'extDB[11]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[11]}]
#Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12
set_property PACKAGE_PIN M17 [get_ports {extDB[12]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:263
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[12]' has been applied to the port object 'extDB[12]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[12]}]
#Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13
set_property PACKAGE_PIN P18 [get_ports {extDB[13]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:264
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[13]' has been applied to the port object 'extDB[13]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[13]}]
#Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14
set_property PACKAGE_PIN N17 [get_ports {extDB[14]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:265
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[14]' has been applied to the port object 'extDB[14]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[14]}]
#Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15
set_property PACKAGE_PIN P17 [get_ports {extDB[15]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:266
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extDB[15]' has been applied to the port object 'extDB[15]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extDB[15]}]
 
#Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0
set_property PACKAGE_PIN J18 [get_ports {extA[1]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:268
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[1]' has been applied to the port object 'extA[1]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[1]}]
#Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1
set_property PACKAGE_PIN H17 [get_ports {extA[2]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:269
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[2]' has been applied to the port object 'extA[2]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[2]}]
#Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2
set_property PACKAGE_PIN H15 [get_ports {extA[3]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:270
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[3]' has been applied to the port object 'extA[3]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[3]}]
#Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3
set_property PACKAGE_PIN J17 [get_ports {extA[4]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:271
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[4]' has been applied to the port object 'extA[4]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[4]}]
#Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4
set_property PACKAGE_PIN H16 [get_ports {extA[5]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:272
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[5]' has been applied to the port object 'extA[5]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[5]}]
#Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5
set_property PACKAGE_PIN K15 [get_ports {extA[6]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:273
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[6]' has been applied to the port object 'extA[6]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[6]}]
#Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6
set_property PACKAGE_PIN K13 [get_ports {extA[7]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:274
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[7]' has been applied to the port object 'extA[7]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[7]}]
#Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7
set_property PACKAGE_PIN N15 [get_ports {extA[8]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:275
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[8]' has been applied to the port object 'extA[8]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[8]}]
#Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8
set_property PACKAGE_PIN V16 [get_ports {extA[9]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:276
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[9]' has been applied to the port object 'extA[9]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[9]}]
#Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9
set_property PACKAGE_PIN U14 [get_ports {extA[10]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:277
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[10]' has been applied to the port object 'extA[10]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[10]}]
#Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10
set_property PACKAGE_PIN V14 [get_ports {extA[11]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:278
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[11]' has been applied to the port object 'extA[11]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[11]}]
#Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11
set_property PACKAGE_PIN V12 [get_ports {extA[12]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:279
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[12]' has been applied to the port object 'extA[12]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[12]}]
#Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12
set_property PACKAGE_PIN P14 [get_ports {extA[13]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:280
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[13]' has been applied to the port object 'extA[13]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[13]}]
#Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13
set_property PACKAGE_PIN U16 [get_ports {extA[14]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:281
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[14]' has been applied to the port object 'extA[14]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[14]}]
#Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14
set_property PACKAGE_PIN R15 [get_ports {extA[15]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:282
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[15]' has been applied to the port object 'extA[15]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[15]}]
#Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15
set_property PACKAGE_PIN N14 [get_ports {extA[16]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:283
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[16]' has been applied to the port object 'extA[16]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[16]}]
#Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16
set_property PACKAGE_PIN N16 [get_ports {extA[17]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:284
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[17]' has been applied to the port object 'extA[17]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[17]}]
#Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17
set_property PACKAGE_PIN M13 [get_ports {extA[18]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:285
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[18]' has been applied to the port object 'extA[18]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[18]}]
#Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18
set_property PACKAGE_PIN V17 [get_ports {extA[19]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:286
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[19]' has been applied to the port object 'extA[19]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[19]}]
#Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19
set_property PACKAGE_PIN U17 [get_ports {extA[20]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:287
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[20]' has been applied to the port object 'extA[20]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[20]}]
#Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20
set_property PACKAGE_PIN T10 [get_ports {extA[21]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:288
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[21]' has been applied to the port object 'extA[21]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[21]}]
#Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21
set_property PACKAGE_PIN M16 [get_ports {extA[22]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:289
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[22]' has been applied to the port object 'extA[22]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[22]}]
#Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22
set_property PACKAGE_PIN U13 [get_ports {extA[23]}]
# /home/leo/cpu/vault.memo/v10.1/TOP_SYS.ucf:290
# The conversion of 'IOSTANDARD' constraint on 'net' object 'extA[23]' has been applied to the port object 'extA[23]'.
set_property IOSTANDARD LVCMOS33 [get_ports {extA[23]}]
 
# PlanAhead Generated physical constraints
 
set_property PACKAGE_PIN T15 [get_ports extCLK]

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