URL
https://opencores.org/ocsvn/v586/v586/trunk
Subversion Repositories v586
Compare Revisions
- This comparison shows the changes necessary to convert path
/v586
- from Rev 96 to Rev 97
- ↔ Reverse comparison
Rev 96 → Rev 97
/trunk/rtl/TOP_SYS.v
1,6 → 1,3
`define PSRAM |
`define etherlite |
|
module TOP_SYS( |
clk100,rstn,gpio_in, |
// uart |
22,7 → 19,6
PhyTxEn, |
PhyTxd, |
PhyClk50Mhz, |
PhyIntn, |
// tiny spi |
miso, |
mosi, |
30,7 → 26,7
aclInt1, |
aclInt2 |
); |
|
|
input clk100; |
input rstn; |
output TXD; |
53,8 → 49,15
inout [15:0] extDB; |
output [23:0] extA; |
|
|
// ethernet |
output PhyMdc; |
inout PhyMdio; |
inout PhyMdio; |
wire PhyMdio_t; |
wire PhyMdio_o; |
wire PhyMdio_i; |
wire int_net; |
|
output PhyRstn; |
output PhyCrs; |
input PhyRxErr; |
61,12 → 64,19
input [1:0] PhyRxd; |
output PhyTxEn; |
output [1:0] PhyTxd; |
output reg PhyClk50Mhz; |
output reg PhyIntn; |
// ethernet |
wire PhyMdio_t; |
wire PhyMdio_o; |
output reg PhyClk50Mhz; |
|
wire rmii2mac_tx_clk; |
wire rmii2mac_rx_clk; |
wire rmii2mac_crs; |
wire rmii2mac_rx_dv; |
wire [3:0] rmii2mac_rxd; |
wire rmii2mac_col; |
wire rmii2mac_rx_er; |
wire mac2rmii_tx_en; |
wire [3:0] mac2rmii_txd; |
wire mac2rmii_tx_er; |
|
// axi cpu bus |
wire [31:0] M_AXI_AW, M_AXI_AR; |
wire M_AXI_AWVALID,M_AXI_ARVALID,M_AXI_WVALID,M_AXI_RREADY; |
272,12 → 282,11
.axi_RREADY(S_AXI_RREADY_rom) |
); |
|
`ifdef etherlite |
axi_ethernetlite_0 i_etherlite ( |
.s_axi_aclk(clk), |
.s_axi_aresetn(rstn), |
|
.ip2intc_irpt(), |
.ip2intc_irpt(int_net), |
|
.s_axi_awid(4'b000), |
.s_axi_awaddr(S_AXI_AW_net[12:0]), |
310,34 → 319,31
.s_axi_rlast(S_AXI_RLAST_net), |
.s_axi_rvalid(S_AXI_RVALID_net), |
.s_axi_rready(S_AXI_RREADY_net), |
|
.phy_tx_clk(clk), |
.phy_rx_clk(clk), |
.phy_crs(PhyCrs), |
.phy_dv(1'b0), |
.phy_rx_data({PhyRxd,2'b00}), |
.phy_col(1'b0), |
.phy_rx_er(PhyRxErr), |
// to RMII converter |
.phy_tx_clk(rmii2mac_tx_clk), |
.phy_rx_clk(rmii2mac_rx_clk), |
.phy_crs(rmii2mac_crs), |
.phy_dv(rmii2mac_rx_dv), |
.phy_rx_data(rmii2mac_rxd), |
.phy_tx_data(mac2rmii_txd), |
.phy_col(rmii2mac_col), |
.phy_rx_er(rmii2mac_rx_er), |
.phy_tx_en(mac2rmii_tx_en), |
|
//.phy_tx_data(PhyTxd), |
.phy_rst_n(PhyRstn), |
.phy_tx_en(PhyTxEn), |
//.phy_tx_data(PhyTxd), |
.phy_mdio_i(PhyMdio), |
.phy_mdio_i(PhyMdio_i), |
.phy_mdio_o(PhyMdio_o), |
.phy_mdio_t(PhyMdio_t), |
.phy_mdc(PhyMdc) |
); |
assign PhyMdio = (PhyMdio_t) ? 1'bz : PhyMdio_o; |
`endif |
|
`ifndef etherlite |
assign S_AXI_AWREADY_net = 1'b1; |
assign S_AXI_WREADY_net = 1'b1; |
assign S_AXI_ARREADY_net = 1'b1; |
assign S_AXI_RVALID_net = 1'b1; |
assign S_AXI_RLAST_net = 1'b0; |
assign S_AXI_R_net = 32'h0; |
`endif |
|
|
IOBUF i_iobuf_mdio( |
.O(PhyMdio_i), |
.IO(PhyMdio), |
.I(PhyMdio_o), |
.T(PhyMdio_t)); |
|
axi_crossbar_0 i_axi_crossbar_0 ( |
.aclk(clk), |
.aresetn(rstn), |
439,7 → 445,7
.int_pic(int_pic), |
.iack(iack), |
.ivect(ivect), |
.int_bus({2'b0,aclInt2,aclInt1}), |
.int_bus({aclInt2,aclInt1,int_net,1'b0}), |
// gpio |
.gpioA_in(gpioA),.gpioB_in(gpioB), |
.gpioA_out(gpioA_out),.gpioB_out(gpioB_out), |
473,4 → 479,26
.s00_AXI_BREADY(1'b1) |
); |
|
mii_to_rmii_0 mii_to_rmii_i ( |
.rst_n(PhyRstn), |
.ref_clk(PhyClk50Mhz), |
// to/from mac |
.mac2rmii_tx_en(mac2rmii_tx_en), |
.mac2rmii_txd(mac2rmii_txd), |
.mac2rmii_tx_er(mac2rmii_tx_er), |
.rmii2mac_tx_clk(rmii2mac_tx_clk), |
.rmii2mac_rx_clk(rmii2mac_rx_clk), |
.rmii2mac_col(rmii2mac_col), |
.rmii2mac_crs(rmii2mac_crs), |
.rmii2mac_rx_dv(rmii2mac_rx_dv), |
.rmii2mac_rx_er(rmii2mac_rx_er), |
.rmii2mac_rxd(rmii2mac_rxd), |
// external connections |
.phy2rmii_crs_dv(PhyCrs), |
.phy2rmii_rx_er(PhyRxErr), |
.phy2rmii_rxd(PhyRxd), |
.rmii2phy_txd(PhyTxd), |
.rmii2phy_tx_en(PhyTxEn) |
); |
|
endmodule |
/trunk/rtl/periph.v
1,10 → 1,4
|
// Generated by ac_shell v5.17-s013 on Fri May 27 23:26:37 CET 2016. |
|
// Restrictions concerning the use of Ambit BuildGates are covered in the |
// license agreement. Distribution to third party EDA vendors is |
// strictly prohibited. |
|
module AWDP_DEC_023900(O0, bit_bang); |
|
output [8:0] O0; |