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Index: addrmux.vhd
===================================================================
--- addrmux.vhd (nonexistent)
+++ addrmux.vhd (revision 4)
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 16 bit two-way multiplexer
+entity addrmux is
+ port( sel: in STD_LOGIC_VECTOR(1 downto 0);
+ a: in STD_LOGIC_VECTOR(15 downto 0);
+ b: in STD_LOGIC_VECTOR(15 downto 0);
+ s: in STD_LOGIC_VECTOR(15 downto 0);
+ y: out STD_LOGIC_VECTOR(15 downto 0)
+ );
+end addrmux;
+
+architecture comb of addrmux is
+constant ADPC: STD_LOGIC_VECTOR(1 downto 0) := "00"; -- select PC
+constant ADMP: STD_LOGIC_VECTOR(1 downto 0) := "01"; -- select MP
+constant ADSP: STD_LOGIC_VECTOR(1 downto 0) := "10"; -- select SP
+constant ADNP: STD_LOGIC_VECTOR(1 downto 0) := "00"; -- no operation
+begin
+ process(sel,a,b,s)
+ begin
+ case sel is
+ when ADPC => y <= a;
+ when ADMP => y <= b;
+ when ADSP => y <= s;
+ when others => y <= a;
+ end case;
+ end process;
+end comb;
+
+
Index: alu_bin.vhd
===================================================================
--- alu_bin.vhd (nonexistent)
+++ alu_bin.vhd (revision 4)
@@ -0,0 +1,203 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit binary alu
+-- Written by Valerio Venturi
+entity alu_bin is
+ port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation)
+ cin: in STD_LOGIC; -- carry/borrow in
+ vin: in STD_LOGIC; -- overflow in
+ op1: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #1
+ op2: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #2
+ fc: in STD_LOGIC_VECTOR(5 downto 0); -- function code (bit #0 serves as flag to signal an branch negative offset)
+ cf: out STD_LOGIC; -- carry/borrow out
+ zf: out STD_LOGIC; -- zero flag out
+ nf: out STD_LOGIC; -- negative flag out
+ vf: out STD_LOGIC; -- overflow flag out
+ pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation
+ bcd_ol: out STD_LOGIC; -- bcd lsb overflow
+ bcd_oh: out STD_LOGIC; -- bcd msb overflow
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit result out
+ );
+end alu_bin;
+
+architecture comb of alu_bin is
+-- ALU function codes
+constant NOP_A: STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- no operation
+constant SUM_A: STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- sum with carry
+constant SUB_A: STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- subtract with borrow
+constant AND_A: STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- and
+constant OR_A: STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- or
+constant XOR_A: STD_LOGIC_VECTOR(5 downto 0) := "001010"; -- xor
+constant INC_A: STD_LOGIC_VECTOR(5 downto 0) := "001100"; -- increment by 1
+constant DEC_A: STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- decrement by 1
+constant SHL_A: STD_LOGIC_VECTOR(5 downto 0) := "010000"; -- shift left
+constant SHR_A: STD_LOGIC_VECTOR(5 downto 0) := "010010"; -- shift right
+constant ROL_A: STD_LOGIC_VECTOR(5 downto 0) := "010100"; -- rotation left
+constant ROR_A: STD_LOGIC_VECTOR(5 downto 0) := "010110"; -- rotation right
+constant SWC_A: STD_LOGIC_VECTOR(5 downto 0) := "011000"; -- sum without carry (used for indexing and branches)
+constant SWC_N: STD_LOGIC_VECTOR(5 downto 0) := "011001"; -- subtract without borrow (used only by branches with negative offset)
+constant BIT_A: STD_LOGIC_VECTOR(5 downto 0) := "011010"; -- bit test (used by BIT opcode)
+constant DAA_A: STD_LOGIC_VECTOR(5 downto 0) := "011100"; -- decimal adjustement for BCD sum
+constant DAS_A: STD_LOGIC_VECTOR(5 downto 0) := "011110"; -- decimal adjustement for BCD subtract
+constant CMP_A: STD_LOGIC_VECTOR(5 downto 0) := "100000"; -- compare
+constant TSB_A: STD_LOGIC_VECTOR(5 downto 0) := "100010"; -- test and set bit
+constant TRB_A: STD_LOGIC_VECTOR(5 downto 0) := "100100"; -- test and reset bit
+signal op: STD_LOGIC_VECTOR(5 downto 0);
+signal c: STD_LOGIC;
+signal pc_c: STD_LOGIC;
+signal v_add: STD_LOGIC;
+signal v_sub: STD_LOGIC;
+signal bcd_l: STD_LOGIC;
+signal bcd_h: STD_LOGIC;
+signal bcd_lh: STD_LOGIC;
+signal n_op2: STD_LOGIC_VECTOR(7 downto 0);
+signal y: STD_LOGIC_VECTOR(8 downto 0);
+
+begin
+ process(fc)
+ begin
+ case fc is
+ when SWC_A => op <= SWC_A;
+ when SWC_N => op <= SWC_N;
+ when others => op(5 downto 1) <= fc(5 downto 1);
+ op(0) <= '0';
+ end case;
+ end process;
+
+ n_op2 <= (not op2);
+ process(alu_byp,op,op1,op2,n_op2,cin)
+ begin
+ if alu_byp = '1' then
+ y(y'left) <= '0';
+ y(y'left-1 downto y'right) <= op1;
+ else
+ case op is
+ when SUM_A => y <= ('0' & op1) + ('0' & op2) + ("00000000" & cin); -- ADC with carry in
+ when SUB_A => y <= ('0' & op1) + ('0' & n_op2) + ("00000000" & cin); -- SBC with borrow in
+ when BIT_A => y <= ('0' & op1) and ('0' & op2); -- BIT test
+ when AND_A => y <= ('0' & op1) and ('0' & op2); -- AND
+ when OR_A => y <= ('0' & op1) or ('0' & op2); -- OR
+ when XOR_A => y <= ('0' & op1) xor ('0' & op2); -- XOR
+ when INC_A => y <= op1 + "000000001"; -- INC
+ when DEC_A => y <= op1 - "000000001"; -- DEC
+ when SHL_A => y(8 downto 1) <= op1; y(0) <= '0'; -- ASL
+ when SHR_A => y <= "00" & op1(op1'left downto op1'right+1); -- LSR
+ when ROL_A => y(8 downto 1) <= op1; y(0) <= cin; -- ROL
+ when ROR_A => y <= '0' & cin & op1(op1'left downto op1'right+1); -- ROR
+ when SWC_A => y <= ('0' & op1) + ('0' & op2); -- ADD without carry in
+ when SWC_N => y <= ('0' & op1) - ('0' & (0 - op2)); -- SUB two complement without borrow in
+ when DAA_A => y <= ('0' & op1) + ('0' & op2); -- ADD without carry in (used for DAA decimal adjustement)
+ when DAS_A => y <= ('0' & op1) - ('0' & op2); -- SUB without borrow in (used for DAS decimal adjustement)
+ when CMP_A => y <= ('1' & op1) - ('0' & op2); -- SBC without borrow in (used for compare)
+ when TSB_A => y <= ('0' & op1) or ('0' & op2); -- TSB
+ when TRB_A => y <= ('0' & not op1) and ('0' & op2); -- TRB
+ when others => y(y'left) <= '0'; y(y'left-1 downto y'right) <= op1; -- NOP
+ end case;
+ end if;
+ end process;
+
+
+ -- flag "C" carry/borrow logic
+ process(op,op1,y,cin)
+ begin
+ case op is
+ when SUM_A => c <= y(y'left);
+ pc_c <= '0';
+ when SUB_A => c <= y(y'left);
+ pc_c <= '0';
+ when SWC_A => pc_c <= y(y'left);
+ c <= cin;
+ when SWC_N => pc_c <= not y(y'left);
+ c <= cin;
+ when SHL_A => c <= y(y'left);
+ pc_c <= '0';
+ when SHR_A => c <= op1(op1'right);
+ pc_c <= '0';
+ when ROL_A => c <= y(y'left);
+ pc_c <= '0';
+ when ROR_A => c <= op1(op1'right);
+ pc_c <= '0';
+ when DAA_A => c <= y(y'left);
+ pc_c <= '0';
+ when DAS_A => c <= cin;
+ pc_c <= '0';
+ when BIT_A => c <= cin;
+ pc_c <= '0';
+ when CMP_A => c <= y(y'left);
+ pc_c <= '0';
+ when others => c <= cin;
+ pc_c <= '0';
+ end case;
+ end process;
+
+ -- flag "V" overflow logic
+ v_add <= (y(7) xor op1(7)) and not (op1(7) xor op2(7));
+ v_sub <= (y(7) xor op1(7)) and (op1(7) xor op2(7));
+ process(op,op2,v_add,v_sub,vin)
+ begin
+ case op is
+ when SUM_A => vf <= v_add;
+ when SUB_A => vf <= v_sub;
+ when BIT_A => vf <= op2(op2'left-1);
+ when others => vf <= vin;
+ end case;
+ end process;
+
+ -- flag "N" negative result logic
+ process(op,op2,y)
+ begin
+ case op is
+ when BIT_A => nf <= op2(op2'left);
+ when others => nf <= y(y'left-1);
+ end case;
+ end process;
+
+ -- flag "Z" zero result logic (always set with zero results)
+ zf <= '1' when y(y'left-1 downto y'right) = "00000000" else '0';
+
+ -- bcd adjustement detection
+ process(y)
+ begin
+ case y(3 downto 0) is
+ when "1010" => bcd_l <= '1'; -- 0xA
+ when "1011" => bcd_l <= '1'; -- 0xB
+ when "1100" => bcd_l <= '1'; -- 0xC
+ when "1101" => bcd_l <= '1'; -- 0xD
+ when "1110" => bcd_l <= '1'; -- 0xE
+ when "1111" => bcd_l <= '1'; -- 0xF
+ when others => bcd_l <= '0';
+ end case;
+ case y(7 downto 4) is
+ when "1010" => bcd_h <= '1'; -- 0xA
+ when "1011" => bcd_h <= '1'; -- 0xB
+ when "1100" => bcd_h <= '1'; -- 0xC
+ when "1101" => bcd_h <= '1'; -- 0xD
+ when "1110" => bcd_h <= '1'; -- 0xE
+ when "1111" => bcd_h <= '1'; -- 0xF
+ when others => bcd_h <= '0';
+ end case;
+ end process;
+ process(y)
+ begin
+ case y(7 downto 0) is
+ when "10011010" => bcd_lh <= '1'; -- 0x9A
+ when "10011011" => bcd_lh <= '1'; -- 0x9B
+ when "10011100" => bcd_lh <= '1'; -- 0x9C
+ when "10011101" => bcd_lh <= '1'; -- 0x9D
+ when "10011110" => bcd_lh <= '1'; -- 0x9E
+ when "10011111" => bcd_lh <= '1'; -- 0x9F
+ when others => bcd_lh <= '0';
+ end case;
+ end process;
+
+ bcd_ol <= bcd_l or bcd_lh;
+ bcd_oh <= bcd_h or bcd_lh;
+ cf <= c;
+ pc_cf <= pc_c;
+ dout <= y(y'left-1 downto y'right);
+end comb;
+
+
Index: ar.vhd
===================================================================
--- ar.vhd (nonexistent)
+++ ar.vhd (revision 4)
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit accumulator register "A"
+entity ar is
+ port( clk: in STD_LOGIC;
+ ld: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end ar;
+
+architecture rtl of ar is
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if ld = '1' then
+ reg <= din;
+ else
+ reg <= reg;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: bcd_reg.vhd
===================================================================
--- bcd_reg.vhd (nonexistent)
+++ bcd_reg.vhd (revision 4)
@@ -0,0 +1,47 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- BCD register
+entity bcd_reg is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ en: in STD_LOGIC;
+ bcd_sl: in STD_LOGIC;
+ bcd_sh: in STD_LOGIC;
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end bcd_reg;
+
+architecture rtl of bcd_reg is
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if clr = '1' or en = '0' then
+ reg <= (others => '0');
+ else
+ if bcd_sl = '1' then
+ reg(3 downto 0) <= "0110"; -- loads 0x6 to lsb
+ else
+ reg(3 downto 0) <= reg(3 downto 0);
+ end if;
+ if bcd_sh = '1' then
+ reg(7 downto 4) <= "0110"; -- loads 0x6 to msb
+ else
+ reg(7 downto 4) <= reg(7 downto 4);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: branch.vhd
===================================================================
--- branch.vhd (nonexistent)
+++ branch.vhd (revision 4)
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- branch resolving logic
+entity branch is
+ port( op: in STD_LOGIC_VECTOR(3 downto 0);
+ n: in STD_LOGIC;
+ v: in STD_LOGIC;
+ z: in STD_LOGIC;
+ c: in STD_LOGIC;
+ bres: out STD_LOGIC
+ );
+end branch;
+
+architecture comb of branch is
+begin
+ process(op,n,v,z,c)
+ begin
+ case op is
+ when "1000" => bres <= '1'; -- BRA
+ when "0001" => bres <= not n; -- BPL
+ when "0011" => bres <= n; -- BMI
+ when "0101" => bres <= not v; -- BVC
+ when "0111" => bres <= v; -- BVS
+ when "1111" => bres <= z; -- BEQ
+ when "1101" => bres <= not z; -- BNE
+ when "1001" => bres <= not c; -- BCC
+ when "1011" => bres <= c; -- BCS
+ when others => bres <= '0';
+ end case;
+ end process;
+end comb;
+
+
Index: cpu_decoder.vhd
===================================================================
--- cpu_decoder.vhd (nonexistent)
+++ cpu_decoder.vhd (revision 4)
@@ -0,0 +1,267 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- Written by Valerio Venturi
+-- CPU decoder
+entity cpu_decoder is
+ port( s: in STD_LOGIC;
+ w: in STD_LOGIC;
+ rs: in STD_LOGIC_VECTOR(15 downto 0);
+ y0: out STD_LOGIC;
+ y1: out STD_LOGIC;
+ y2: out STD_LOGIC;
+ y3: out STD_LOGIC;
+ y4: out STD_LOGIC;
+ y5: out STD_LOGIC;
+ y6: out STD_LOGIC;
+ y7: out STD_LOGIC;
+ y8: out STD_LOGIC;
+ y9: out STD_LOGIC;
+ y10: out STD_LOGIC;
+ y11: out STD_LOGIC;
+ y12: out STD_LOGIC;
+ y13: out STD_LOGIC;
+ y14: out STD_LOGIC;
+ y15: out STD_LOGIC;
+ y16: out STD_LOGIC;
+ y17: out STD_LOGIC;
+ y18: out STD_LOGIC;
+ y19: out STD_LOGIC;
+ y20: out STD_LOGIC;
+ y21: out STD_LOGIC;
+ y22: out STD_LOGIC;
+ y23: out STD_LOGIC;
+ y24: out STD_LOGIC;
+ y25: out STD_LOGIC;
+ y26: out STD_LOGIC;
+ y27: out STD_LOGIC;
+ y28: out STD_LOGIC;
+ y29: out STD_LOGIC
+ );
+end cpu_decoder;
+
+architecture comb of cpu_decoder is
+-- internal SRAM address map declaration
+-- bit (4) is external\internal SRAM bank select switch (ext_sram)
+constant SRAM_BANK0: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SRAM BANK #0 0x0000-0x0FFF
+constant SRAM_BANK1: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SRAM BANK #1 0x1000-0x1FFF
+constant SRAM_BANK2: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- SRAM BANK #2 0x2000-0x2FFF
+constant SRAM_BANK3: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- SRAM BANK #3 0x3000-0x3FFF
+constant SRAM_BANK4: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- SRAM BANK #4 0x4000-0x4FFF
+constant SRAM_BANK5: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- SRAM BANK #5 0x5000-0x5FFF
+constant SRAM_BANK6: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- SRAM BANK #6 0x6000-0x6FFF
+constant SRAM_BANK7: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- SRAM BANK #7 0x7000-0x7FFF
+constant SRAM_BANK8: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- SRAM BANK #8 0x8000-0x8FFF
+constant SRAM_BANK9: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- SRAM BANK #9 0x9000-0x9FFF
+constant SRAM_BANK10: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- SRAM BANK #10 0xA000-0xAFFF
+constant SRAM_BANK11: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- SRAM BANK #11 0xB000-0xBFFF
+constant SRAM_BANK13: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- SRAM BANK #12 0xD000-0xDFFF
+constant SRAM_BANK14: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- SRAM BANK #13 0xE000-0xEFFF
+constant SRAM_BANK15: STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- SRAM BANK #14 0xF000-0xFFFF
+
+constant PRA_REG: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000000"; -- PRA 0xC000
+constant PRB_REG: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000001"; -- PRB 0xC001
+constant PRC_REG: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000010"; -- PRC 0xC002
+constant PRD_REG: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000011"; -- PRD 0xC003
+constant DIGIT0: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000100"; -- DIGIT #0 0xC004
+constant DIGIT1: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000101"; -- DIGIT #1 0xC005
+constant DIGIT2: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000110"; -- DIGIT #2 0xC006
+constant DIGIT3: STD_LOGIC_VECTOR(15 downto 0) := "1100000000000111"; -- DIGIT #3 0xC007
+constant DIGIT4: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001000"; -- DIGIT #4 0xC008
+constant DIGIT5: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001001"; -- DIGIT #5 0xC009
+constant DIGIT6: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001010"; -- DIGIT #6 0xC00A
+constant DIGIT7: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001011"; -- DIGIT #7 0xC00B
+constant TIMER1_CLI: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001100"; -- TIMER1_CLI 0xC00C
+constant TIMER2_CLI: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001101"; -- TIMER2_CLI 0xC00D
+constant LCD_DATA: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001110"; -- LCD_DATA 0xC00E
+constant LCD_CTRL: STD_LOGIC_VECTOR(15 downto 0) := "1100000000001111"; -- LCD_CTRL 0xC00F
+constant UART_TX: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010000"; -- UART_TX 0xC010
+constant UART_RX: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010001"; -- UART_RX 0xC011
+constant UART_STS: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010010"; -- UART_STS 0xC012
+constant VGA_PIXEL_WRITE_LSB: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010011"; -- VGA pixel lsb write 0xC013
+constant VGA_PIXEL_WRITE_MSB: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010100"; -- VGA pixel msb write 0xC014
+constant VGA_PIXEL_WRITE_CMD: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010101"; -- VGA pixel write command 0xC015
+constant VGA_PIXEL_READ_LSB: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010110"; -- VGA pixel lsb read 0xC016
+constant VGA_PIXEL_READ_MSB: STD_LOGIC_VECTOR(15 downto 0) := "1100000000010111"; -- VGA pixel msb read 0xC017
+constant VGA_PIXEL_READ_CMD: STD_LOGIC_VECTOR(15 downto 0) := "1100000000011000"; -- VGA pixel read command 0xC018
+constant VGA_ADDR_LOW: STD_LOGIC_VECTOR(15 downto 0) := "1100000000011001"; -- VGA low address (bit 7..0) 0xC019
+constant VGA_ADDR_MID: STD_LOGIC_VECTOR(15 downto 0) := "1100000000011010"; -- VGA middle address (bit 15..8) 0xC01A
+constant VGA_ADDR_HIGH: STD_LOGIC_VECTOR(15 downto 0) := "1100000000011011"; -- VGA high address (bit 19..16) 0xC01B
+constant VGA_STS: STD_LOGIC_VECTOR(15 downto 0) := "1100000000011100"; -- VGA_STS 0xC01C
+
+signal x: STD_LOGIC_VECTOR(28 downto 0);
+signal sram_rs: STD_LOGIC_VECTOR(3 downto 0);
+signal sram: STD_LOGIC;
+
+begin
+ -- SRAM decoder
+ sram_rs(3 downto 0) <= rs(15 downto 12);
+
+ process(w,sram_rs)
+ begin
+ sram <= '1';
+ -- read
+ if w = '1' then
+ case sram_rs is
+ when SRAM_BANK0 => sram <= '0';
+ when SRAM_BANK1 => sram <= '0';
+ when SRAM_BANK2 => sram <= '0';
+ when SRAM_BANK3 => sram <= '0';
+ when SRAM_BANK4 => sram <= '0';
+ when SRAM_BANK5 => sram <= '0';
+ when SRAM_BANK6 => sram <= '0';
+ when SRAM_BANK7 => sram <= '0';
+ when SRAM_BANK8 => sram <= '0';
+ when SRAM_BANK9 => sram <= '0';
+ when SRAM_BANK10 => sram <= '0';
+ when SRAM_BANK11 => sram <= '0';
+ when SRAM_BANK13 => sram <= '0';
+ when SRAM_BANK14 => sram <= '0';
+ when SRAM_BANK15 => sram <= '0';
+ when others => sram <= '1';
+ end case;
+ else
+ -- write
+ case sram_rs is
+ when SRAM_BANK0 => sram <= '0';
+ when SRAM_BANK1 => sram <= '0';
+ when SRAM_BANK2 => sram <= '0';
+ when SRAM_BANK3 => sram <= '0';
+ when SRAM_BANK4 => sram <= '0';
+ when SRAM_BANK5 => sram <= '0';
+ when SRAM_BANK6 => sram <= '0';
+ when SRAM_BANK7 => sram <= '0';
+ when SRAM_BANK8 => sram <= '0';
+ when SRAM_BANK9 => sram <= '0';
+ when SRAM_BANK10 => sram <= '0';
+ when SRAM_BANK11 => sram <= '0';
+ when SRAM_BANK13 => sram <= '0';
+ when SRAM_BANK14 => sram <= '0';
+ when SRAM_BANK15 => sram <= '0';
+ when others => sram <= '1';
+ end case;
+ end if;
+ end process;
+
+ -- I/O decoder
+ process(w,rs)
+ begin
+ x <= (others => '1');
+ -- read
+ if w = '1' then
+ case rs is
+ when PRA_REG => x <= "11111111111111111111111111110";
+ when TIMER1_CLI => x <= "11111111111111111111111110111";
+ when TIMER2_CLI => x <= "11111111111111101111111111111";
+ when LCD_DATA => x <= "11111111111110111111111111111";
+ when UART_RX => x <= "11111111111011111111111111111";
+ when UART_STS => x <= "11111111110111111111111111111";
+ when VGA_PIXEL_READ_LSB => x <= "11111011111111111111111111111";
+ when VGA_PIXEL_READ_MSB => x <= "11110111111111111111111111111";
+ when VGA_PIXEL_READ_CMD => x <= "11101111111111111111111111111";
+ when others => x <= (others => '1');
+ end case;
+ else
+ -- write
+ case rs is
+ when PRB_REG => x <= "11111111111111111111111111101";
+ when PRC_REG => x <= "11111111111111111111111111011";
+ when TIMER1_CLI => x <= "11111111111111111111111110111";
+ when DIGIT0 => x <= "11111111111111111111111101111";
+ when DIGIT1 => x <= "11111111111111111111111011111";
+ when DIGIT2 => x <= "11111111111111111111110111111";
+ when DIGIT3 => x <= "11111111111111111111101111111";
+ when DIGIT4 => x <= "11111111111111111111011111111";
+ when DIGIT5 => x <= "11111111111111111110111111111";
+ when DIGIT6 => x <= "11111111111111111101111111111";
+ when DIGIT7 => x <= "11111111111111111011111111111";
+ when PRD_REG => x <= "11111111111111110111111111111";
+ when LCD_DATA => x <= "11111111111111011111111111111";
+ when LCD_CTRL => x <= "11111111111101111111111111111";
+ when UART_TX => x <= "11111111101111111111111111111";
+ when VGA_PIXEL_WRITE_LSB => x <= "11111111011111111111111111111";
+ when VGA_PIXEL_WRITE_MSB => x <= "11111110111111111111111111111";
+ when VGA_PIXEL_WRITE_CMD => x <= "11111101111111111111111111111";
+ when VGA_ADDR_LOW => x <= "11011111111111111111111111111";
+ when VGA_ADDR_MID => x <= "10111111111111111111111111111";
+ when VGA_ADDR_HIGH => x <= "01111111111111111111111111111";
+ when others => x <= (others => '1');
+ end case;
+ end if;
+ end process;
+
+ process(s,sram,x)
+ begin
+ if s = '1' then
+ y0 <= '1';
+ y1 <= '1';
+ y2 <= '1';
+ y3 <= '1';
+ y4 <= '1';
+ y5 <= '1';
+ y6 <= '1';
+ y7 <= '1';
+ y8 <= '1';
+ y9 <= '1';
+ y10 <= '1';
+ y11 <= '1';
+ y12 <= '1';
+ y13 <= '1';
+ y14 <= '1';
+ y15 <= '1';
+ y16 <= '1';
+ y17 <= '1';
+ y18 <= '1';
+ y19 <= '1';
+ y20 <= '1';
+ y21 <= '1';
+ y22 <= '1';
+ y23 <= '1';
+ y24 <= '1';
+ y25 <= '1';
+ y26 <= '1';
+ y27 <= '1';
+ y28 <= '1';
+ y29 <= '1';
+ else
+ y0 <= sram;
+ y1 <= x(0);
+ y2 <= x(1);
+ y3 <= x(2);
+ y4 <= x(3);
+ y5 <= x(4);
+ y6 <= x(5);
+ y7 <= x(6);
+ y8 <= x(7);
+ y9 <= x(8);
+ y10 <= x(9);
+ y11 <= x(10);
+ y12 <= x(11);
+ y13 <= x(12);
+ y14 <= x(13);
+ y15 <= x(14);
+ y16 <= x(15);
+ y17 <= x(16);
+ y18 <= x(17);
+ y19 <= x(18);
+ y20 <= x(19);
+ y21 <= x(20);
+ y22 <= x(21);
+ y23 <= x(22);
+ y24 <= x(23);
+ y25 <= x(24);
+ y26 <= x(25);
+ y27 <= x(26);
+ y28 <= x(27);
+ y29 <= x(28);
+ end if;
+ end process;
+end comb;
+
+
+
+
+
+
Index: cpufsm.vhd
===================================================================
--- cpufsm.vhd (nonexistent)
+++ cpufsm.vhd (revision 4)
@@ -0,0 +1,281 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- CPU FSM main state machine
+entity cpufsm is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ireq: in STD_LOGIC;
+ branch: in STD_LOGIC;
+ bflag: in STD_LOGIC;
+ aim: in STD_LOGIC;
+ bcarry: in STD_LOGIC;
+ icarry: in STD_LOGIC;
+ p1: in STD_LOGIC_VECTOR(1 downto 0);
+ e_ei: in STD_LOGIC;
+ mc_ei: in STD_LOGIC;
+ addsub: in STD_LOGIC;
+ dec_mode: in STD_LOGIC;
+ fetch: out STD_LOGIC;
+ op_sync: out STD_LOGIC;
+ pci: out STD_LOGIC;
+ pq: out STD_LOGIC_VECTOR(1 downto 0);
+ fb: out STD_LOGIC;
+ od: out STD_LOGIC;
+ mc_nop: out STD_LOGIC
+ );
+end cpufsm;
+
+architecture rtl of cpufsm is
+type states is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
+attribute ENUM_ENCODING:STRING;
+attribute ENUM_ENCODING of states: type is "000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000"; -- one hot encoding for all states
+signal present,nxt:states;
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ present <= present;
+ else
+ present <= nxt;
+ end if;
+ end if;
+ end process;
+
+ process(present,ireq,branch,bflag,bcarry,icarry,p1,e_ei,mc_ei,aim,clr,addsub,dec_mode)
+ begin
+ case present is
+ -- reset
+ when s0 =>
+ fetch <= '0';
+ op_sync <= '0';
+ pci <= '0';
+ pq <= "00";
+ fb <= '1'; -- force BRK
+ od <= '1'; -- clear microcode sequencer
+ mc_nop <= '0';
+ if clr = '1' then
+ nxt <= s0;
+ else
+ nxt <= s2;
+ end if;
+
+ -- fetch opcode
+ when s1 =>
+ pq <= "00";
+ if ireq = '1' then -- if interrupt request
+ od <= '0';
+ fetch <= '0';
+ fb <= '0';
+ pci <= '0'; -- PC doesn't increment
+ op_sync <= '0';
+ mc_nop <= '1'; -- stop microcode execution
+ nxt <= s8; -- goto s8
+ else
+ od <= '1'; -- clear microcode sequencer
+ fetch <= '1'; -- fetch opcode
+ fb <= '0';
+ pci <= '1'; -- PC increment
+ if addsub = '1'then -- if ADD/SUB opcode may require an extra cycle for DAA/DAS adjustement
+ op_sync <= '0';
+ mc_nop <= '0';
+ nxt <= s7; -- goto s7
+ else
+ if e_ei = '1' then -- if end of instruction is reached on fetch
+ mc_nop <= '1';
+ if clr = '1' then -- if reset
+ op_sync <= '0';
+ nxt <= s0; -- goto reset
+ else
+ op_sync <= '1'; -- remain in this state to fetch a new opcode
+ nxt <= s1;
+ end if;
+ else
+ mc_nop <= '0';
+ op_sync <= '0'; -- goto s2
+ nxt <= s2;
+ end if;
+ end if;
+ end if;
+
+ -- wait until end of instruction
+ when s2 =>
+ fetch <= '0';
+ pq <= p1;
+ fb <= '0';
+ od <= '0';
+ if branch = '0' then -- normal execution
+ mc_nop <= '0';
+ pci <= '0';
+ if aim = '1' then -- opcode with indexed mode
+ op_sync <= '0';
+ nxt <= s5;
+ else
+ if mc_ei = '1' then -- if end of instruction is reached
+ if clr = '1' then
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+ else
+ op_sync <= '0';
+ nxt <= s2;
+ end if;
+ end if;
+ else -- branch opcode execution
+ pci <= '1';
+ if bflag = '0' then -- branch not taken
+ mc_nop <= '1';
+ if clr = '1' then
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+ else
+ mc_nop <= '0';
+ op_sync <= '0';
+ nxt <= s3; -- branch taken
+ end if;
+ end if;
+
+ -- branch taken: add branch offset to lsb PC
+ when s3 =>
+ fetch <= '0';
+ pq <= p1;
+ fb <= '0';
+ od <= '0';
+ pci <= '0';
+ if bcarry = '0' then
+ mc_nop <= '1'; -- stops microcode execution to avoid PC msb adjustement
+ if clr = '1' then
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+ else
+ mc_nop <= '0';
+ op_sync <= '0';
+ nxt <= s4;
+ end if;
+
+ -- branch taken: adjust msb PC
+ when s4 =>
+ fetch <= '0';
+ pq <= p1;
+ fb <= '0';
+ od <= '0';
+ mc_nop <= '0';
+ pci <= '0';
+ if clr = '1' then
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+
+ when s5 => -- opcode with absolute indexed mode
+ fetch <= '0';
+ pq <= p1;
+ fb <= '0';
+ od <= '0';
+ pci <= '0';
+ if mc_ei = '1' then -- if end of instruction is reached
+ if icarry = '0' then
+ mc_nop <= '1';
+ if clr = '1' then
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+ else
+ op_sync <= '0';
+ mc_nop <= '0';
+ nxt <= s6;
+ end if;
+ else
+ op_sync <= '0';
+ mc_nop <= '0';
+ nxt <= s5;
+ end if;
+
+ when s6 => -- opcode with absolute indexed mode: add carry to msb PC
+ fetch <= '0';
+ pq <= p1;
+ fb <= '0';
+ od <= '0';
+ pci <= '0';
+ if clr = '1' then
+ mc_nop <= '0';
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ mc_nop <= '1';
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+
+ -- ADD/SUB decimal adjustement extra cycle
+ when s7 =>
+ fetch <= '0';
+ pq <= p1;
+ fb <= '0';
+ od <= '0';
+ pci <= '0';
+ if mc_ei = '1' then
+ if dec_mode = '0' then
+ mc_nop <= '1';
+ else
+ mc_nop <= '0';
+ end if;
+ if clr = '1' then
+ op_sync <= '0';
+ nxt <= s0;
+ else
+ op_sync <= '1';
+ nxt <= s1;
+ end if;
+ else
+ mc_nop <= '0';
+ op_sync <= '0';
+ nxt <= s7;
+ end if;
+
+ when s8 =>
+ pq <= "00";
+ od <= '1'; -- clear microcode sequencer
+ fetch <= '0';
+ fb <= '1'; -- force load BRK to opcode register
+ pci <= '0'; -- PC doesn't increment
+ op_sync <= '1';
+ mc_nop <= '0';
+ nxt <= s2; -- goto s2
+
+ -- illegal state covering
+ when others =>
+ fetch <= '0';
+ op_sync <= '0';
+ pci <= '0';
+ pq <= "00";
+ fb <= '0';
+ od <= '1';
+ mc_nop <= '0';
+ nxt <= s0;
+
+ end case;
+ end process;
+end rtl;
+
+
Index: data_mux.vhd
===================================================================
--- data_mux.vhd (nonexistent)
+++ data_mux.vhd (revision 4)
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit three-way multiplexer
+entity data_mux is
+ port( s: in STD_LOGIC_VECTOR(3 downto 0);
+ a: in STD_LOGIC_VECTOR(7 downto 0);
+ b: in STD_LOGIC_VECTOR(7 downto 0);
+ c: in STD_LOGIC_VECTOR(7 downto 0);
+ d: in STD_LOGIC_VECTOR(7 downto 0);
+ y: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end data_mux;
+
+architecture comb of data_mux is
+
+begin
+ process(s,a,b,c,d)
+ begin
+ case s is
+ when "1110" => y <= a;
+ when "1101" => y <= b;
+ when "1011" => y <= c;
+ when "0111" => y <= d;
+ when others => y <= a;
+ end case;
+ end process;
+end comb;
+
+
Index: decreg.vhd
===================================================================
--- decreg.vhd (nonexistent)
+++ decreg.vhd (revision 4)
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- register operation decode
+entity decreg is
+ port( r: in STD_LOGIC_VECTOR(3 downto 0);
+ y: out STD_LOGIC_VECTOR(8 downto 0)
+ );
+end decreg;
+
+architecture comb of decreg is
+constant NOP_R: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
+constant ALD_R: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- register A load
+constant XLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- register X load
+constant YLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- register Y load
+constant ZLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- register Z load
+constant OLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- register O load
+constant SLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- register S load lsb
+constant SLM_R: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- register S load msb
+constant SUP_R: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- register S increment by 1
+constant SDW_R: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- register S decrement by 1
+constant SAU_R: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- register A load/register S increment by 1
+constant SXU_R: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- register X load/register S increment by 1
+constant SYU_R: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- register Y load/register S increment by 1
+constant SZU_R: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- register Z load/register S increment by 1
+
+begin
+ process(r)
+ begin
+ case r is
+ when NOP_R => y <= "000000000";
+ when ALD_R => y <= "000000001";
+ when XLD_R => y <= "000000010";
+ when YLD_R => y <= "000000100";
+ when ZLD_R => y <= "000001000";
+ when OLD_R => y <= "000010000";
+ when SLD_R => y <= "000100000";
+ when SLM_R => y <= "001000000";
+ when SUP_R => y <= "010000000";
+ when SDW_R => y <= "100000000";
+ when SAU_R => y <= "010000001";
+ when SXU_R => y <= "010000010";
+ when SYU_R => y <= "010000100";
+ when SZU_R => y <= "010001000";
+ when others => y <= "000000000";
+ end case;
+ end process;
+end comb;
+
+
Index: dmux.vhd
===================================================================
--- dmux.vhd (nonexistent)
+++ dmux.vhd (revision 4)
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit three-way multiplexer
+entity dmux is
+ port( sel: in STD_LOGIC_VECTOR(1 downto 0);
+ a: in STD_LOGIC_VECTOR(7 downto 0);
+ b: in STD_LOGIC_VECTOR(7 downto 0);
+ c: in STD_LOGIC_VECTOR(7 downto 0);
+ y: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end dmux;
+
+architecture comb of dmux is
+constant NOP_D: STD_LOGIC_VECTOR(1 downto 0) := "00";
+constant ORD_D: STD_LOGIC_VECTOR(1 downto 0) := "01";
+constant EXT_D: STD_LOGIC_VECTOR(1 downto 0) := "10";
+constant BCD_D: STD_LOGIC_VECTOR(1 downto 0) := "11";
+begin
+ process(sel,a,b,c)
+ begin
+ case sel is
+ when ORD_D => y <= a;
+ when EXT_D => y <= b;
+ when BCD_D => y <= c;
+ when others => y <= "00000000";
+ end case;
+ end process;
+end comb;
+
+
Index: intlog.vhd
===================================================================
--- intlog.vhd (nonexistent)
+++ intlog.vhd (revision 4)
@@ -0,0 +1,111 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- interrupt request logic
+entity intlog is
+ port( clk: in STD_LOGIC;
+ iack: in STD_LOGIC; -- interrupt acknowledge by microcode
+ r: in STD_LOGIC; -- RESET request
+ n: in STD_LOGIC; -- NMI request
+ i: in STD_LOGIC; -- IRQ request
+ b: in STD_LOGIC; -- BRK opcode
+ s: in STD_LOGIC; -- SO
+ imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ)
+ ioffs: in STD_LOGIC_VECTOR(1 downto 0); -- interrupt servicing offset
+ ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI)
+ vset: out STD_LOGIC; -- SO output
+ voffs: out STD_LOGIC_VECTOR(2 downto 0) -- interrupt vector offset
+ );
+end intlog;
+
+architecture rtl of intlog is
+signal irq_sync: STD_LOGIC_VECTOR(1 downto 0);
+signal nmi_sync: STD_LOGIC_VECTOR(1 downto 0);
+signal res_sync: STD_LOGIC_VECTOR(1 downto 0);
+signal irq_req: STD_LOGIC;
+signal nmi_req: STD_LOGIC;
+signal res_req: STD_LOGIC;
+signal nmi_clr: STD_LOGIC;
+signal res_clr: STD_LOGIC;
+signal irq_brk: STD_LOGIC;
+signal so_sync: STD_LOGIC_VECTOR(1 downto 0);
+
+begin
+ process(clk) -- IRQ/NMI synchronization
+ begin
+ if(clk'event and clk = '1')then
+ res_sync <= res_sync(res_sync'left-1 downto res_sync'right) & r; -- RES sampling
+ nmi_sync <= nmi_sync(nmi_sync'left-1 downto nmi_sync'right) & n; -- NMI sampling
+ irq_sync <= irq_sync(irq_sync'left-1 downto irq_sync'right) & i; -- IRQ sampling
+ if res_clr = '1' then -- RES ack
+ res_req <= '0';
+ else
+ if res_sync = "11" then -- level detection for RES
+ res_req <= '1';
+ else
+ res_req <= res_req;
+ end if;
+ end if;
+ if nmi_clr = '1' then -- NMI ack
+ nmi_req <= '0';
+ else
+ if nmi_sync = "01" then -- edge detection for NMI
+ nmi_req <= '1';
+ else
+ nmi_req <= nmi_req;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(imask, irq_sync)
+ begin
+ if imask = '0' then
+ if irq_sync = "11" then
+ irq_req <= '1';
+ else
+ irq_req <= '0';
+ end if;
+ else
+ irq_req <= '0';
+ end if;
+ end process;
+
+ irq_brk <= irq_req or b; -- IRQ | BRK (opcode)
+
+ -- priority encoder and vector offset generation (vector bits 2..0)
+ voffs <= "100" when res_req = '1' else -- RESET VECTOR: 0xFFFC - 0xFFFD
+ "010" when nmi_req = '1' else -- NMI VECTOR: 0xFFFA - 0xFFFB
+ "110" when irq_brk = '1' else "XXX"; -- IRQ/BRK VECTOR: 0xFFFE - 0xFFFF
+
+ process(iack,ioffs) -- interrupt acknowledge and flags clear
+ begin
+ if iack = '1' then
+ case ioffs is
+ when "10" => res_clr <= '1'; -- RESET acknowledge
+ nmi_clr <= '1'; -- also NMI acknowledge
+ when "01" => nmi_clr <= '1'; -- NMI acknowledge
+ res_clr <= '0';
+ when others => res_clr <= '0';
+ nmi_clr <= '0';
+ end case;
+ else
+ res_clr <= '0';
+ nmi_clr <= '0';
+ end if;
+ end process;
+
+ process(clk) -- SO synchronization
+ begin
+ if(clk'event and clk = '1')then
+ so_sync <= so_sync(so_sync'left-1 downto so_sync'right) & s; -- SO sampling (edge detection)
+ end if;
+ end process;
+
+ ireq <= res_req or nmi_req or irq_req;
+ vset <= '0' when so_sync = "10" else '1';
+end rtl;
+
+
Index: mcpla.vhd
===================================================================
--- mcpla.vhd (nonexistent)
+++ mcpla.vhd (revision 4)
@@ -0,0 +1,1793 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- microcode PLA (NMOS 6502 opcode mask covering)
+-- Written by Valerio Venturi
+-- output fields format:
+-- fields:
+-- RSEL: registers output multiplexer select
+-- REGOP: registers load/increment/decrement etc.
+-- ALUOP: ALU operation
+-- P_OP: register P set/reset bit
+-- MPR: register MP
+-- PCR: register PC
+-- CLI: clear interrupt request
+-- BR: branch opcode
+-- EI: end of microcode sequence
+-- W: read/write control
+-- PD: PC/MP output multiplexer select
+entity mcpla is
+ port( a: in STD_LOGIC_VECTOR(10 downto 0);
+ q: out STD_LOGIC_VECTOR(34 downto 0)
+ );
+end mcpla;
+
+architecture comb of mcpla is
+
+------------------------------------
+-- IMPLIED --
+------------------------------------
+constant NOP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101010000"; -- 0xEA NOP
+
+-- interrupts
+constant BRK_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000000000"; -- 0x00 BRK/IRQ/NMI/RES
+constant BRK_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000000001"; -- 0x00 BRK/IRQ/NMI/RES
+constant BRK_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000000010"; -- 0x00 BRK/IRQ/NMI/RES
+constant BRK_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000000011"; -- 0x00 BRK/IRQ/NMI/RES
+constant BRK_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00000000100"; -- 0x00 BRK/IRQ/NMI/RES
+constant BRK_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00000000101"; -- 0x00 BRK/IRQ/NMI/RES
+constant BRK_OP6: STD_LOGIC_VECTOR(10 downto 0) := "00000000110"; -- 0x00 BRK/IRQ/NMI/RES
+
+-- IMPLIED
+constant CLC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011000000"; -- 0x18 CLC 0->C
+constant SEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111000000"; -- 0x38 SEC 1->C
+constant CLI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011000000"; -- 0x58 CLI 0->I
+constant SEI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111000000"; -- 0x78 SEI 1->I
+constant CLV_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111000000"; -- 0xB8 CLV 0->V
+constant CLD_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011000000"; -- 0xD8 CLD 0->D
+constant SED_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111000000"; -- 0xF8 SED 1->D
+constant TAX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101010000"; -- 0xAA TAX A->X
+constant TAY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101000000"; -- 0xA8 TAY A->Y
+constant TXA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001010000"; -- 0x8A TXA X->A
+constant TYA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011000000"; -- 0x98 TYA Y->A
+constant TXY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011011000"; -- 0x9B TXY X->Y
+constant TYX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111011000"; -- 0xBB TYX Y->X
+constant TXS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011010000"; -- 0x9A TXS X->S
+constant TSX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111010000"; -- 0xBA TSX S->X
+constant TAZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011011000"; -- 0x1B TAZ A->Z
+constant TZA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111011000"; -- 0x3B TZA Z->A
+constant PHP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001000000"; -- 0x08 PHP P->S
+constant PHA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001000000"; -- 0x48 PHA A->S
+constant PHX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011010000"; -- 0xDA PHX X->S
+constant PHY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011010000"; -- 0x5A PHY X->S
+constant PHR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001011000"; -- 0x8B PHR AXY->S
+constant PHR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001011001"; -- 0x8B PHR AXY->S
+constant PHR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001011010"; -- 0x8B PHR AXY->S
+constant PLP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101000000"; -- 0x28 PLP S->P
+constant PLP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101000001"; -- 0x28 PLP S->P
+constant PLA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101000000"; -- 0x68 PLA S->A
+constant PLA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101000001"; -- 0x68 PLA S->A
+constant PLX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111010000"; -- 0xFA PLX S->X
+constant PLX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111010001"; -- 0xFA PLX S->X
+constant PLY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111010000"; -- 0x7A PLY S->Y
+constant PLY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111010001"; -- 0x7A PLY S->Y
+constant PLR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101011000"; -- 0xAB PLR S->YXA
+constant PLR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101011001"; -- 0xAB PLR S->YXA
+constant PLR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101011010"; -- 0xAB PLR S->YXA
+constant PLR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10101011011"; -- 0xAB PLR S->YXA
+constant INC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011010000"; -- 0x1A INC A +1
+constant DEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111010000"; -- 0x3A DEC A -1
+constant INX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101000000"; -- 0xE8 INX X +1
+constant DEX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001010000"; -- 0xCA DEX X -1
+constant INY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001000000"; -- 0xC8 INY Y +1
+constant DEY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001000000"; -- 0x88 DEY Y -1
+constant RTS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100000000"; -- 0x60 RTS
+constant RTS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100000001"; -- 0x60 RTS
+constant RTS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100000010"; -- 0x60 RTS
+constant RTS_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100000011"; -- 0x60 RTS
+constant RTS_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01100000100"; -- 0x60 RTS
+constant RTI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000000000"; -- 0x40 RTI
+constant RTI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000000001"; -- 0x40 RTI
+constant RTI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000000010"; -- 0x40 RTI
+constant RTI_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000000011"; -- 0x40 RTI
+constant RTI_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01000000100"; -- 0x40 RTI
+constant RTI_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01000000101"; -- 0x40 RTI
+constant ASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001010000"; -- 0x0A ASL A
+constant LSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001010000"; -- 0x4A LSR A
+constant ROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101010000"; -- 0x2A ROL A
+constant ROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101010000"; -- 0x6A ROR A
+constant XYX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101011000"; -- 0xEB EXCHANGE X <-> Y
+constant XYX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101011001"; -- 0xEB EXCHANGE X <-> Y
+constant XYX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101011010"; -- 0xEB EXCHANGE X <-> Y
+constant XAX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001011000"; -- 0x0B EXCHANGE A <-> X
+constant XAX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001011001"; -- 0x0B EXCHANGE A <-> X
+constant XAX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001011010"; -- 0x0B EXCHANGE A <-> X
+constant XAY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101011000"; -- 0x2B EXCHANGE A <-> Y
+constant XAY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101011001"; -- 0x2B EXCHANGE A <-> Y
+constant XAY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101011010"; -- 0x2B EXCHANGE A <-> Y
+constant ISP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001011000"; -- 0x4B init SP X -> S lsb; A -> S msb
+constant ISP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001011001"; -- 0x4B init SP X -> S lsb; A -> S msb
+constant TSP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011011000"; -- 0x5B transfer SP S lsb -> X; S msb -> A
+constant TSP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011011001"; -- 0x5B transfer SP S lsb -> X; S msb -> A
+
+------------------------------------
+-- IMMEDIATE --
+------------------------------------
+constant IMLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101001000"; -- 0xA9 LDA #IMM
+constant IMLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100010000"; -- 0xA2 LDX #IMM
+constant IMLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100000000"; -- 0xA0 LDY #IMM
+constant IMADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101001000"; -- 0x69 ADC #IMM
+constant IMADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101001001"; -- 0x69 ADC #IMM
+constant IMSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101001000"; -- 0xE9 SBC #IMM
+constant IMSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101001001"; -- 0xE9 SBC #IMM
+constant IMAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101001000"; -- 0x29 AND #IMM
+constant IMORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001001000"; -- 0x09 ORA #IMM
+constant IMEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001001000"; -- 0x49 EOR #IMM
+constant IMCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001001000"; -- 0xC9 CMP #IMM
+constant IMCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100000000"; -- 0xE0 CPX #IMM
+constant IMCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000000000"; -- 0xC0 CPY #IMM
+constant IMBRK_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001001000"; -- 0x89 BRK #IMM
+
+------------------------------------
+-- ZERO PAGE --
+------------------------------------
+constant ZPLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100101000"; -- 0xA5 LDA ZP
+constant ZPLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100101001"; -- 0xA5 LDA ZP
+constant ZPLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100110000"; -- 0xA6 LDX ZP
+constant ZPLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100110001"; -- 0xA6 LDX ZP
+constant ZPLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100100000"; -- 0xA4 LDY ZP
+constant ZPLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100100001"; -- 0xA4 LDY ZP
+constant ZPSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000101000"; -- 0x85 STA ZP
+constant ZPSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000101001"; -- 0x85 STA ZP
+constant ZPSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000110000"; -- 0x86 STX ZP
+constant ZPSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000110001"; -- 0x86 STX ZP
+constant ZPSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000100000"; -- 0x84 STY ZP
+constant ZPSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000100001"; -- 0x84 STY ZP
+constant ZPSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100100000"; -- 0x64 STZ ZP
+constant ZPSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100100001"; -- 0x64 STZ ZP
+constant ZPADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100101000"; -- 0x65 ADC ZP
+constant ZPADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100101001"; -- 0x65 ADC ZP
+constant ZPADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100101010"; -- 0x65 ADC ZP
+constant ZPSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100101000"; -- 0xE5 SBC ZP
+constant ZPSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100101001"; -- 0xE5 SBC ZP
+constant ZPSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100101010"; -- 0xE5 SBC ZP
+constant ZPCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000101000"; -- 0xC5 CMP ZP
+constant ZPCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000101001"; -- 0xC5 CMP ZP
+constant ZPCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100100000"; -- 0xE4 CPX ZP
+constant ZPCPX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100100001"; -- 0xE4 CPX ZP
+constant ZPCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000100000"; -- 0xC4 CPY ZP
+constant ZPCPY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000100001"; -- 0xC4 CPY ZP
+constant ZPAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100101000"; -- 0x25 AND ZP
+constant ZPAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100101001"; -- 0x25 AND ZP
+constant ZPORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000101000"; -- 0x05 ORA ZP
+constant ZPORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000101001"; -- 0x05 ORA ZP
+constant ZPEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000101000"; -- 0x45 EOR ZP
+constant ZPEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000101001"; -- 0x45 EOR ZP
+constant ZPBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100100000"; -- 0x24 BIT ZP
+constant ZPBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100100001"; -- 0x24 BIT ZP
+constant ZPASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000110000"; -- 0x06 ASL ZP
+constant ZPASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000110001"; -- 0x06 ASL ZP
+constant ZPASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000110010"; -- 0x06 ASL ZP
+constant ZPASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000110011"; -- 0x06 ASL ZP
+constant ZPLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000110000"; -- 0x46 LSR ZP
+constant ZPLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000110001"; -- 0x46 LSR ZP
+constant ZPLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000110010"; -- 0x46 LSR ZP
+constant ZPLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000110011"; -- 0x46 LSR ZP
+constant ZPROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100110000"; -- 0x26 ROL ZP
+constant ZPROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100110001"; -- 0x26 ROL ZP
+constant ZPROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100110010"; -- 0x26 ROL ZP
+constant ZPROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100110011"; -- 0x26 ROL ZP
+constant ZPROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100110000"; -- 0x66 ROR ZP
+constant ZPROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100110001"; -- 0x66 ROR ZP
+constant ZPROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100110010"; -- 0x66 ROR ZP
+constant ZPROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100110011"; -- 0x66 ROR ZP
+constant ZPINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100110000"; -- 0xE6 INC ZP
+constant ZPINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100110001"; -- 0xE6 INC ZP
+constant ZPINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100110010"; -- 0xE6 INC ZP
+constant ZPINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11100110011"; -- 0xE6 INC ZP
+constant ZPDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000110000"; -- 0xC6 DEC ZP
+constant ZPDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000110001"; -- 0xC6 DEC ZP
+constant ZPDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11000110010"; -- 0xC6 DEC ZP
+constant ZPDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11000110011"; -- 0xC6 DEC ZP
+constant ZPTSB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000100000"; -- 0x04 TSB ZP
+constant ZPTSB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000100001"; -- 0x04 TSB ZP
+constant ZPTSB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000100010"; -- 0x04 TSB ZP
+constant ZPTSB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000100011"; -- 0x04 TSB ZP
+constant ZPTSB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00000100100"; -- 0x04 TSB ZP
+constant ZPTRB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010100000"; -- 0x14 TRB ZP
+constant ZPTRB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010100001"; -- 0x14 TRB ZP
+constant ZPTRB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010100010"; -- 0x14 TRB ZP
+constant ZPTRB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010100011"; -- 0x14 TRB ZP
+constant ZPTRB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010100100"; -- 0x14 TRB ZP
+
+------------------------------------
+-- ZERO PAGE,X --
+------------------------------------
+constant ZXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110101000"; -- 0xB5 LDA ZP,X
+constant ZXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110101001"; -- 0xB5 LDA ZP,X
+constant ZXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110101010"; -- 0xB5 LDA ZP,X
+constant ZXLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110100000"; -- 0xB4 LDY ZP,X
+constant ZXLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110100001"; -- 0xB4 LDY ZP,X
+constant ZXLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110100010"; -- 0xB4 LDY ZP,X
+constant ZXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010101000"; -- 0x95 STA ZP,X
+constant ZXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010101001"; -- 0x95 STA ZP,X
+constant ZXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010101010"; -- 0x95 STA ZP,X
+constant ZXSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010100000"; -- 0x94 STY ZP,X
+constant ZXSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010100001"; -- 0x94 STY ZP,X
+constant ZXSTY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010100010"; -- 0x94 STY ZP,X
+constant ZXSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110100000"; -- 0x74 STZ ZP,X
+constant ZXSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110100001"; -- 0x74 STZ ZP,X
+constant ZXSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110100010"; -- 0x74 STZ ZP,X
+constant ZXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110101000"; -- 0x75 ADC ZP,X
+constant ZXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110101001"; -- 0x75 ADC ZP,X
+constant ZXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110101010"; -- 0x75 ADC ZP,X
+constant ZXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110101011"; -- 0x75 ADC ZP,X
+constant ZXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110101000"; -- 0xF5 SBC ZP,X
+constant ZXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110101001"; -- 0xF5 SBC ZP,X
+constant ZXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110101010"; -- 0xF5 SBC ZP,X
+constant ZXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110101011"; -- 0xF5 SBC ZP,X
+constant ZXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010101000"; -- 0xD5 CMP ZP,X
+constant ZXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010101001"; -- 0xD5 CMP ZP,X
+constant ZXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010101010"; -- 0xD5 CMP ZP,X
+constant ZXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110101000"; -- 0x35 AND ZP,X
+constant ZXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110101001"; -- 0x35 AND ZP,X
+constant ZXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110101010"; -- 0x35 AND ZP,X
+constant ZXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010101000"; -- 0x15 ORA ZP,X
+constant ZXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010101001"; -- 0x15 ORA ZP,X
+constant ZXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010101010"; -- 0x15 ORA ZP,X
+constant ZXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010101000"; -- 0x55 EOR ZP,X
+constant ZXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010101001"; -- 0x55 EOR ZP,X
+constant ZXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010101010"; -- 0x55 EOR ZP,X
+constant ZXASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010110000"; -- 0x16 ASL ZP,X
+constant ZXASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010110001"; -- 0x16 ASL ZP,X
+constant ZXASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010110010"; -- 0x16 ASL ZP,X
+constant ZXASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010110011"; -- 0x16 ASL ZP,X
+constant ZXASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010110100"; -- 0x16 ASL ZP,X
+constant ZXLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010110000"; -- 0x56 LSR ZP,X
+constant ZXLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010110001"; -- 0x56 LSR ZP,X
+constant ZXLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010110010"; -- 0x56 LSR ZP,X
+constant ZXLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01010110011"; -- 0x56 LSR ZP,X
+constant ZXLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01010110100"; -- 0x56 LSR ZP,X
+constant ZXROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110110000"; -- 0x36 ROL ZP,X
+constant ZXROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110110001"; -- 0x36 ROL ZP,X
+constant ZXROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110110010"; -- 0x36 ROL ZP,X
+constant ZXROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00110110011"; -- 0x36 ROL ZP,X
+constant ZXROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00110110100"; -- 0x36 ROL ZP,X
+constant ZXROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110110000"; -- 0x76 ROR ZP,X
+constant ZXROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110110001"; -- 0x76 ROR ZP,X
+constant ZXROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110110010"; -- 0x76 ROR ZP,X
+constant ZXROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110110011"; -- 0x76 ROR ZP,X
+constant ZXROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01110110100"; -- 0x76 ROR ZP,X
+constant ZXDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010110000"; -- 0xD6 DEC ZP,X
+constant ZXDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010110001"; -- 0xD6 DEC ZP,X
+constant ZXDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010110010"; -- 0xD6 DEC ZP,X
+constant ZXDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11010110011"; -- 0xD6 DEC ZP,X
+constant ZXDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11010110100"; -- 0xD6 DEC ZP,X
+constant ZXINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110110000"; -- 0xF6 INC ZP,X
+constant ZXINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110110001"; -- 0xF6 INC ZP,X
+constant ZXINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110110010"; -- 0xF6 INC ZP,X
+constant ZXINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110110011"; -- 0xF6 INC ZP,X
+constant ZXINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11110110100"; -- 0xF6 INC ZP,X
+constant ZXBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110100000"; -- 0x34 BIT ZP,X
+constant ZXBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110100001"; -- 0x34 BIT ZP,X
+constant ZXBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110100010"; -- 0x34 BIT ZP,X
+
+------------------------------------
+-- ZERO PAGE,Y --
+------------------------------------
+constant ZYLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110110000"; -- 0xB6 LDX ZP,Y
+constant ZYLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110110001"; -- 0xB6 LDX ZP,Y
+constant ZYLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110110010"; -- 0xB6 LDX ZP,Y
+constant ZYSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010110000"; -- 0x96 STX ZP,Y
+constant ZYSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010110001"; -- 0x96 STX ZP,Y
+constant ZYSTX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010110010"; -- 0x96 STX ZP,Y
+
+------------------------------------
+-- INDIRECT --
+------------------------------------
+constant INJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101100000"; -- 0x6C JMP (IND)
+constant INJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101100001"; -- 0x6C JMP (IND)
+constant INJMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101100010"; -- 0x6C JMP (IND)
+constant INJMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101100011"; -- 0x6C JMP (IND)
+
+------------------------------------
+-- INDIRECT,Y --
+------------------------------------
+constant IYLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110001000"; -- 0xB1 LDA (IND_ZP),Y
+constant IYLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110001001"; -- 0xB1 LDA (IND_ZP),Y
+constant IYLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110001010"; -- 0xB1 LDA (IND_ZP),Y
+constant IYLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10110001011"; -- 0xB1 LDA (IND_ZP),Y
+constant IYLDA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "10110001100"; -- 0xB1 LDA (IND_ZP),Y
+constant IYSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010001000"; -- 0x91 STA (IND_ZP),Y
+constant IYSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010001001"; -- 0x91 STA (IND_ZP),Y
+constant IYSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010001010"; -- 0x91 STA (IND_ZP),Y
+constant IYSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10010001011"; -- 0x91 STA (IND_ZP),Y
+constant IYSTA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "10010001100"; -- 0x91 STA (IND_ZP),Y
+constant IYADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110001000"; -- 0x71 ADC (IND_ZP),Y
+constant IYADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110001001"; -- 0x71 ADC (IND_ZP),Y
+constant IYADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110001010"; -- 0x71 ADC (IND_ZP),Y
+constant IYADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01110001011"; -- 0x71 ADC (IND_ZP),Y
+constant IYADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01110001100"; -- 0x71 ADC (IND_ZP),Y
+constant IYADC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01110001101"; -- 0x71 ADC (IND_ZP),Y
+constant IYSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110001000"; -- 0xF1 SBC (IND_ZP),Y
+constant IYSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110001001"; -- 0xF1 SBC (IND_ZP),Y
+constant IYSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110001010"; -- 0xF1 SBC (IND_ZP),Y
+constant IYSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11110001011"; -- 0xF1 SBC (IND_ZP),Y
+constant IYSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11110001100"; -- 0xF1 SBC (IND_ZP),Y
+constant IYSBC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11110001101"; -- 0xF1 SBC (IND_ZP),Y
+constant IYCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010001000"; -- 0xD1 CMP (IND_ZP),Y
+constant IYCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010001001"; -- 0xD1 CMP (IND_ZP),Y
+constant IYCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010001010"; -- 0xD1 CMP (IND_ZP),Y
+constant IYCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11010001011"; -- 0xD1 CMP (IND_ZP),Y
+constant IYCMP_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11010001100"; -- 0xD1 CMP (IND_ZP),Y
+constant IYAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110001000"; -- 0x31 AND (IND_ZP),Y
+constant IYAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110001001"; -- 0x31 AND (IND_ZP),Y
+constant IYAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110001010"; -- 0x31 AND (IND_ZP),Y
+constant IYAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00110001011"; -- 0x31 AND (IND_ZP),Y
+constant IYAND_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00110001100"; -- 0x31 AND (IND_ZP),Y
+constant IYORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010001000"; -- 0x11 ORA (IND_ZP),Y
+constant IYORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010001001"; -- 0x11 ORA (IND_ZP),Y
+constant IYORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010001010"; -- 0x11 ORA (IND_ZP),Y
+constant IYORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00010001011"; -- 0x11 ORA (IND_ZP),Y
+constant IYORA_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00010001100"; -- 0x11 ORA (IND_ZP),Y
+constant IYEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010001000"; -- 0x51 EOR (IND_ZP),Y
+constant IYEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010001001"; -- 0x51 EOR (IND_ZP),Y
+constant IYEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010001010"; -- 0x51 EOR (IND_ZP),Y
+constant IYEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01010001011"; -- 0x51 EOR (IND_ZP),Y
+constant IYEOR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01010001100"; -- 0x51 EOR (IND_ZP),Y
+
+------------------------------------
+-- INDIRECT,X --
+------------------------------------
+constant IXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10100001000"; -- 0xA1 LDA (IND_ZP,X)
+constant IXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10100001001"; -- 0xA1 LDA (IND_ZP,X)
+constant IXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10100001010"; -- 0xA1 LDA (IND_ZP,X)
+constant IXLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10100001011"; -- 0xA1 LDA (IND_ZP,X)
+constant IXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000001000"; -- 0x81 STA (IND_ZP,X)
+constant IXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000001001"; -- 0x81 STA (IND_ZP,X)
+constant IXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000001010"; -- 0x81 STA (IND_ZP,X)
+constant IXSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10000001011"; -- 0x81 STA (IND_ZP,X)
+constant IXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100001000"; -- 0x21 AND (IND_ZP,X)
+constant IXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100001001"; -- 0x21 AND (IND_ZP,X)
+constant IXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100001010"; -- 0x21 AND (IND_ZP,X)
+constant IXAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100001011"; -- 0x21 AND (IND_ZP,X)
+constant IXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00000001000"; -- 0x01 ORA (IND_ZP,X)
+constant IXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00000001001"; -- 0x01 ORA (IND_ZP,X)
+constant IXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00000001010"; -- 0x01 ORA (IND_ZP,X)
+constant IXORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00000001011"; -- 0x01 ORA (IND_ZP,X)
+constant IXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01000001000"; -- 0x41 EOR (IND_ZP,X)
+constant IXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01000001001"; -- 0x41 EOR (IND_ZP,X)
+constant IXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01000001010"; -- 0x41 EOR (IND_ZP,X)
+constant IXEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01000001011"; -- 0x41 EOR (IND_ZP,X)
+constant IXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11000001000"; -- 0xC1 CMP (IND_ZP,X)
+constant IXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11000001001"; -- 0xC1 CMP (IND_ZP,X)
+constant IXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11000001010"; -- 0xC1 CMP (IND_ZP,X)
+constant IXCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11000001011"; -- 0xC1 CMP (IND_ZP,X)
+constant IXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01100001000"; -- 0x61 ADC (IND_ZP,X)
+constant IXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01100001001"; -- 0x61 ADC (IND_ZP,X)
+constant IXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01100001010"; -- 0x61 ADC (IND_ZP,X)
+constant IXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01100001011"; -- 0x61 ADC (IND_ZP,X)
+constant IXADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01100001100"; -- 0x61 ADC (IND_ZP,X)
+constant IXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11100001000"; -- 0xE1 SBC (IND_ZP,X)
+constant IXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11100001001"; -- 0xE1 SBC (IND_ZP,X)
+constant IXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11100001010"; -- 0xE1 SBC (IND_ZP,X)
+constant IXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11100001011"; -- 0xE1 SBC (IND_ZP,X)
+constant IXSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11100001100"; -- 0xE1 SBC (IND_ZP,X)
+constant IXJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111100000"; -- 0x7C JMP (IND,X)
+constant IXJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111100001"; -- 0x7C JMP (IND,X)
+constant IXJMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111100010"; -- 0x7C JMP (IND,X)
+constant IXJMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111100011"; -- 0x7C JMP (IND,X)
+constant IXJMP_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111100100"; -- 0x7C JMP (IND,X)
+constant IXJSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111100000"; -- 0xFC JSR (IND,X)
+constant IXJSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111100001"; -- 0xFC JSR (IND,X)
+constant IXJSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111100010"; -- 0xFC JSR (IND,X)
+constant IXJSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111100011"; -- 0xFC JSR (IND,X)
+constant IXJSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111100100"; -- 0xFC JSR (IND,X)
+constant IXJSR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11111100101"; -- 0xFC JSR (IND,X)
+
+------------------------------------
+-- ABSOLUTE --
+------------------------------------
+constant ABLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101101000"; -- 0xAD LDA ABS
+constant ABLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101101001"; -- 0xAD LDA ABS
+constant ABLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101101010"; -- 0xAD LDA ABS
+constant ABLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101110000"; -- 0xAE LDX ABS
+constant ABLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101110001"; -- 0xAE LDX ABS
+constant ABLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101110010"; -- 0xAE LDX ABS
+constant ABLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10101100000"; -- 0xAC LDY ABS
+constant ABLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10101100001"; -- 0xAC LDY ABS
+constant ABLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10101100010"; -- 0xAC LDY ABS
+constant ABSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001101000"; -- 0x8D STA ABS
+constant ABSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001101001"; -- 0x8D STA ABS
+constant ABSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001101010"; -- 0x8D STA ABS
+constant ABSTX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001110000"; -- 0x8E STX ABS
+constant ABSTX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001110001"; -- 0x8E STX ABS
+constant ABSTX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001110010"; -- 0x8E STX ABS
+constant ABSTY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10001100000"; -- 0x8C STY ABS
+constant ABSTY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10001100001"; -- 0x8C STY ABS
+constant ABSTY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10001100010"; -- 0x8C STY ABS
+constant ABSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011100000"; -- 0x9C STZ ABS
+constant ABSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011100001"; -- 0x9C STZ ABS
+constant ABSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011100010"; -- 0x9C STZ ABS
+constant ABADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101101000"; -- 0x6D ADC ABS
+constant ABADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101101001"; -- 0x6D ADC ABS
+constant ABADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101101010"; -- 0x6D ADC ABS
+constant ABADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101101011"; -- 0x6D ADC ABS
+constant ABSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101101000"; -- 0xED SBC ABS
+constant ABSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101101001"; -- 0xED SBC ABS
+constant ABSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101101010"; -- 0xED SBC ABS
+constant ABSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11101101011"; -- 0xED SBC ABS
+constant ABORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001101000"; -- 0x0D ORA ABS
+constant ABORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001101001"; -- 0x0D ORA ABS
+constant ABORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001101010"; -- 0x0D ORA ABS
+constant ABAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101101000"; -- 0x2D AND ABS
+constant ABAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101101001"; -- 0x2D AND ABS
+constant ABAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101101010"; -- 0x2D AND ABS
+constant ABEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001101000"; -- 0x4D EOR ABS
+constant ABEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001101001"; -- 0x4D EOR ABS
+constant ABEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01001101010"; -- 0x4D EOR ABS
+constant ABCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001101000"; -- 0xCD CMP ABS
+constant ABCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001101001"; -- 0xCD CMP ABS
+constant ABCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001101010"; -- 0xCD CMP ABS
+constant ABCPX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101100000"; -- 0xEC CPX ABS
+constant ABCPX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101100001"; -- 0xEC CPX ABS
+constant ABCPX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101100010"; -- 0xEC CPX ABS
+constant ABCPY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001100000"; -- 0xCC CPY ABS
+constant ABCPY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001100001"; -- 0xCC CPY ABS
+constant ABCPY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001100010"; -- 0xCC CPY ABS
+constant ABJMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001100000"; -- 0x4C JMP ABS
+constant ABJMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001100001"; -- 0x4C JMP ABS
+constant ABJSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00100000000"; -- 0x20 JSR ABS
+constant ABJSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00100000001"; -- 0x20 JSR ABS
+constant ABJSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00100000010"; -- 0x20 JSR ABS
+constant ABJSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00100000011"; -- 0x20 JSR ABS
+constant ABBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101100000"; -- 0x2C BIT ABS
+constant ABBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101100001"; -- 0x2C BIT ABS
+constant ABBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101100010"; -- 0x2C BIT ABS
+constant ABASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001110000"; -- 0x0E ASL ABS
+constant ABASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001110001"; -- 0x0E ASL ABS
+constant ABASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001110010"; -- 0x0E ASL ABS
+constant ABASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00001110011"; -- 0x0E ASL ABS
+constant ABASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00001110100"; -- 0x0E ASL ABS
+constant ABLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01001110000"; -- 0x4E LSR ABS
+constant ABLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01001110001"; -- 0x4E LSR ABS
+constant ABLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01001110010"; -- 0x4E LSR ABS
+constant ABLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01001110011"; -- 0x4E LSR ABS
+constant ABLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01001110100"; -- 0x4E LSR ABS
+constant ABROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00101110000"; -- 0x2E ROL ABS
+constant ABROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00101110001"; -- 0x2E ROL ABS
+constant ABROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00101110010"; -- 0x2E ROL ABS
+constant ABROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00101110011"; -- 0x2E ROL ABS
+constant ABROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00101110100"; -- 0x2E ROL ABS
+constant ABROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01101110000"; -- 0x6E ROR ABS
+constant ABROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01101110001"; -- 0x6E ROR ABS
+constant ABROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01101110010"; -- 0x6E ROR ABS
+constant ABROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01101110011"; -- 0x6E ROR ABS
+constant ABROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01101110100"; -- 0x6E ROR ABS
+constant ABINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11101110000"; -- 0xEE INC ABS
+constant ABINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11101110001"; -- 0xEE INC ABS
+constant ABINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11101110010"; -- 0xEE INC ABS
+constant ABINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11101110011"; -- 0xEE INC ABS
+constant ABINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11101110100"; -- 0xEE INC ABS
+constant ABDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11001110000"; -- 0xCE DEC ABS
+constant ABDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11001110001"; -- 0xCE DEC ABS
+constant ABDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11001110010"; -- 0xCE DEC ABS
+constant ABDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11001110011"; -- 0xCE DEC ABS
+constant ABDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11001110100"; -- 0xCE DEC ABS
+constant ABTSB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00001100000"; -- 0x0C TSB ABS
+constant ABTSB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00001100001"; -- 0x0C TSB ABS
+constant ABTSB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00001100010"; -- 0x0C TSB ABS
+constant ABTSB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00001100011"; -- 0x0C TSB ABS
+constant ABTSB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00001100100"; -- 0x0C TSB ABS
+constant ABTSB_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00001100101"; -- 0x0C TSB ABS
+constant ABTRB_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011100000"; -- 0x1C TRB ABS
+constant ABTRB_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011100001"; -- 0x1C TRB ABS
+constant ABTRB_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011100010"; -- 0x1C TRB ABS
+constant ABTRB_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011100011"; -- 0x1C TRB ABS
+constant ABTRB_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00011100100"; -- 0x1C TRB ABS
+constant ABTRB_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00011100101"; -- 0x1C TRB ABS
+
+------------------------------------
+-- ABSOLUTE,X --
+------------------------------------
+constant AXLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111101000"; -- 0xBD LDA ABS,X
+constant AXLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111101001"; -- 0xBD LDA ABS,X
+constant AXLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111101010"; -- 0xBD LDA ABS,X
+constant AXLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111101011"; -- 0xBD LDA ABS,X
+constant AXLDY_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111100000"; -- 0xBC LDY ABS,X
+constant AXLDY_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111100001"; -- 0xBC LDY ABS,X
+constant AXLDY_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111100010"; -- 0xBC LDY ABS,X
+constant AXLDY_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111100011"; -- 0xBC LDY ABS,X
+constant AXSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011101000"; -- 0x9D STA ABS,X
+constant AXSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011101001"; -- 0x9D STA ABS,X
+constant AXSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011101010"; -- 0x9D STA ABS,X
+constant AXSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011101011"; -- 0x9D STA ABS,X
+constant AXSTZ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011110000"; -- 0x9E STZ ABS,X
+constant AXSTZ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011110001"; -- 0x9E STZ ABS,X
+constant AXSTZ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011110010"; -- 0x9E STZ ABS,X
+constant AXSTZ_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011110011"; -- 0x9E STZ ABS,X
+constant AXADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111101000"; -- 0x7D ADC ABS,X
+constant AXADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111101001"; -- 0x7D ADC ABS,X
+constant AXADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111101010"; -- 0x7D ADC ABS,X
+constant AXADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111101011"; -- 0x7D ADC ABS,X
+constant AXADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111101100"; -- 0x7D ADC ABS,X
+constant AXSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111101000"; -- 0xFD SBC ABS,X
+constant AXSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111101001"; -- 0xFD SBC ABS,X
+constant AXSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111101010"; -- 0xFD SBC ABS,X
+constant AXSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111101011"; -- 0xFD SBC ABS,X
+constant AXSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111101100"; -- 0xFD SBC ABS,X
+constant AXCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011101000"; -- 0xDD CMP ABS,X
+constant AXCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011101001"; -- 0xDD CMP ABS,X
+constant AXCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011101010"; -- 0xDD CMP ABS,X
+constant AXCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011101011"; -- 0xDD CMP ABS,X
+constant AXINC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111110000"; -- 0xFE INC ABS,X
+constant AXINC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111110001"; -- 0xFE INC ABS,X
+constant AXINC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111110010"; -- 0xFE INC ABS,X
+constant AXINC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111110011"; -- 0xFE INC ABS,X
+constant AXINC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111110100"; -- 0xFE INC ABS,X
+constant AXINC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11111110101"; -- 0xFE INC ABS,X
+constant AXDEC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011110000"; -- 0xDE DEC ABS,X
+constant AXDEC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011110001"; -- 0xDE DEC ABS,X
+constant AXDEC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011110010"; -- 0xDE DEC ABS,X
+constant AXDEC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011110011"; -- 0xDE DEC ABS,X
+constant AXDEC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11011110100"; -- 0xDE DEC ABS,X
+constant AXDEC_OP5: STD_LOGIC_VECTOR(10 downto 0) := "11011110101"; -- 0xDE DEC ABS,X
+constant AXASL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011110000"; -- 0x1E ASL ABS,X
+constant AXASL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011110001"; -- 0x1E ASL ABS,X
+constant AXASL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011110010"; -- 0x1E ASL ABS,X
+constant AXASL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011110011"; -- 0x1E ASL ABS,X
+constant AXASL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00011110100"; -- 0x1E ASL ABS,X
+constant AXASL_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00011110101"; -- 0x1E ASL ABS,X
+constant AXLSR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011110000"; -- 0x5E LSR ABS,X
+constant AXLSR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011110001"; -- 0x5E LSR ABS,X
+constant AXLSR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011110010"; -- 0x5E LSR ABS,X
+constant AXLSR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011110011"; -- 0x5E LSR ABS,X
+constant AXLSR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01011110100"; -- 0x5E LSR ABS,X
+constant AXLSR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01011110101"; -- 0x5E LSR ABS,X
+constant AXROL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111110000"; -- 0x3E ROL ABS,X
+constant AXROL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111110001"; -- 0x3E ROL ABS,X
+constant AXROL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111110010"; -- 0x3E ROL ABS,X
+constant AXROL_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111110011"; -- 0x3E ROL ABS,X
+constant AXROL_OP4: STD_LOGIC_VECTOR(10 downto 0) := "00111110100"; -- 0x3E ROL ABS,X
+constant AXROL_OP5: STD_LOGIC_VECTOR(10 downto 0) := "00111110101"; -- 0x3E ROL ABS,X
+constant AXROR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111110000"; -- 0x7E ROR ABS,X
+constant AXROR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111110001"; -- 0x7E ROR ABS,X
+constant AXROR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111110010"; -- 0x7E ROR ABS,X
+constant AXROR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111110011"; -- 0x7E ROR ABS,X
+constant AXROR_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111110100"; -- 0x7E ROR ABS,X
+constant AXROR_OP5: STD_LOGIC_VECTOR(10 downto 0) := "01111110101"; -- 0x7E ROR ABS,X
+constant AXAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111101000"; -- 0x3D AND ABS,X
+constant AXAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111101001"; -- 0x3D AND ABS,X
+constant AXAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111101010"; -- 0x3D AND ABS,X
+constant AXAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111101011"; -- 0x3D AND ABS,X
+constant AXORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011101000"; -- 0x1D ORA ABS,X
+constant AXORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011101001"; -- 0x1D ORA ABS,X
+constant AXORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011101010"; -- 0x1D ORA ABS,X
+constant AXORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011101011"; -- 0x1D ORA ABS,X
+constant AXEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011101000"; -- 0x5D EOR ABS,X
+constant AXEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011101001"; -- 0x5D EOR ABS,X
+constant AXEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011101010"; -- 0x5D EOR ABS,X
+constant AXEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011101011"; -- 0x5D EOR ABS,X
+constant AXBIT_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111100000"; -- 0x3C BIT ABS,X
+constant AXBIT_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111100001"; -- 0x3C BIT ABS,X
+constant AXBIT_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111100010"; -- 0x3C BIT ABS,X
+constant AXBIT_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111100011"; -- 0x3C BIT ABS,X
+
+------------------------------------
+-- ABSOLUTE,Y --
+------------------------------------
+constant AYLDA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111001000"; -- 0xB9 LDA ABS,Y
+constant AYLDA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111001001"; -- 0xB9 LDA ABS,Y
+constant AYLDA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111001010"; -- 0xB9 LDA ABS,Y
+constant AYLDA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111001011"; -- 0xB9 LDA ABS,Y
+constant AYLDX_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10111110000"; -- 0xBE LDX ABS,Y
+constant AYLDX_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10111110001"; -- 0xBE LDX ABS,Y
+constant AYLDX_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10111110010"; -- 0xBE LDX ABS,Y
+constant AYLDX_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10111110011"; -- 0xBE LDX ABS,Y
+constant AYSTA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10011001000"; -- 0x99 STA ABS,Y
+constant AYSTA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10011001001"; -- 0x99 STA ABS,Y
+constant AYSTA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10011001010"; -- 0x99 STA ABS,Y
+constant AYSTA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "10011001011"; -- 0x99 STA ABS,Y
+constant AYADC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01111001000"; -- 0x79 ADC ABS,Y
+constant AYADC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01111001001"; -- 0x79 ADC ABS,Y
+constant AYADC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01111001010"; -- 0x79 ADC ABS,Y
+constant AYADC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01111001011"; -- 0x79 ADC ABS,Y
+constant AYADC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "01111001100"; -- 0x79 ADC ABS,Y
+constant AYSBC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11111001000"; -- 0xF9 SBC ABS,Y
+constant AYSBC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11111001001"; -- 0xF9 SBC ABS,Y
+constant AYSBC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11111001010"; -- 0xF9 SBC ABS,Y
+constant AYSBC_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11111001011"; -- 0xF9 SBC ABS,Y
+constant AYSBC_OP4: STD_LOGIC_VECTOR(10 downto 0) := "11111001100"; -- 0xF9 SBC ABS,Y
+constant AYCMP_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11011001000"; -- 0xD9 CMP ABS,Y
+constant AYCMP_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11011001001"; -- 0xD9 CMP ABS,Y
+constant AYCMP_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11011001010"; -- 0xD9 CMP ABS,Y
+constant AYCMP_OP3: STD_LOGIC_VECTOR(10 downto 0) := "11011001011"; -- 0xD9 CMP ABS,Y
+constant AYORA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00011001000"; -- 0x19 ORA ABS,Y
+constant AYORA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00011001001"; -- 0x19 ORA ABS,Y
+constant AYORA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00011001010"; -- 0x19 ORA ABS,Y
+constant AYORA_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00011001011"; -- 0x19 ORA ABS,Y
+constant AYAND_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00111001000"; -- 0x39 AND ABS,Y
+constant AYAND_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00111001001"; -- 0x39 AND ABS,Y
+constant AYAND_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00111001010"; -- 0x39 AND ABS,Y
+constant AYAND_OP3: STD_LOGIC_VECTOR(10 downto 0) := "00111001011"; -- 0x39 AND ABS,Y
+constant AYEOR_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01011001000"; -- 0x59 EOR ABS,Y
+constant AYEOR_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01011001001"; -- 0x59 EOR ABS,Y
+constant AYEOR_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01011001010"; -- 0x59 EOR ABS,Y
+constant AYEOR_OP3: STD_LOGIC_VECTOR(10 downto 0) := "01011001011"; -- 0x59 EOR ABS,Y
+
+------------------------------------
+-- RELATIVE --
+------------------------------------
+constant BRA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000000000"; -- 0x80 BRA
+constant BRA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000000001"; -- 0x80 BRA
+constant BRA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000000010"; -- 0x80 BRA
+constant BCC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010000000"; -- 0x90 BCC
+constant BCC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010000001"; -- 0x90 BCC
+constant BCC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010000010"; -- 0x90 BCC
+constant BCS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110000000"; -- 0xB0 BCS
+constant BCS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110000001"; -- 0xB0 BCS
+constant BCS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110000010"; -- 0xB0 BCS
+constant BEQ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110000000"; -- 0xF0 BEQ
+constant BEQ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110000001"; -- 0xF0 BEQ
+constant BEQ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110000010"; -- 0xF0 BEQ
+constant BNE_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010000000"; -- 0xD0 BNE
+constant BNE_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010000001"; -- 0xD0 BNE
+constant BNE_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010000010"; -- 0xD0 BNE
+constant BPL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010000000"; -- 0x10 BPL
+constant BPL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010000001"; -- 0x10 BPL
+constant BPL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010000010"; -- 0x10 BPL
+constant BMI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110000000"; -- 0x30 BMI
+constant BMI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110000001"; -- 0x30 BMI
+constant BMI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110000010"; -- 0x30 BMI
+constant BVC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010000000"; -- 0x50 BVC
+constant BVC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010000001"; -- 0x50 BVC
+constant BVC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010000010"; -- 0x50 BVC
+constant BVS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110000000"; -- 0x70 BVS
+constant BVS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110000001"; -- 0x70 BVS
+constant BVS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110000010"; -- 0x70 BVS
+
+-- ALU microcode
+constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- ALU no operation
+constant SUM_A: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- ALU add with carry
+constant SUB_A: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- ALU sub with borrow
+constant AND_A: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- ALU and
+constant OR_A: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- ALU or
+constant XOR_A: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- ALU xor
+constant INC_A: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- ALU increment by 1
+constant DEC_A: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- ALU decrement by 1
+constant SHL_A: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- ALU bit shift left
+constant SHR_A: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- ALU bit shift right
+constant ROL_A: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- ALU bit rotation left
+constant ROR_A: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- ALU bit rotation right
+constant SWC_A: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- ALU add without carry
+constant BIT_A: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- ALU bit test
+constant DAA_A: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- ALU add without carry (used for DAA decimal adjustement)
+constant DAS_A: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- ALU sub without borrow (used for DAA decimal adjustement)
+constant CMP_A: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- SBC without borrow in (used for CMP instruction)
+constant TSB_A: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- test and set bit
+constant TRB_A: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- test and reset bit
+
+-- PCR microcode
+constant NOP_PC: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- PC no operation
+constant LSB_PC: STD_LOGIC_VECTOR(2 downto 0) := "001"; -- PC load lsb
+constant MSB_PC: STD_LOGIC_VECTOR(2 downto 0) := "010"; -- PC load msb
+constant INC_PC: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- PC increment by 1
+constant LOD_PC: STD_LOGIC_VECTOR(2 downto 0) := "100"; -- PC load lsb\msb
+constant ADJ_PC: STD_LOGIC_VECTOR(2 downto 0) := "101"; -- PC msb adjustement (+/- by 1)
+
+-- MPR microcode
+constant NOP_M: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
+constant LSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- load lsb
+constant MSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- load msb
+constant INC_M: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- increment LSB
+constant VEC_M: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- load vector
+constant ZPL_M: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- load ZEROPAGE
+constant ALL_M: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- load all 16 bit register
+constant ICC_M: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- increment MSB with carry
+constant INM_M: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- increment MSB/LSB
+
+-- address multiplexer microcode
+constant ADPC: STD_LOGIC_VECTOR(1 downto 0) := "00"; -- select PC
+constant ADMP: STD_LOGIC_VECTOR(1 downto 0) := "01"; -- select MP
+constant ADSP: STD_LOGIC_VECTOR(1 downto 0) := "10"; -- select MP/SP
+constant ADNP: STD_LOGIC_VECTOR(1 downto 0) := "00"; -- no operation
+
+-- PR microcode
+constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
+constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
+constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
+constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
+constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
+constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
+constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
+constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
+constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
+constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
+constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
+constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
+constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
+constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
+
+-- register operation microcode REGOP
+constant NOP_R: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
+constant ALD_R: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- register A load
+constant XLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- register X load
+constant YLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- register Y load
+constant ZLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- register Z load
+constant OLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- register O load
+constant SLD_R: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- register S load lsb
+constant SLM_R: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- register S load msb
+constant SUP_R: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- register S increment by 1
+constant SDW_R: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- register S decrement by 1
+constant SAU_R: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- register A load/register S increment by 1
+constant SXU_R: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- register X load/register S increment by 1
+constant SYU_R: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- register Y load/register S increment by 1
+constant SZU_R: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- register Z load/register S increment by 1
+
+-- register multiplexer microcode RSEL (ALU operand #1)
+constant EXT_O: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- external data bus
+constant ARD_O: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- register A select
+constant XRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- register X select
+constant YRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- register Y select
+constant SRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- register S lsb select
+constant SRM_O: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- register S msb select
+constant PRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- register P select
+constant PLR_O: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- register PCL select
+constant PHR_O: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- register PCH select
+constant ORD_O: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- register O select
+constant Z00_O: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- select (all zero output)
+constant ZRD_O: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- register Z select (all zero output)
+
+-- data multiplexer microcode DMUX (ALU operand #2)
+constant NOP_D: STD_LOGIC_VECTOR(1 downto 0) := "00";
+constant ORD_D: STD_LOGIC_VECTOR(1 downto 0) := "01";
+constant EXT_D: STD_LOGIC_VECTOR(1 downto 0) := "10";
+constant BCD_D: STD_LOGIC_VECTOR(1 downto 0) := "11";
+
+-- read/write control
+constant RDE: STD_LOGIC_VECTOR(1 downto 0) := "11"; -- data bus read
+constant WRE: STD_LOGIC_VECTOR(1 downto 0) := "10"; -- data bus write (combinatorial mode)
+constant WRL: STD_LOGIC_VECTOR(1 downto 0) := "01"; -- data bus write (registered mode)
+
+begin
+ process(a)
+ begin
+ -- The PLA is arranged like an ROM, there are an address input "a" and an data output "q". The address of PLA is 11 bit wide
+ -- and composed in this way:
+ --
+ -- ---- CPU OPCODE ---- - MPC -
+ -- | | | |
+ -- | | | |
+ -- X--X--X--X--X--X--X--X--Y--Y--Y
+ -- 10-09-08-07-06-05-04-03-02-01-00
+ --
+ -- the bits (10-3) (X field) is formed by CPU instruction opcode
+ -- the bits (2-0) (Y field) is formed by the three bit wide microinstruction program counter (MPC)
+ -- The MPC field is cleared at each opcode fetch by FSM and since it's three bit wide there are
+ -- an maximum of eight microinstructions available per opcode
+ --
+ -- The bits 10-3 of PLA address serves to select the microcode group of a related CPU opcode
+ -- and they are stable for all instruction execution time, instead the remaining three bit 2-0 (MPC field) of PLA address
+ -- increment at each clock in order to address the next microcode instructions.
+ -- microcode assembly:
+ -- Due the particulary pipeline structure of this CPU, all microinstructions have an extra cycle hidden on fetch
+ -- of the next opcode instruction and normally this extra cycle is coded as "NOP" (see the last line "when others =>...").
+ -- However there are some instructions where this extra cycle is used for some functions like decimal adjustments etc of
+ -- ADC and SBC instructions (see DAA and DAS).
+ --
+ -- Microcode fields:
+ --
+ -- DMUX: ALU operand #2 multiplexer
+ -- | AI: effective address is indexed (X or Y)
+ -- | | VP: vector pull
+ -- | | | BR: branch opcode
+ -- | | | | EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction)
+ -- | | | | | W: read/write control
+ -- | | | | | | CLI: clear interrupt request
+ -- | | | | | | | PD: PC/MP address output multiplexer select
+ -- | | | | | | | | PCR: register PC (program counter)
+ -- | | | | | | | | | MPR: register MP (memory pointer)
+ -- | | | | | | | | | | P_OP: register P set/reset bit
+ -- | | | | | | | | | | | ALUOP: ALU operation
+ -- | | | | | | | | | | | | REGOP: registers load/increment/decrement etc.
+ -- | | | | | | | | | | | | | RSEL: registers output multiplexer select
+ -- | | | | | | | | | | | | | |
+ -- | | | | | | | | | | | | | |
+ case a is -- DMUX AI VP BR EI W CLI PD PCR MPR P_OP ALUOP REGOP RSEL
+ ------------------------------------
+ -- IMPLIED --
+ ------------------------------------
+ -- BRK
+ when BRK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- NOPs
+ when BRK_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1
+ when BRK_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1
+ when BRK_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ZRD_O; -- Z->S; SP-1; EI
+ when BRK_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & SDW_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD
+ when BRK_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP
+ when BRK_OP6 => q <= ORD_D &'0'&'1'&'0'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP
+
+ -- NOP
+ when NOP_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI
+
+ -- CLC
+ when CLC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLC_P & NOP_A & NOP_R & EXT_O; -- 0->C; EI
+
+ -- SEC
+ when SEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEC_P & NOP_A & NOP_R & EXT_O; -- 1->C; EI
+
+ -- CLI
+ when CLI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLI_P & NOP_A & NOP_R & EXT_O; -- 0->I; EI
+
+ -- SEI
+ when SEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEI_P & NOP_A & NOP_R & EXT_O; -- 1->I; EI
+
+ -- CLV
+ when CLV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLV_P & NOP_A & NOP_R & EXT_O; -- 0->V; EI
+
+ -- CLD
+ when CLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLD_P & NOP_A & NOP_R & EXT_O; -- 0->D; EI
+
+ -- SED
+ when SED_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & SED_P & NOP_A & NOP_R & EXT_O; -- 1->D; EI
+
+ -- TAX
+ when TAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & ARD_O; -- A->X; EI
+
+ -- TXA
+ when TXA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & XRD_O; -- X->A; EI
+
+ -- TAY
+ when TAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & ARD_O; -- A->Y; EI
+
+ -- TYA
+ when TYA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & YRD_O; -- Y->A; EI
+
+ -- TXY
+ when TXY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & XRD_O; -- X->Y; EI
+
+ -- TYX
+ when TYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & YRD_O; -- Y->X; EI
+
+ -- TAZ
+ when TAZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ZLD_R & ARD_O; -- A->Z; EI
+
+ -- TZA
+ when TZA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & ZRD_O; -- Z->A; EI
+
+ -- TXS
+ when TXS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLD_R & XRD_O; -- X->S; EI
+
+ -- TSX
+ when TSX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & SRD_O; -- S->X; EI
+
+ -- INC A
+ when INC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & ALD_R & ARD_O; -- A+1; EI
+
+ -- DEC A
+ when DEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & ALD_R & ARD_O; -- A-1; EI
+
+ -- INX
+ when INX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & XLD_R & XRD_O; -- X+1; EI
+
+ -- DEX
+ when DEX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & XLD_R & XRD_O; -- X-1; EI
+
+ -- INY
+ when INY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & YLD_R & YRD_O; -- Y+1; EI
+
+ -- DEY
+ when DEY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & YLD_R & YRD_O; -- Y-1; EI
+
+ -- PHP
+ when PHP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PRD_O; -- P->S; SP-1; EI
+
+ -- PHA
+ when PHA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1; EI
+
+ -- PHX
+ when PHX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1; EI
+
+ -- PHY
+ when PHY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- X->S; SP-1; EI
+
+ -- PHR
+ when PHR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1;
+ when PHR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1;
+ when PHR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y->S; SP-1; EI
+
+ -- PLP
+ when PLP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
+ when PLP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & NOP_R & EXT_O; -- S->P; EI
+
+ -- PLA
+ when PLA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
+ when PLA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- S->A; EI
+
+ -- PLX
+ when PLX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
+ when PLX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- S->X; EI
+
+ -- PLY
+ when PLY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
+ when PLY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- S->Y; EI
+
+ -- PLR
+ when PLR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1
+ when PLR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y;
+ when PLR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X;
+ when PLR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & EXT_O; -- S->A; EI
+
+ -- RTI
+ when RTI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; MP=01XX (STACK)
+ when RTI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; MEM->P; SP +1
+ when RTI_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SZU_R & EXT_O; -- S->Z;
+ when RTI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB PC->O; SP +1;
+ when RTI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; SP +1;
+ when RTI_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; MSB->MP; EI
+
+ -- RTS
+ when RTS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1
+ when RTS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O;
+ when RTS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1;
+ when RTS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC
+ when RTS_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI
+
+ -- ASL (A)
+ when ASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & SHL_A & ALD_R & ARD_O; -- A SHIFT LEFT; EI
+
+ -- LSR (A)
+ when LSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & SHR_A & ALD_R & ARD_O; -- A SHIFT RIGHT; EI
+
+ -- ROL (A)
+ when ROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & ROL_A & ALD_R & ARD_O; -- A ROTATE LEFT; EI
+
+ -- ROR (A)
+ when ROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & ROR_A & ALD_R & ARD_O; -- A ROTATE RIGHT; EI
+
+ -- XYX
+ when XYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
+ when XYX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLD_R & YRD_O; -- Y->X;
+ when XYX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLD_R & ORD_O; -- O->Y; EI
+
+ -- XAX
+ when XAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
+ when XAX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLD_R & ARD_O; -- A->X;
+ when XAX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & ORD_O; -- O->A; EI
+
+ -- XAY
+ when XAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & YRD_O; -- Y->O;
+ when XAY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLD_R & ARD_O; -- A->Y;
+ when XAY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & ALD_R & ORD_O; -- O->A; EI
+
+ -- ISP
+ when ISP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLD_R & XRD_O; -- X->S lsb;
+ when ISP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SLM_R & ARD_O; -- A->S msb; EI
+
+ -- TSP
+ when TSP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & SRD_O; -- S lsb ->X;
+ when TSP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & SRM_O; -- S msb ->A; EI
+
+
+ ------------------------------------
+ -- IMMEDIATE --
+ ------------------------------------
+ -- LDA #xx
+ when IMLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MEM->A; PC +1; EI
+
+ -- LDX #xx
+ when IMLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MEM->X; PC +1; EI
+
+ -- LDY #yy
+ when IMLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MEM->Y; PC +1; EI
+
+ -- ADC #xx (immediate)
+ when IMADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; PC +1; EI
+ when IMADC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC #xx (immediate)
+ when IMSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; PC +1; EI
+ when IMSBC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
+
+ -- CMP #xx (immediate)
+ when IMCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI
+
+ -- CPX #xx (immediate)
+ when IMCPX_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI
+
+ -- CPY #xx (immediate)
+ when IMCPY_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI
+
+ -- AND #xx (immediate)
+ when IMAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A AND MEM -> A; PC +1;
+
+ -- ORA #xx (immediate)
+ when IMORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- A OR MEM -> A; PC +1;
+
+ -- EOR #xx (immediate)
+ when IMEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A XOR MEM -> A; PC +1;
+
+ -- BIT #xx (immediate)
+ when IMBRK_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & LDZ_P & BIT_A & NOP_R & ARD_O; -- A AND MEM; PC +1;
+
+
+ ------------------------------------
+ -- ZERO PAGE --
+ ------------------------------------
+ -- LDA $xx (zero page)
+ when ZPLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; PC+1; EI
+
+ -- LDX $xx (zero page)
+ when ZPLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; PC+1; EI
+
+ -- LDY $xx (zero page)
+ when ZPLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; PC+1; EI
+
+ -- STA $xx (zero page)
+ when ZPSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1; EI
+
+ -- STX $xx (zero page)
+ when ZPSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1; EI
+
+ -- STY $xx (zero page)
+ when ZPSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1; EI
+
+ -- STZ $xx (zero page)
+ when ZPSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1; EI
+
+ -- ADC $xx (zero page)
+ when ZPADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
+ when ZPADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC $xx (zero page)
+ when ZPSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
+ when ZPSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
+
+ -- CMP $xx (zeropage)
+ when ZPCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
+
+ -- CPX $xx (zeropage)
+ when ZPCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPCPX_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI
+
+ -- CPY $xx (zeropage)
+ when ZPCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPCPY_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI
+
+ -- AND $xx (zeropage)
+ when ZPAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM; EI
+
+ -- ORA $xx (zeropage)
+ when ZPORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- A = A OR MEM; EI
+
+ -- EOR $xx (zeropage)
+ when ZPEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM; EI
+
+ -- BIT $xx (zero page)
+ when ZPBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPBIT_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & INC_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1; EI
+
+ -- ASL $xx (zero page)
+ when ZPASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
+ when ZPASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- LSR $xx (zero page)
+ when ZPLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
+ when ZPLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- ROL $xx (zero page)
+ when ZPROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
+ when ZPROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- ROR $xx (zero page)
+ when ZPROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
+ when ZPROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- INC $xx (zero page)
+ when ZPINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
+ when ZPINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- DEC $xx (zero page)
+ when ZPDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
+ when ZPDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- TSB $xx (zero page)
+ when ZPTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPTSB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
+ when ZPTSB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O -> O
+ when ZPTSB_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ -- TRB $xx (zero page)
+ when ZPTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when ZPTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
+ when ZPTRB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
+ when ZPTRB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O -> O
+ when ZPTRB_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
+
+ ------------------------------------
+ -- ZERO PAGE,X --
+ ------------------------------------
+ -- LDA $xx,X (zero page indexed)
+ when ZXLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
+ when ZXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
+
+ -- LDY $xx,X (zero page indexed)
+ when ZXLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; EI
+
+ -- STA $xx,X (zero page indexed)
+ when ZXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
+
+ -- STY $xx,X (zero page indexed)
+ when ZXSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; EI
+
+ -- STZ $xx,X (zero page indexed)
+ when ZXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; X->MEM; EI
+
+ -- ADC $xx,X (zero page indexed)
+ when ZXADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
+ when ZXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
+ when ZXADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); EI
+
+ -- SBC $xx,X (zero page indexed)
+ when ZXSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
+ when ZXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
+ when ZXSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); EI
+
+ -- CMP $xx,X (zero page indexed)
+ when ZXCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
+ when ZXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
+ when ZXCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
+
+ -- AND $xx,X (zero page indexed)
+ when ZXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
+ when ZXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
+ when ZXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM; EI
+
+ -- ORA $xx,X (zero page indexed)
+ when ZXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
+ when ZXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
+ when ZXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- A = A OR MEM; EI
+
+ -- EOR $xx,X (zero page indexed)
+ when ZXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
+ when ZXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM; EI
+
+ -- ASL $xx,X (zero page indexed)
+ when ZXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X PC+1;
+ when ZXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
+ when ZXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
+ when ZXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- LSR $xx,X (zero page indexed)
+ when ZXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP
+ when ZXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
+ when ZXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
+ when ZXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- ROL $xx,X (zero page indexed)
+ when ZXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
+ when ZXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
+ when ZXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- ROR $xx,X (zero page indexed)
+ when ZXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
+ when ZXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
+ when ZXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- INC $xx,X (zero page indexed)
+ when ZXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
+ when ZXINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
+ when ZXINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- DEC $xx,X (zero page indexed)
+ when ZXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZXDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
+ when ZXDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
+ when ZXDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
+ when ZXDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- BIT $xx,X (zero page indexed)
+ when ZXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
+ when ZXBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
+ when ZXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A = A AND MEM; EI
+
+ ------------------------------------
+ -- ZERO PAGE,Y --
+ ------------------------------------
+ -- LDX $xx,Y (zero page indexed)
+ when ZYLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZYLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & YRD_O; -- MP+=Y; PC+1;
+ when ZYLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; EI
+
+ -- STX $xx,Y (zero page indexed)
+ when ZYSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
+ when ZYSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & YRD_O; -- MP+=Y; PC+1;
+ when ZYSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; EI
+
+ ------------------------------------
+ -- INDIRECT --
+ ------------------------------------
+ -- JMP ($xxxx) (indirect)
+ when INJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when INJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when INJMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1
+ when INJMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC; O->PC; EI
+
+ ------------------------------------
+ -- INDIRECT,Y --
+ ------------------------------------
+ -- LDA ($xx),Y (zeropage - indirect - indexed)
+ when IYLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYLDA_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- O->MP; (LSB POINTER)
+ when IYLDA_OP4 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
+
+ -- STA ($xx),Y (zeropage - indirect - indexed)
+ when IYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O->MP; (LSB POINTER)
+ when IYSTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
+
+ -- ADC ($xx),Y (zeropage - indirect - indexed)
+ when IYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
+ when IYADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
+ when IYADC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC ($xx),Y (zeropage - indirect - indexed)
+ when IYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
+ when IYSBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
+ when IYSBC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAS); PC +1; EI
+
+ -- CMP ($xx),Y (zeropage - indirect - indexed)
+ when IYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYCMP_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYCMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
+ when IYCMP_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
+
+ -- AND ($xx),Y (zeropage - indirect - indexed)
+ when IYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYAND_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYAND_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYAND_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
+ when IYAND_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A = A AND MEM; EI
+
+ -- ORA ($xx),Y (zeropage - indirect - indexed)
+ when IYORA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYORA_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYORA_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYORA_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
+ when IYORA_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- A = A OR MEM; EI
+
+ -- EOR ($xx),Y (zeropage - indirect - indexed)
+ when IYEOR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
+ when IYEOR_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
+ when IYEOR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
+ when IYEOR_OP3 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
+ when IYEOR_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A = A XOR MEM; EI
+
+ ------------------------------------
+ -- INDIRECT,X --
+ ------------------------------------
+ -- LDA ($xx,X) (zero page - indexed - indirect)
+ when IXLDA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI=1
+
+ -- STA ($xx,X) (zero page - indexed - indirect)
+ when IXSTA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- A->MEM; EI=1
+
+ -- AND ($xx,X) (zero page - indexed - indirect)
+ when IXAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; A=A AND MEM; EI=1
+
+ -- ORA ($xx,X) (zero page - indexed - indirect)
+ when IXORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- MP->MEM; A=A OR MEM; EI=1
+
+ -- EOR ($xx,X) (zero page - indexed - indirect)
+ when IXEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
+
+ -- ADC ($xx,X) (zero page - indexed - indirect)
+ when IXADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
+ when IXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC ($xx,X) (zero page - indexed - indirect)
+ when IXSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
+ when IXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- CMP ($xx,X) (zero page - indexed - indirect)
+ when IXCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
+ when IXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
+ when IXCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
+ when IXCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
+
+ -- JMP ($xxxx,X) (absolute indexed - indirect)
+ when IXJMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when IXJMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when IXJMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
+ when IXJMP_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INM_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when IXJMP_OP4 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
+
+ -- JSR ($xxxx,X) (absolute indexed - indirect)
+ when IXJSR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when IXJSR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1;
+ when IXJSR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1;
+ when IXJSR_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when IXJSR_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INM_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when IXJSR_OP5 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
+
+ ------------------------------------
+ -- ABSOLUTE --
+ ------------------------------------
+ -- LDA $xxxx (absolute)
+ when ABLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; PC+1
+
+ -- LDX $xxxx (absolute)
+ when ABLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; PC+1
+
+ -- LDY $xxxx (absolute)
+ when ABLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; PC+1
+
+ -- STA $xxxx (absolute)
+ when ABSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1
+
+ -- STX $xxxx (absolute)
+ when ABSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1
+
+ -- STY $xxxx (absolute)
+ when ABSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1
+
+ -- STZ $xxxx (absolute)
+ when ABSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1
+
+ -- JMP $xxxx (absolute)
+ when ABJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1
+ when ABJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
+
+ -- JSR $xxxx (absolute)
+ when ABJSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1
+ when ABJSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1;
+ when ABJSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1;
+ when ABJSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI
+
+ -- BIT $xxxx (absolute)
+ when ABBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1
+
+ -- ADC $xxxx (absolute)
+ when ABADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; EI
+ when ABADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC $xxxx (absolute)
+ when ABSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; EI
+ when ABSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
+
+ -- CMP $xxxx (absolute)
+ when ABCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI
+
+ -- CPX $xxxx (absolute)
+ when ABCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABCPX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABCPX_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI
+
+ -- CPY $xxxx (absolute)
+ when ABCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABCPY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABCPY_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-EXT; EI
+
+ -- ORA $xxxx (absolute)
+ when ABORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- A=A OR MEM; EI
+
+ -- AND $xxxx (absolute)
+ when ABAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A=A AND MEM; EI
+
+ -- EOR $xxxx (absolute)
+ when ABEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- A=A XOR MEM; EI
+
+ -- ASL $xxxx (absolute)
+ when ABASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
+ when ABASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- LSR $xxxx (absolute)
+ when ABLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
+ when ABLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- ROL $xxxx (absolute)
+ when ABROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
+ when ABROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- ROR $xxxx (absolute)
+ when ABROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
+ when ABROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- INC $xxxx (absolute)
+ when ABINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
+ when ABINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- DEC $xxxx (absolute)
+ when ABDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
+ when ABDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- TSB $xxxx (absolute)
+ when ABTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABTSB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABTSB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
+ when ABTSB_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O => O
+ when ABTSB_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ -- TRB $xxxx (absolute)
+ when ABTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
+ when ABTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
+ when ABTRB_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
+ when ABTRB_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z
+ when ABTRB_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O => O
+ when ABTRB_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
+
+ ------------------------------------
+ -- ABSOLUTE,X --
+ ------------------------------------
+ -- DMUX: ALU operand #2 multiplexer
+ -- | AI: effective address is indexed (X or Y)
+ -- | | VP: vector pull
+ -- | | | BR: branch opcode
+ -- | | | | EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction)
+ -- | | | | | W: read/write control
+ -- | | | | | | CLI: clear interrupt request
+ -- | | | | | | | PD: PC/MP address output multiplexer select
+ -- | | | | | | | | PCR: register PC (program counter)
+ -- | | | | | | | | | MPR: register MP (memory pointer)
+ -- | | | | | | | | | | P_OP: register P set/reset bit
+ -- | | | | | | | | | | | ALUOP: ALU operation
+ -- | | | | | | | | | | | | REGOP: registers load/increment/decrement etc.
+ -- | | | | | | | | | | | | | RSEL: registers output multiplexer select
+ -- | | | | | | | | | | | | | |
+ -- | | | | | | | | | | | | | |
+ -- -- DMUX AI VP BR EI W CLI PD PCR MPR P_OP ALUOP REGOP RSEL
+ -- LDA $xxxx,X (absolute indexed)
+ when AXLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXLDA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
+ when AXLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
+
+ -- LDY $xxxx,X (absolute indexed)
+ when AXLDY_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXLDY_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXLDY_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y, MP_MSB+CARRY, EI
+ when AXLDY_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MP->MEM; MEM->Y; EI
+
+ -- STA $xxxx,X (absolute indexed)
+ when AXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
+
+ -- STZ $xxxx,X (absolute indexed)
+ when AXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXSTZ_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI
+
+ -- ADC $xxxx,X (absolute indexed)
+ when AXADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
+ when AXADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
+ when AXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC $xxxx,X (absolute indexed)
+ when AXSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
+ when AXSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
+ when AXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
+
+ -- CMP $xxxx,X (absolute indexed)
+ when AXCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
+ when AXCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
+
+ -- INC $xxxx,X (absolute indexed)
+ when AXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXINC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXINC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when AXINC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1
+ when AXINC_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- DEC $xxxx,X (absolute indexed)
+ when AXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXDEC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXDEC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when AXDEC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1
+ when AXDEC_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- ASL $xxxx,X (absolute indexed)
+ when AXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when AXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT
+ when AXASL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- LSR $xxxx,X (absolute indexed)
+ when AXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when AXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT
+ when AXLSR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- ROL $xxxx,X (absolute indexed)
+ when AXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when AXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT
+ when AXROL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- ROR $xxxx,X (absolute indexed)
+ when AXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
+ when AXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT
+ when AXROR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
+
+ -- AND $xxxx,X (absolute indexed)
+ when AXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; EI
+
+ -- ORA $xxxx,X (absolute indexed)
+ when AXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; EI
+
+ -- EOR $xxxx,X (absolute indexed)
+ when AXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; EI
+
+ -- BIT $xxxx,X (absolute indexed)
+ when AXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AXBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
+ when AXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AXBIT_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; EXT BIT A; EI
+
+ ------------------------------------
+ -- ABSOLUTE,Y --
+ ------------------------------------
+ -- LDA $xxxx,X (absolute indexed)
+ when AYLDA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYLDA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYLDA_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI
+ when AYLDA_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALD_R & EXT_O; -- MP->MEM; MEM->A; EI
+
+ -- LDX $xxxx,Y (absolute indexed)
+ when AYLDX_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYLDX_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYLDX_OP2 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; MP_MSB+CARRY, EI
+ when AYLDX_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLD_R & EXT_O; -- MP->MEM; MEM->X; EI
+
+ -- STA $xxxx,Y (absolute indexed)
+ when AYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
+ when AYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI
+
+ -- ADC $xxxx,Y (absolute indexed)
+ when AYADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
+ when AYADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
+ when AYADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
+
+ -- SBC $xxxx,Y (absolute indexed)
+ when AYSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
+ when AYSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
+ when AYSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
+
+ -- CMP $xxxx,Y (absolute indexed)
+ when AYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
+ when AYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
+
+ -- AND $xxxx,Y (absolute indexed)
+ when AYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYAND_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYAND_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; MP_MSB+CARRY, EI
+ when AYAND_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- MP->MEM; EXT AND A; EI
+
+ -- ORA $xxxx,Y (absolute indexed)
+ when AYORA_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYORA_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYORA_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; MP_MSB+CARRY, EI
+ when AYORA_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALD_R & ARD_O; -- MP->MEM; EXT OR A; EI
+
+ -- EOR $xxxx,Y (absolute indexed)
+ when AYEOR_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
+ when AYEOR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
+ when AYEOR_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; MP_MSB+CARRY, EI
+ when AYEOR_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALD_R & ARD_O; -- MP->MEM; EXT XOR A; EI
+
+ ------------------------------------
+ -- RELATIVE --
+ ------------------------------------
+ -- BRA xx
+ when BRA_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BRA_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BRA_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BEQ xx
+ when BEQ_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BEQ_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BEQ_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BNE xx
+ when BNE_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BNE_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BNE_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BCC xx
+ when BCC_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BCC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BCC_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BCS xx
+ when BCS_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BCS_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BCS_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BVC xx
+ when BVC_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BVC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BVC_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BVS xx
+ when BVS_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BVS_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BVS_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BPL xx
+ when BPL_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BPL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BPL_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ -- BMI xx
+ when BMI_OP0 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC +1;
+ when BMI_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'& RDE &'0'& ADPC & LSB_PC & NOP_M & NOP_P & SWC_A & NOP_R & PLR_O; -- PCL+O->PCL;
+ when BMI_OP2 => q <= ORD_D &'0'&'0'&'1'&'1'& RDE &'0'& ADPC & ADJ_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PCH ADJUSTMENT;
+
+ when others => q <= NOP_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI
+ end case;
+ end process;
+end comb;
+
+
Index: mcseq.vhd
===================================================================
--- mcseq.vhd (nonexistent)
+++ mcseq.vhd (revision 4)
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- opcode => microcode address translation logic (L1 microrom)
+entity mcseq is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ mc_nop: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ q: out STD_LOGIC_VECTOR(2 downto 0)
+ );
+end mcseq;
+
+architecture comb of mcseq is
+signal reg: STD_LOGIC_VECTOR(2 downto 0);
+begin
+ process(clk)
+ begin
+ if(clk'event and clk = '1')then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if clr = '1' then
+ reg <= "000";
+ else
+ if mc_nop = '1' then
+ reg <= "111";
+ else
+ reg <= reg +1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ q <= reg;
+end comb;
+
+
Index: mpr.vhd
===================================================================
--- mpr.vhd (nonexistent)
+++ mpr.vhd (revision 4)
@@ -0,0 +1,56 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 16 bit memory pointer address register
+entity mpr is
+ port( clk: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ c: in STD_LOGIC; -- carry input
+ fc: in STD_LOGIC_VECTOR(3 downto 0);
+ din_l: in STD_LOGIC_VECTOR(7 downto 0);
+ din_h: in STD_LOGIC_VECTOR(7 downto 0);
+ zp: in STD_LOGIC_VECTOR(7 downto 0);
+ v: in STD_LOGIC_VECTOR(2 downto 0);
+ dout: out STD_LOGIC_VECTOR(15 downto 0)
+ );
+end mpr;
+
+architecture rtl of mpr is
+constant NOP_M: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
+constant LSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- load lsb
+constant MSB_M: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- load msb
+constant INC_M: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- increment LSB
+constant VEC_M: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- load vector
+constant ZPL_M: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- load ZEROPAGE
+constant ALL_M: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- load all 16 bit register
+constant ICC_M: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- increment MSB with carry
+constant INM_M: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- increment MSB/LSB
+
+signal reg: STD_LOGIC_VECTOR(15 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ case fc is
+ when LSB_M => reg(7 downto 0) <= din_l; reg(15 downto 8) <= reg(15 downto 8);
+ when MSB_M => reg(15 downto 8) <= din_h; reg(7 downto 0) <= reg(7 downto 0);
+ when ALL_M => reg(15 downto 8) <= din_h; reg(7 downto 0) <= din_l;
+ when INC_M => reg(7 downto 0) <= reg(7 downto 0) +1;
+ when VEC_M => reg(15 downto 3) <= "1111111111111"; reg(2 downto 0) <= v; -- 0xFFFX load vector
+ when ZPL_M => reg(15 downto 8) <= zp; reg(7 downto 0) <= din_l; -- 0xXXXX zeropage operation
+ when ICC_M => reg(15 downto 8) <= reg(15 downto 8) + c; -- increment MSB for indexed addressing mode
+ when INM_M => reg <= reg +1;
+ when others => reg <= reg;
+ end case;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: oper.vhd
===================================================================
--- oper.vhd (nonexistent)
+++ oper.vhd (revision 4)
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit operand hold operand register
+entity oper is
+ port( clk: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end oper;
+
+architecture rtl of oper is
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if ld = '1' then
+ reg <= din;
+ else
+ reg <= reg;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: opr.vhd
===================================================================
--- opr.vhd (nonexistent)
+++ opr.vhd (revision 4)
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit opcode hold register
+entity opr is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ b: out STD_LOGIC;
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end opr;
+
+architecture rtl of opr is
+constant BRK_OP: STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- 0x00 BRK/IRQ/NMI/RES
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+signal bf: STD_LOGIC;
+begin
+ process(clk)
+ begin
+ if(clk'event and clk = '1')then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if clr = '1' then -- clr serves to force an "BRK" opcode on RES-NMI-IRQ interrupt
+ reg <= BRK_OP;
+ bf <= '0';
+ else
+ if ld = '1' then
+ reg <= din;
+ if din = BRK_OP then -- check if the opcode "BRK" was loaded as normal instruction or it was forced
+ bf <= '1'; -- by an interrupt request, thus in order to set properly the flag "B" of status register
+ else
+ bf <= '0';
+ end if;
+ else
+ reg <= reg;
+ bf <= bf;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ b <= bf;
+ dout <= reg;
+end rtl;
+
+
Index: pcr.vhd
===================================================================
--- pcr.vhd (nonexistent)
+++ pcr.vhd (revision 4)
@@ -0,0 +1,66 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 16 bit program counter register "PC"
+entity pcr is
+ port( clk: in STD_LOGIC;
+ i: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ fc: in STD_LOGIC_VECTOR(3 downto 0);
+ din1: in STD_LOGIC_VECTOR(7 downto 0);
+ din2: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(15 downto 0)
+ );
+end pcr;
+
+architecture rtl of pcr is
+constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PC no operation
+constant LSB_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- PC load lsb
+constant MSB_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- PC load msb
+constant INC_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- PC increment by 1
+constant LOD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- PC load lsb\msb
+constant ADJ_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- PC msb increment by 1
+constant ADJ_N: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- PC msb decrement by 1
+signal op: STD_LOGIC_VECTOR(3 downto 0);
+signal reg: STD_LOGIC_VECTOR(15 downto 0);
+
+begin
+ process(fc)
+ begin
+ case fc is
+ when ADJ_P => op <= ADJ_P;
+ when ADJ_N => op <= ADJ_N;
+ when others => op(3 downto 1) <= fc(3 downto 1);
+ op(0) <= '0';
+ end case;
+ end process;
+
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if i = '1' then
+ reg <= reg +1;
+ else
+ case op is
+ when LSB_P => reg(7 downto 0) <= din1; reg(15 downto 8) <= reg(15 downto 8);
+ when MSB_P => reg(15 downto 8) <= din1; reg(7 downto 0) <= reg(7 downto 0);
+ when INC_P => reg <= reg +1;
+ when LOD_P => reg(15 downto 8) <= din1; reg(7 downto 0) <= din2;
+ when ADJ_P => reg(15 downto 8) <= reg(15 downto 8) + ("00000001"); reg(7 downto 0) <= reg(7 downto 0);
+ when ADJ_N => reg(15 downto 8) <= reg(15 downto 8) - ("00000001"); reg(7 downto 0) <= reg(7 downto 0);
+ when NOP_P => reg <= reg;
+ when others => reg <= reg;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: pr.vhd
===================================================================
--- pr.vhd (nonexistent)
+++ pr.vhd (revision 4)
@@ -0,0 +1,119 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit processor status register P
+-- NV1BDIZC
+-- 76543210
+-- ||||||||
+-- ||||||||--- C = carry/borrow flag
+-- |||||||---- Z = zero flag
+-- ||||||----- I = interrupt mask
+-- |||||------ D = decimal/binary alu mode
+-- ||||------- B = break opcode flag
+-- |||-------- 1 = always "1'
+-- ||--------- V = overflow flag
+-- |---------- N = negative flag
+entity pr is
+ port( clk: in STD_LOGIC; -- clock
+ clr: in STD_LOGIC; -- clear
+ fwait: in STD_LOGIC;
+ n: in STD_LOGIC; -- N input
+ v: in STD_LOGIC; -- V input
+ z: in STD_LOGIC; -- Z input
+ c: in STD_LOGIC; -- C input
+ b: in STD_LOGIC; -- B input
+ sv: in STD_LOGIC; -- set overflow (by external pin SO)
+ acr_in: in STD_LOGIC; -- auxiliary carry in
+ fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
+ acr_out: out STD_LOGIC -- auxiliary carry out
+ );
+end pr;
+
+architecture rtl of pr is
+constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
+constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
+constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
+constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
+constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
+constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
+constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
+constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
+constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
+constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
+constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
+constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
+constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
+constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
+
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+signal acr: STD_LOGIC; -- carry/borrow used for effectve address calculation
+signal i_so: STD_LOGIC;
+
+begin
+ i_so <= reg(6) when sv = '1' else '1'; -- logic for external pin SO
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if clr = '1' then
+ reg <= "00100100";
+ acr <= '0';
+ else
+ case fc is
+ when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
+ reg(5) <= '1';
+ reg(4 downto 0) <= din(4 downto 0);
+ acr <= '0';
+ when FLD_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NVZC
+ acr <= '0';
+ when SEC_P => reg <= reg or "00000001"; -- 1 => C
+ acr <= acr;
+ when CLC_P => reg <= reg and "11111110"; -- 0 => C
+ acr <= acr;
+ when CLI_P => reg <= reg and "11111011"; -- 0 => I
+ acr <= acr;
+ when SED_P => reg <= reg or "00001000"; -- 1 => D
+ acr <= acr;
+ when CLD_P => reg <= reg and "11110111"; -- 0 => D
+ acr <= acr;
+ when LDZ_P => reg(1) <= z; -- z => Z
+ reg(7 downto 2) <= reg(7 downto 2);
+ reg(0) <= reg(0);
+ when SEI_P => reg(7 downto 5) <= reg(7 downto 5);
+ reg(4) <= reg(4);
+ reg(3) <= reg(3);
+ reg(2) <= '1'; -- 1 => I
+ reg(1 downto 0) <= reg(1 downto 0);
+ acr <= acr;
+ when SID_P => reg(7 downto 5) <= reg(7 downto 5); -- set I and clear D decimal flag (used by interrupt sequence)
+ reg(4) <= b; -- 1 => B (if BRK)
+ reg(3) <= '0'; -- 0 -> D
+ reg(2) <= '1'; -- 1 => I
+ reg(1 downto 0) <= reg(1 downto 0);
+ acr <= acr;
+ when CLV_P => reg <= reg and "10111111"; -- 0 => V
+ acr <= acr;
+ when AUC_P => acr <= acr_in; -- store auxiliary carry (ACR)
+ reg <= reg;
+ when HAC_P => acr <= acr; -- holds auxiliary carry (ACR)
+ reg <= reg;
+ when others => reg(7) <= reg(7);
+ reg(6) <= i_so; -- set overflow by pin SO
+ reg(5 downto 0) <= reg(5 downto 0);
+ acr <= '0';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+ acr_out <= acr;
+end rtl;
+
+
Index: pre_dec.vhd
===================================================================
--- pre_dec.vhd (nonexistent)
+++ pre_dec.vhd (revision 4)
@@ -0,0 +1,152 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- opcode decimal instructions and prefetch prediction logic
+entity pre_dec is
+ port( op: in STD_LOGIC_VECTOR(7 downto 0);
+ fetch: in STD_LOGIC;
+ ei: out STD_LOGIC;
+ dec: out STD_LOGIC
+ );
+end pre_dec;
+
+architecture comb of pre_dec is
+constant NOP_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101010"; -- 0xEA NOP
+constant CLC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011000"; -- 0x18 CLC 0->C
+constant SEC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111000"; -- 0x38 SEC 1->C
+constant CLI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01011000"; -- 0x58 CLI 0->I
+constant SEI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111000"; -- 0x78 SEI 1->I
+constant CLV_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111000"; -- 0xB8 CLV 0->V
+constant CLD_OP: STD_LOGIC_VECTOR(7 downto 0) := "11011000"; -- 0xD8 CLD 0->D
+constant SED_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111000"; -- 0xF8 SED 1->D
+constant TAX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101010"; -- 0xAA TAX A->X
+constant TAY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101000"; -- 0xA8 TAY A->Y
+constant TXA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001010"; -- 0x8A TXA X->A
+constant TYA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011000"; -- 0x98 TYA Y->A
+constant TXY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011011"; -- 0x9B TXY X->Y
+constant TYX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111011"; -- 0xBB TYX Y->X
+constant TXS_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011010"; -- 0x9A TXS X->S
+constant TSX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111010"; -- 0xBA TSX S->X
+constant TAZ_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011011"; -- 0x1B TAZ A->Z
+constant TZA_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111011"; -- 0x3B TZA Z->A
+constant INX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101000"; -- 0xE8 INX X +1
+constant DEX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001010"; -- 0xCA DEX X -1
+constant INY_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001000"; -- 0xC8 INY Y +1
+constant DEY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001000"; -- 0x88 DEY Y -1
+constant ASL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00001010"; -- 0x0A ASL A
+constant LSR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01001010"; -- 0x4A LSR A
+constant ROL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00101010"; -- 0x2A ROL A
+constant ROR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101010"; -- 0x6A ROR A
+constant ADC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100001"; -- 0x61 ADC ($xx,X)
+constant ADC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110001"; -- 0x71 ADC ($xx),Y
+constant ADC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100101"; -- 0x65 ADC $xx
+constant ADC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110101"; -- 0x75 ADC $xx,X
+constant ADC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101001"; -- 0x69 ADC #xx
+constant ADC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111001"; -- 0x79 ADC $xxxx,Y
+constant ADC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111101"; -- 0x7D ADC $xxxx,X
+constant SBC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100001"; -- 0xE1 SBC ($xx,X)
+constant SBC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110001"; -- 0xF1 SBC ($xx),Y
+constant SBC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100101"; -- 0xE5 SBC $xx
+constant SBC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110101"; -- 0xF5 SBC $xx,X
+constant SBC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101001"; -- 0xE9 SBC #xx
+constant SBC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111001"; -- 0xF9 SBC $xxxx,Y
+constant SBC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111101"; -- 0xFD SBC $xxxx,X
+
+signal eoi: STD_LOGIC;
+begin
+ process(op)
+ begin
+ case op is
+ when NOP_OP => eoi <= '1';
+ dec <= '0';
+ when CLC_OP => eoi <= '1';
+ dec <= '0';
+ when SEC_OP => eoi <= '1';
+ dec <= '0';
+ when CLI_OP => eoi <= '1';
+ dec <= '0';
+ when SEI_OP => eoi <= '1';
+ dec <= '0';
+ when CLV_OP => eoi <= '1';
+ dec <= '0';
+ when CLD_OP => eoi <= '1';
+ dec <= '0';
+ when SED_OP => eoi <= '1';
+ dec <= '0';
+ when TAX_OP => eoi <= '1';
+ dec <= '0';
+ when TAY_OP => eoi <= '1';
+ dec <= '0';
+ when TAZ_OP => eoi <= '1';
+ dec <= '0';
+ when TXA_OP => eoi <= '1';
+ dec <= '0';
+ when TYA_OP => eoi <= '1';
+ dec <= '0';
+ when TXY_OP => eoi <= '1';
+ dec <= '0';
+ when TYX_OP => eoi <= '1';
+ dec <= '0';
+ when TZA_OP => eoi <= '1';
+ dec <= '0';
+ when TXS_OP => eoi <= '1';
+ dec <= '0';
+ when TSX_OP => eoi <= '1';
+ dec <= '0';
+ when INX_OP => eoi <= '1';
+ dec <= '0';
+ when DEX_OP => eoi <= '1';
+ dec <= '0';
+ when INY_OP => eoi <= '1';
+ dec <= '0';
+ when DEY_OP => eoi <= '1';
+ dec <= '0';
+ when ASL_OP => eoi <= '1';
+ dec <= '0';
+ when LSR_OP => eoi <= '1';
+ dec <= '0';
+ when ROL_OP => eoi <= '1';
+ dec <= '0';
+ when ROR_OP => eoi <= '1';
+ dec <= '0';
+ -- ADC/SBC
+ when ADC1_OP => eoi <= '0';
+ dec <= '1';
+ when ADC2_OP => eoi <= '0';
+ dec <= '1';
+ when ADC3_OP => eoi <= '0';
+ dec <= '1';
+ when ADC4_OP => eoi <= '0';
+ dec <= '1';
+ when ADC5_OP => eoi <= '0';
+ dec <= '1';
+ when ADC6_OP => eoi <= '0';
+ dec <= '1';
+ when ADC7_OP => eoi <= '0';
+ dec <= '1';
+ when SBC1_OP => eoi <= '0';
+ dec <= '1';
+ when SBC2_OP => eoi <= '0';
+ dec <= '1';
+ when SBC3_OP => eoi <= '0';
+ dec <= '1';
+ when SBC4_OP => eoi <= '0';
+ dec <= '1';
+ when SBC5_OP => eoi <= '0';
+ dec <= '1';
+ when SBC6_OP => eoi <= '0';
+ dec <= '1';
+ when SBC7_OP => eoi <= '0';
+ dec <= '1';
+ when others => eoi <= '0';
+ dec <= '0';
+ end case;
+ end process;
+ ei <= eoi when fetch = '1' else '0';
+end comb;
+
+
+
+
Index: regmux.vhd
===================================================================
--- regmux.vhd (nonexistent)
+++ regmux.vhd (revision 4)
@@ -0,0 +1,60 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit seven-way multiplexer
+entity regmux is
+ port( sel: in STD_LOGIC_VECTOR(3 downto 0);
+ a: in STD_LOGIC_VECTOR(7 downto 0);
+ b: in STD_LOGIC_VECTOR(7 downto 0);
+ c: in STD_LOGIC_VECTOR(7 downto 0);
+ d: in STD_LOGIC_VECTOR(7 downto 0);
+ e: in STD_LOGIC_VECTOR(7 downto 0);
+ f: in STD_LOGIC_VECTOR(7 downto 0);
+ g: in STD_LOGIC_VECTOR(7 downto 0);
+ h: in STD_LOGIC_VECTOR(7 downto 0);
+ i: in STD_LOGIC_VECTOR(7 downto 0);
+ j: in STD_LOGIC_VECTOR(7 downto 0);
+ k: in STD_LOGIC_VECTOR(7 downto 0);
+ y: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end regmux;
+
+architecture comb of regmux is
+constant EXT_O: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- external data bus
+constant ARD_O: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- register A select
+constant XRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- register X select
+constant YRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- register Y select
+constant SRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- register S lsb select
+constant SRM_O: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- register S msb select
+constant PRD_O: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- register P select
+constant PLR_O: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- register PCL select
+constant PHR_O: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- register PCH select
+constant ORD_O: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- register O select
+constant Z00_O: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- select (all zero output)
+constant ZRD_O: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- register Z select (all zero output)
+
+begin
+ process(sel,a,b,c,d,e,f,g,h,i,j,k)
+ begin
+ case sel is
+ when EXT_O => y <= a;
+ when ARD_O => y <= b;
+ when XRD_O => y <= c;
+ when YRD_O => y <= d;
+ when SRD_O => y <= e;
+ when SRM_O => y <= f;
+
+ when PRD_O => y <= g;
+ when PLR_O => y <= h;
+ when PHR_O => y <= i;
+ when ORD_O => y <= j;
+ when Z00_O => y <= (others => '0');
+ when ZRD_O => y <= k;
+ when others => y <= a;
+ end case;
+ end process;
+end comb;
+
+
Index: spr.vhd
===================================================================
--- spr.vhd (nonexistent)
+++ spr.vhd (revision 4)
@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8/16 bit stack pointer register "S"
+entity spr is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ld_l: in STD_LOGIC;
+ ld_h: in STD_LOGIC;
+ u: in STD_LOGIC;
+ d: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(15 downto 0)
+ );
+end spr;
+
+architecture rtl of spr is
+constant SP_6502_VALUE: STD_LOGIC_VECTOR(15 downto 0) := "0000000111111111"; -- $01FF standard 6502 stack pointer
+signal x: STD_LOGIC_VECTOR(3 downto 0);
+signal reg: STD_LOGIC_VECTOR(15 downto 0);
+
+begin
+ x(0) <= ld_l;
+ x(1) <= ld_h;
+ x(2) <= u;
+ x(3) <= d;
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if clr = '1' then
+ reg <= SP_6502_VALUE;
+ else
+ case x is
+ when "0001" => reg(7 downto 0) <= din;
+ reg(15 downto 8) <= reg(15 downto 8);
+ when "0010" => reg(15 downto 8) <= din;
+ reg(7 downto 0) <= reg(7 downto 0);
+ when "0100" => reg <= reg + 1;
+ when "1000" => reg <= reg - 1;
+ when others => reg <= reg;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: v6502.vhd
===================================================================
--- v6502.vhd (nonexistent)
+++ v6502.vhd (revision 4)
@@ -0,0 +1,745 @@
+----------------------------------------------------------------------
+-- 8 bit microprocessor (65C02) with some enhances VHDL project --
+-- Full RTL synchronous pipelined architecture --
+-- Project by Valerio Venturi (Italy) --
+-- Date: 14/04/2011 --
+-- Last revision: 05/05/2011 --
+----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- global architecture
+entity v6502 is
+ port( clk0: in STD_LOGIC; -- PHASE0 clock input
+ res: in STD_LOGIC; -- reset input
+ irq: in STD_LOGIC; -- interrupt request input
+ nmi: in STD_LOGIC; -- not maskable interrupt input
+ rdy: in STD_LOGIC; -- wait state input (read/write)
+ so: in STD_LOGIC; -- set overflow V input
+ rw: out STD_LOGIC; -- read/write out
+ sync: out STD_LOGIC; -- opcode fetch out
+ vp: out STD_LOGIC; -- vector pull
+ ope: out STD_LOGIC; -- microcode end
+ addr: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit address bus out
+ data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus
+ data_out: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit output data bus
+ );
+end v6502;
+
+architecture struct of v6502 is
+ signal i_res: STD_LOGIC; -- internal global reset RES
+ signal i_irq: STD_LOGIC; -- internal interrupt request IRQ
+ signal i_nmi: STD_LOGIC; -- internal interrupt request NMI
+ signal i_rdy: STD_LOGIC; -- internal wait request RDY
+ signal i_so: STD_LOGIC; -- internal set overflow SO
+ signal i_vp: STD_LOGIC; -- internal VP (vector pull)
+ signal int: STD_LOGIC; -- internal global interrupt (instruction boundary synchronized)
+ signal we: STD_LOGIC; -- write enable (combinatorial from PLA)
+ signal we_r: STD_LOGIC; -- write enable (registered)
+ signal ien: STD_LOGIC; -- interrupt IRQ enable
+
+ -- microcode signals (register control)
+ signal regop: STD_LOGIC_VECTOR(3 downto 0); -- register operation microcode
+ signal rsel: STD_LOGIC_VECTOR(3 downto 0); -- register select microcode
+ signal a_l: STD_LOGIC; -- A load
+ signal x_l: STD_LOGIC; -- X load
+ signal y_l: STD_LOGIC; -- Y load
+ signal z_l: STD_LOGIC; -- Y load
+ signal p_l: STD_LOGIC; -- P load
+ signal o_l: STD_LOGIC; -- OPE load
+ signal sp_ll: STD_LOGIC; -- SP load lsb
+ signal sp_lh: STD_LOGIC; -- SP load msb
+ signal sp_u: STD_LOGIC; -- SP increment
+ signal sp_d: STD_LOGIC; -- SP decrement
+ signal dmux_sel: STD_LOGIC_VECTOR(1 downto 0); -- ALU operand #2 data multiplexer
+
+ -- microcode signals (ALU control)
+ signal aluop: STD_LOGIC_VECTOR(4 downto 0); -- ALU operation code
+
+ -- microcode signals CPU control logic
+ signal opfetch: STD_LOGIC; -- opcode fetch
+ signal i_sync: STD_LOGIC; -- internal SYNC not latched
+ signal m_sync: STD_LOGIC; -- internal SYNC latched
+ signal opdec: STD_LOGIC; -- opcode decode
+ signal pcmp: STD_LOGIC_VECTOR(1 downto 0); -- PC/MP out control effective
+ signal pcmp_mc: STD_LOGIC_VECTOR(1 downto 0); -- PC/MP out control microcode
+ signal pcinc: STD_LOGIC; -- PC increment
+ signal e_eop: STD_LOGIC; -- early microcode sequence end (for some opcodes)
+ signal mc_eop: STD_LOGIC; -- microcode sequence end (for some opcodes)
+ signal eop: STD_LOGIC; -- microcode sequence end (effective)
+ signal we_mc: STD_LOGIC; -- microcode write enable
+ signal we_mc_l: STD_LOGIC; -- microcode write enable to latch
+ signal fbrk: STD_LOGIC; -- force BRK opcode (used by hardware interrupts)
+ signal opbrk: STD_LOGIC; -- BRK opcode (used for distinguish between hardware/software interrupts)
+ signal bcf: STD_LOGIC; -- branch condition resolved
+ signal pcc: STD_LOGIC; -- PC carry
+ signal clri: STD_LOGIC; -- clear interrupt request pending microcode
+ signal vso: STD_LOGIC; -- SO input high to low edge flag
+ signal mc_branch: STD_LOGIC; -- branch (relative) opcode
+ signal adc_sbc_mc: STD_LOGIC; -- ADC/SBC opcode (used for decimal adjustment)
+ signal ai_op: STD_LOGIC; -- opcode with absolute indexed addressing mode
+ signal daa_req: STD_LOGIC; -- DAA required
+ signal mcad: STD_LOGIC_VECTOR(10 downto 0); -- microcode address
+ signal mcscan: STD_LOGIC_VECTOR(2 downto 0); -- microcode pointer control
+ signal p_op: STD_LOGIC_VECTOR(3 downto 0); -- microcode control bits register P
+ signal pcr_fc: STD_LOGIC_VECTOR(2 downto 0); -- microcode control PC
+ signal mpr_fc: STD_LOGIC_VECTOR(3 downto 0); -- microcode control MP
+ signal mcbit: STD_LOGIC_VECTOR(34 downto 0); -- microcode control bits
+ signal regbit: STD_LOGIC_VECTOR(8 downto 0); -- microcode control bits
+ signal ivoffs: STD_LOGIC_VECTOR(2 downto 0); -- microcode interrupt vector offset encoding
+ signal mcn: STD_LOGIC; -- microcode does NOPs
+ signal add_sub_op: STD_LOGIC; -- ADC/SBC opcode
+
+ -- ALU signals
+ signal bcd: STD_LOGIC; -- ALU binary/bcd mode
+ signal c_flg: STD_LOGIC; -- ALU carry flag
+ signal z_flg: STD_LOGIC; -- ALU zero flag
+ signal v_flg: STD_LOGIC; -- ALU overflow flag
+ signal n_flg: STD_LOGIC; -- ALU negative flag
+ signal pc_c_alu_flg: STD_LOGIC; -- ALU PC carry flag
+ signal acr_reg: STD_LOGIC; -- ALU auxiliary carry (registered)
+ signal bcd_lsb: STD_LOGIC; -- bcd lsb overflow flag
+ signal bcd_msb: STD_LOGIC; -- bcd msb overflow flag
+ signal branch_neg: STD_LOGIC; -- branch negative offset flag
+
+ -- bus
+ signal dbin: STD_LOGIC_VECTOR(7 downto 0); -- input data bus D0..D7
+ signal dbout: STD_LOGIC_VECTOR(7 downto 0); -- output data bus D0..D7
+ signal a_bus: STD_LOGIC_VECTOR(7 downto 0); -- accumulator register A bus
+ signal x_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register X bus
+ signal y_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register Y bus
+ signal z_bus: STD_LOGIC_VECTOR(7 downto 0); -- index register Z bus
+ signal sp_bus: STD_LOGIC_VECTOR(15 downto 0); -- stack pointer register S bus
+ signal p_bus: STD_LOGIC_VECTOR(7 downto 0); -- status register P bus
+ signal op_bus: STD_LOGIC_VECTOR(7 downto 0); -- opcode register bus
+ signal o_bus: STD_LOGIC_VECTOR(7 downto 0); -- operand register bus
+ signal bcd_bus: STD_LOGIC_VECTOR(7 downto 0); -- bcd constants bus (used for decimal adjustement)
+ signal oper_bus: STD_LOGIC_VECTOR(7 downto 0); -- operand bus (ALU operand #2 bus)
+ signal r_bus: STD_LOGIC_VECTOR(7 downto 0); -- general register bus (ALU operand #2 bus)
+ signal alu_bus: STD_LOGIC_VECTOR(7 downto 0); -- ALU output bus
+ signal pc_bus: STD_LOGIC_VECTOR(15 downto 0); -- program counter register PC bus
+ signal mp_bus: STD_LOGIC_VECTOR(15 downto 0); -- memory pointer register PC bus
+ signal ad_bus: STD_LOGIC_VECTOR(15 downto 0); -- address bus
+
+ -- 16 bit program counter register (PC)
+ component pcr
+ port( clk: in STD_LOGIC; -- clock
+ i: in STD_LOGIC; -- increment
+ fwait: in STD_LOGIC; -- wait
+ fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
+ din1: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ din2: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
+ );
+ end component;
+
+ -- 16 bit memory pointer register (MP)
+ component mpr
+ port( clk: in STD_LOGIC; -- clock
+ fwait: in STD_LOGIC; -- wait
+ c: in STD_LOGIC; -- carry input
+ fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
+ din_l: in STD_LOGIC_VECTOR(7 downto 0); -- input LSB
+ din_h: in STD_LOGIC_VECTOR(7 downto 0); -- input MSB
+ zp: in STD_LOGIC_VECTOR(7 downto 0); -- input zero bage register Z
+ v: in STD_LOGIC_VECTOR(2 downto 0); -- vector offset input
+ dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit opcode register opr (pipeline opcode prefetch register)
+ component opr
+ port( clk: in STD_LOGIC; -- clock
+ clr: in STD_LOGIC; -- force BRK opcode
+ fwait: in STD_LOGIC; -- wait
+ ld: in STD_LOGIC; -- load
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ b: out STD_LOGIC; -- BRK opcode
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit operand hold register oper
+ component oper
+ port( clk: in STD_LOGIC; -- clock
+ fwait: in STD_LOGIC; -- wait
+ ld: in STD_LOGIC; -- load
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit accumulator register A
+ component ar
+ port( clk: in STD_LOGIC; -- clock
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC; -- load
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit index register X
+ component xr
+ port( clk: in STD_LOGIC; -- clock
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC; -- load
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit index register Y
+ component yr
+ port( clk: in STD_LOGIC; -- clock
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC; -- load
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit zero page register Z
+ -- cleared by any interrupts
+ component zr
+ port( clk: in STD_LOGIC; -- clock
+ clr: in STD_LOGIC; -- reset
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC; -- load
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- output
+ );
+ end component;
+
+ -- 16 bit stack pointer SP
+ component spr
+ port( clk: in STD_LOGIC; -- clock
+ fwait: in STD_LOGIC; -- wait
+ clr: in STD_LOGIC; -- load init value
+ ld_l: in STD_LOGIC; -- load lsb
+ ld_h: in STD_LOGIC; -- load msb
+ u: in STD_LOGIC; -- increment
+ d: in STD_LOGIC; -- decrement
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(15 downto 0) -- output
+ );
+ end component;
+
+ -- 8 bit processor status register P
+ -- NV1BDIZC
+ -- 76543210
+ -- ||||||||
+ -- ||||||||--- C = carry/borrow flag
+ -- |||||||---- Z = zero flag
+ -- ||||||----- I = interrupt mask
+ -- |||||------ D = decimal/binary alu mode
+ -- ||||------- B = break opcode flag
+ -- |||-------- 1 = always "1'
+ -- ||--------- V = overflow flag
+ -- |---------- N = negative flag
+ -- The P register also contains an additional carry/borrow flag (ACR) used for effective address calculation but
+ -- it is not visible at program level
+ component pr
+ port( clk: in STD_LOGIC; -- clock
+ clr: in STD_LOGIC; -- clear
+ fwait: in STD_LOGIC; -- wait
+ n: in STD_LOGIC; -- N input
+ v: in STD_LOGIC; -- V input
+ z: in STD_LOGIC; -- Z input
+ c: in STD_LOGIC; -- C input
+ b: in STD_LOGIC; -- B input
+ sv: in STD_LOGIC; -- set overflow
+ acr_in: in STD_LOGIC; -- auxiliary carry in
+ fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code
+ din: in STD_LOGIC_VECTOR(7 downto 0); -- input
+ dout: out STD_LOGIC_VECTOR(7 downto 0); -- output
+ acr_out: out STD_LOGIC -- auxiliary carry out
+ );
+ end component;
+
+ -- BCD register (used for decimal adjustement)
+ component bcd_reg is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ en: in STD_LOGIC;
+ bcd_sl: in STD_LOGIC; -- loads "6" to lsb
+ bcd_sh: in STD_LOGIC; -- loads "6" to msb
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+ end component;
+
+ -- 8 bit (binary/bcd) two-way through pass ALU
+ -- operation:
+ -- aluop = "0000" => dout <= op1 (pass/test)
+ -- aluop = "0001" => dout <= op1 + op2 + carry
+ -- aluop = "0010" => dout <= op1 - op2 - carry
+ -- aluop = "0011" => dout <= op1 and op2
+ -- aluop = "0100" => dout <= op1 or op2
+ -- aluop = "0101" => dout <= op1 xor op2
+ -- aluop = "0110" => dout <= op1 + 1
+ -- aluop = "0111" => dout <= op1 - 1
+ -- aluop = "1000" => dout <= op1 << 1 (ASL)
+ -- aluop = "1001" => dout <= op1 >> 1 (LSR)
+ -- aluop = "1010" => dout <= op1 << 1 (ROL)
+ -- aluop = "1011" => dout <= op1 >> 1 (ROR)
+ component alu_bin
+ port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation)
+ cin: in STD_LOGIC; -- carry/borrow in
+ vin: in STD_LOGIC; -- overflow in
+ op1: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #1
+ op2: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit operand #2
+ fc: in STD_LOGIC_VECTOR(5 downto 0); -- function code
+ cf: out STD_LOGIC; -- carry/borrow (byte) out
+ zf: out STD_LOGIC; -- zero flag out
+ nf: out STD_LOGIC; -- negative flag out
+ vf: out STD_LOGIC; -- overflow flag out
+ pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation
+ bcd_ol: out STD_LOGIC; -- bcd lsb overflow
+ bcd_oh: out STD_LOGIC; -- bcd msb overflow
+ dout: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit result out
+ );
+ end component;
+
+ -- PC/MP address multiplexer
+ component addrmux
+ port( sel: in STD_LOGIC_VECTOR(1 downto 0);
+ a: in STD_LOGIC_VECTOR(15 downto 0);
+ b: in STD_LOGIC_VECTOR(15 downto 0);
+ s: in STD_LOGIC_VECTOR(15 downto 0);
+ y: out STD_LOGIC_VECTOR(15 downto 0)
+ );
+ end component;
+
+ -- register multiplexer
+ component regmux
+ port( sel: in STD_LOGIC_VECTOR(3 downto 0);
+ a: in STD_LOGIC_VECTOR(7 downto 0);
+ b: in STD_LOGIC_VECTOR(7 downto 0);
+ c: in STD_LOGIC_VECTOR(7 downto 0);
+ d: in STD_LOGIC_VECTOR(7 downto 0);
+ e: in STD_LOGIC_VECTOR(7 downto 0);
+ f: in STD_LOGIC_VECTOR(7 downto 0);
+ g: in STD_LOGIC_VECTOR(7 downto 0);
+ h: in STD_LOGIC_VECTOR(7 downto 0);
+ i: in STD_LOGIC_VECTOR(7 downto 0);
+ j: in STD_LOGIC_VECTOR(7 downto 0);
+ k: in STD_LOGIC_VECTOR(7 downto 0);
+ y: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+ end component;
+
+ -- data multiplexer (register "O" bypass)
+ component dmux is
+ port( sel: in STD_LOGIC_VECTOR(1 downto 0);
+ a: in STD_LOGIC_VECTOR(7 downto 0);
+ b: in STD_LOGIC_VECTOR(7 downto 0);
+ c: in STD_LOGIC_VECTOR(7 downto 0);
+ y: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+ end component dmux;
+
+ -- microcode sequencer logic
+ component mcseq
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ mc_nop: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ q: out STD_LOGIC_VECTOR(2 downto 0)
+ );
+ end component;
+
+ -- micropla logic
+ -- output fields format:
+ component mcpla
+ port( a: in STD_LOGIC_VECTOR(10 downto 0);
+ q: out STD_LOGIC_VECTOR(34 downto 0)
+ );
+ end component;
+
+ -- register operation decoding logic
+ component decreg
+ port( r: in STD_LOGIC_VECTOR(3 downto 0);
+ y: out STD_LOGIC_VECTOR(8 downto 0)
+ );
+ end component;
+
+ -- cpu main state machine
+ component cpufsm
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ireq: in STD_LOGIC;
+ branch: in STD_LOGIC;
+ bflag: in STD_LOGIC;
+ aim: in STD_LOGIC;
+ bcarry: in STD_LOGIC;
+ icarry: in STD_LOGIC;
+ p1: in STD_LOGIC_VECTOR(1 downto 0);
+ e_ei: in STD_LOGIC;
+ mc_ei: in STD_LOGIC;
+ addsub: in STD_LOGIC;
+ dec_mode: in STD_LOGIC;
+ fetch: out STD_LOGIC;
+ op_sync: out STD_LOGIC;
+ pci: out STD_LOGIC;
+ pq: out STD_LOGIC_VECTOR(1 downto 0);
+ fb: out STD_LOGIC;
+ od: out STD_LOGIC;
+ mc_nop: out STD_LOGIC
+ );
+ end component;
+
+ -- interrupt logic
+ component intlog
+ port( clk: in STD_LOGIC;
+ iack: in STD_LOGIC; -- interrupt acknowledge by microcode
+ r: in STD_LOGIC; -- RESET request
+ n: in STD_LOGIC; -- NMI request
+ i: in STD_LOGIC; -- IRQ request
+ b: in STD_LOGIC; -- BRK opcode
+ s: in STD_LOGIC; -- SO
+ imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ)
+ ioffs: in STD_LOGIC_VECTOR(1 downto 0); -- interrupt servicing offset
+ ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI)
+ vset: out STD_LOGIC; -- SO output
+ voffs: out STD_LOGIC_VECTOR(2 downto 0) -- interrupt vector offset
+ );
+ end component;
+
+ -- branch logic
+ component branch
+ port( op: in STD_LOGIC_VECTOR(3 downto 0);
+ n: in STD_LOGIC;
+ v: in STD_LOGIC;
+ z: in STD_LOGIC;
+ c: in STD_LOGIC;
+ bres: out STD_LOGIC
+ );
+ end component;
+
+ -- opcode decimal instructions and prefetch prediction logic
+ component pre_dec
+ port( op: in STD_LOGIC_VECTOR(7 downto 0);
+ fetch: in STD_LOGIC;
+ ei: out STD_LOGIC;
+ dec: out STD_LOGIC
+ );
+ end component;
+
+ begin
+ u1:pcr port map(clk=>clk0,
+ i=>pcinc,
+ fwait=>i_rdy,
+ fc(3 downto 1)=>pcr_fc,
+ fc(0)=>o_bus(7),
+ din1=>alu_bus,
+ din2=>o_bus,
+ dout=>pc_bus
+ );
+
+ u2:mpr port map(clk=>clk0,
+ fwait=>i_rdy,
+ c=>acr_reg,
+ fc=>mpr_fc,
+ din_l=>alu_bus,
+ din_h=>dbin,
+ zp=>z_bus,
+ v=>ivoffs,
+ dout=>mp_bus
+ );
+
+ u3:ar port map(clk=>clk0,
+ fwait=>i_rdy,
+ ld=>a_l,
+ din=>alu_bus,
+ dout=>a_bus
+ );
+
+ u4:xr port map(clk=>clk0,
+ fwait=>i_rdy,
+ ld=>x_l,
+ din=>alu_bus,
+ dout=>x_bus
+ );
+
+ u5:yr port map(clk=>clk0,
+ fwait=>i_rdy,
+ ld=>y_l,
+ din=>alu_bus,
+ dout=>y_bus
+ );
+
+ u6:zr port map(clk=>clk0,
+ clr=>clri,
+ fwait=>i_rdy,
+ ld=>z_l,
+ din=>alu_bus,
+ dout=>z_bus
+ );
+
+ u7:spr port map(clk=>clk0,
+ clr=>i_res,
+ fwait=>i_rdy,
+ ld_l=>sp_ll,
+ ld_h=>sp_lh,
+ u=>sp_u,
+ d=>sp_d,
+ din=>alu_bus,
+ dout=>sp_bus
+ );
+
+ u8:pr port map(clk=>clk0,
+ clr=>i_res,
+ fwait=>i_rdy,
+ n=>n_flg,
+ v=>v_flg,
+ z=>z_flg,
+ c=>c_flg,
+ b=>opbrk,
+ sv=>vso,
+ acr_in=>pc_c_alu_flg,
+ fc=>p_op,
+ din=>dbin,
+ dout=>p_bus,
+ acr_out=>acr_reg
+ );
+
+ u9:opr port map(clk=>clk0,
+ clr=>fbrk,
+ fwait=>i_rdy,
+ ld=>opfetch,
+ din=>dbin,
+ b=>opbrk,
+ dout=>op_bus
+ );
+
+ u10:oper port map(clk=>clk0,
+ fwait=>i_rdy,
+ ld=>o_l,
+ din=>alu_bus,
+ dout=>o_bus
+ );
+
+ u11:bcd_reg port map(clk=>clk0,
+ clr=>opfetch,
+ fwait=>i_rdy,
+ en=>bcd,
+ bcd_sl=>bcd_lsb,
+ bcd_sh=>bcd_msb,
+ dout=>bcd_bus
+ );
+
+ u12:alu_bin port map(alu_byp=>acr_reg,
+ cin=>p_bus(0),
+ vin=>p_bus(6),
+ op1=>r_bus,
+ op2=>oper_bus,
+ fc(5 downto 1)=>aluop,
+ fc(0)=>branch_neg,
+ cf=>c_flg,
+ zf=>z_flg,
+ nf=>n_flg,
+ vf=>v_flg,
+ pc_cf=>pc_c_alu_flg,
+ bcd_ol=>bcd_lsb,
+ bcd_oh=>bcd_msb,
+ dout=>alu_bus
+ );
+
+ u13:addrmux port map(sel=>pcmp,
+ a=>pc_bus,
+ b=>mp_bus,
+ s=>sp_bus,
+ y=>addr
+ );
+
+ u14:regmux port map(sel=>rsel,
+ a=>dbin,
+ b=>a_bus,
+ c=>x_bus,
+ d=>y_bus,
+ e=>sp_bus(7 downto 0),
+ f=>sp_bus(15 downto 8),
+ g=>p_bus,
+ h=>pc_bus(7 downto 0),
+ i=>pc_bus(15 downto 8),
+ j=>o_bus,
+ k=>z_bus,
+ y=>r_bus
+ );
+
+ u15:dmux port map(sel=>dmux_sel,
+ a=>o_bus,
+ b=>dbin,
+ c=>bcd_bus,
+ y=>oper_bus
+ );
+
+ u16:mcseq port map(clk=>clk0,
+ clr=>opdec,
+ mc_nop=>mcn,
+ fwait=>i_rdy,
+ q=>mcscan
+ );
+
+ u17:mcpla port map(a=>mcad,
+ q=>mcbit
+ );
+
+ u18:decreg port map(r=>regop,
+ y=>regbit
+ );
+
+ u19:cpufsm port map(clk=>clk0,
+ clr=>i_res,
+ fwait=>i_rdy,
+ ireq=>int,
+ branch=>mc_branch,
+ bflag=>bcf,
+ aim=>ai_op,
+ bcarry=>pcc,
+ icarry=>acr_reg,
+ p1=>pcmp_mc,
+ e_ei=>e_eop,
+ mc_ei=>mc_eop,
+ addsub=>add_sub_op,
+ dec_mode=>p_bus(3),
+ fetch=>opfetch,
+ op_sync=>i_sync,
+ pci=>pcinc,
+ pq=>pcmp,
+ fb=>fbrk,
+ od=>opdec,
+ mc_nop=>mcn
+ );
+
+ u20:intlog port map(clk=>clk0,
+ iack=>clri,
+ r=>i_res,
+ n=>i_nmi,
+ i=>i_irq,
+ b=>opbrk,
+ s=>i_so,
+ imask=>ien,
+ ioffs=>mp_bus(2 downto 1),
+ ireq=>int,
+ vset=>vso,
+ voffs=>ivoffs
+ );
+
+ u21:branch port map(op=>op_bus(7 downto 4),
+ n=>p_bus(7),
+ v=>p_bus(6),
+ z=>p_bus(1),
+ c=>p_bus(0),
+ bres=>bcf
+ );
+
+ u22:pre_dec port map(op=>dbin,
+ fetch=>opfetch,
+ ei=>e_eop,
+ dec=>add_sub_op
+ );
+
+ -- asynchronous CPU link section
+ ien <= p_bus(2); -- P(I) flag
+ bcd <= p_bus(3); -- P(D) flag
+ i_res <= not res; -- internal reset
+ i_nmi <= not nmi; -- internal NMI
+ i_irq <= not irq; -- internal IRQ
+ i_rdy <= not rdy; -- internal RDY
+ i_so <= not so; -- internal SO
+ mcad <= op_bus & mcscan; -- microcode address
+ rsel <= mcbit(3 downto 0); -- registers read microcode
+ regop <= mcbit(7 downto 4); -- registers operation microcode
+ aluop <= mcbit(12 downto 8); -- ALU microcode
+ p_op <= mcbit(16 downto 13); -- register P microcode
+ mpr_fc <= mcbit(20 downto 17); -- MPR microcode
+ pcr_fc <= mcbit(23 downto 21); -- PCR microcode
+ pcmp_mc <= mcbit(25 downto 24); -- PCR/MPR multiplexer microcode
+ clri <= mcbit(26); -- clear interrupt request (also serves as register Z clear)
+ we_mc <= mcbit(27); -- write enable (combinatorial) microcode
+ we_mc_l <= mcbit(28); -- write enable (latched) microcode
+ mc_eop <= mcbit(29); -- end of instruction reached
+ mc_branch <= mcbit(30); -- branch opcode
+ i_vp <= mcbit(31); -- vector pull
+ ai_op <= mcbit(32); -- opcode with addressing indexed microcode
+ dmux_sel <= mcbit(34 downto 33); -- data multiplexer microcode
+ ope <= eop;
+ eop <= '1' when mc_eop = '1' or e_eop = '1' else '0';
+ branch_neg <= '0' when mc_branch = '0' else o_bus(7); -- flag for branch negative offset is valid only with branches opcode
+ vp <= not i_vp;
+
+ -- register operations
+ a_l <= regbit(0); -- A load
+ x_l <= regbit(1); -- X load
+ y_l <= regbit(2); -- Y load
+ z_l <= regbit(3); -- Z load
+ o_l <= regbit(4); -- O load
+ sp_ll <= regbit(5); -- S load lsb
+ sp_lh <= regbit(6); -- S load msb
+ sp_u <= regbit(7); -- S += 1
+ sp_d <= regbit(8); -- S -= 1
+ we <= we_mc or opfetch; -- write enable
+ sync <= m_sync;
+
+ -- SYNC latched
+ process(clk0)
+ begin
+ if (clk0'event and clk0 = '1') then
+ if i_rdy = '0' then
+ m_sync <= i_sync;
+ else
+ m_sync <= m_sync;
+ end if;
+ end if;
+ end process;
+
+ -- PC carry logic
+ process(o_bus,pc_c_alu_flg)
+ begin
+ if o_bus(7) = '0' then -- check for positive/negative branch offset (bit 7)
+ pcc <= pc_c_alu_flg;
+ else
+ pcc <= not pc_c_alu_flg;
+ end if;
+ end process;
+
+ -- write enable registered
+ process(clk0)
+ begin
+ if (clk0'event and clk0 = '1') then
+ if i_res = '1' then
+ we_r <= '1';
+ else
+ if i_rdy = '0' then
+ we_r <= we_mc_l;
+ else
+ we_r <= we_r;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ rw <= we and we_r;
+
+ -- data bus tristate (buffer ring gated) control logic
+ --process(clk0,we,we_r,alu_bus)
+ --begin
+ -- if clock = '0' and (we = '0' or we_r = '0') then
+ -- data <= alu_bus;
+ -- else
+ -- data <= "ZZZZZZZZ";
+ -- end if;
+ --end process;
+ data_out <= alu_bus;
+ dbin <= data_in or "00000000";
+
+end struct;
+
+
+
Index: xr.vhd
===================================================================
--- xr.vhd (nonexistent)
+++ xr.vhd (revision 4)
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit index register "X"
+entity xr is
+ port( clk: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end xr;
+
+architecture rtl of xr is
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if ld = '1' then
+ reg <= din;
+ else
+ reg <= reg;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: yr.vhd
===================================================================
--- yr.vhd (nonexistent)
+++ yr.vhd (revision 4)
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit index register "Y"
+entity yr is
+ port( clk: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end yr;
+
+architecture rtl of yr is
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if ld = '1' then
+ reg <= din;
+ else
+ reg <= reg;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+
Index: zr.vhd
===================================================================
--- zr.vhd (nonexistent)
+++ zr.vhd (revision 4)
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.std_logic_1164.all; -- defines std_logic types
+use IEEE.STD_LOGIC_unsigned.all;
+use IEEE.STD_LOGIC_arith.all;
+
+-- 8 bit zero page register "Z"
+entity zr is
+ port( clk: in STD_LOGIC;
+ clr: in STD_LOGIC;
+ fwait: in STD_LOGIC;
+ ld: in STD_LOGIC;
+ din: in STD_LOGIC_VECTOR(7 downto 0);
+ dout: out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end zr;
+
+architecture rtl of zr is
+signal reg: STD_LOGIC_VECTOR(7 downto 0);
+begin
+ process(clk)
+ begin
+ if (clk'event and clk = '1') then
+ if fwait = '1' then
+ reg <= reg;
+ else
+ if clr = '1' then
+ reg <= "00000000";
+ else
+ if ld = '1' then
+ reg <= din;
+ else
+ reg <= reg;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+ dout <= reg;
+end rtl;
+
+