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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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/versatile_fifo/trunk/rtl/verilog
- from Rev 5 to Rev 6
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Rev 5 → Rev 6
/verastile_fifo_async_cmp.v
1,7 → 1,7
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
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parameter ADR_LENGTH = 6; |
parameter N = ADR_LENGTH-1; |
parameter ADDR_WIDTH = 6; |
parameter N = ADDR_WIDTH-1; |
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parameter Q1 = 2'b00; |
parameter Q2 = 2'b01; |