URL
https://opencores.org/ocsvn/versatile_io/versatile_io/trunk
Subversion Repositories versatile_io
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_io/trunk/rtl/verilog
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/top/versatile_io_top.v
65,7 → 65,7
// UART signals |
.rx(uart0_rx_pad_i), |
.tx(uart0_tx_pad_o), |
.int(uart0_irq), |
.irq(uart0_irq), |
// wishbone slave |
.wbs_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), |
.wbs_adr_i(wbs_adr_i[2:0]), |
/versatile_io.v
1471,7 → 1471,7
// UART signals |
.rx(uart0_rx_pad_i), |
.tx(uart0_tx_pad_o), |
.int(uart0_irq), |
.irq(uart0_irq), |
// wishbone slave |
.wbs_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), |
.wbs_adr_i(wbs_adr_i[2:0]), |