URL
https://opencores.org/ocsvn/versatile_io/versatile_io/trunk
Subversion Repositories versatile_io
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_io/trunk/rtl/verilog
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/top/versatile_io_module.v
File deleted
/top/versatile_io_module_inst.v
File deleted
/top/versatile_io_wires.v
File deleted
/top/versatile_io_top.v
1,7 → 1,3
`include "include/versatile_io_defines.v" |
`ifdef UART0 |
`include "uart16550_ip.v" |
`endif |
module versatile_io ( |
input [31:0] wbs_dat_i, |
input [31:0] wbs_adr_i, |
/versatile_io_wires.v
0,0 → 1,16
`include "versatile_io_defines.v" |
wire [31:0] wbs_vio_dat_i; |
wire [31:0] wbs_vio_adr_i; |
wire [3:0] wbs_vio_sel_i; |
wire wbs_vio_we_i, wbs_vio_stb_i, wbs_vio_cyc_i; |
wire [31:0] wbs_vio_dat_o; |
wire wbs_vio_ack_o, wbs_vio_err_o; |
`ifdef B4 |
wire wbs_vio_stall_o; |
`endif |
`ifdef UART0 |
wire vio_uart0_irq; |
`endif |
`ifdef UART1 |
wire vio_uart1_irq; |
`endif |
/include/versatile_io_defines.v
5,8 → 5,16
`define UART0_BASE_ADR 32'h92000000 |
`define UART0_MEM_MAP_HI 31 |
`define UART0_MEM_MAP_LO 24 |
`ifdef UART0 |
`define UART |
`endif |
//=comment |
//`define UART1 |
`define UART1_BASE 32'h92100000 |
`define UART1_MEM_MAP_HI 31 |
`define UART1_MEM_MAP_LO 24 |
`ifdef UART1 |
`ifndef UART |
`define UART |
`endif |
`endif |
/versatile_io_module_inst.v
0,0 → 1,26
`include "versatile_io_defines.v" |
|
versatile_io vio0 ( |
.wbs_dat_i(wbs_vio_dat_i), |
.wbs_adr_i(wbs_vio_adr_i); |
.wbs_sel_i(wbs_vio_sel_i); |
.wbs_we_i(wbs_vio_we_i), |
.wbs_stb_i(wbs_vio_stb_i), |
.wbs_cyc_i(wbs_vio_cyc_i), |
.wbs_dat_o(wbs_vio_dat_o), |
.wbs_ack_o(wbs_vio_ack_o), |
`ifdef B4 |
.wbs_stall_o(wbs_vio_stall_o), |
`endif |
`ifdef UART0 |
.uart0_rx_pad_i(uart0_rx_pad_i), |
.uart0_tx_pad_i(uart0_tx_pad_i), |
.uart0_irq(vio_uart0_irq), |
`endif |
`ifdef UART1 |
.uart1_rx_pad_i(uart1_rx_pad_i), |
.uart1_tx_pad_i(uart1_tx_pad_i), |
.uart1_irq(vio_uart1_irq), |
`endif |
.wbs_clk(wb_clk), .wbs_rst(wb_rst), |
.clk(), .rst()); |
/Makefile
3,10 → 3,10
|
ip: |
make -C uart16550/ ip |
vppreproc --simple -Iinclude -Iuart16550 top/versatile_io_top.v > versatile_io_ip.v |
vppreproc --simple -Iinclude include/versatile_io_module.v > versatile_io_module.v |
vppreproc --simple -Iinclude include/versatile_io_wires.v > versatile_io_wires.v |
vppreproc --simple -Iinclude include/versatile_io_module_inst > versatile_io_module_inst.v |
vppreproc --noline --noblank -Iuart16550 top/ip.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' | cat - top/versatile_io_top.v > versatile_io.v |
vppreproc --simple -Iinclude top/versatile_io_module.v > versatile_io_module.v |
vppreproc --simple -Iinclude top/versatile_io_wires.v > versatile_io_wires.v |
vppreproc --simple -Iinclude top/versatile_io_module_inst > versatile_io_module_inst.v |
|
clean: |
make -C uart16550/ clean |
/versatile_io_module.v
0,0 → 1,9
`include "versatile_io_defines.v" |
`ifdef UART0 |
input uart0_rx_pad_i, |
output uart0_tx_pad_i, |
`endif |
`ifdef UART1 |
input uart1_rx_pad_i, |
output uart1_tx_pad_i, |
`endif |