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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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/versatile_library
- from Rev 58 to Rev 59
- ↔ Reverse comparison
Rev 58 → Rev 59
/trunk/rtl/verilog/versatile_library.v
61,6 → 61,7
|
`define WB3WB3_BRIDGE |
`define WB3_ARBITER_TYPE1 |
`define WB_B3_RAM_BE |
`define WB_B4_RAM_BE |
`define WB_B4_ROM |
`define WB_BOOT_ROM |
4639,6 → 4640,66
|
`ifdef WB_B4_RAM_BE |
// WB RAM with byte enable |
`define MODULE wb_b3_ram_be |
module `BASE`MODULE ( |
`undef MODULE |
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
|
parameter dat_width = 32; |
parameter adr_width = 8; |
|
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
|
wire [dat_width/8-1:0] cke; |
|
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
endmodule |
`endif |
|
`ifdef WB_B4_RAM_BE |
// WB RAM with byte enable |
`define MODULE wb_b4_ram_be |
module `BASE`MODULE ( |
`undef MODULE |
4674,8 → 4735,14
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
|
/trunk/rtl/verilog/versatile_library_actel.v
1944,6 → 1944,56
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel; |
endmodule |
// WB RAM with byte enable |
module vl_wb_b3_ram_be ( |
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
parameter dat_width = 32; |
parameter adr_width = 8; |
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
wire [dat_width/8-1:0] cke; |
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
endmodule |
// WB RAM with byte enable |
module vl_wb_b4_ram_be ( |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst); |
1973,8 → 2023,14
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
always @ (posedge wb_clk or posedge wb_rst) |
/trunk/rtl/verilog/wb.v
469,6 → 469,66
|
`ifdef WB_B4_RAM_BE |
// WB RAM with byte enable |
`define MODULE wb_b3_ram_be |
module `BASE`MODULE ( |
`undef MODULE |
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
|
parameter dat_width = 32; |
parameter adr_width = 8; |
|
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
|
wire [dat_width/8-1:0] cke; |
|
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
endmodule |
`endif |
|
`ifdef WB_B4_RAM_BE |
// WB RAM with byte enable |
`define MODULE wb_b4_ram_be |
module `BASE`MODULE ( |
`undef MODULE |
504,8 → 564,14
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
|
/trunk/rtl/verilog/versatile_library_altera.v
2049,6 → 2049,56
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel; |
endmodule |
// WB RAM with byte enable |
module vl_wb_b3_ram_be ( |
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
parameter dat_width = 32; |
parameter adr_width = 8; |
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
wire [dat_width/8-1:0] cke; |
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
endmodule |
// WB RAM with byte enable |
module vl_wb_b4_ram_be ( |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst); |
2078,8 → 2128,14
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
end |
endgenerate |
always @ (posedge wb_clk or posedge wb_rst) |
/trunk/rtl/verilog/defines.v
61,6 → 61,7
|
`define WB3WB3_BRIDGE |
`define WB3_ARBITER_TYPE1 |
`define WB_B3_RAM_BE |
`define WB_B4_RAM_BE |
`define WB_B4_ROM |
`define WB_BOOT_ROM |