URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library
- from Rev 64 to Rev 65
- ↔ Reverse comparison
Rev 64 → Rev 65
/trunk/rtl/verilog/versatile_library.v
3531,8 → 3531,12
output reg [(data_width-1):0] q; |
input clk; |
|
`ifdef SYSTEMVERILOG |
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width |
`else |
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
|
`endif |
|
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (memory_init) begin : init_mem |
3547,16 → 3551,15
// use a multi-dimensional packed array |
//to model individual bytes within the word |
|
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
q <= ram[adr]; |
end |
|
`else |
/trunk/rtl/verilog/versatile_library_actel.v
1128,7 → 1128,11
input we; |
output reg [(data_width-1):0] q; |
input clk; |
`ifdef SYSTEMVERILOG |
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width |
`else |
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
`endif |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (memory_init) begin : init_mem |
1141,16 → 1145,15
`ifdef SYSTEMVERILOG |
// use a multi-dimensional packed array |
//to model individual bytes within the word |
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
q <= ram[adr]; |
end |
`else |
genvar i; |
/trunk/rtl/verilog/versatile_library_altera.v
1236,7 → 1236,11
input we; |
output reg [(data_width-1):0] q; |
input clk; |
`ifdef SYSTEMVERILOG |
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width |
`else |
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
`endif |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (memory_init) begin : init_mem |
1249,16 → 1253,15
`ifdef SYSTEMVERILOG |
// use a multi-dimensional packed array |
//to model individual bytes within the word |
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
q <= ram[adr]; |
end |
`else |
genvar i; |
/trunk/rtl/verilog/memories.v
112,8 → 112,12
output reg [(data_width-1):0] q; |
input clk; |
|
//E2_ifdef SYSTEMVERILOG |
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width |
//E2_else |
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
|
//E2_endif |
|
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (memory_init) begin : init_mem |
128,16 → 132,15
// use a multi-dimensional packed array |
//to model individual bytes within the word |
|
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
q <= ram[adr]; |
end |
|
//E2_else |