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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

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    /versatile_mem_ctrl/tags
    from Rev 87 to Rev 88
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Rev 87 → Rev 88

/Rev1/backend/ACTEL/TwoPortRAM_256x36_work.ixf
0,0 → 1,?rev2len?
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>TwoPortRAM_256x36</name><vendor/><library/><version/><fileSets/><hwModel><views/></hwModel><vendorExtension><componentID name="TwoPortRAM_256x36::work"/></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtension><coreDefFile path="./TwoPortRAM_256x36/TwoPortRAM_256x36.cxf"/></vendorExtension><model><signals><signal><name>WEN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>REN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WD</name><direction>in</direction><left>35</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RD</name><direction>out</direction><left>35</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WADDR</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RADDR</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
/Rev1/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.v
0,0 → 1,55
`timescale 1 ns/100 ps
// Version: 8.5 SP2 8.5.2.4
 
 
module TwoPortRAM_256x36(WD,RD,WEN,REN,WADDR,RADDR,WCLK,RCLK);
input [35:0] WD;
output [35:0] RD;
input WEN, REN;
input [7:0] WADDR, RADDR;
input WCLK, RCLK;
 
wire WEAP, WEBP, VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM512X18 TwoPortRAM_256x36_R0C1(.RADDR8(GND), .RADDR7(
RADDR[7]), .RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4(
RADDR[4]), .RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1(
RADDR[1]), .RADDR0(RADDR[0]), .WADDR8(GND), .WADDR7(
WADDR[7]), .WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4(
WADDR[4]), .WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1(
WADDR[1]), .WADDR0(WADDR[0]), .WD17(WD[35]), .WD16(WD[34])
, .WD15(WD[33]), .WD14(WD[32]), .WD13(WD[31]), .WD12(
WD[30]), .WD11(WD[29]), .WD10(WD[28]), .WD9(WD[27]), .WD8(
WD[26]), .WD7(WD[25]), .WD6(WD[24]), .WD5(WD[23]), .WD4(
WD[22]), .WD3(WD[21]), .WD2(WD[20]), .WD1(WD[19]), .WD0(
WD[18]), .RW0(GND), .RW1(VCC), .WW0(GND), .WW1(VCC),
.PIPE(GND), .REN(WEBP), .WEN(WEAP), .RCLK(RCLK), .WCLK(
WCLK), .RESET(VCC), .RD17(RD[35]), .RD16(RD[34]), .RD15(
RD[33]), .RD14(RD[32]), .RD13(RD[31]), .RD12(RD[30]),
.RD11(RD[29]), .RD10(RD[28]), .RD9(RD[27]), .RD8(RD[26]),
.RD7(RD[25]), .RD6(RD[24]), .RD5(RD[23]), .RD4(RD[22]),
.RD3(RD[21]), .RD2(RD[20]), .RD1(RD[19]), .RD0(RD[18]));
RAM512X18 TwoPortRAM_256x36_R0C0(.RADDR8(GND), .RADDR7(
RADDR[7]), .RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4(
RADDR[4]), .RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1(
RADDR[1]), .RADDR0(RADDR[0]), .WADDR8(GND), .WADDR7(
WADDR[7]), .WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4(
WADDR[4]), .WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1(
WADDR[1]), .WADDR0(WADDR[0]), .WD17(WD[17]), .WD16(WD[16])
, .WD15(WD[15]), .WD14(WD[14]), .WD13(WD[13]), .WD12(
WD[12]), .WD11(WD[11]), .WD10(WD[10]), .WD9(WD[9]), .WD8(
WD[8]), .WD7(WD[7]), .WD6(WD[6]), .WD5(WD[5]), .WD4(WD[4])
, .WD3(WD[3]), .WD2(WD[2]), .WD1(WD[1]), .WD0(WD[0]),
.RW0(GND), .RW1(VCC), .WW0(GND), .WW1(VCC), .PIPE(GND),
.REN(WEBP), .WEN(WEAP), .RCLK(RCLK), .WCLK(WCLK), .RESET(
VCC), .RD17(RD[17]), .RD16(RD[16]), .RD15(RD[15]), .RD14(
RD[14]), .RD13(RD[13]), .RD12(RD[12]), .RD11(RD[11]),
.RD10(RD[10]), .RD9(RD[9]), .RD8(RD[8]), .RD7(RD[7]),
.RD6(RD[6]), .RD5(RD[5]), .RD4(RD[4]), .RD3(RD[3]), .RD2(
RD[2]), .RD1(RD[1]), .RD0(RD[0]));
INV WEBUBBLEB(.A(REN), .Y(WEBP));
INV WEBUBBLEA(.A(WEN), .Y(WEAP));
endmodule
/Rev1/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.gen
0,0 → 1,41
Version:8.5.2.4
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_RAM
LPM_HINT:TWO
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
DESDIR:L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS8X8M2
SMARTGEN_PACKAGE:pq208
AGENIII_IS_SUBPROJECT_LIBERO:T
WWIDTH:36
WDEPTH:256
RWIDTH:36
RDEPTH:256
CLKS:2
RESET_POLARITY:2
INIT_RAM:F
DEFAULT_WORD:0x000000000
CASCADE:0
WCLK_EDGE:RISE
RCLK_EDGE:RISE
WCLOCK_PN:WCLK
RCLOCK_PN:RCLK
PMODE2:0
DATA_IN_PN:WD
WADDRESS_PN:WADDR
WE_PN:WEN
DATA_OUT_PN:RD
RADDRESS_PN:RADDR
RE_PN:REN
WE_POLARITY:1
RE_POLARITY:1
PTYPE:1
/Rev1/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.cxf
0,0 → 1,41
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>TwoPortRAM_256x36</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>TwoPortRAM_256x36.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="1"><name>TwoPortRAM_256x36.gen</name><userFileType>GEN</userFileType></file><file fileid="2"><name>TwoPortRAM_256x36.log</name><userFileType>LOG</userFileType></file><file fileid="3"><name>TwoPortRAM_256x36.shx</name><userFileType>Other</userFileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="4"><name>TwoPortRAM_256x36_R0C0.mem</name><userFileType>MEM</userFileType></file><file fileid="5"><name>TwoPortRAM_256x36_R0C1.mem</name><userFileType>MEM</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel><category>RAM</category><function>RAM</function><variation>Two Port RAM</variation><vendor>Actel</vendor><version>2.2</version><model><signals><signal><name>WD</name><direction>in</direction><left>35</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RD</name><direction>out</direction><left>35</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WEN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>REN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WADDR</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RADDR</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
/Rev1/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.log
0,0 → 1,87
** Message System Log
** Database:
** Date: Thu Jun 25 17:18:45 2009
 
 
****************
Macro Parameters
****************
 
Name : TwoPortRAM_256x36
Family : ProASIC3
Output Format : VERILOG
Type : RAM
Write Enable : Active High
Read Enable : Active High
Reset : None
LP : None
FF : None
Read Clock : Rising
Write Clock : Rising
Write Depth : 256
Write Width : 36
Read Depth : 256
Read Width : 36
RAM Type : Two Port
Clocks : Independent Read and Write Clocks
Write Mode A : Hold Data
Write Mode B : Hold Data
Read Pipeline A : No
Read Pipeline B : No
Optimized for : Speed
Portname DataIn : WD
Portname DataOut : RD
Portname Write En : WEN
Portname Read En : REN
Portname WClock : WCLK
Portname RClock : RCLK
Portname WAddress : WADDR
Portname RAddress : RADDR
Portname Reset :
Portname Clock :
Portname DataAIn :
Portname DataBIn :
Portname DataAOut :
Portname DataBOut :
Portname AddressA :
Portname AddressB :
Portname CLKA :
Portname CLKB :
Portname RWA :
Portname RWB :
Portname BLKA :
Portname BLKB :
Portname LP :
Portname FF :
Initialize RAM : False
 
Cascade Configuration:
Write Port configuration : 256x18
Read Port configuration : 256x18
Number of blocks depth wise: 1
Number of blocks width wise: 2
 
**************
Compile Report
**************
 
 
Netlist Resource Report
=======================
 
CORE Used: 2 Total: 24576 (0.01%)
IO (W/ clocks) Used: 0 Total: 154 (0.00%)
Differential IO Used: 0 Total: 35 (0.00%)
GLOBAL (Chip+Quadrant) Used: 0 Total: 18 (0.00%)
PLL Used: 0 Total: 1 (0.00%)
RAM/FIFO Used: 2 Total: 32 (6.25%)
Low Static ICC Used: 0 Total: 1 (0.00%)
FlashROM Used: 0 Total: 1 (0.00%)
User JTAG Used: 0 Total: 1 (0.00%)
 
Wrote Verilog netlist to
L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36\Two\
PortRAM_256x36.v.
 
** Log Ended: Thu Jun 25 17:18:46 2009
 
/Rev1/backend/ACTEL/TwoPortRAM_256x36/TwoPortRAM_256x36.shx
0,0 → 1,256
0:0000000000
1:0000000000
2:0000000000
3:0000000000
4:0000000000
5:0000000000
6:0000000000
7:0000000000
8:0000000000
9:0000000000
A:0000000000
B:0000000000
C:0000000000
D:0000000000
E:0000000000
F:0000000000
10:0000000000
11:0000000000
12:0000000000
13:0000000000
14:0000000000
15:0000000000
16:0000000000
17:0000000000
18:0000000000
19:0000000000
1A:0000000000
1B:0000000000
1C:0000000000
1D:0000000000
1E:0000000000
1F:0000000000
20:0000000000
21:0000000000
22:0000000000
23:0000000000
24:0000000000
25:0000000000
26:0000000000
27:0000000000
28:0000000000
29:0000000000
2A:0000000000
2B:0000000000
2C:0000000000
2D:0000000000
2E:0000000000
2F:0000000000
30:0000000000
31:0000000000
32:0000000000
33:0000000000
34:0000000000
35:0000000000
36:0000000000
37:0000000000
38:0000000000
39:0000000000
3A:0000000000
3B:0000000000
3C:0000000000
3D:0000000000
3E:0000000000
3F:0000000000
40:0000000000
41:0000000000
42:0000000000
43:0000000000
44:0000000000
45:0000000000
46:0000000000
47:0000000000
48:0000000000
49:0000000000
4A:0000000000
4B:0000000000
4C:0000000000
4D:0000000000
4E:0000000000
4F:0000000000
50:0000000000
51:0000000000
52:0000000000
53:0000000000
54:0000000000
55:0000000000
56:0000000000
57:0000000000
58:0000000000
59:0000000000
5A:0000000000
5B:0000000000
5C:0000000000
5D:0000000000
5E:0000000000
5F:0000000000
60:0000000000
61:0000000000
62:0000000000
63:0000000000
64:0000000000
65:0000000000
66:0000000000
67:0000000000
68:0000000000
69:0000000000
6A:0000000000
6B:0000000000
6C:0000000000
6D:0000000000
6E:0000000000
6F:0000000000
70:0000000000
71:0000000000
72:0000000000
73:0000000000
74:0000000000
75:0000000000
76:0000000000
77:0000000000
78:0000000000
79:0000000000
7A:0000000000
7B:0000000000
7C:0000000000
7D:0000000000
7E:0000000000
7F:0000000000
80:0000000000
81:0000000000
82:0000000000
83:0000000000
84:0000000000
85:0000000000
86:0000000000
87:0000000000
88:0000000000
89:0000000000
8A:0000000000
8B:0000000000
8C:0000000000
8D:0000000000
8E:0000000000
8F:0000000000
90:0000000000
91:0000000000
92:0000000000
93:0000000000
94:0000000000
95:0000000000
96:0000000000
97:0000000000
98:0000000000
99:0000000000
9A:0000000000
9B:0000000000
9C:0000000000
9D:0000000000
9E:0000000000
9F:0000000000
A0:0000000000
A1:0000000000
A2:0000000000
A3:0000000000
A4:0000000000
A5:0000000000
A6:0000000000
A7:0000000000
A8:0000000000
A9:0000000000
AA:0000000000
AB:0000000000
AC:0000000000
AD:0000000000
AE:0000000000
AF:0000000000
B0:0000000000
B1:0000000000
B2:0000000000
B3:0000000000
B4:0000000000
B5:0000000000
B6:0000000000
B7:0000000000
B8:0000000000
B9:0000000000
BA:0000000000
BB:0000000000
BC:0000000000
BD:0000000000
BE:0000000000
BF:0000000000
C0:0000000000
C1:0000000000
C2:0000000000
C3:0000000000
C4:0000000000
C5:0000000000
C6:0000000000
C7:0000000000
C8:0000000000
C9:0000000000
CA:0000000000
CB:0000000000
CC:0000000000
CD:0000000000
CE:0000000000
CF:0000000000
D0:0000000000
D1:0000000000
D2:0000000000
D3:0000000000
D4:0000000000
D5:0000000000
D6:0000000000
D7:0000000000
D8:0000000000
D9:0000000000
DA:0000000000
DB:0000000000
DC:0000000000
DD:0000000000
DE:0000000000
DF:0000000000
E0:0000000000
E1:0000000000
E2:0000000000
E3:0000000000
E4:0000000000
E5:0000000000
E6:0000000000
E7:0000000000
E8:0000000000
E9:0000000000
EA:0000000000
EB:0000000000
EC:0000000000
ED:0000000000
EE:0000000000
EF:0000000000
F0:0000000000
F1:0000000000
F2:0000000000
F3:0000000000
F4:0000000000
F5:0000000000
F6:0000000000
F7:0000000000
F8:0000000000
F9:0000000000
FA:0000000000
FB:0000000000
FC:0000000000
FD:0000000000
FE:0000000000
FF:0000000000

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