OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /versatile_mem_ctrl/tags
    from Rev 92 to Rev 93
    ↔ Reverse comparison
  •

Rev 92 → Rev 93

/Rev1/syn/altera/bin/versatile_memory_controller.sdc
0,0 → 1,248
#**************************************************************
# Timimg Information for DDR2 SDRAM
#**************************************************************
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E)
 
# Clock cycle time: min=5.00ns, max=8.00ns
set tCK 8.000
 
# Data Strobe Out
# DQS output access time from CK/CK#
set tDQSCKmin -0.500
set tDQSCKmax 0.500
 
# Data Strobe In
# DQS rising edge to CK rising edge
set tDQSSmin [expr -0.25 * $tCK]
set tDQSSmax [expr 0.25 * $tCK]
# DQS falling to CK rising: setup time
set tDSSmin [expr 0.2 * $tCK]
# DQS falling from CK rising: hold time
set tDSHmin [expr 0.2 * $tCK]
 
# Data Out
# DQ output access time from CK/CK#
set tACmin -0.600
set tACmax 0.600
 
# Data In
# DQ and DM input setup time to DQS
set tDSb 0.150
# DQ and DM input hold time to DQS
set tDHb 0.275
# DQ and DM input setup time to DQS
set tDSa 0.400
# DQ and DM input hold time to DQS
set tDHa 0.400
 
# Command and Address
# Input setup time
set tISb 0.350
set tISa 0.600
# Input hold time
set tIHb 0.470
set tIHa 0.600
 
 
#**************************************************************
# Timimg Information
#**************************************************************
 
# Trace delay for data
set tTDDmin 0.100
set tTDDmax 0.200
 
# Trace delay for clock
set tTDCmin 0.100
set tTDCmax 0.200
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
# Clock frequency
set wb_clk_period 20.000
set sdram_clk_period $tCK
 
# Clocks
create_clock -name {wb_clk[*]} -period $wb_clk_period [get_ports {wb_clk[*]}]
create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
 
# Virtual clocks
#create_clock -name {v_wb_clk_in} -period $wb_clk_period
#create_clock -name {v_wb_clk_out} -period $wb_clk_period
#create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
#create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {versatile_mem_ctrl_ddr_0|ddr_ff_out_ck|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports {ck_pad_o}]
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
derive_clock_uncertainty
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
# Double Data Rate requires constraints for both rising and falling clock edge
# Input max delay value = max trace delay for data + tCO of external device – min trace delay for clock
# Input min delay value = min trace delay for data + tCOmin of external device – max trace delay for clock
# Assume (for now): max trace delay for data = min trace delay for clock
# min trace delay for data = max trace delay for clock
# Data
set_input_delay -clock {ck_pad_o} -max $tACmax [get_ports {dq_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
# Data Strobe
set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
# Data Strobe
set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_n_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_n_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
# Data Mask
set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dm_rdqs_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dm_rdqs_pad_io[*]}] -add_delay
set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
 
# Single Data Rate requires constraints for rising clock edge only
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
# Double Data Rate requires constraints for both rising and falling clock edge
# Output max delay = max trace delay for data + tSU of external register – min trace delay for clock
# Output min delay = min trace delay for data – tH of external register – max trace delay for clock
# Assume (for now): max trace delay for data = min trace delay for clock
# min trace delay for data = max trace delay for clock
# Data
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dq_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dq_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
# Data Strobe
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dqs_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dqs_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
# Data Strobe
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dqs_n_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dqs_n_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay
# Data Mask
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {dm_rdqs_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -max $tISa -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {dm_rdqs_pad_io[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa -clock_fall [get_ports {dm_rdqs_pad_io[*]}] -add_delay
 
# Single Data Rate requires constraints for rising clock edge only
# Chip Select
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cs_n_pad_o}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cs_n_pad_o}] -add_delay
# Row Address Strobe
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {ras_pad_o}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {ras_pad_o}] -add_delay
# Column Address Strobe
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cas_pad_o}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cas_pad_o}] -add_delay
# Write Enable
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {we_pad_o}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {we_pad_o}] -add_delay
# Bank Address
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {ba_pad_o[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {ba_pad_o[*]}] -add_delay
# Address
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {addr_pad_o[*]}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {addr_pad_o[*]}] -add_delay
# Clock Enable
set_output_delay -clock {ck_pad_o} -max $tISa [get_ports {cke_pad_o}] -add_delay
set_output_delay -clock {ck_pad_o} -min -$tIHa [get_ports {cke_pad_o}] -add_delay
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
# Reset
set_false_path -from [get_ports {wb_rst[*]}]
 
# Input Timing Exceptions
# False path exceptions for opposite-edge transfer
# Data
set_false_path -setup -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
set_false_path -setup -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
set_false_path -hold -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270]
set_false_path -hold -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270]
# Data Strobe
#set_false_path -setup -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0]
#set_false_path -setup -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0]
#set_false_path -hold -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0]
#set_false_path -hold -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0]
 
# Output Timing Exceptions
# False path exceptions for opposite-edge transfer
# Data
set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o]
set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o]
# Data Strobe
set_false_path -setup -rise_from [get_clocks sdram_clk_0] -fall_to [get_clocks ck_pad_o]
set_false_path -setup -fall_from [get_clocks sdram_clk_0] -rise_to [get_clocks ck_pad_o]
set_false_path -hold -rise_from [get_clocks sdram_clk_0] -rise_to [get_clocks ck_pad_o]
set_false_path -hold -fall_from [get_clocks sdram_clk_0] -fall_to [get_clocks ck_pad_o]
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
 
/Rev1/syn/altera/bin/versatile_memory_controller.tcl
0,0 → 1,67
# Usage:
# cd /versatile_mem_ctrl/trunk/syn/altera/run/
# quartus_sh -t ../bin/versatile_memory_controller.tcl
 
# Load Quartus II Tcl Project package
package require ::quartus::project
 
# Add the next line to get the execute_flow command
package require ::quartus::flow
 
set need_to_close_project 0
set make_assignments 1
 
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "versatile_memory_controller"]} {
puts "Project versatile_memory_controller is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists versatile_memory_controller]} {
project_open -revision versatile_mem_ctrl_top versatile_memory_controller
} else {
project_new -revision versatile_mem_ctrl_top versatile_memory_controller
}
set need_to_close_project 1
}
 
# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Stratix III"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:18:52 DECEMBER 14, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name SEARCH_PATH core_prbs/rtl/
set_global_assignment -name SEARCH_PATH core_prbs/
set_global_assignment -name SEARCH_PATH NPU1C_XCVR_reconfig/
set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/
set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/rate_match_fifo/
set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/tx_phase_comp_fifo/
set_global_assignment -name SEARCH_PATH altera/90/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run/versatile_mem_ctrl_top.dpf
set_global_assignment -name SDC_FILE ../bin/versatile_memory_controller.sdc
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/versatile_mem_ctrl_ip.v
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run -section_id eda_simulation
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
# Commit assignments
export_assignments
 
# Compile
execute_flow -compile
 
 
# Close project
if {$need_to_close_project} {
project_close
}
}
/Rev1/syn/xilinx/bin/versatile_memory_controller.ucf
0,0 → 1,122
#**************************************************************
# System Level Constraints
#**************************************************************
NET sdram_clk LOC = "F13" | IOSTANDARD = LVCMOS33;
NET wb_clk LOC = "K14" | IOSTANDARD = LVCMOS33;
NET wb_rst LOC = "Y16" | IOSTANDARD = LVTTL;
NET wb_rst TIG;
 
#**************************************************************
# Timing Constraints
#**************************************************************
 
#**************************************************************
# Clocks
#**************************************************************
NET "sdram_clk" TNM_NET = sdram_clk;
TIMESPEC TS_sdram_clk = PERIOD "sdram_clk" 8 ns HIGH 50%; # 125 MHz
NET "wb_clk" TNM_NET = wb_clk;
TIMESPEC TS_wb_clk = PERIOD "wb_clk" 40 ns HIGH 50%; # 25 MHz
 
# External feedback to DCM
NET "ck_fb_pad_i" FEEDBACK = 2 ns NET "ck_fb_pad_o";
 
#
NET "wb_clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "sdram_clk" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "dcm_pll_0/DCM_external/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
 
#**************************************************************
# DDR2 IF
#**************************************************************
# Data
#NET dq_pad_io<31> LOC="U9" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<30> LOC="V8" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<29> LOC="AB1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<28> LOC="AC1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<27> LOC="Y5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<26> LOC="Y6" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<25> LOC="U7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<24> LOC="U8" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<23> LOC="AA2" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<22> LOC="AA3" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<21> LOC="Y1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<20> LOC="Y2" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<19> LOC="T7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<18> LOC="U6" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<17> LOC="U5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<16> LOC="V5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
NET dq_pad_io<15> LOC="R8" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<14> LOC="R7" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<13> LOC="U1" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<12> LOC="U2" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<11> LOC="P8" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<10> LOC="P9" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<9> LOC="R5" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<8> LOC="R6" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<7> LOC="P7" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<6> LOC="P6" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<5> LOC="T3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<4> LOC="T4" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<3> LOC="N9" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<2> LOC="P10" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<1> LOC="P4" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<0> LOC="P3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
# Address
NET addr_pad_o<0> LOC="M4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<1> LOC="M3" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<2> LOC="M8" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<3> LOC="M7" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<4> LOC="L4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<5> LOC="L3" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<6> LOC="K3" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<7> LOC="K2" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<8> LOC="K5" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<9> LOC="K4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<10> LOC="M10" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<11> LOC="M9" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<12> LOC="J5" |IOSTANDARD = SSTL18_I |IOB = TRUE;
# Bank address
NET ba_pad_o<0> LOC="J4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET ba_pad_o<1> LOC="K6" |IOSTANDARD = SSTL18_I |IOB = TRUE;
# Control
NET cas_pad_o LOC="L10" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET cke_pad_o LOC="L7" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET cs_n_pad_o LOC="H2" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET ras_pad_o LOC="H1" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET we_pad_o LOC="L9" |IOSTANDARD = SSTL18_I |IOB = TRUE;
# Data mask
NET dm_rdqs_pad_io<0> LOC="M6" |IOSTANDARD = SSTL18_II |IOB = TRUE;
NET dm_rdqs_pad_io<1> LOC="R2" |IOSTANDARD = SSTL18_II |IOB = TRUE;
#NET dm_rdqs_pad_io<2> LOC="V1" | IOSTANDARD = SSTL18_II | IOB = TRUE;
#NET dm_rdqs_pad_io<3> LOC="V2" | IOSTANDARD = SSTL18_II | IOB = TRUE;
# Strobe
NET dqs_pad_io<0> LOC="R3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dqs_pad_io<1> LOC="T5" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
#NET dqs_pad_io<2> LOC="W3" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dqs_pad_io<3> LOC="V7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
# Clocks
NET ck_pad_o LOC="N5" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET ck_n_pad_o LOC="N4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
#NET ck_pad_o<1> LOC="N1" | IOSTANDARD = SSTL18_I | IOB = TRUE;
#NET ck_n_pad_o<1> LOC="N2" | IOSTANDARD = SSTL18_I | IOB = TRUE;
NET ck_fb_pad_o LOC="M2" |IOSTANDARD = LVCMOS18 |IOB = TRUE;
NET ck_fb_pad_i LOC="N7" |IOSTANDARD = LVCMOS18 |IOB = TRUE;
#
INST "dq_pad_io<0>" TNM = TNM_dq_in;
INST "dq_pad_io<1>" TNM = TNM_dq_in;
INST "dq_pad_io<2>" TNM = TNM_dq_in;
INST "dq_pad_io<3>" TNM = TNM_dq_in;
INST "dq_pad_io<4>" TNM = TNM_dq_in;
INST "dq_pad_io<5>" TNM = TNM_dq_in;
INST "dq_pad_io<6>" TNM = TNM_dq_in;
INST "dq_pad_io<7>" TNM = TNM_dq_in;
INST "dq_pad_io<8>" TNM = TNM_dq_in;
INST "dq_pad_io<9>" TNM = TNM_dq_in;
INST "dq_pad_io<10>" TNM = TNM_dq_in;
INST "dq_pad_io<11>" TNM = TNM_dq_in;
INST "dq_pad_io<12>" TNM = TNM_dq_in;
INST "dq_pad_io<13>" TNM = TNM_dq_in;
INST "dq_pad_io<14>" TNM = TNM_dq_in;
INST "dq_pad_io<15>" TNM = TNM_dq_in;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.