OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

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  • This comparison shows the changes necessary to convert path 
    /versatile_mem_ctrl/trunk/bench
    from Rev 75 to Rev 80
    ↔ Reverse comparison
  •

Rev 75 → Rev 80

/tb.v
5,7 → 5,9
output OK
);
 
reg sdram_clk, wb_clk, wb_rst;
reg wb_clk, wb_rst;
reg sdram_clk, sdram_rst;
reg tb_rst;
 
wire [31:0] wb0_dat_i;
wire [3:0] wb0_sel_i;
110,7 → 112,7
.ack(wb0_ack_o),
.clk(wb_clk),
.dat_i(wb0_dat_o),
.reset(wb_rst)
.reset(tb_rst)
);
wb1_ddr wb1i
(
125,7 → 127,7
.ack(wb1_ack_o),
.clk(wb_clk),
.dat_i(wb1_dat_o),
.reset(wb_rst)
.reset(tb_rst)
);
wb4_ddr wb4i
(
140,13 → 142,13
.ack(wb4_ack_o),
.clk(wb_clk),
.dat_i(wb4_dat_o),
.reset(wb_rst)
.reset(tb_rst)
);
`endif
 
versatile_mem_ctrl_top # (
.nr_of_wb_clk_domains(2),
.nr_of_wb_ports_clk0(2),
.nr_of_wb_ports_clk0(1),
.nr_of_wb_ports_clk1(1),
.nr_of_wb_ports_clk2(0),
.nr_of_wb_ports_clk3(0))
279,26 → 281,48
.odt()
);
`endif
 
// Wishbone reset
initial
begin
#0 wb_rst = 1'b1;
#200 wb_rst = 1'b1;
#0 wb_rst = 1'b1;
#200 wb_rst = 1'b1;
#200000 wb_rst = 1'b0;
end
 
// SDRAM reset
initial
begin
#0 sdram_rst = 1'b1;
#200 sdram_rst = 1'b1;
#200000 sdram_rst = 1'b0;
end
// Test bench reset
initial
begin
#0 tb_rst = 1'b1;
#200 tb_rst = 1'b1;
//#200000 tb_rst = 1'b0;
#300000 tb_rst = 1'b0; // hold reset to let initialization complete
end
 
// Wishbone clock
initial
begin
#0 wb_clk = 1'b0;
forever
#200 wb_clk = !wb_clk; // 25MHz
//#200 wb_clk = !wb_clk; // 2.5 MHz
#20 wb_clk = !wb_clk; // 25 MHz
end
 
// SDRAM clock
initial
begin
#0 sdram_clk = 1'b0;
forever
#4 sdram_clk = !sdram_clk; // 125MHz
//#4 sdram_clk = !sdram_clk; // 125 MHz
#5 sdram_clk = !sdram_clk; // 100 MHz
end
endmodule // versatile_mem_ctrl_tb
/wb1_ddr.fzm
1,4 → 1,4
## File last modified by Fizzim: 1:27:11 PM on 4/13/10
## File last modified by Fizzim: 1:20:37 PM on 6/7/10
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1251,10 → 1251,10
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def_type
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output
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<type>
output
<status>
GLOBAL_VAR
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LOCAL
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</value>
<vis>
1
<status>
GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
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<comment>
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GLOBAL_VAR
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<color>
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<status>
GLOBAL_VAR
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<vis>
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<status>
GLOBAL_VAR
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</vis>
<type>
output
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GLOBAL_VAR
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</type>
<comment>
<status>
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<color>
-16777216
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<reset>
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<color>
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<state>
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<status>
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state10
<status>
LOCAL
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</value>
<vis>
1
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GLOBAL_VAR
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</vis>
<type>
def_type
<status>
GLOBAL_VAR
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</type>
<comment>
<status>
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<color>
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</color>
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<value>
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1
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GLOBAL_VAR
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<type>
output
<status>
GLOBAL_VAR
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<value>
32'h0
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GLOBAL_VAR
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GLOBAL_VAR
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</vis>
<type>
output
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GLOBAL_VAR
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</type>
<comment>
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<color>
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<status>
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</color>
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4'b1111
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output
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GLOBAL_VAR
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<status>
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3287,16 → 5305,16
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525
25
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680
755
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<reset>
false
3317,7 → 5335,7
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trans3
trans6
<status>
LOCAL
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3361,9 → 5379,9
ABS
</status>
<value>
ack
1
<status>
LOCAL
GLOBAL_VAR
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</value>
<vis>
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14
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<page>
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3402,34 → 5420,34
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state10
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3480,7 → 5498,7
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state8
state13
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3873,16 → 5891,16
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550
800
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775
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680
930
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155
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3903,7 → 5921,7
ABS
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trans5
trans9
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3977,10 → 5995,10
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44
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<page>
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3988,34 → 6006,34
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state11_1
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trans10
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def_type
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def_type
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4066,7 → 6247,7
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state14_0
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4110,7 → 6291,7
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32'h2014
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<type>
output
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32'h2014
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32'h0
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