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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

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  • This comparison shows the changes necessary to convert path 
    /versatile_mem_ctrl/trunk/rtl/verilog
    from Rev 34 to Rev 35
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  •

Rev 34 → Rev 35

/versatile_mem_ctrl_top.v
1,7 → 1,4
`timescale 1ns/1ns
`ifdef SDR_16
`include "sdr_16_defines.v"
`endif
`ifdef DDR_16
`include "ddr_16_defines.v"
`endif
40,8 → 37,11
parameter nr_of_wb_ports_clk2 = 0;
parameter nr_of_wb_ports_clk3 = 0;
parameter tot_nr_of_wb_ports = nr_of_wb_ports_clk0 + nr_of_wb_ports_clk1 + nr_of_wb_ports_clk2 + nr_of_wb_ports_clk3;
 
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
parameter [2:0] init_cl = 3'b010; // valid options 010, 011 used for SDR LMR
input [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_0;
input [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_0;
output [32*nr_of_wb_ports_clk0-1:0] wb_dat_o_0;
66,12 → 66,12
input [0:nr_of_wb_clk_domains-1] wb_rst;
`ifdef SDR_16
output [1:0] ba_pad_o;
output [1:0] ba_pad_o;
output [12:0] a_pad_o;
output cs_n_pad_o;
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
output cs_n_pad_o;
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
output reg [15:0] dq_o;
output reg [1:0] dqm_pad_o;
input [15:0] dq_i;
101,8 → 101,8
input sdram_clk, sdram_rst;
 
wire [0:15] fifo_empty[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
//wire [0:15] fifo_rd[0:3];
wire [35:0] fifo_dat_o[0:3];
wire [31:0] fifo_dat_i;
wire [0:15] fifo_we[0:3];
189,11 → 189,11
.wb_clk(wb_clk[2]),
.wb_rst(wb_rst[2]),
// SDRAM controller interface
.sdram_dat_o(),
.sdram_fifo_empty(),
.sdram_fifo_rd(),
.sdram_dat_i(),
.sdram_fifo_wr(),
.sdram_dat_o(fifo_dat_o[2]),
.sdram_fifo_empty(fifo_empty[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_rd(fifo_re[2][0:nr_of_wb_ports_clk2-1] & {nr_of_wb_ports_clk2{fifo_rd}}),
.sdram_dat_i(fifo_dat_i),
.sdram_fifo_wr(fifo_we[2][0:nr_of_wb_ports_clk2-1] & {nr_of_wb_ports_clk2{fifo_wr}}),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk2 < 16) begin
220,11 → 220,11
.wb_clk(wb_clk[3]),
.wb_rst(wb_rst[3]),
// SDRAM controller interface
.sdram_dat_o(),
.sdram_fifo_empty(),
.sdram_fifo_rd(),
.sdram_dat_i(),
.sdram_fifo_wr(),
.sdram_dat_o(fifo_dat_o[3]),
.sdram_fifo_empty(fifo_empty[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_rd(fifo_re[3][0:nr_of_wb_ports_clk3-1] & {nr_of_wb_ports_clk3{fifo_rd}}),
.sdram_dat_i(fifo_dat_i),
.sdram_fifo_wr(fifo_we[3][0:nr_of_wb_ports_clk3-1] & {nr_of_wb_ports_clk3{fifo_wr}}),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk3 < 16) begin
246,6 → 246,10
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3])
);
 
// fifo_re[0-3] is a one-hot read enable structure
// fifo_empty should go active when chosen fifo queue is empty
assign current_fifo_empty = (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3]));
 
decode decode1 (
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly),
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3])
269,14 → 273,14
refresh_req <= 1'b0;
// SDR SDRAM 16 FSM
fsm_sdr_16 # ( .ba_size(`BA_SIZE), .row_size(`ROW_SIZE), .col_size(`COL_SIZE))
fsm_sdr_16 # ( .ba_size(ba_size), .row_size(row_size), .col_size(col_size))
fsm_sdr_16(
.adr_i({fifo_dat_o[fifo_sel_domain_reg][`BA_SIZE+`ROW_SIZE+`COL_SIZE+6-2:6],1'b0}),
.adr_i({fifo_dat_o[fifo_sel_domain_reg][ba_size+row_size+col_size+6-2:6],1'b0}),
.we_i(fifo_dat_o[fifo_sel_domain_reg][5]),
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.fifo_sel_i(fifo_sel_i), .fifo_sel_domain_i(fifo_sel_domain_i),
.fifo_sel_reg(fifo_sel_reg), .fifo_sel_domain_reg(fifo_sel_domain_reg),
.fifo_rd(fifo_rd),
.fifo_empty(current_fifo_empty), .fifo_rd(fifo_rd),
.count0(count0),
.refresh_req(refresh_req),
.cmd_aref(cmd_aref), .cmd_read(cmd_read),
291,7 → 295,7
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay0.depth=`CL+2;
defparam delay0.depth=init_cl+2;
defparam delay0.width=1;
delay delay0 (
.d(fifo_sel_reg[i]),
301,7 → 305,7
);
end
defparam delay1.depth=`CL+2;
defparam delay1.depth=init_cl+2;
defparam delay1.width=2;
delay delay1 (
.d(fifo_sel_domain_reg),
310,7 → 314,7
.rst(sdram_rst)
);
defparam delay2.depth=`CL+2;
defparam delay2.depth=init_cl+2;
defparam delay2.width=1;
delay delay2 (
.d(cmd_read),
/versatile_mem_ctrl_ip.v
289,7 → 289,7
adr_i, we_i, bte_i,
fifo_sel_i, fifo_sel_domain_i,
fifo_sel_reg, fifo_sel_domain_reg,
fifo_rd, count0,
fifo_empty, fifo_rd, count0,
refresh_req, cmd_aref, cmd_read,
ba, a, cmd, dq_oe,
sdram_clk, sdram_rst
304,6 → 304,7
input [1:0] fifo_sel_domain_i;
output [0:15] fifo_sel_reg;
output [1:0] fifo_sel_domain_reg;
input fifo_empty;
output fifo_rd;
output count0;
input refresh_req;
413,7 → 414,8
if (state!=next)
counter <= 5'd0;
else
counter <= counter + 5'd1;
if (~(state==rw & fifo_empty & ~counter[0] & we_reg))
counter <= counter + 5'd1;
end
always @ (posedge sdram_clk or posedge sdram_rst)
begin
448,10 → 450,10
{ba,a,cmd} = {ba_reg,(13'd0 | row_reg),cmd_act};
{rw,5'bxxxxx}:
begin
if (!counter[0])
{cmd,cmd_read} = {{2'b10,!we_reg},~we_reg};
else
cmd = cmd_nop;
casex ({we_reg,counter[0],fifo_empty})
{1'b0,1'b0,1'bx}: {cmd,cmd_read} = {cmd_rd,1'b1};
{1'b1,1'b0,1'b0}: cmd = cmd_wr;
endcase
case (bte_reg)
linear: {ba,a} = {ba_reg,col_reg_a10_fix};
beat4: {ba,a} = {ba_reg,col_reg_a10_fix[12:2],col_reg_a10_fix[2:0] + counter[2:0]};
463,7 → 465,7
end
end
assign fifo_rd = ((state==idle) & (next==adr)) ? 1'b1 :
((state==rw) & we_reg & !counter[0]) ? 1'b1 :
((state==rw) & we_reg & !counter[0] & !fifo_empty) ? 1'b1 :
1'b0;
assign count0 = counter[0];
always @ (posedge sdram_clk or posedge sdram_rst)
470,10 → 472,10
if (sdram_rst)
dq_oe <= 1'b0;
else
dq_oe <= (state==rw & we_reg);
dq_oe <= ((state==rw & we_reg & ~counter[0] & !fifo_empty) | (state==rw & we_reg & counter[0]));
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{open_ba,open_row[0],open_row[1],open_row[2],open_row[3]} <= {4'b0000,{row_size{1'b0}},{row_size{1'b0}},{row_size{1'b0}},{row_size{1'b0}}};
{open_ba,open_row[0],open_row[1],open_row[2],open_row[3]} <= {4'b0000,{row_size*4{1'b0}}};
else
casex ({ba,a[10],cmd})
{2'bxx,1'b1,cmd_pch}: open_ba <= 4'b0000;
721,6 → 723,7
output cke_pad_o;
input sdram_clk, sdram_rst;
wire [0:15] fifo_empty[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
wire [35:0] fifo_dat_o[0:3];
wire [31:0] fifo_dat_i;
847,6 → 850,7
.fifo_sel(fifo_sel_reg), .fifo_sel_domain(fifo_sel_domain_reg),
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3])
);
assign current_fifo_empty = (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3]));
decode decode1 (
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly),
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3])
870,7 → 874,7
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.fifo_sel_i(fifo_sel_i), .fifo_sel_domain_i(fifo_sel_domain_i),
.fifo_sel_reg(fifo_sel_reg), .fifo_sel_domain_reg(fifo_sel_domain_reg),
.fifo_rd(fifo_rd),
.fifo_empty(current_fifo_empty), .fifo_rd(fifo_rd),
.count0(count0),
.refresh_req(refresh_req),
.cmd_aref(cmd_aref), .cmd_read(cmd_read),
/versatile_mem_ctrl_wb.v
30,7 → 30,7
input sdram_clk;
input sdram_rst;
 
parameter linear_burst = 2'b00;
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
85,15 → 85,7
assign egress_fifo_di[i] = (wb_state[i]==idle) ? wb_adr_i[i] : wb_dat_i[i];
end
endgenerate
/*
// fifo write adr
generate
assign wr_adr[0] = ((wb_state[0]==idle) & wb_cyc_i[0] & wb_stb_i[0] & !egress_fifo_full[0]);
for (i=1;i<nr_of_wb_ports;i=i+1) begin : fifo_wr_adr
assign wr_adr[i] = (|(wr_adr[0:i-1])) ? 1'b0 : ((wb_state[i]==idle) & wb_cyc_i[i] & wb_stb_i[i] & !egress_fifo_full[i]);
end
endgenerate
*/
 
// wr_ack
generate
assign wb_wr_ack[0] = ((wb_state[0]==idle | wb_state[0]==wr) & wb_cyc_i[0] & wb_stb_i[0] & !egress_fifo_full[0]);
136,10 → 128,10
else if (wb_wr_ack[i])
wb_state[i] <= rd;
rd:
if ((wb_adr_i[i][`CTI_I]==classic | wb_adr_i[i][`CTI_I]==endofburst) & wb_ack_o[i])
if ((wb_adr_i[i][`CTI_I]==classic | wb_adr_i[i][`CTI_I]==endofburst | wb_adr_i[i][`BTE_I]==linear) & wb_ack_o[i])
wb_state[i] <= idle;
wr:
if ((wb_adr_i[i][`CTI_I]==classic | wb_adr_i[i][`CTI_I]==endofburst) & wb_ack_o[i])
if ((wb_adr_i[i][`CTI_I]==classic | wb_adr_i[i][`CTI_I]==endofburst | wb_adr_i[i][`BTE_I]==linear) & wb_ack_o[i])
wb_state[i] <= idle;
default: ;
endcase
146,28 → 138,7
end
endgenerate
 
/*
generate
 
for (i=0;i<nr_of_wb_ports;i=i+1) begin : ack
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o[i] <= 1'b0;
else
case (wb_state[i])
idle:
wb_ack_o[i] <= 1'b0;
wr:
wb_ack_o[i] <= wb_wr_ack[i];
rd:
wb_ack_o[i] <= wb_rd_ack[i];
default: ;
endcase
end
endgenerate
*/
generate
for (i=0;i<nr_of_wb_ports;i=i+1) begin : fifo_adr
// egress queue
/Makefile
1,4 → 1,4
svn_export: versatile_fifo_dual_port_ram.v versatile_fifo_async_cmp.v lfsr_polynom.v versatile_counter.v
svn_export: versatile_fifo_dual_port_ram.v versatile_fifo_async_cmp.v
 
versatile_fifo_dual_port_ram.v:
svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
6,18 → 6,16
versatile_fifo_async_cmp.v:
svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v
 
lfsr_polynom.v:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/lfsr_polynom.v
versatile_counter_generator.php:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php
 
versatile_counter.v:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter.v
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php
CSV.class.php:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php
 
versatile_fifo_dual_port_ram_dc_dw.v: versatile_fifo_dual_port_ram.v
vppreproc +define+TYPE+"dc_dw" +define+DC +define+DW +define+DATA_WIDTH+36 +define+ADDR_WIDTH+8 --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
 
versatile_counter: versatile_counter.xls versatile_counter.v versatile_counter_generator.php
versatile_counter: versatile_counter_generator.php CSV.class.php
excel2csv versatile_counter.xls -S ,
./versatile_counter_generator.php fifo_adr_counter.csv > fifo_adr_counter.v
./versatile_counter_generator.php ctrl_counter.csv > ctrl_counter.v
29,10 → 27,6
fifo_fill.v: fifo_fill.fzm
perl fizzim.pl -encoding onehot < fifo_fill.fzm > fifo_fill.v
 
sdr_16.v: sdr_16.fzm sdr_16_defines.v
perl fizzim.pl -encoding onehot < sdr_16.fzm > tmp1.v
vppreproc --simple tmp1.v > sdr_16.v
 
ddr_16.v: ddr_16.fzm ddr_16_defines.v
perl fizzim.pl -encoding onehot < ddr_16.fzm > tmp1.v
vppreproc --simple tmp1.v > ddr_16.v
42,11 → 36,13
 
all: svn_export versatile_fifo_dual_port_ram_dc_dw.v versatile_counter fifo_fill.v sdr_16.v ddr_16.v versatile_mem_ctrl_ip.v
 
test: versatile_fifo_dual_port_ram_dc_dw.v
vppreproc --simple +define+SDR_16 delay.v codec.v fifo_adr_counter.v versatile_fifo_async_cmp.v ref_counter.v fsm_sdr_16.v versatile_mem_ctrl_wb.v versatile_mem_ctrl_top.v > versatile_mem_ctrl_ip.v
sdr_16.v: versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v versatile_counter
vppreproc --simple +define+SDR_16 delay.v codec.v fifo_adr_counter.v versatile_fifo_async_cmp.v ref_counter.v fsm_sdr_16.v versatile_mem_ctrl_wb.v versatile_mem_ctrl_top.v > sdr_16.v
 
all: sdr_16.v
 
clean:
rm -rf versatile_fifo_dual_port_ram_dc_dw.v versatile_fifo_async_cmp.v lfsr_polynom.v versatile_counter.v
rm -rf versatile_fifo_dual_port_ram_dc_dw.v versatile_fifo_async_cmp.v
rm -rf fifo_fill.v sdr_16.v ddr_16.v
rm -rf *_counter.v
rm -rf *.csv

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