URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/rtl/verilog
- from Rev 48 to Rev 49
- ↔ Reverse comparison
Rev 48 → Rev 49
/Makefile
24,6 → 24,9
versatile_fifo_dual_port_ram_dc_dw.v: versatile_fifo_dual_port_ram.v |
vppreproc +define+TYPE+"dc_dw" +define+DC +define+DW +define+DATA_WIDTH+36 +define+ADDR_WIDTH+8 --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v |
|
versatile_fifo_dual_port_ram_dc_sw.v: |
svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v |
|
versatile_counter: versatile_counter_generator.php CSV.class.php |
excel2csv versatile_counter.xls -S , |
./versatile_counter_generator.php gray_counter.csv > gray_counter.v |