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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

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/versatile_counter.xls Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/versatile_mem_ctrl_top.v
2,132 → 2,124
`ifdef DDR_16
`include "ddr_16_defines.v"
`endif
`ifdef SDR_16
`include "sdr_16_defines.v"
`endif
 
module versatile_mem_ctrl_top
(
// wishbone side
wb_adr_i_0, wb_dat_i_0, wb_dat_o_0,
wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0,
wb_adr_i_1, wb_dat_i_1, wb_dat_o_1,
wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1,
wb_adr_i_2, wb_dat_i_2, wb_dat_o_2,
wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2,
wb_adr_i_3, wb_dat_i_3, wb_dat_o_3,
wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3,
wb_clk, wb_rst,
// wishbone side
wb_adr_i_0, wb_dat_i_0, wb_dat_o_0,
wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0,
wb_adr_i_1, wb_dat_i_1, wb_dat_o_1,
wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1,
wb_adr_i_2, wb_dat_i_2, wb_dat_o_2,
wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2,
wb_adr_i_3, wb_dat_i_3, wb_dat_o_3,
wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3,
wb_clk, wb_rst,
 
`ifdef SDR_16
ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o, dq_o, dqm_pad_o, dq_i, dq_oe, cke_pad_o,
ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o, dq_o, dqm_pad_o, dq_i, dq_oe, cke_pad_o,
`endif
 
`ifdef DDR_16
ck_pad_o, ck_n_pad_o, cke_pad_o, ck_fb_pad_o, ck_fb_pad_i,
cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o,
dm_rdqs_pad_io, ba_pad_o, addr_pad_o, dq_pad_io, dqs_pad_io, dqs_oe, dqs_n_pad_io, rdqs_n_pad_i, odt_pad_o,
ck_pad_o, ck_n_pad_o, cke_pad_o, ck_fb_pad_o, ck_fb_pad_i,
cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o,
dm_rdqs_pad_io, ba_pad_o, addr_pad_o, dq_pad_io, dqs_pad_io, dqs_oe, dqs_n_pad_io, rdqs_n_pad_i, odt_pad_o,
`endif
// SDRAM signals
sdram_clk, sdram_rst
);
 
// number of wb clock domains
parameter nr_of_wb_clk_domains = 1;
// number of wb ports in each wb clock domain
parameter nr_of_wb_ports_clk0 = 1;
parameter nr_of_wb_ports_clk1 = 0;
parameter nr_of_wb_ports_clk2 = 0;
parameter nr_of_wb_ports_clk3 = 0;
 
/*
// Now these are defines, synthesis tool was doing strange things! jb
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
parameter [2:0] cl = 3'b010; // valid options 010, 011 used for SDR LMR
*/
input [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_0;
input [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_0;
output [32*nr_of_wb_ports_clk0-1:0] wb_dat_o_0;
input [0:nr_of_wb_ports_clk0-1] wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0;
input [36*nr_of_wb_ports_clk1-1:0] wb_adr_i_1;
input [36*nr_of_wb_ports_clk1-1:0] wb_dat_i_1;
output [32*nr_of_wb_ports_clk1-1:0] wb_dat_o_1;
input [0:nr_of_wb_ports_clk1-1] wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1;
input [36*nr_of_wb_ports_clk2-1:0] wb_adr_i_2;
input [36*nr_of_wb_ports_clk2-1:0] wb_dat_i_2;
output [32*nr_of_wb_ports_clk2-1:0] wb_dat_o_2;
input [0:nr_of_wb_ports_clk2-1] wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2;
input [36*nr_of_wb_ports_clk3-1:0] wb_adr_i_3;
input [36*nr_of_wb_ports_clk3-1:0] wb_dat_i_3;
output [32*nr_of_wb_ports_clk3-1:0] wb_dat_o_3;
input [0:nr_of_wb_ports_clk3-1] wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3;
input [0:nr_of_wb_clk_domains-1] wb_clk;
input [0:nr_of_wb_clk_domains-1] wb_rst;
// number of wb clock domains
parameter nr_of_wb_clk_domains = 1;
// number of wb ports in each wb clock domain
parameter nr_of_wb_ports_clk0 = 1;
parameter nr_of_wb_ports_clk1 = 0;
parameter nr_of_wb_ports_clk2 = 0;
parameter nr_of_wb_ports_clk3 = 0;
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
parameter [2:0] cl = 3'b010; // valid options 010, 011 used for SDR LMR
input [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_0;
input [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_0;
output [32*nr_of_wb_ports_clk0-1:0] wb_dat_o_0;
input [0:nr_of_wb_ports_clk0-1] wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0;
input [36*nr_of_wb_ports_clk1-1:0] wb_adr_i_1;
input [36*nr_of_wb_ports_clk1-1:0] wb_dat_i_1;
output [32*nr_of_wb_ports_clk1-1:0] wb_dat_o_1;
input [0:nr_of_wb_ports_clk1-1] wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1;
input [36*nr_of_wb_ports_clk2-1:0] wb_adr_i_2;
input [36*nr_of_wb_ports_clk2-1:0] wb_dat_i_2;
output [32*nr_of_wb_ports_clk2-1:0] wb_dat_o_2;
input [0:nr_of_wb_ports_clk2-1] wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2;
input [36*nr_of_wb_ports_clk3-1:0] wb_adr_i_3;
input [36*nr_of_wb_ports_clk3-1:0] wb_dat_i_3;
output [32*nr_of_wb_ports_clk3-1:0] wb_dat_o_3;
input [0:nr_of_wb_ports_clk3-1] wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3;
input [0:nr_of_wb_clk_domains-1] wb_clk;
input [0:nr_of_wb_clk_domains-1] wb_rst;
`ifdef SDR_16
output [1:0] ba_pad_o;
output [12:0] a_pad_o;
output cs_n_pad_o;
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
output reg [(`SDRAM_DATA_WIDTH)-1:0] dq_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output [1:0] dqm_pad_o;
input [(`SDRAM_DATA_WIDTH)-1:0] dq_i /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output dq_oe;
output cke_pad_o;
output [1:0] ba_pad_o;
output [12:0] a_pad_o;
output cs_n_pad_o;
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
output reg [15:0] dq_o;
output reg [1:0] dqm_pad_o;
input [15:0] dq_i;
output dq_oe;
output cke_pad_o;
`endif
`ifdef DDR_16
output ck_pad_o;
output ck_n_pad_o;
output cke_pad_o;
output ck_fb_pad_o;
input ck_fb_pad_i;
output cs_n_pad_o;
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
inout [1:0] dm_rdqs_pad_io;
output [1:0] ba_pad_o;
output [12:0] addr_pad_o;
inout [15:0] dq_pad_io;
inout [1:0] dqs_pad_io;
output dqs_oe;
inout [1:0] dqs_n_pad_io;
input [1:0] rdqs_n_pad_i;
output odt_pad_o;
output ck_pad_o;
output ck_n_pad_o;
output cke_pad_o;
output ck_fb_pad_o;
input ck_fb_pad_i;
output cs_n_pad_o;
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
inout [1:0] dm_rdqs_pad_io;
output [1:0] ba_pad_o;
output [12:0] addr_pad_o;
inout [15:0] dq_pad_io;
inout [1:0] dqs_pad_io;
output dqs_oe;
inout [1:0] dqs_n_pad_io;
input [1:0] rdqs_n_pad_i;
output odt_pad_o;
`endif
input sdram_clk, sdram_rst;
input sdram_clk, sdram_rst;
 
wire [0:15] fifo_empty[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
wire [35:0] fifo_dat_o[0:3];
wire [31:0] fifo_dat_i;
wire [0:15] fifo_we[0:3];
wire fifo_rd_adr, fifo_rd_data, fifo_wr, idle, count0;
wire [0:15] fifo_sel_i, fifo_sel_dly;
reg [0:15] fifo_sel_reg;
wire [1:0] fifo_sel_domain_i, fifo_sel_domain_dly;
reg [1:0] fifo_sel_domain_reg;
wire [0:15] fifo_empty[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
wire [35:0] fifo_dat_o[0:3];
wire [31:0] fifo_dat_i;
wire [0:15] fifo_we[0:3];
wire fifo_rd_adr, fifo_rd_data, fifo_wr, idle, count0;
wire [0:15] fifo_sel_i, fifo_sel_dly;
reg [0:15] fifo_sel_reg;
wire [1:0] fifo_sel_domain_i, fifo_sel_domain_dly;
reg [1:0] fifo_sel_domain_reg;
 
reg refresh_req;
wire [35:0] tx_fifo_dat_o; // tmp added /MF
 
generate
if (nr_of_wb_clk_domains > 0) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk0))
wb0
(
reg refresh_req;
generate
if (nr_of_wb_clk_domains > 0) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk0))
wb0(
// wishbone side
.wb_adr_i_v(wb_adr_i_0),
.wb_dat_i_v(wb_dat_i_0),
148,18 → 140,17
.sdram_fifo_we(fifo_we[0][0:nr_of_wb_ports_clk0-1]),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
end
if (nr_of_wb_ports_clk0 < 16) begin
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}};
end
endgenerate
end
if (nr_of_wb_ports_clk0 < 16) begin
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}};
end
endgenerate
 
generate
if (nr_of_wb_clk_domains > 1) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk1))
wb1
(
generate
if (nr_of_wb_clk_domains > 1) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk1))
wb1(
// wishbone side
.wb_adr_i_v(wb_adr_i_1),
.wb_dat_i_v(wb_dat_i_1),
180,21 → 171,20
.sdram_fifo_we(fifo_we[1][0:nr_of_wb_ports_clk1-1]),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk1 < 16) begin
if (nr_of_wb_ports_clk1 < 16) begin
assign fifo_empty[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b1}};
end
end else begin
assign fifo_empty[1] = {16{1'b1}};
assign fifo_dat_o[1] = {36{1'b0}};
end
endgenerate
end
end else begin
assign fifo_empty[1] = {16{1'b1}};
assign fifo_dat_o[1] = {36{1'b0}};
end
endgenerate
 
generate
if (nr_of_wb_clk_domains > 2) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk1))
wb2
(
generate
if (nr_of_wb_clk_domains > 2) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk1))
wb2(
// wishbone side
.wb_adr_i_v(wb_adr_i_2),
.wb_dat_i_v(wb_dat_i_2),
215,21 → 205,20
.sdram_fifo_we(fifo_we[2][0:nr_of_wb_ports_clk2-1]),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk2 < 16) begin
if (nr_of_wb_ports_clk2 < 16) begin
assign fifo_empty[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b1}};
end
end else begin
assign fifo_empty[2] = {16{1'b1}};
assign fifo_dat_o[2] = {36{1'b0}};
end
endgenerate
end
end else begin
assign fifo_empty[2] = {16{1'b1}};
assign fifo_dat_o[2] = {36{1'b0}};
end
endgenerate
 
generate
if (nr_of_wb_clk_domains > 3) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk3))
wb3
(
generate
if (nr_of_wb_clk_domains > 3) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk3))
wb3(
// wishbone side
.wb_adr_i_v(wb_adr_i_3),
.wb_dat_i_v(wb_dat_i_3),
250,134 → 239,117
.sdram_fifo_we(fifo_we[3][0:nr_of_wb_ports_clk3-1]),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk3 < 16) begin
if (nr_of_wb_ports_clk3 < 16) begin
assign fifo_empty[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b1}};
end
end else begin
assign fifo_empty[3] = {16{1'b1}};
assign fifo_dat_o[3] = {36{1'b0}};
end
endgenerate
end
end else begin
assign fifo_empty[3] = {16{1'b1}};
assign fifo_dat_o[3] = {36{1'b0}};
end
endgenerate
 
encode encode0
(
.fifo_empty_0(fifo_empty[0]), .fifo_empty_1(fifo_empty[1]), .fifo_empty_2(fifo_empty[2]), .fifo_empty_3(fifo_empty[3]),
.fifo_sel(fifo_sel_i), .fifo_sel_domain(fifo_sel_domain_i)
);
encode encode0 (
.fifo_empty_0(fifo_empty[0]), .fifo_empty_1(fifo_empty[1]), .fifo_empty_2(fifo_empty[2]), .fifo_empty_3(fifo_empty[3]),
.fifo_sel(fifo_sel_i), .fifo_sel_domain(fifo_sel_domain_i)
);
 
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst)
{fifo_sel_reg,fifo_sel_domain_reg} <= {16'h0,2'b00};
else
if (idle)
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst)
{fifo_sel_reg,fifo_sel_domain_reg} <= {16'h0,2'b00};
else
if (idle)
{fifo_sel_reg,fifo_sel_domain_reg} <= {fifo_sel_i,fifo_sel_domain_i};
end
end
 
decode decode0
(
.fifo_sel(fifo_sel_reg), .fifo_sel_domain(fifo_sel_domain_reg),
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3])
);
decode decode0 (
.fifo_sel(fifo_sel_reg), .fifo_sel_domain(fifo_sel_domain_reg),
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3])
);
 
// fifo_re[0-3] is a one-hot read enable structure
// fifo_empty should go active when chosen fifo queue is empty
assign current_fifo_empty = (idle) ? (!(|fifo_sel_i)) : (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3]));
// fifo_re[0-3] is a one-hot read enable structure
// fifo_empty should go active when chosen fifo queue is empty
assign current_fifo_empty = (idle) ? (!(|fifo_sel_i)) : (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3]));
 
decode decode1
(
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly),
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3])
);
decode decode1 (
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly),
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3])
);
 
`ifdef SDR_16
 
wire ref_cnt_zero;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_reg, dq_i_tmp_reg;
reg [17:0] dq_o_tmp_reg;
wire cmd_aref, cmd_read;
wire ref_cnt_zero;
reg [15:0] dq_i_reg, dq_i_tmp_reg;
reg [17:0] dq_o_tmp_reg;
wire cmd_aref, cmd_read;
// refresch counter
ref_counter ref_counter0( .zq(ref_cnt_zero), .rst(sdram_rst), .clk(sdram_clk));
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
// SDR SDRAM 16 FSM
fsm_sdr_16 # ( .ba_size(ba_size), .row_size(row_size), .col_size(col_size), .init_cl(cl))
fsm_sdr_16(
.adr_i({fifo_dat_o[fifo_sel_domain_reg][ba_size+row_size+col_size+6-2:6],1'b0}),
.we_i(fifo_dat_o[fifo_sel_domain_reg][5]),
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.fifo_empty(current_fifo_empty), .fifo_rd_adr(fifo_rd_adr), .fifo_rd_data(fifo_rd_data),
.state_idle(idle), .count0(count0),
.refresh_req(refresh_req),
.cmd_aref(cmd_aref), .cmd_read(cmd_read),
.ba(ba_pad_o), .a(a_pad_o), .cmd({ras_pad_o, cas_pad_o, we_pad_o}), .dq_oe(dq_oe),
.sdram_clk(sdram_clk), .sdram_rst(sdram_rst)
);
// refresch counter
ref_counter ref_counter0( .zq(ref_cnt_zero), .rst(sdram_rst), .clk(sdram_clk));
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
// SDR SDRAM 16 FSM
fsm_sdr_16 fsm_sdr_16_0
(
.adr_i({fifo_dat_o[fifo_sel_domain_reg][`BA_SIZE+`ROW_SIZE+`COL_SIZE+6-2:6],1'b0}),
.we_i(fifo_dat_o[fifo_sel_domain_reg][5]),
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.sel_i({fifo_dat_o[fifo_sel_domain_reg][3:2],dq_o_tmp_reg[1:0]}),
.fifo_empty(current_fifo_empty),
.fifo_rd_adr(fifo_rd_adr),
.fifo_rd_data(fifo_rd_data),
.state_idle(idle),
.count0(count0),
.refresh_req(refresh_req),
.cmd_aref(cmd_aref),
.cmd_read(cmd_read),
.ba(ba_pad_o), .a(a_pad_o),
.cmd({ras_pad_o, cas_pad_o, we_pad_o}),
.dq_oe(dq_oe),
.dqm(dqm_pad_o),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst)
);
/*
defparam fsm_sdr_16_0.ba_size = ba_size;
defparam fsm_sdr_16_0.row_size = row_size;
defparam fsm_sdr_16_0.col_size = col_size;
defparam fsm_sdr_16_0.init_cl = cl;
*/
assign cs_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
assign cs_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
 
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay0.depth=`INIT_CL+2;
defparam delay0.width=1;
delay delay0 (
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
end
defparam delay1.depth=`INIT_CL+2;
defparam delay1.width=2;
delay delay1 (
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
defparam delay2.depth=`INIT_CL+2;
defparam delay2.width=1;
delay delay2 (
.d(cmd_read),
.q(fifo_wr),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
defparam delay0.depth=cl+2;
defparam delay0.width=1;
delay delay0 (
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
end
defparam delay1.depth=cl+2;
defparam delay1.width=2;
delay delay1 (
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
defparam delay2.depth=cl+2;
defparam delay2.width=1;
delay delay2 (
.d(cmd_read),
.q(fifo_wr),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
 
// output registers
assign cs_n_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
always @ (posedge sdram_clk or posedge sdram_rst)
// output registers
assign cs_n_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{dq_i_reg, dq_i_tmp_reg} <= {16'h0000,16'h0000};
else
384,54 → 356,25
{dq_i_reg, dq_i_tmp_reg} <= {dq_i, dq_i_reg};
 
assign fifo_dat_i = {dq_i_tmp_reg, dq_i_reg};
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
dq_o_tmp_reg <= 18'h0;
else
dq_o_tmp_reg <= {fifo_dat_o[fifo_sel_domain_reg][19:4],fifo_dat_o[fifo_sel_domain_reg][1:0]};
// output dq_o mux and dffs
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
dq_o <= 16'h0000;
else
if (~count0)
dq_o <= fifo_dat_o[fifo_sel_domain_reg][35:20];
else
dq_o <= dq_o_tmp_reg[17:2];
/*
// data mask signals should be not(sel_i) for write and 2'b00 for read
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
dqm_pad_o <= 2'b00;
else
if (~count0)
dqm_pad_o <= ~fifo_dat_o[fifo_sel_domain_reg][3:2];
else
dqm_pad_o <= ~dq_o_tmp_reg[1:0];
*/
/*
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst) begin
{dq_o, dqm_pad_o} <= {16'h0000,2'b00};
{dq_o, dqm_pad_o} <= {16'h0000,2'b00};
dq_o_tmp_reg <= 18'h0;
end else
if (~count0) begin
dq_o <= fifo_dat_o[fifo_sel_domain_reg][35:20];
dq_o_tmp_reg[17:2] <= fifo_dat_o[fifo_sel_domain_reg][19:4];
if (cmd_read)
dqm_pad_o <= 2'b00;
else
dqm_pad_o <= ~fifo_dat_o[fifo_sel_domain_reg][3:2];
if (cmd_read)
dq_o_tmp_reg[1:0] <= 2'b00;
else
dq_o_tmp_reg[1:0] <= ~fifo_dat_o[fifo_sel_domain_reg][1:0];
if (~count0) begin
dq_o <= fifo_dat_o[fifo_sel_domain_reg][35:20];
dq_o_tmp_reg[17:2] <= fifo_dat_o[fifo_sel_domain_reg][19:4];
if (cmd_read)
dqm_pad_o <= 2'b00;
else
dqm_pad_o <= ~fifo_dat_o[fifo_sel_domain_reg][3:2];
if (cmd_read)
dq_o_tmp_reg[1:0] <= 2'b00;
else
dq_o_tmp_reg[1:0] <= ~fifo_dat_o[fifo_sel_domain_reg][1:0];
end else
{dq_o,dqm_pad_o} <= dq_o_tmp_reg;
*/
{dq_o,dqm_pad_o} <= dq_o_tmp_reg;
 
 
`endif // `ifdef SDR_16
442,45 → 385,71
wire sdram_clk_90, sdram_clk_180, sdram_clk_270;
wire ck_fb;
reg cke, ras, cas, we, cs_n;
reg cke_d, ras_d, cas_d, we_d, cs_n_d;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire [1:0] ba_o;
wire [12:0] addr_o;
reg [1:0] ba;
reg [12:0] addr;
reg [1:0] ba;
reg [1:0] ba_d;
reg [12:0] addr;
reg [12:0] addr_d;
wire dq_en, dqm_en;
reg [15:0] dq_tx_reg;
reg [15:0] dq_tx_reg;
wire [15:0] dq_tx;
reg [31:0] dq_rx_reg;
reg [31:0] dq_rx_reg;
wire [31:0] dq_rx;
wire [15:0] dq_o;
reg [3:0] dqm_tx_reg;
wire [3:0] dqm_tx;
wire [1:0] dqm_o, dqs_o, dqs_n_o;
reg [3:0] dqm_tx_reg;
wire [3:0] dqm_tx;
wire [1:0] dqm_o, dqs_o, dqs_n_o;
wire ref_delay, ref_delay_ack;
wire bl_en, bl_ack;
wire tx_fifo_re_i;
wire tx_fifo_re, tx_fifo_re_i;
wire adr_init_delay;
reg adr_init_delay_i;
reg [3:0] burst_cnt;
wire [3:0] burst_next_cnt, burst_length;
reg [3:0] burst_cnt;
wire [3:0] burst_next_cnt, burst_length;
wire burst_mask;
wire [12:0] cur_row;
// new
wire [3:0] burst_adr;
wire [2:0] tx_fifo_b_sel_i_cur;
wire [2:0] rx_fifo_a_sel_i;
wire [7:0] tx_fifo_empty;
wire rx_fifo_we;
 
wire ref_cnt_zero;
wire cmd_aref;
// refresh counter
ref_counter ref_counter0(
.zq(ref_cnt_zero),
.rst(sdram_rst),
.clk(sdram_clk));
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
// DDR SDRAM 16 FSM
ddr_16 ddr_16_0
(
ddr_16 ddr_16_0 (
.adr_init(adr_init),
.fifo_re(tx_fifo_re_i),
.fifo_re_d(tx_fifo_re),
.tx_fifo_dat_o(tx_fifo_dat_o),
.tx_fifo_dat_o(fifo_dat_o[fifo_sel_domain_reg]),
.burst_adr(burst_adr),
.fifo_empty(tx_fifo_empty),
.fifo_empty(current_fifo_empty),
.fifo_sel(tx_fifo_b_sel_i_cur),
.read(read),
.write(write),
.ref_req(ref_req),
.ref_ack(ref_ack),
.ref_req(refresh_req),
.ref_ack(cmd_aref),
.ref_delay(ref_delay),
.state_idle(idle),
.ref_delay_ack(ref_delay_ack),
.bl_en(bl_en),
.bl_ack(bl_ack),
488,51 → 457,45
.cmd({ras_o,cas_o,we_o}),
.cs_n(cs_n_o),
.cur_row(cur_row),
.sdram_clk(sdram_clk_0),
.wb_rst(wb_rst)
);
.clk(sdram_clk_0),
.rst(sdram_rst));
 
inc_adr inc_adr0
(
.adr_i(tx_fifo_dat_o[9:6]),
.bte_i(tx_fifo_dat_o[4:3]),
.cti_i(tx_fifo_dat_o[2:0]),
inc_adr inc_adr0 (
.adr_i(fifo_dat_o[fifo_sel_domain_reg][9:6]),
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.cti_i(fifo_dat_o[fifo_sel_domain_reg][2:0]),
.init(adr_init),
.inc(),
.adr_o(burst_adr),
.done(done),
.clk(sdram_clk_0),
.rst(wb_rst)
);
.rst(sdram_rst));
 
// Delay, refresh to activate/refresh
ref_delay_counter ref_delay_counter0
(
ref_delay_counter ref_delay_counter0 (
.cke(ref_delay),
.zq(ref_delay_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
.rst(sdram_rst));
// Burst length, DDR2 SDRAM
burst_length_counter burst_length_counter0
(
burst_length_counter burst_length_counter0 (
.cke(bl_en),
.zq(bl_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
.rst(sdram_rst));
 
// Wishbone burst length
assign burst_length = (adr_init && tx_fifo_dat_o[2:0] == 3'b000) ? 4'd1 : // classic cycle
(adr_init && tx_fifo_dat_o[2:0] == 3'b010) ? 4'd4 : // incremental burst cycle
burst_length;
assign burst_length =
(adr_init && fifo_dat_o[fifo_sel_domain_reg][2:0] == 3'b000) ? 4'd1 : // classic cycle
(adr_init && fifo_dat_o[fifo_sel_domain_reg][2:0] == 3'b010) ? 4'd4 : // incremental burst cycle
burst_length;
 
// Burst mask
// Burst length counter
assign burst_next_cnt = (burst_cnt == 3) ? 4'd0 : burst_cnt + 4'd1;
always @ (posedge sdram_clk_0 or posedge wb_rst)
if (wb_rst)
always @ (posedge sdram_clk_0 or posedge sdram_rst)
if (sdram_rst)
burst_cnt <= 4'h0;
else
if (bl_en)
541,88 → 504,142
assign burst_mask = (burst_cnt >= burst_length) ? 1'b1 : 1'b0;
 
// Control outports, DDR2 SDRAM
always @ (posedge sdram_clk_180 or posedge wb_rst)
if (wb_rst) begin
cs_n <= 1'b0;
cke <= 1'b0;
ras <= 1'b0;
cas <= 1'b0;
we <= 1'b0;
ba <= 2'b00;
addr <= 13'b0000000000000;
always @ (posedge sdram_clk_180 or posedge sdram_rst)
if (sdram_rst) begin
cs_n <= 1'b0;
cke <= 1'b0;
ras <= 1'b0;
cas <= 1'b0;
we <= 1'b0;
ba <= 2'b00;
addr <= 13'b0000000000000;
end
else begin
cs_n <= cs_n_o;
cke <= 1'b1;
ras <= ras_o;
cas <= cas_o;
we <= we_o;
ba <= ba_o;
addr <= addr_o;
cs_n <= cs_n_o;
cke <= 1'b1;
ras <= ras_o;
cas <= cas_o;
we <= we_o;
ba <= ba_o;
addr <= addr_o;
end
 
assign cke_pad_o = cke;
assign ras_pad_o = ras;
assign cas_pad_o = cas;
assign we_pad_o = we;
assign ba_pad_o = ba;
assign addr_pad_o = addr;
assign cs_n_pad_o = cs_n;
// Add one cycle delay to address and control to compensate for increased delay i wb fifos
always @ (posedge sdram_clk_180 or posedge sdram_rst)
if (sdram_rst) begin
cs_n_d <= 1'b0;
cke_d <= 1'b0;
ras_d <= 1'b0;
cas_d <= 1'b0;
we_d <= 1'b0;
ba_d <= 2'b00;
addr_d <= 13'b0000000000000;
end
else begin
cs_n_d <= cs_n;
cke_d <= cke;
ras_d <= ras;
cas_d <= cas;
we_d <= we;
ba_d <= ba;
addr_d <= addr;
end
 
// Assing outputs
// Non-DDR outputs
assign cke_pad_o = cke_d;
assign ras_pad_o = ras_d;
assign cas_pad_o = cas_d;
assign we_pad_o = we_d;
assign ba_pad_o = ba_d;
assign addr_pad_o = addr_d;
assign cs_n_pad_o = cs_n_d;
 
assign ck_fb_pad_o = ck_fb;
assign dqs_oe = dq_en;
 
// Read latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay0.depth=`INIT_CL+`AL+2;
defparam delay0.depth=`CL+`AL+2;
defparam delay0.width=4;
delay delay0
(
delay delay0 (
.d({read && !burst_mask,tx_fifo_b_sel_i_cur}),
.q({rx_fifo_we,rx_fifo_a_sel_i}),
.clk(sdram_clk_0),
.rst(wb_rst)
.rst(sdram_rst)
);
 
// temp assign rx_fifo_we to fifo_wr
assign fifo_wr = rx_fifo_we;
// write latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay1.depth=`INIT_CL+`AL-1;
// defparam delay1.depth=`CL+`AL-1;
defparam delay1.depth=`CL+`AL;
defparam delay1.width=2;
delay delay1
(
delay delay1 (
.d({write, burst_mask}),
.q({dq_en, dqm_en}),
.clk(sdram_clk_270),
.rst(wb_rst)
.rst(sdram_rst)
);
 
// if CL>3 delay read from Tx FIFO
defparam delay2.depth=`INIT_CL+`AL-3;
/* // if CL>3 delay read from Tx FIFO
defparam delay2.depth=`CL+`AL-3;
defparam delay2.width=1;
delay delay2
(
.d(tx_fifo_re_i && !burst_mask),
.q(tx_fifo_re),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
delay delay2 (
.d(tx_fifo_re_i && !burst_mask),
.q(tx_fifo_re),
.clk(sdram_clk_0),
.rst(sdram_rst)
);
*/
// if CL=3, no delay
//assign tx_fifo_re = tx_fifo_re_i && !burst_mask;
assign tx_fifo_re = tx_fifo_re_i && !burst_mask;
 
 
// temp assign tx_fifo_re to fifo_rd_adr
assign fifo_rd_adr = tx_fifo_re;
 
// New
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay10.depth=cl+2;
defparam delay10.width=1;
delay delay10 (
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
end
defparam delay11.depth=cl+2;
defparam delay11.width=2;
delay delay11 (
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
 
 
// Increment address
defparam delay3.depth=`INIT_CL+`AL-1;
defparam delay3.depth=`CL+`AL-1;
defparam delay3.width=1;
delay delay3
(
delay delay3 (
.d({write|read}),
.q({adr_inc}),
.clk(sdram_clk_0),
.rst(wb_rst)
.rst(sdram_rst)
);
 
// DCM/PLL with internal and external feedback
// Remove skew from internal and external clock
// Parameters are set in dcm_pll.v
dcm_pll dcm_pll_0
(
.rst(wb_rst),
dcm_pll dcm_pll_0 (
.rst(sdram_rst),
.clk_in(sdram_clk),
.clkfb_in(ck_fb_pad_i),
.clk0_out(sdram_clk_0),
633,8 → 650,7
);
 
// DDR2 IF
versatile_mem_ctrl_ddr versatile_mem_ctrl_ddr_0
(
versatile_mem_ctrl_ddr versatile_mem_ctrl_ddr_0 (
// DDR2 SDRAM ports
.ck_o(ck_pad_o),
.ck_n_o(ck_n_pad_o),
643,27 → 659,16
.dqs_n_io(dqs_n_pad_io),
.dm_rdqs_io(dm_rdqs_pad_io),
// Memory controller side
.tx_dat_i(tx_fifo_dat_o),
.rx_dat_o(rx_fifo_dat_i),
.tx_dat_i(fifo_dat_o[fifo_sel_domain_reg]),
.rx_dat_o(fifo_dat_i),
.dq_en(dq_en),
.dqm_en(dqm_en),
.wb_rst(wb_rst),
.sdram_clk_0(sdram_clk_0),
.sdram_clk_90(sdram_clk_90),
.sdram_clk_180(sdram_clk_180),
.sdram_clk_270(sdram_clk_270));
.rst(sdram_rst),
.clk_0(sdram_clk_0),
.clk_90(sdram_clk_90),
.clk_180(sdram_clk_180),
.clk_270(sdram_clk_270));
 
// Assing outputs
// Non-DDR outputs
assign ba_pad_o = ba;
assign addr_pad_o = addr;
assign dqs_oe = dq_en;
assign cke_pad_o = cke;
assign ras_pad_o = ras;
assign cas_pad_o = cas;
assign we_pad_o = we;
assign cs_n_pad_o = cs_n;
assign ck_fb_pad_o = ck_fb;
 
`endif // `ifdef DDR_16
/ddr_16.fzm
1,4 → 1,4
## File last modified by Fizzim: 3:40:29 PM on 2/23/10
## File last modified by Fizzim: 10:11:38 AM on 4/6/10
<version>
8.04.05
</version>
53,7 → 53,7
ABS
</status>
<value>
sdram_clk
clk
<status>
GLOBAL_VAR
</status>
97,7 → 97,7
ABS
</status>
<value>
wb_rst
rst
<status>
GLOBAL_VAR
</status>
314,7 → 314,7
-1
</page>
</ref_req>
<sdram_clk>
<clk>
<status>
GLOBAL_FIXED
</status>
357,8 → 357,8
<page>
-1
</page>
</sdram_clk>
<wb_rst>
</clk>
<rst>
<status>
GLOBAL_FIXED
</status>
401,8 → 401,8
<page>
-1
</page>
</wb_rst>
<fifo_empty[7:0]>
</rst>
<fifo_empty>
<status>
GLOBAL_FIXED
</status>
445,7 → 445,7
<page>
-1
</page>
</fifo_empty[7:0]>
</fifo_empty>
<fifo_sel[2:0]>
<status>
GLOBAL_FIXED
1163,7 → 1163,7
</status>
</value>
<vis>
0
2
<status>
GLOBAL_VAR
</status>
1196,6 → 1196,50
-1
</page>
</cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
comb
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</state_idle>
</outputs>
<state>
<name>
1693,10 → 1737,54
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
1725,7 → 1813,7
<page>
-1
</page>
</cur_row[12:0]>
</state_idle>
</state>
<trans>
<name>
1869,7 → 1957,7
</tabs>
## START PREFERENCES
<SCounter>
113
115
</SCounter>
<TCounter>
174
2407,10 → 2495,54
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
2439,7 → 2571,7
<page>
2
</page>
</cur_row[12:0]>
</state_idle>
</attributes>
<x0>
75
2962,10 → 3094,54
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
2994,7 → 3170,7
<page>
2
</page>
</cur_row[12:0]>
</state_idle>
</attributes>
<x0>
75
3736,10 → 3912,54
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
3768,7 → 3988,7
<page>
2
</page>
</cur_row[12:0]>
</state_idle>
</attributes>
<x0>
75
4021,7 → 4241,7
GLOBAL_FIXED
</status>
<value>
!(&fifo_empty)
!fifo_empty
<status>
LOCAL
</status>
4291,7 → 4511,7
</status>
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2
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<type>
output
18744,7 → 20020,7
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2
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<x0>
675
19267,10 → 20543,54
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2
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GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
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<vis>
2
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GLOBAL_VAR
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</vis>
<type>
output
19299,7 → 20619,7
<page>
2
</page>
</cur_row[12:0]>
</state_idle>
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<x0>
675
19822,10 → 21142,54
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<vis>
2
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GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
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<vis>
2
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GLOBAL_VAR
</status>
</vis>
<type>
output
19854,7 → 21218,7
<page>
2
</page>
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<x0>
675
20377,10 → 21741,54
</status>
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<vis>
2
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GLOBAL_VAR
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<type>
output
<status>
GLOBAL_VAR
</status>
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<vis>
2
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GLOBAL_VAR
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<type>
output
20409,7 → 21817,7
<page>
2
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<x0>
675
24658,10 → 26066,54
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2
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GLOBAL_VAR
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<type>
output
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GLOBAL_VAR
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<vis>
2
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GLOBAL_VAR
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<type>
output
24690,7 → 26142,7
<page>
2
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<x0>
675
25420,10 → 26872,54
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<vis>
2
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GLOBAL_VAR
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<type>
output
<status>
GLOBAL_VAR
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2
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GLOBAL_VAR
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<type>
output
25452,7 → 26948,7
<page>
3
</page>
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<x0>
475
26596,10 → 28092,54
</status>
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<vis>
2
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GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
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<comment>
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GLOBAL_VAR
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GLOBAL_FIXED
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1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
26628,7 → 28168,7
<page>
3
</page>
</cur_row[12:0]>
</state_idle>
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<x0>
75
27151,10 → 28691,54
</status>
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<vis>
2
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GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
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<comment>
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<status>
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</value>
<vis>
2
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GLOBAL_VAR
</status>
</vis>
<type>
output
27183,7 → 28767,7
<page>
3
</page>
</cur_row[12:0]>
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<x0>
75
27913,10 → 29497,54
</status>
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<vis>
2
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GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
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<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
27945,7 → 29573,7
<page>
3
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<x0>
475
28468,10 → 30096,54
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<vis>
2
<status>
GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
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<comment>
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<vis>
2
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GLOBAL_VAR
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</vis>
<type>
output
28500,7 → 30172,7
<page>
3
</page>
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<x0>
275
29023,10 → 30695,54
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<vis>
2
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GLOBAL_VAR
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output
<status>
GLOBAL_VAR
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<vis>
2
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GLOBAL_VAR
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<type>
output
29055,7 → 30771,7
<page>
3
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<x0>
75
30199,10 → 31915,54
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<vis>
2
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GLOBAL_VAR
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output
<status>
GLOBAL_VAR
</status>
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<comment>
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2
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30231,7 → 31991,7
<page>
3
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275
31825,10 → 33585,54
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output
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<comment>
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GLOBAL_VAR
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<vis>
2
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GLOBAL_VAR
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<type>
output
31857,7 → 33661,7
<page>
3
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<x0>
75
32794,10 → 34598,54
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<vis>
2
<status>
GLOBAL_VAR
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output
<status>
GLOBAL_VAR
</status>
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<comment>
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GLOBAL_VAR
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<vis>
2
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GLOBAL_VAR
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<type>
output
32826,7 → 34674,7
<page>
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<x0>
475
33349,7 → 35197,7
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33382,127 → 35230,12
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## START STATE TRANSITION OBJECT
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trans168
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1'b0
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33514,7 → 35247,7
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<page>
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33584,35 → 35296,8
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## END STATE TRANSITION OBJECT
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## END STATE OBJECT
## START STATE TRANSITION OBJECT
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33621,7 → 35306,7
ABS
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trans169
trans168
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LOCAL
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33665,7 → 35350,7
ABS
</status>
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!fifo_re_d
<status>
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33695,10 → 35380,10
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33709,9 → 35394,9
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1000
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GLOBAL_VAR
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## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
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trans170
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def_type
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GLOBAL_VAR
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<page>
3
34525,10 → 36003,54
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<vis>
2
<status>
GLOBAL_VAR
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output
<status>
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<vis>
2
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GLOBAL_VAR
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<type>
output
34557,7 → 36079,7
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3
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<x0>
475
35287,10 → 36809,54
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<vis>
2
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output
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</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
35319,7 → 36885,7
<page>
3
</page>
</cur_row[12:0]>
</state_idle>
</attributes>
<x0>
375
/versatile_mem_ctrl_ip.v
1462,7 → 1462,7
// BINARY counter
module burst_length_counter ( cke, zq, rst, clk);
 
parameter length = 3;
parameter length = 2;
input cke;
output reg zq;
input rst;
1474,7 → 1474,7
 
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
assign q_next = (qi == wrap_value) ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
always @ (posedge clk or posedge rst)
if (rst)
1492,24 → 1492,126
if (cke)
zq <= q_next == {length{1'b0}};
endmodule
`line 1 "sdr_16_defines.v" 1
//
// Specify either type of memory
// or
// BA_SIZE, ROW_SIZE, COL_SIZE and SDRAM_DATA_WIDTH
//
// either in this file or as command line option; +define+MT48LC16M16
//
 
// Most of these defines have an effect on things in fsm_sdr_16.v
 
//`define MT48LC16M16 // 32MB part
// 8MB part
 
 
 
 
 
 
`line 24 "sdr_16_defines.v" 0
// `ifdef MT48LC16M16
 
// using 1 of MT48LC4M16
// SDRAM data width is 16
 
// `ifdef MT48LC4M16
 
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
`line 48 "sdr_16_defines.v" 2
`line 1 "versatile_fifo_async_cmp.v" 1
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
 
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
wire direction;
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
1518,6 → 1620,8
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
 
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
1529,25 → 1633,57
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
 
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
 
 
 
`line 101 "versatile_fifo_async_cmp.v" 0
 
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule
 
endmodule // async_comp
`line 125 "versatile_fifo_async_cmp.v" 2
`line 1 "async_fifo_mq.v" 1
// async FIFO with multiple queues
 
module async_fifo_mq (
d, fifo_full, write, write_enable, clk1, rst1,
q, fifo_empty, read, read_enable, clk2, rst2
);
 
parameter a_hi_size = 4;
parameter a_lo_size = 4;
parameter nr_of_queues = 16;
parameter data_width = 36;
 
input [data_width-1:0] d;
output [0:nr_of_queues-1] fifo_full;
input write;
1554,6 → 1690,7
input [0:nr_of_queues-1] write_enable;
input clk1;
input rst1;
 
output [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
input read;
1560,6 → 1697,7
input [0:nr_of_queues-1] read_enable;
input clk2;
input rst2;
 
wire [a_lo_size-1:0] fifo_wadr_bin[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_wadr_gray[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_radr_bin[0:nr_of_queues-1];
1568,8 → 1706,10
reg [a_lo_size-1:0] radr;
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
 
genvar i;
integer j,k,l;
 
function [a_lo_size-1:0] onehot2bin;
input [0:nr_of_queues-1] a;
integer i;
1581,8 → 1721,10
end
end
endfunction
 
generate
for (i=0;i<nr_of_queues;i=i+1) begin : fifo_adr
gray_counter wadrcnt (
.cke(write & write_enable[i]),
.q(fifo_wadr_gray[i]),
1589,6 → 1731,7
.q_bin(fifo_wadr_bin[i]),
.rst(rst1),
.clk(clk1));
gray_counter radrcnt (
.cke(read & read_enable[i]),
.q(fifo_radr_gray[i]),
1595,6 → 1738,7
.q_bin(fifo_radr_bin[i]),
.rst(rst2),
.clk(clk2));
versatile_fifo_async_cmp
#(.ADDR_WIDTH(a_lo_size))
egresscmp (
1605,8 → 1749,11
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
end
endgenerate
 
// and-or mux write address
always @*
begin
wadr = {a_lo_size{1'b0}};
1614,6 → 1761,8
wadr = (fifo_wadr_bin[j] & {a_lo_size{write_enable[j]}}) | wadr;
end
end
 
// and-or mux read address
always @*
begin
radr = {a_lo_size{1'b0}};
1621,6 → 1770,7
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable[k]}}) | radr;
end
end
 
vfifo_dual_port_ram_dc_sw # ( .DATA_WIDTH(data_width), .ADDR_WIDTH(a_hi_size+a_lo_size))
dpram (
.d_a(d),
1630,17 → 1780,25
.q_b(q),
.adr_b({onehot2bin(read_enable),radr}),
.clk_b(clk2) );
 
endmodule
`line 111 "async_fifo_mq.v" 2
`line 1 "delay.v" 1
`timescale 1ns/1ns
module delay (d, q, clk, rst);
 
parameter width = 4;
parameter depth = 3;
 
input [width-1:0] d;
output [width-1:0] q;
input clk;
input rst;
 
reg [width-1:0] dffs [1:depth];
 
integer i;
always @ (posedge clk or posedge rst)
if (rst)
for ( i=1; i <= depth; i=i+1)
1651,16 → 1809,24
for ( i=2; i <= depth; i=i+1 )
dffs[i] <= dffs[i-1];
end
 
assign q = dffs[depth];
endmodule
endmodule //delay
 
`line 32 "delay.v" 2
`line 1 "codec.v" 1
`timescale 1ns/1ns
module encode (
fifo_empty_0, fifo_empty_1, fifo_empty_2, fifo_empty_3,
fifo_sel, fifo_sel_domain
);
 
input [0:15] fifo_empty_0, fifo_empty_1, fifo_empty_2, fifo_empty_3;
output [0:15] fifo_sel;
output [1:0] fifo_sel_domain;
 
function [0:15] encode;
input [0:15] a;
input [0:15] b;
1750,26 → 1916,78
endcase
end
endfunction
 
assign fifo_sel = encode( fifo_empty_0, fifo_empty_1, fifo_empty_2, fifo_empty_3);
assign fifo_sel_domain = (!(&fifo_empty_3)) ? 2'b11 :
(!(&fifo_empty_2)) ? 2'b10 :
(!(&fifo_empty_1)) ? 2'b01 :
2'b00;
endmodule
 
`timescale 1ns/1ns
module decode (
fifo_sel, fifo_sel_domain,
fifo_we_0, fifo_we_1, fifo_we_2, fifo_we_3
);
 
input [0:15] fifo_sel;
input [1:0] fifo_sel_domain;
output [0:15] fifo_we_0, fifo_we_1, fifo_we_2, fifo_we_3;
 
assign fifo_we_0 = (fifo_sel_domain == 2'b00) ? fifo_sel : {16{1'b0}};
assign fifo_we_1 = (fifo_sel_domain == 2'b01) ? fifo_sel : {16{1'b0}};
assign fifo_we_2 = (fifo_sel_domain == 2'b10) ? fifo_sel : {16{1'b0}};
assign fifo_we_3 = (fifo_sel_domain == 2'b11) ? fifo_sel : {16{1'b0}};
 
endmodule
`line 125 "codec.v" 2
`line 1 "gray_counter.v" 1
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// GRAY counter
module gray_counter ( cke, q, q_bin, rst, clk);
 
parameter length = 4;
input cke;
output reg [length:1] q;
1776,10 → 1994,13
output [length:1] q_bin;
input rst;
input clk;
 
parameter clear_value = 0;
 
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
 
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
1786,6 → 2007,7
else
if (cke)
qi <= q_next;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= {length{1'b0}};
1792,16 → 2014,24
else
if (cke)
q <= (q_next>>1) ^ q_next;
 
assign q_bin = qi;
 
endmodule
`line 76 "gray_counter.v" 2
`line 1 "egress_fifo.v" 1
// async FIFO with multiple queues, multiple data
 
module egress_fifo (
d, fifo_full, write, write_enable, clk1, rst1,
q, fifo_empty, read_adr, read_data, read_enable, clk2, rst2
);
 
parameter a_hi_size = 4;
parameter a_lo_size = 4;
parameter nr_of_queues = 16;
parameter data_width = 36;
 
input [data_width*nr_of_queues-1:0] d;
output [0:nr_of_queues-1] fifo_full;
input write;
1808,12 → 2038,16
input [0:nr_of_queues-1] write_enable;
input clk1;
input rst1;
output [data_width-1:0] q;
 
output reg [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
input read_adr, read_data;
input [0:nr_of_queues-1] read_enable;
input clk2;
input rst2;
 
wire [data_width-1:0] fifo_q;
wire [a_lo_size-1:0] fifo_wadr_bin[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_wadr_gray[0:nr_of_queues-1];
wire [a_lo_size-1:0] fifo_radr_bin[0:nr_of_queues-1];
1822,10 → 2056,13
reg [a_lo_size-1:0] radr;
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
 
reg read_adr_reg;
reg [0:nr_of_queues-1] read_enable_reg;
 
genvar i;
integer j,k,l;
 
function [a_lo_size-1:0] onehot2bin;
input [0:nr_of_queues-1] a;
integer i;
1837,11 → 2074,14
end
end
endfunction
 
// a pipeline stage for adress read gives higher clock frequency but adds one clock latency for adr read
always @ (posedge clk2 or posedge rst2)
if (rst2)
read_adr_reg <= 1'b0;
else
read_adr_reg <= read_adr;
always @ (posedge clk2 or posedge rst2)
if (rst2)
read_enable_reg <= {nr_of_queues{1'b0}};
1848,8 → 2088,11
else
if (read_adr)
read_enable_reg <= read_enable;
 
generate
for (i=0;i<nr_of_queues;i=i+1) begin : fifo_adr
gray_counter wadrcnt (
.cke(write & write_enable[i]),
.q(fifo_wadr_gray[i]),
1856,6 → 2099,7
.q_bin(fifo_wadr_bin[i]),
.rst(rst1),
.clk(clk1));
gray_counter radrcnt (
.cke((read_adr_reg | read_data) & read_enable_reg[i]),
.q(fifo_radr_gray[i]),
1862,6 → 2106,7
.q_bin(fifo_radr_bin[i]),
.rst(rst2),
.clk(clk2));
versatile_fifo_async_cmp
#(.ADDR_WIDTH(a_lo_size))
egresscmp (
1872,8 → 2117,11
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
end
endgenerate
 
// and-or mux write address
always @*
begin
wadr = {a_lo_size{1'b0}};
1881,6 → 2129,8
wadr = (fifo_wadr_bin[j] & {a_lo_size{write_enable[j]}}) | wadr;
end
end
 
// and-or mux read address
always @*
begin
radr = {a_lo_size{1'b0}};
1888,11 → 2138,14
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
 
// and-or mux write data
generate
for (i=0;i<nr_of_queues;i=i+1) begin : vector2array
assign wdataa[i] = d[(nr_of_queues-i)*data_width-1:(nr_of_queues-1-i)*data_width];
end
endgenerate
 
always @*
begin
wdata = {data_width{1'b0}};
1900,6 → 2153,9
wdata = (wdataa[l] & {data_width{write_enable[l]}}) | wdata;
end
end
 
 
vfifo_dual_port_ram_dc_sw # ( .DATA_WIDTH(data_width), .ADDR_WIDTH(a_hi_size+a_lo_size))
dpram (
.d_a(wdata),
1906,10 → 2162,18
.adr_a({onehot2bin(write_enable),wadr}),
.we_a(write),
.clk_a(clk1),
.q_b(q),
.q_b(fifo_q),
.adr_b({onehot2bin(read_enable_reg),radr}),
.clk_b(clk2) );
 
// Added registering of FIFO output to break a timing path
always@(posedge clk2)
q <= fifo_q;
 
endmodule
`line 153 "egress_fifo.v" 2
`line 1 "versatile_fifo_dual_port_ram_dc_sw.v" 1
module vfifo_dual_port_ram_dc_sw
(
d_a,
1937,12 → 2201,58
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
`line 28 "versatile_fifo_dual_port_ram_dc_sw.v" 2
`line 1 "dff_sr.v" 1
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module dff_sr ( aclr, aset, clock, data, q);
 
input aclr;
input aset;
input clock;
input data;
output reg q;
 
always @ (posedge clock or posedge aclr or posedge aset)
if (aclr)
q <= 1'b0;
1950,54 → 2260,104
q <= 1'b1;
else
q <= data;
 
endmodule
`line 60 "dff_sr.v" 2
`line 1 "ref_counter.v" 1
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
module ref_counter ( zq, rst, clk);
 
parameter length = 10;
output reg zq;
input rst;
input clk;
 
parameter clear_value = 0;
parameter set_value = 0;
parameter wrap_value = 417;
 
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
 
always @ (qi)
begin
case (length)
2: polynom = 32'b11;
3: polynom = 32'b110;
4: polynom = 32'b1100;
5: polynom = 32'b10100;
6: polynom = 32'b110000;
7: polynom = 32'b1100000;
8: polynom = 32'b10111000;
9: polynom = 32'b100010000;
10: polynom = 32'b1001000000;
11: polynom = 32'b10100000000;
12: polynom = 32'b100000101001;
13: polynom = 32'b1000000001100;
14: polynom = 32'b10000000010101;
15: polynom = 32'b110000000000000;
16: polynom = 32'b1101000000001000;
17: polynom = 32'b10010000000000000;
18: polynom = 32'b100000010000000000;
19: polynom = 32'b1000000000000100011;
20: polynom = 32'b10000010000000000000;
21: polynom = 32'b101000000000000000000;
22: polynom = 32'b1100000000000000000000;
23: polynom = 32'b10000100000000000000000;
24: polynom = 32'b111000010000000000000000;
25: polynom = 32'b1001000000000000000000000;
26: polynom = 32'b10000000000000000000100011;
27: polynom = 32'b100000000000000000000010011;
28: polynom = 32'b1100100000000000000000000000;
29: polynom = 32'b10100000000000000000000000000;
30: polynom = 32'b100000000000000000000000101001;
31: polynom = 32'b1001000000000000000000000000000;
32: polynom = 32'b10000000001000000000000000000011;
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10000010000000000000; // 0x82000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
2007,11 → 2367,15
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
 
 
 
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
2018,53 → 2382,129
else
zq <= q_next == {length{1'b0}};
endmodule
`line 119 "ref_counter.v" 2
`line 1 "fsm_sdr_16.v" 1
`timescale 1ns/1ns
`line 2 "fsm_sdr_16.v" 0
`line 1 "sdr_16_defines.v" 1
//
// Specify either type of memory
// or
// BA_SIZE, ROW_SIZE, COL_SIZE and SDRAM_DATA_WIDTH
//
// either in this file or as command line option; +define+MT48LC16M16
//
 
// Most of these defines have an effect on things in fsm_sdr_16.v
 
//`define MT48LC16M16 // 32MB part
// 8MB part
 
 
 
 
 
 
`line 24 "sdr_16_defines.v" 0
// `ifdef MT48LC16M16
 
// using 1 of MT48LC4M16
// SDRAM data width is 16
 
// `ifdef MT48LC4M16
 
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
`line 48 "sdr_16_defines.v" 2
`line 2 "fsm_sdr_16.v" 0
 
module fsm_sdr_16 (
adr_i, we_i, bte_i,
fifo_empty, fifo_rd_adr, fifo_rd_data, count0,
refresh_req, cmd_aref, cmd_read, state_idle,
ba, a, cmd, dq_oe,
sdram_clk, sdram_rst
);
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
input [ba_size+row_size+col_size-1:0] adr_i;
input we_i;
input [1:0] bte_i;
input fifo_empty;
output fifo_rd_adr, fifo_rd_data;
output count0;
input refresh_req;
output reg cmd_aref;
output reg cmd_read;
output state_idle;
output reg [1:0] ba;
output reg [12:0] a;
output reg [2:0] cmd;
output reg dq_oe;
input sdram_clk, sdram_rst;
wire [ba_size-1:0] bank;
wire [row_size-1:0] row;
wire [col_size-1:0] col;
wire [12:0] col_reg_a10_fix;
reg [4:0] counter;
reg [0:15] fifo_sel_reg_int;
reg [1:0] fifo_sel_domain_reg_int;
reg [1:0] ba_reg;
reg [row_size-1:0] row_reg;
reg [col_size-1:0] col_reg;
reg we_reg;
reg [1:0] bte_reg;
reg [row_size-1:0] open_row[0:3];
reg [0:3] open_ba;
wire current_bank_closed, current_row_open;
reg current_bank_closed_reg, current_row_open_reg;
parameter [1:0] linear = 2'b00,
adr_i, we_i, bte_i, sel_i,
fifo_empty, fifo_rd_adr, fifo_rd_data, count0,
refresh_req, cmd_aref, cmd_read, state_idle,
ba, a, cmd, dqm, dq_oe,
sdram_clk, sdram_rst
);
 
/* Now these are defined
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
*/
input [2+12+8-1:0] adr_i;
input we_i;
input [1:0] bte_i;
input [3:0] sel_i;
 
input fifo_empty;
output fifo_rd_adr, fifo_rd_data;
output reg count0;
 
input refresh_req;
output reg cmd_aref; // used for rerfresh ack
output reg cmd_read; // used for ingress fifo control
output state_idle; // state=idle
 
output reg [1:0] ba /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output reg [12:0] a /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output reg [2:0] cmd /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output reg [1:0] dqm /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output reg dq_oe;
 
input sdram_clk, sdram_rst;
 
wire [2-1:0] bank;
wire [12-1:0] row;
wire [8-1:0] col;
wire [12:0] col_reg_a10_fix;
reg [0:31] shreg;
wire stall; // active if write burst need data
 
reg [0:15] fifo_sel_reg_int;
reg [1:0] fifo_sel_domain_reg_int;
 
// adr_reg {ba,row,col,we}
reg [1:0] ba_reg;
reg [12-1:0] row_reg;
reg [8-1:0] col_reg;
reg we_reg;
reg [1:0] bte_reg;
 
// to keep track of open rows per bank
reg [12-1:0] open_row[0:3];
reg [0:3] open_ba;
wire current_bank_closed, current_row_open;
reg current_bank_closed_reg, current_row_open_reg;
 
parameter [1:0] linear = 2'b00,
beat4 = 2'b01,
beat8 = 2'b10,
beat16 = 2'b11;
parameter [2:0] cmd_nop = 3'b111,
 
parameter [2:0] cmd_nop = 3'b111,
cmd_act = 3'b011,
cmd_rd = 3'b101,
cmd_wr = 3'b100,
2071,7 → 2511,11
cmd_pch = 3'b010,
cmd_rfr = 3'b001,
cmd_lmr = 3'b000;
parameter [2:0] init = 3'b000,
 
// ctrl FSM
/* define instead of param, as synplify is doing weird things
parameter [2:0] init = 3'b000,
idle = 3'b001,
rfr = 3'b010,
adr = 3'b011,
2079,158 → 2523,227
act = 3'b101,
w4d = 3'b110,
rw = 3'b111;
reg [2:0] state, next;
function [12:0] a10_fix;
input [col_size-1:0] a;
integer i;
begin
for (i=0;i<13;i=i+1) begin
if (i<10)
if (i<col_size)
*/
reg [2:0] state, next;
 
function [12:0] a10_fix;
input [8-1:0] a;
integer i;
begin
for (i=0;i<13;i=i+1) begin
if (i<10)
if (i<8)
a10_fix[i] = a[i];
else
a10_fix[i] = 1'b0;
else if (i==10)
a10_fix[i] = 1'b0;
else
a10_fix[i] = 1'b0;
else if (i==10)
a10_fix[i] = 1'b0;
else
if (i<col_size)
if (i<8)
a10_fix[i] = a[i-1];
else
else
a10_fix[i] = 1'b0;
end
end
endfunction
assign {bank,row,col} = adr_i;
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{ba_reg,row_reg,col_reg,we_reg,bte_reg} <= {2'b00, {row_size{1'b0}}, {col_size{1'b0}}, 1'b0, 2'b00 };
else
if (state==adr & counter[1:0]==2'b10)
{ba_reg,row_reg,col_reg,we_reg,bte_reg} <= {bank,row,col,we_i,bte_i};
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
state <= init;
else
state <= next;
always @*
begin
next = 3'bx;
case (state)
init: if (counter==5'd31) next = idle;
else next = init;
idle: if (refresh_req) next = rfr;
else if (!fifo_empty) next = adr;
else next = idle;
rfr: if (counter==5'd5) next = idle;
else next = rfr;
adr: if (current_row_open_reg & (counter[1:0]==2'b11) & we_reg) next = w4d;
else if (current_row_open_reg & (counter[1:0]==2'b11)) next = rw;
else if (current_bank_closed_reg & (counter[1:0]==2'b11)) next = act;
else if ((counter[1:0]==2'b11)) next = pch;
else next = adr;
pch: if (counter[0]) next = act;
else next = pch;
act: if (counter[1:0]==2'd2 & !fifo_empty) next = rw;
else if (counter[1:0]==2'd2 & fifo_empty) next = w4d;
else next = act;
w4d: if (!fifo_empty) next = rw;
else next = w4d;
rw: casex ({bte_reg,counter})
{linear,5'bxxxx1},{beat4,5'bxx111},{beat8,5'bx1111},{beat16,5'b11111}: next = idle;
default: next = rw;
endcase
endcase
end
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst)
counter <= 5'd0;
else
if (state!=next)
counter <= 5'd0;
else
if (~(state==rw & next==rw & fifo_empty & counter[0] & we_reg))
counter <= counter + 5'd1;
end
assign count0 = counter[0];
parameter [0:0] init_wb = 1'b0;
parameter [2:0] init_cl = 3'b010;
parameter [0:0] init_bt = 1'b0;
parameter [2:0] init_bl = 3'b001;
assign col_reg_a10_fix = a10_fix(col_reg);
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst) begin
{ba,a,cmd} = {2'b00,13'd0,cmd_nop};
cmd_aref = 1'b0;
cmd_read = 1'b0;
dq_oe = 1'b0;
{open_ba,open_row[0],open_row[1],open_row[2],open_row[3]} <= {4'b0000,{row_size*4{1'b0}}};
end else begin
{ba,a,cmd} = {2'b00,13'd0,cmd_nop};
cmd_aref = 1'b0;
cmd_read = 1'b0;
dq_oe = 1'b0;
casex ({state,counter})
{init,5'd3}, {rfr,5'd0}: begin
{ba,a,cmd} = {2'b00, 13'b0010000000000, cmd_pch};
open_ba[ba_reg] <= 1'b0;
end
end
endfunction
 
 
assign {bank,row,col} = adr_i;
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
state <= 3'b000;
else
state <= next;
always @*
begin
next = 3'bx;
case (state)
3'b000: if (shreg[31]) next = 3'b001;
else next = 3'b000;
3'b001: if (refresh_req) next = 3'b010;
else if (!fifo_empty) next = 3'b011;
else next = 3'b001;
3'b010: if (shreg[5]) next = 3'b001;
else next = 3'b010;
3'b011: if (current_row_open_reg & (shreg[4]) & we_reg) next = 3'b110;
else if (current_row_open_reg & shreg[4]) next = 3'b111;
else if (current_bank_closed_reg & shreg[4]) next = 3'b101;
else if (shreg[4]) next = 3'b100;
else next = 3'b011;
3'b100: if (shreg[1]) next = 3'b101;
else next = 3'b100;
3'b101: if (shreg[2] & (!fifo_empty | !we_reg)) next = 3'b111;
else if (shreg[2] & fifo_empty) next = 3'b110;
else next = 3'b101;
3'b110: if (!fifo_empty) next = 3'b111;
else next = 3'b110;
3'b111: if (bte_reg==linear & shreg[1])
next = 3'b001;
else if (bte_reg==beat4 & shreg[7])
next = 3'b001;
else if (bte_reg==beat8 & shreg[15])
next = 3'b001;
else if (bte_reg==beat16 & shreg[31])
next = 3'b001;
else
next = 3'b111;
endcase
end
 
// active if write burst need data
assign stall = state==3'b111 & next==3'b111 & fifo_empty & count0 & we_reg;
 
// counter
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst) begin
shreg <= {1'b1,{31{1'b0}}};
count0 <= 1'b0;
end else
if (state!=next) begin
shreg <= {1'b1,{31{1'b0}}};
count0 <= 1'b0;
end else
if (~stall) begin
shreg <= shreg >> 1;
count0 <= ~count0;
end
{init,5'd7}, {init,5'd19}, {rfr,5'd2}:
{ba,a,cmd,cmd_aref} = {2'b00, 13'd0, cmd_rfr,1'b1};
{init,5'd31}:
{ba,a,cmd} = {2'b00,3'b000,init_wb,2'b00,init_cl,init_bt,init_bl, cmd_lmr};
{pch,5'bxxxx0}: begin
{ba,a,cmd} = {ba_reg,13'd0,cmd_pch};
open_ba <= 4'b0000;
end
{act,5'd0}: begin
{ba,a,cmd} = {ba_reg,(13'd0 | row_reg),cmd_act};
{open_ba[ba_reg],open_row[ba_reg]} <= {1'b1,row_reg};
end
{rw,5'bxxxxx}:
begin
if (we_reg & !counter[0])
cmd = cmd_wr;
else if (!counter[0])
{cmd,cmd_read} = {cmd_rd,1'b1};
else
cmd = cmd_nop;
if (we_reg)
dq_oe = 1'b1;
case (bte_reg)
linear: {ba,a} = {ba_reg,col_reg_a10_fix};
beat4: {ba,a} = {ba_reg,col_reg_a10_fix[12:3],col_reg_a10_fix[2:0] + counter[2:0]};
beat8: {ba,a} = {ba_reg,col_reg_a10_fix[12:4],col_reg_a10_fix[3:0] + counter[3:0]};
beat16: {ba,a} = {ba_reg,col_reg_a10_fix[12:5],col_reg_a10_fix[4:0] + counter[4:0]};
endcase
end
endcase
end
end
assign fifo_rd_adr = ((state==adr) & (counter[1:0]==2'b00)) ? 1'b1 : 1'b0;
assign fifo_rd_data = (state==w4d & !fifo_empty) ? 1'b1 :
((state==rw & next==rw) & we_reg & !counter[0] & !fifo_empty) ? 1'b1 :
1'b0;
assign state_idle = (state==idle);
assign current_bank_closed = !(open_ba[bank]);
assign current_row_open = open_ba[bank] & (open_row[bank]==row);
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{current_bank_closed_reg, current_row_open_reg} <= {1'b1, 1'b0};
else
{current_bank_closed_reg, current_row_open_reg} <= {current_bank_closed, current_row_open};
end
 
// ba, a, cmd
// col_reg_a10 has bit [10] set to zero to disable auto precharge
assign col_reg_a10_fix = a10_fix(col_reg);
 
// outputs dependent on state vector
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst) begin
{ba,a,cmd} <= {2'b00,13'd0,cmd_nop};
dqm <= 2'b11;
cmd_aref <= 1'b0;
cmd_read <= 1'b0;
dq_oe <= 1'b0;
{open_ba,open_row[0],open_row[1],open_row[2],open_row[3]} <=
{4'b0000,{12*4{1'b0}}};
{ba_reg,row_reg,col_reg,we_reg,bte_reg} <=
{2'b00, {12{1'b0}}, {8{1'b0}}, 1'b0, 2'b00 };
end else begin
{ba,a,cmd} <= {2'b00,13'd0,cmd_nop};
dqm <= 2'b11;
cmd_aref <= 1'b0;
cmd_read <= 1'b0;
dq_oe <= 1'b0;
case (state)
3'b000:
if (shreg[3]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
open_ba[ba_reg] <= 1'b0;
end else if (shreg[7] | shreg[19])
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1};
else if (shreg[31])
{ba,a,cmd} <=
{2'b00,3'b000,1'b0,2'b00,3'b010,1'b0,3'b001, cmd_lmr};
3'b010:
if (shreg[0]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
open_ba <= 4'b0000;
end else if (shreg[2])
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1};
3'b011:
if (shreg[3])
{ba_reg,row_reg,col_reg,we_reg,bte_reg} <=
{bank,row,col,we_i,bte_i};
3'b100:
if (shreg[0]) begin
{ba,a,cmd} <= {ba_reg,13'd0,cmd_pch};
//open_ba <= 4'b0000;
open_ba[ba_reg] <= 1'b0;
end
3'b101:
if (shreg[0]) begin
{ba,a,cmd} <= {ba_reg,(13'd0 | row_reg),cmd_act};
{open_ba[ba_reg],open_row[ba_reg]} <= {1'b1,row_reg};
end
3'b111:
begin
if (we_reg & !count0)
cmd <= cmd_wr;
else if (!count0)
{cmd,cmd_read} <= {cmd_rd,1'b1};
else
cmd <= cmd_nop;
if (we_reg & !count0)
dqm <= ~sel_i[3:2];
else if (we_reg & count0)
dqm <= ~sel_i[1:0];
else
dqm <= 2'b00;
if (we_reg)
dq_oe <= 1'b1;
if (~stall)
case (bte_reg)
linear: {ba,a} <= {ba_reg,col_reg_a10_fix};
beat4: {ba,a,col_reg[2:0]} <=
{ba_reg,col_reg_a10_fix, col_reg[2:0] + 3'd1};
beat8: {ba,a,col_reg[3:0]} <=
{ba_reg,col_reg_a10_fix, col_reg[3:0] + 4'd1};
beat16: {ba,a,col_reg[4:0]} <=
{ba_reg,col_reg_a10_fix, col_reg[4:0] + 5'd1};
endcase
end
endcase
end
end
 
// rd_adr goes high when next adr is fetched from sync RAM and during write burst
assign fifo_rd_adr = state==3'b011 & shreg[0];
assign fifo_rd_data = ((state==3'b111 & next==3'b111) &
we_reg & !count0 & !fifo_empty);
 
assign state_idle = (state==3'b001);
 
// bank and row open ?
assign current_bank_closed = !(open_ba[bank]);
assign current_row_open = open_ba[bank] & (open_row[bank]==row);
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{current_bank_closed_reg, current_row_open_reg} <= {1'b1, 1'b0};
else
//if (state==adr & counter[1:0]==2'b10)
{current_bank_closed_reg, current_row_open_reg} <=
{current_bank_closed, current_row_open};
 
endmodule
`line 290 "fsm_sdr_16.v" 2
`line 1 "versatile_mem_ctrl_wb.v" 1
`timescale 1ns/1ns
module versatile_mem_ctrl_wb (
// wishbone side
wb_adr_i_v, wb_dat_i_v, wb_dat_o_v,
wb_stb_i, wb_cyc_i, wb_ack_o,
wb_clk, wb_rst,
// SDRAM controller interface
sdram_dat_o, sdram_fifo_empty, sdram_fifo_rd_adr, sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_i, sdram_fifo_wr, sdram_fifo_we,
sdram_clk, sdram_rst
 
);
 
parameter nr_of_wb_ports = 3;
input [36*nr_of_wb_ports-1:0] wb_adr_i_v;
input [36*nr_of_wb_ports-1:0] wb_dat_i_v;
input [0:nr_of_wb_ports-1] wb_stb_i;
2239,6 → 2752,7
output [0:nr_of_wb_ports-1] wb_ack_o;
input wb_clk;
input wb_rst;
 
output [35:0] sdram_dat_o;
output [0:nr_of_wb_ports-1] sdram_fifo_empty;
input sdram_fifo_rd_adr, sdram_fifo_rd_data;
2248,6 → 2762,7
input [0:nr_of_wb_ports-1] sdram_fifo_we;
input sdram_clk;
input sdram_rst;
 
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
2254,87 → 2769,92
parameter wrap16 = 2'b11;
parameter classic = 3'b000;
parameter endofburst = 3'b111;
 
 
parameter idle = 2'b00;
parameter rd = 2'b01;
parameter wr = 2'b10;
parameter fe = 2'b11;
 
reg [1:0] wb_state[0:nr_of_wb_ports-1];
 
wire [35:0] wb_adr_i[0:nr_of_wb_ports-1];
wire [35:0] wb_dat_i[0:nr_of_wb_ports-1];
wire [36*nr_of_wb_ports-1:0] egress_fifo_di;
wire [31:0] wb_dat_o;
wire [0:nr_of_wb_ports-1] wb_wr_ack, wb_rd_ack, wr_adr;
reg [0:nr_of_wb_ports-1] wb_rd_ack_dly;
wire [0:nr_of_wb_ports-1] egress_fifo_full;
wire [0:nr_of_wb_ports-1] ingress_fifo_empty;
 
wire [0:nr_of_wb_ports] stall;
wire [0:nr_of_wb_ports-1] state_idle;
wire [0:nr_of_wb_ports-1] egress_fifo_we, egress_fifo_full;
wire [0:nr_of_wb_ports-1] ingress_fifo_re, ingress_fifo_empty;
 
genvar i;
 
assign stall[0] = 1'b0;
 
generate
for (i=0;i<nr_of_wb_ports;i=i+1) begin : vector2array
assign wb_adr_i[i] = wb_adr_i_v[(nr_of_wb_ports-i)*36-1:(nr_of_wb_ports-1-i)*36];
assign wb_dat_i[i] = wb_dat_i_v[(nr_of_wb_ports-i)*36-1:(nr_of_wb_ports-1-i)*36];
assign egress_fifo_di[(nr_of_wb_ports-i)*36-1:(nr_of_wb_ports-1-i)*36] = (wb_state[i]==idle) ? wb_adr_i[i] : wb_dat_i[i];
assign egress_fifo_di[(nr_of_wb_ports-i)*36-1:(nr_of_wb_ports-1-i)*36] = (state_idle[i]) ? wb_adr_i[i] : wb_dat_i[i];
end
endgenerate
 
generate
assign wb_wr_ack[0] = ((wb_state[0]==idle | wb_state[0]==wr) & wb_cyc_i[0] & wb_stb_i[0] & !egress_fifo_full[0]);
for (i=1;i<nr_of_wb_ports;i=i+1) begin : wr_ack
assign wb_wr_ack[i] = (|(wb_wr_ack[0:i-1])) ? 1'b0 : ((wb_state[i]==idle | wb_state[i]==wr) & wb_cyc_i[i] & wb_stb_i[i] & !egress_fifo_full[i]);
end
endgenerate
generate
assign wb_rd_ack[0] = ((wb_state[0]==rd) & wb_cyc_i[0] & wb_stb_i[0] & !ingress_fifo_empty[0]);
for (i=1;i<nr_of_wb_ports;i=i+1) begin : rd_ack
assign wb_rd_ack[i] = (|(wb_rd_ack[0:i-1])) ? 1'b0 : ((wb_state[i]==rd) & wb_cyc_i[i] & wb_stb_i[i] & !ingress_fifo_empty[i]);
end
endgenerate
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_rd_ack_dly <= {nr_of_wb_ports{1'b0}};
else
wb_rd_ack_dly <= wb_rd_ack;
generate
for (i=0;i<nr_of_wb_ports;i=i+1) begin : wb_ack
assign wb_ack_o[i] = (wb_state[i]==wr & wb_wr_ack[i]) | wb_rd_ack_dly[i];
end
endgenerate
generate
for (i=0;i<nr_of_wb_ports;i=i+1) begin : fsm
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_state[i] <= idle;
else
case (wb_state[i])
idle:
if (wb_wr_ack[i] & wb_adr_i[i][5])
wb_state[i] <= wr;
else if (wb_wr_ack[i])
wb_state[i] <= rd;
rd:
if ((wb_adr_i[i][2:0]==classic | wb_adr_i[i][2:0]==endofburst | wb_adr_i[i][4:3]==linear) & wb_ack_o[i])
wb_state[i] <= idle;
wr:
if ((wb_adr_i[i][2:0]==classic | wb_adr_i[i][2:0]==endofburst | wb_adr_i[i][4:3]==linear) & wb_ack_o[i])
wb_state[i] <= idle;
default: ;
endcase
fsm_wb fsm_wb_i (
.stall_i(stall[i]),
.stall_o(stall[i+1]),
.we_i (wb_adr_i[i][5]),
.cti_i(wb_adr_i[i][2:0]),
.bte_i(wb_adr_i[i][4:3]),
.stb_i(wb_stb_i[i]),
.cyc_i(wb_cyc_i[i]),
.ack_o(wb_ack_o[i]),
.egress_fifo_we(egress_fifo_we[i]),
.egress_fifo_full(egress_fifo_full[i]),
.ingress_fifo_re(ingress_fifo_re[i]),
.ingress_fifo_empty(ingress_fifo_empty[i]),
.state_idle(state_idle[i]),
.wb_clk(wb_clk),
.wb_rst(wb_rst)
);
end
endgenerate
 
egress_fifo # (.a_hi_size(4),.a_lo_size(4),.nr_of_queues(nr_of_wb_ports),.data_width(36))
egress_FIFO(
.d(egress_fifo_di), .fifo_full(egress_fifo_full), .write(|(wb_wr_ack)), .write_enable(wb_wr_ack),
.d(egress_fifo_di), .fifo_full(egress_fifo_full), .write(|(egress_fifo_we)), .write_enable(egress_fifo_we),
.q(sdram_dat_o), .fifo_empty(sdram_fifo_empty), .read_adr(sdram_fifo_rd_adr), .read_data(sdram_fifo_rd_data), .read_enable(sdram_fifo_re),
.clk1(wb_clk), .rst1(wb_rst), .clk2(sdram_clk), .rst2(sdram_rst)
);
 
async_fifo_mq # (.a_hi_size(4),.a_lo_size(4),.nr_of_queues(nr_of_wb_ports),.data_width(32))
ingress_FIFO(
.d(sdram_dat_i), .fifo_full(), .write(sdram_fifo_wr), .write_enable(sdram_fifo_we),
.q(wb_dat_o), .fifo_empty(ingress_fifo_empty), .read(|(wb_rd_ack)), .read_enable(wb_rd_ack),
.q(wb_dat_o), .fifo_empty(ingress_fifo_empty), .read(|(ingress_fifo_re)), .read_enable(ingress_fifo_re),
.clk1(sdram_clk), .rst1(sdram_rst), .clk2(wb_clk), .rst2(wb_rst)
);
 
assign wb_dat_o_v = {nr_of_wb_ports{wb_dat_o}};
 
endmodule
`line 114 "versatile_mem_ctrl_wb.v" 2
`line 1 "versatile_mem_ctrl_top.v" 1
`timescale 1ns/1ns
 
`line 4 "versatile_mem_ctrl_top.v" 0
 
 
module versatile_mem_ctrl_top
(
// wishbone side
wb_adr_i_0, wb_dat_i_0, wb_dat_o_0,
wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0,
wb_adr_i_1, wb_dat_i_1, wb_dat_o_1,
2344,36 → 2864,59
wb_adr_i_3, wb_dat_i_3, wb_dat_o_3,
wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3,
wb_clk, wb_rst,
 
ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o, dq_o, dqm_pad_o, dq_i, dq_oe, cke_pad_o,
 
 
 
`line 27 "versatile_mem_ctrl_top.v" 0
 
// SDRAM signals
sdram_clk, sdram_rst
);
 
// number of wb clock domains
parameter nr_of_wb_clk_domains = 1;
// number of wb ports in each wb clock domain
parameter nr_of_wb_ports_clk0 = 1;
parameter nr_of_wb_ports_clk1 = 0;
parameter nr_of_wb_ports_clk2 = 0;
parameter nr_of_wb_ports_clk3 = 0;
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
parameter [2:0] cl = 3'b010;
parameter [2:0] cl = 3'b010; // valid options 010, 011 used for SDR LMR
input [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_0;
input [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_0;
output [32*nr_of_wb_ports_clk0-1:0] wb_dat_o_0;
input [0:nr_of_wb_ports_clk0-1] wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0;
input [36*nr_of_wb_ports_clk1-1:0] wb_adr_i_1;
input [36*nr_of_wb_ports_clk1-1:0] wb_dat_i_1;
output [32*nr_of_wb_ports_clk1-1:0] wb_dat_o_1;
input [0:nr_of_wb_ports_clk1-1] wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1;
input [36*nr_of_wb_ports_clk2-1:0] wb_adr_i_2;
input [36*nr_of_wb_ports_clk2-1:0] wb_dat_i_2;
output [32*nr_of_wb_ports_clk2-1:0] wb_dat_o_2;
input [0:nr_of_wb_ports_clk2-1] wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2;
input [36*nr_of_wb_ports_clk3-1:0] wb_adr_i_3;
input [36*nr_of_wb_ports_clk3-1:0] wb_dat_i_3;
output [32*nr_of_wb_ports_clk3-1:0] wb_dat_o_3;
input [0:nr_of_wb_ports_clk3-1] wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3;
input [0:nr_of_wb_clk_domains-1] wb_clk;
input [0:nr_of_wb_clk_domains-1] wb_rst;
output [1:0] ba_pad_o;
output [12:0] a_pad_o;
output cs_n_pad_o;
2385,7 → 2928,31
input [15:0] dq_i;
output dq_oe;
output cke_pad_o;
 
 
`line 100 "versatile_mem_ctrl_top.v" 0
 
input sdram_clk, sdram_rst;
 
wire [0:15] fifo_empty[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
2393,17 → 2960,20
wire [31:0] fifo_dat_i;
wire [0:15] fifo_we[0:3];
wire fifo_rd_adr, fifo_rd_data, fifo_wr, idle, count0;
wire [0:15] fifo_sel_i, fifo_sel_dly;
reg [0:15] fifo_sel_reg;
wire [1:0] fifo_sel_domain_i, fifo_sel_domain_dly;
reg [1:0] fifo_sel_domain_reg;
 
reg refresh_req;
wire [35:0] tx_fifo_dat_o;
generate
if (nr_of_wb_clk_domains > 0) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk0))
wb0(
// wishbone side
.wb_adr_i_v(wb_adr_i_0),
.wb_dat_i_v(wb_dat_i_0),
.wb_dat_o_v(wb_dat_o_0),
2412,6 → 2982,7
.wb_ack_o(wb_ack_o_0),
.wb_clk(wb_clk[0]),
.wb_rst(wb_rst[0]),
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[0]),
.sdram_fifo_empty(fifo_empty[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
2427,11 → 2998,13
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}};
end
endgenerate
 
generate
if (nr_of_wb_clk_domains > 1) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk1))
wb1(
// wishbone side
.wb_adr_i_v(wb_adr_i_1),
.wb_dat_i_v(wb_dat_i_1),
.wb_dat_o_v(wb_dat_o_1),
2440,6 → 3013,7
.wb_ack_o(wb_ack_o_1),
.wb_clk(wb_clk[1]),
.wb_rst(wb_rst[1]),
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[1]),
.sdram_fifo_empty(fifo_empty[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
2458,11 → 3032,13
assign fifo_dat_o[1] = {36{1'b0}};
end
endgenerate
 
generate
if (nr_of_wb_clk_domains > 2) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk1))
wb2(
// wishbone side
.wb_adr_i_v(wb_adr_i_2),
.wb_dat_i_v(wb_dat_i_2),
.wb_dat_o_v(wb_dat_o_2),
2471,6 → 3047,7
.wb_ack_o(wb_ack_o_2),
.wb_clk(wb_clk[2]),
.wb_rst(wb_rst[2]),
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[2]),
.sdram_fifo_empty(fifo_empty[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
2489,11 → 3066,13
assign fifo_dat_o[2] = {36{1'b0}};
end
endgenerate
 
generate
if (nr_of_wb_clk_domains > 3) begin
versatile_mem_ctrl_wb
# (.nr_of_wb_ports(nr_of_wb_ports_clk3))
wb3(
// wishbone side
.wb_adr_i_v(wb_adr_i_3),
.wb_dat_i_v(wb_dat_i_3),
.wb_dat_o_v(wb_dat_o_3),
2502,6 → 3081,7
.wb_ack_o(wb_ack_o_3),
.wb_clk(wb_clk[3]),
.wb_rst(wb_rst[3]),
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[3]),
.sdram_fifo_empty(fifo_empty[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
2520,10 → 3100,12
assign fifo_dat_o[3] = {36{1'b0}};
end
endgenerate
 
encode encode0 (
.fifo_empty_0(fifo_empty[0]), .fifo_empty_1(fifo_empty[1]), .fifo_empty_2(fifo_empty[2]), .fifo_empty_3(fifo_empty[3]),
.fifo_sel(fifo_sel_i), .fifo_sel_domain(fifo_sel_domain_i)
);
 
always @ (posedge sdram_clk or posedge sdram_rst)
begin
if (sdram_rst)
2532,19 → 3114,29
if (idle)
{fifo_sel_reg,fifo_sel_domain_reg} <= {fifo_sel_i,fifo_sel_domain_i};
end
 
decode decode0 (
.fifo_sel(fifo_sel_reg), .fifo_sel_domain(fifo_sel_domain_reg),
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3])
);
 
// fifo_re[0-3] is a one-hot read enable structure
// fifo_empty should go active when chosen fifo queue is empty
assign current_fifo_empty = (idle) ? (!(|fifo_sel_i)) : (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3]));
 
decode decode1 (
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly),
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3])
);
 
 
wire ref_cnt_zero;
reg [15:0] dq_i_reg, dq_i_tmp_reg;
reg [17:0] dq_o_tmp_reg;
wire cmd_aref, cmd_read;
// refresch counter
ref_counter ref_counter0( .zq(ref_cnt_zero), .rst(sdram_rst), .clk(sdram_clk));
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
2554,6 → 3146,8
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
// SDR SDRAM 16 FSM
fsm_sdr_16 # ( .ba_size(ba_size), .row_size(row_size), .col_size(col_size), .init_cl(cl))
fsm_sdr_16(
.adr_i({fifo_dat_o[fifo_sel_domain_reg][ba_size+row_size+col_size+6-2:6],1'b0}),
2566,11 → 3160,14
.ba(ba_pad_o), .a(a_pad_o), .cmd({ras_pad_o, cas_pad_o, we_pad_o}), .dq_oe(dq_oe),
.sdram_clk(sdram_clk), .sdram_rst(sdram_rst)
);
assign cs_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
 
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay0.depth=cl+2;
defparam delay0.width=1;
delay delay0 (
2580,6 → 3177,7
.rst(sdram_rst)
);
end
defparam delay1.depth=cl+2;
defparam delay1.width=2;
delay delay1 (
2588,6 → 3186,7
.clk(sdram_clk),
.rst(sdram_rst)
);
defparam delay2.depth=cl+2;
defparam delay2.width=1;
delay delay2 (
2596,15 → 3195,21
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
 
// output registers
assign cs_n_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{dq_i_reg, dq_i_tmp_reg} <= {16'h0000,16'h0000};
else
{dq_i_reg, dq_i_tmp_reg} <= {dq_i, dq_i_reg};
 
assign fifo_dat_i = {dq_i_tmp_reg, dq_i_reg};
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst) begin
{dq_o, dqm_pad_o} <= {16'h0000,2'b00};
2623,7 → 3228,306
dq_o_tmp_reg[1:0] <= ~fifo_dat_o[fifo_sel_domain_reg][1:0];
end else
{dq_o,dqm_pad_o} <= dq_o_tmp_reg;
endmodule
 
 
// `ifdef SDR_16
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`line 681 "versatile_mem_ctrl_top.v" 0
// `ifdef DDR_16
endmodule // wb_sdram_ctrl_top
`line 684 "versatile_mem_ctrl_top.v" 2
`timescale 1ns/1ns
module ddr_16 (
output reg [14:0] a,
2636,17 → 3540,18
output reg read,
output reg ref_ack,
output reg ref_delay,
output reg state_idle,
output reg write,
input wire bl_ack,
input wire [3:0] burst_adr,
input wire [7:0] fifo_empty,
input wire clk,
input wire fifo_empty,
input wire fifo_re_d,
input wire [2:0] fifo_sel,
input wire ref_delay_ack,
input wire ref_req,
input wire sdram_clk,
input wire [35:0] tx_fifo_dat_o,
input wire wb_rst
input wire rst,
input wire [35:0] tx_fifo_dat_o
);
parameter
IDLE = 0,
2702,6 → 3607,7
read = 1'b0;
ref_ack = 1'b0;
ref_delay = 1'b0;
state_idle = 1'b0;
write = 1'b0;
case (1'b1)
state[IDLE] : begin
2737,11 → 3643,12
end
end
state[AWAIT_CMD] : begin
adr_init = !(&fifo_empty);
adr_init = !fifo_empty;
state_idle = 1'b1;
if (ref_req) begin
nextstate[AREF] = 1'b1;
end
else if (!(&fifo_empty)) begin
else if (!fifo_empty) begin
nextstate[NOP12] = 1'b1;
end
else begin
2943,13 → 3850,7
end
end
state[NOP_tWR] : begin
if (!(tx_fifo_dat_o[5]) && (cur_row == tx_fifo_dat_o[26:14])) begin
nextstate[READ_ADDR] = 1'b1;
end
else if (tx_fifo_dat_o[5] && (cur_row == tx_fifo_dat_o[26:14])) begin
nextstate[WRITE_ADDR] = 1'b1;
end
else begin
begin
nextstate[PRECHARGE] = 1'b1;
end
end
3009,14 → 3910,14
end
endcase
end
always @(posedge sdram_clk or posedge wb_rst) begin
if (wb_rst)
always @(posedge clk or posedge rst) begin
if (rst)
state <= 43'b0000000000000000000000000000000000000000001 << IDLE;
else
state <= nextstate;
end
always @(posedge sdram_clk or posedge wb_rst) begin
if (wb_rst) begin
always @(posedge clk or posedge rst) begin
if (rst) begin
a[14:0] <= 15'd0;
cmd[2:0] <= 3'b111;
cs_n <= 1'b1;
3269,7 → 4170,95
endcase
end
endmodule
`timescale 1ns/1ns
module fsm_wb (
stall_i, stall_o,
we_i, cti_i, bte_i, stb_i, cyc_i, ack_o,
egress_fifo_we, egress_fifo_full,
ingress_fifo_re, ingress_fifo_empty,
state_idle,
wb_clk, wb_rst
);
 
input stall_i;
output stall_o;
 
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, stb_i, cyc_i;
output ack_o;
output egress_fifo_we, ingress_fifo_re;
input egress_fifo_full, ingress_fifo_empty;
output state_idle;
input wb_clk, wb_rst;
 
reg ingress_fifo_read_reg;
 
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter endofburst = 3'b111;
 
parameter idle = 2'b00;
parameter rd = 2'b01;
parameter wr = 2'b10;
parameter fe = 2'b11;
reg [1:0] state;
 
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
state <= idle;
else
case (state)
idle:
if (we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= wr;
else if (!we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= rd;
wr:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= idle;
rd:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) & stb_i & cyc_i & ack_o)
state <= fe;
fe:
if (ingress_fifo_empty)
state <= idle;
default: ;
endcase
assign state_idle = (state==idle);
assign stall_o = (stall_i) ? 1'b1 :
(state==idle & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==rd & stb_i & cyc_i & !ingress_fifo_empty) ? 1'b1 :
(state==fe & !ingress_fifo_empty) ? 1'b1 :
1'b0;
assign egress_fifo_we = (state==idle & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;
assign ingress_fifo_re = (state==rd & stb_i & cyc_i & !ingress_fifo_empty & !stall_i) ? 1'b1 :
(state==fe & !ingress_fifo_empty & !stall_i) ? 1'b1:
1'b0;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
ingress_fifo_read_reg <= 1'b0;
else
ingress_fifo_read_reg <= ingress_fifo_re;
assign ack_o = (ingress_fifo_read_reg) ? 1'b1 :
(state==fe) ? 1'b0 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;
 
endmodule`timescale 1ns/1ns
module delay (d, q, clk, rst);
 
parameter width = 4;
3752,7 → 4741,7
// Memory controller side
tx_dat_i, rx_dat_o,
dq_en, dqm_en,
wb_rst, sdram_clk_0, sdram_clk_90, sdram_clk_180, sdram_clk_270
rst, clk_0, clk_90, clk_180, clk_270
);
 
output ck_o;
3764,14 → 4753,14
//input [1:0] rdqs_n_i;
//output odt_o;
input [35:0] tx_dat_i;
output [35:0] rx_dat_o;
output [31:0] rx_dat_o;
input dq_en;
input dqm_en;
input wb_rst;
input sdram_clk_0;
input sdram_clk_90;
input sdram_clk_180;
input sdram_clk_270;
input rst;
input clk_0;
input clk_90;
input clk_180;
input clk_270;
 
reg [31:0] dq_rx_reg;
wire [31:0] dq_rx;
3791,8 → 4780,8
// Generate clock with equal delay as data
ddr_ff_out ddr_ff_out_ck (
.Q(ck_o),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
3801,8 → 4790,8
 
ddr_ff_out ddr_ff_out_ck_n (
.Q(ck_n_o),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
3814,8 → 4803,8
for (i=0; i<2; i=i+1) begin:dqs_oddr
ddr_ff_out ddr_ff_out_dqs (
.Q(dqs_o[i]),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
3828,8 → 4817,8
for (i=0; i<2; i=i+1) begin:dqs_n_oddr
ddr_ff_out ddr_ff_out_dqs_n (
.Q(dqs_n_o[i]),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
3887,7 → 4876,7
 
 
// Data from Tx FIFO
always @ (posedge sdram_clk_270 or posedge wb_rst)
always @ (posedge clk_270 or posedge wb_rst)
if (wb_rst)
dq_tx_reg[15:0] <= 16'h0;
else
3903,8 → 4892,8
for (i=0; i<16; i=i+1) begin:data_out_oddr
ddr_ff_out ddr_ff_out_inst_0 (
.Q(dq_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(dq_tx[i]),
.D1(dq_tx_reg[i]),
3914,7 → 4903,7
endgenerate
 
// Data mask from Tx FIFO
always @ (posedge sdram_clk_270 or posedge wb_rst)
always @ (posedge clk_270 or posedge wb_rst)
if (wb_rst)
dqm_tx_reg[1:0] <= 2'b00;
else
3923,7 → 4912,7
else
dqm_tx_reg[1:0] <= tx_dat_i[1:0];
 
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst)
dqm_tx_reg[3:2] <= 2'b00;
else
3939,8 → 4928,8
for (i=0; i<2; i=i+1) begin:data_mask_oddr
ddr_ff_out ddr_ff_out_inst_1 (
.Q(dqm_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(!dqm_tx[i]),
.D1(!dqm_tx_reg[i]),
3969,8 → 4958,8
ddr_ff_in ddr_ff_in_inst_0 (
.Q0(dq_rx[i]),
.Q1(dq_rx[i+16]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(1'b1),
.D(dq_io[i]),
.R(wb_rst),
3979,19 → 4968,19
endgenerate
 
// Data to Rx FIFO
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[31:16] <= 16'h0;
else
dq_rx_reg[31:16] <= dq_rx[31:16];
 
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[15:0] <= 16'h0;
else
dq_rx_reg[15:0] <= dq_rx[15:0];
 
assign rx_dat_o = {dq_rx_reg, 4'h0};
assign rx_dat_o = dq_rx_reg;
`endif // INT_CLOCKED_DATA_CAPTURE
 
 
4019,19 → 5008,19
endgenerate
 
// Data to Rx FIFO
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[31:16] <= 16'h0;
else
dq_rx_reg[31:16] <= dq_rx[31:16];
 
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[15:0] <= 16'h0;
else
dq_rx_reg[15:0] <= dq_rx[15:0];
 
assign rx_dat_o = {dq_rx_reg, 4'h0};
assign rx_dat_o = dq_rx_reg;
`endif // DEL_DQS_DATA_CAPTURE_1
 
4087,7 → 5076,7
endgenerate
// Rise & fall clocked FF
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst) begin
dq_fall_1 <= 16'h0;
dq_rise_1 <= 16'h0;
4096,7 → 5085,7
dq_rise_1 <= dq_iddr_rise;
end
 
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst) begin
dq_fall_2 <= 16'h0;
dq_rise_2 <= 16'h0;
4106,7 → 5095,7
end
// Fall sync FF
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst) begin
dq_fall_3 <= 16'h0;
dq_rise_3 <= 16'h0;
4116,7 → 5105,6
end
// Mux
assign rx_dat_o[35:32] = 4'h0;
assign rx_dat_o[31:16] = dq_fall_1;
assign rx_dat_o[15:0] = dq_rise_1;
 
4165,8 → 5153,8
for (i=0; i<16; i=i+1) begin:data_out_oddr
ddr_ff_out ddr_ff_out_inst_0 (
.Q(dq_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(tx_dat_i[i+16+4]),
.D1(tx_dat_i[i+4]),
4187,8 → 5175,8
for (i=0; i<2; i=i+1) begin:data_mask_oddr
ddr_ff_out ddr_ff_out_inst_1 (
.Q(dqm_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(!dqm_tx[i+2]),
.D1(!dqm_tx[i]),
4209,8 → 5197,8
ddr_ff_in ddr_ff_in_inst_0 (
.Q0(dq_rx[i]),
.Q1(dq_rx[i+16]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(1'b1),
.D(dq_io[i]),
.R(wb_rst),
4219,13 → 5207,13
endgenerate
 
// Data to Rx FIFO
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst)
dq_rx_reg <= 32'h0;
else
dq_rx_reg <= dq_rx;
 
assign rx_dat_o = {dq_rx_reg, 4'h0};
assign rx_dat_o = dq_rx_reg;
`endif // INT_CLOCKED_DATA_CAPTURE
 
`ifdef DEL_DQS_DATA_CAPTURE_1
4368,8 → 5356,6
 
reg refresh_req;
wire [35:0] tx_fifo_dat_o; // tmp added /MF
 
generate
if (nr_of_wb_clk_domains > 0) begin
versatile_mem_ctrl_wb
4640,11 → 5626,14
wire sdram_clk_90, sdram_clk_180, sdram_clk_270;
wire ck_fb;
reg cke, ras, cas, we, cs_n;
reg cke_d, ras_d, cas_d, we_d, cs_n_d;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire [12:0] addr_o;
reg [1:0] ba;
reg [1:0] ba_d;
reg [12:0] addr;
reg [12:0] addr_d;
wire dq_en, dqm_en;
reg [15:0] dq_tx_reg;
wire [15:0] dq_tx;
4656,7 → 5645,7
wire [1:0] dqm_o, dqs_o, dqs_n_o;
wire ref_delay, ref_delay_ack;
wire bl_en, bl_ack;
wire tx_fifo_re_i;
wire tx_fifo_re, tx_fifo_re_i;
wire adr_init_delay;
reg adr_init_delay_i;
reg [3:0] burst_cnt;
4663,22 → 5652,45
wire [3:0] burst_next_cnt, burst_length;
wire burst_mask;
wire [12:0] cur_row;
// new
wire [3:0] burst_adr;
wire [2:0] tx_fifo_b_sel_i_cur;
wire [2:0] rx_fifo_a_sel_i;
wire [7:0] tx_fifo_empty;
wire rx_fifo_we;
 
wire ref_cnt_zero;
wire cmd_aref;
// refresh counter
ref_counter ref_counter0(
.zq(ref_cnt_zero),
.rst(sdram_rst),
.clk(sdram_clk));
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
// DDR SDRAM 16 FSM
ddr_16 ddr_16_0
(
ddr_16 ddr_16_0 (
.adr_init(adr_init),
.fifo_re(tx_fifo_re_i),
.fifo_re_d(tx_fifo_re),
.tx_fifo_dat_o(tx_fifo_dat_o),
.tx_fifo_dat_o(fifo_dat_o[fifo_sel_domain_reg]),
.burst_adr(burst_adr),
.fifo_empty(tx_fifo_empty),
.fifo_empty(current_fifo_empty),
.fifo_sel(tx_fifo_b_sel_i_cur),
.read(read),
.write(write),
.ref_req(ref_req),
.ref_ack(ref_ack),
.ref_req(refresh_req),
.ref_ack(cmd_aref),
.ref_delay(ref_delay),
.state_idle(idle),
.ref_delay_ack(ref_delay_ack),
.bl_en(bl_en),
.bl_ack(bl_ack),
4686,51 → 5698,45
.cmd({ras_o,cas_o,we_o}),
.cs_n(cs_n_o),
.cur_row(cur_row),
.sdram_clk(sdram_clk_0),
.wb_rst(wb_rst)
);
.clk(sdram_clk_0),
.rst(sdram_rst));
 
inc_adr inc_adr0
(
.adr_i(tx_fifo_dat_o[9:6]),
.bte_i(tx_fifo_dat_o[4:3]),
.cti_i(tx_fifo_dat_o[2:0]),
inc_adr inc_adr0 (
.adr_i(fifo_dat_o[fifo_sel_domain_reg][9:6]),
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.cti_i(fifo_dat_o[fifo_sel_domain_reg][2:0]),
.init(adr_init),
.inc(),
.adr_o(burst_adr),
.done(done),
.clk(sdram_clk_0),
.rst(wb_rst)
);
.rst(sdram_rst));
 
// Delay, refresh to activate/refresh
ref_delay_counter ref_delay_counter0
(
ref_delay_counter ref_delay_counter0 (
.cke(ref_delay),
.zq(ref_delay_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
.rst(sdram_rst));
// Burst length, DDR2 SDRAM
burst_length_counter burst_length_counter0
(
burst_length_counter burst_length_counter0 (
.cke(bl_en),
.zq(bl_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
.rst(sdram_rst));
 
// Wishbone burst length
assign burst_length = (adr_init && tx_fifo_dat_o[2:0] == 3'b000) ? 4'd1 : // classic cycle
(adr_init && tx_fifo_dat_o[2:0] == 3'b010) ? 4'd4 : // incremental burst cycle
burst_length;
assign burst_length =
(adr_init && fifo_dat_o[fifo_sel_domain_reg][2:0] == 3'b000) ? 4'd1 : // classic cycle
(adr_init && fifo_dat_o[fifo_sel_domain_reg][2:0] == 3'b010) ? 4'd4 : // incremental burst cycle
burst_length;
 
// Burst mask
// Burst length counter
assign burst_next_cnt = (burst_cnt == 3) ? 4'd0 : burst_cnt + 4'd1;
always @ (posedge sdram_clk_0 or posedge wb_rst)
if (wb_rst)
always @ (posedge sdram_clk_0 or posedge sdram_rst)
if (sdram_rst)
burst_cnt <= 4'h0;
else
if (bl_en)
4739,8 → 5745,8
assign burst_mask = (burst_cnt >= burst_length) ? 1'b1 : 1'b0;
 
// Control outports, DDR2 SDRAM
always @ (posedge sdram_clk_180 or posedge wb_rst)
if (wb_rst) begin
always @ (posedge sdram_clk_180 or posedge sdram_rst)
if (sdram_rst) begin
cs_n <= 1'b0;
cke <= 1'b0;
ras <= 1'b0;
4759,15 → 5765,48
addr <= addr_o;
end
 
assign cke_pad_o = cke;
assign ras_pad_o = ras;
assign cas_pad_o = cas;
assign we_pad_o = we;
assign ba_pad_o = ba;
assign addr_pad_o = addr;
assign cs_n_pad_o = cs_n;
// Add one cycle delay to address and control to compensate for increased delay i wb fifos
always @ (posedge sdram_clk_180 or posedge sdram_rst)
if (sdram_rst) begin
cke_d <= 1'b0;
ras_d <= 1'b0;
cas_d <= 1'b0;
we_d <= 1'b0;
ba_d <= 2'b00;
addr_d <= 13'b0000000000000;
cs_n_d <= 1'b0;
end
else begin
cke_d <= cke;
ras_d <= ras;
cas_d <= cas;
we_d <= we;
ba_d <= ba;
addr_d <= addr;
cs_n_d <= cs_n;
end
 
// Assing outputs
// Non-DDR outputs
// assign cke_pad_o = cke;
// assign ras_pad_o = ras;
// assign cas_pad_o = cas;
// assign we_pad_o = we;
// assign ba_pad_o = ba;
// assign addr_pad_o = addr;
// assign cs_n_pad_o = cs_n;
 
assign cke_pad_o = cke_d;
assign ras_pad_o = ras_d;
assign cas_pad_o = cas_d;
assign we_pad_o = we_d;
assign ba_pad_o = ba_d;
assign addr_pad_o = addr_d;
assign cs_n_pad_o = cs_n_d;
 
assign ck_fb_pad_o = ck_fb;
assign dqs_oe = dq_en;
 
// Read latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay0.depth=`CL+`AL+2;
defparam delay0.width=4;
4775,20 → 5814,24
.d({read && !burst_mask,tx_fifo_b_sel_i_cur}),
.q({rx_fifo_we,rx_fifo_a_sel_i}),
.clk(sdram_clk_0),
.rst(wb_rst)
.rst(sdram_rst)
);
 
// temp assign rx_fifo_we to fifo_wr
assign fifo_wr = rx_fifo_we;
// write latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay1.depth=`CL+`AL-1;
// defparam delay1.depth=`CL+`AL-1;
defparam delay1.depth=`CL+`AL;
defparam delay1.width=2;
delay delay1 (
.d({write, burst_mask}),
.q({dq_en, dqm_en}),
.clk(sdram_clk_270),
.rst(wb_rst)
.rst(sdram_rst)
);
 
// if CL>3 delay read from Tx FIFO
/* // if CL>3 delay read from Tx FIFO
defparam delay2.depth=`CL+`AL-3;
defparam delay2.width=1;
delay delay2 (
4795,12 → 5838,42
.d(tx_fifo_re_i && !burst_mask),
.q(tx_fifo_re),
.clk(sdram_clk_0),
.rst(wb_rst)
.rst(sdram_rst)
);
 
*/
// if CL=3, no delay
//assign tx_fifo_re = tx_fifo_re_i && !burst_mask;
assign tx_fifo_re = tx_fifo_re_i && !burst_mask;
 
 
// temp assign tx_fifo_re to fifo_rd_adr
assign fifo_rd_adr = tx_fifo_re;
 
// New
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay10.depth=cl+2;
defparam delay10.width=1;
delay delay10 (
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
end
defparam delay11.depth=cl+2;
defparam delay11.width=2;
delay delay11 (
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
 
 
// Increment address
defparam delay3.depth=`CL+`AL-1;
defparam delay3.width=1;
4808,7 → 5881,7
.d({write|read}),
.q({adr_inc}),
.clk(sdram_clk_0),
.rst(wb_rst)
.rst(sdram_rst)
);
 
// DCM/PLL with internal and external feedback
4815,7 → 5888,7
// Remove skew from internal and external clock
// Parameters are set in dcm_pll.v
dcm_pll dcm_pll_0 (
.rst(wb_rst),
.rst(sdram_rst),
.clk_in(sdram_clk),
.clkfb_in(ck_fb_pad_i),
.clk0_out(sdram_clk_0),
4835,27 → 5908,16
.dqs_n_io(dqs_n_pad_io),
.dm_rdqs_io(dm_rdqs_pad_io),
// Memory controller side
.tx_dat_i(tx_fifo_dat_o),
.rx_dat_o(rx_fifo_dat_i),
.tx_dat_i(fifo_dat_o[fifo_sel_domain_reg]),
.rx_dat_o(fifo_dat_i),
.dq_en(dq_en),
.dqm_en(dqm_en),
.wb_rst(wb_rst),
.sdram_clk_0(sdram_clk_0),
.sdram_clk_90(sdram_clk_90),
.sdram_clk_180(sdram_clk_180),
.sdram_clk_270(sdram_clk_270));
.rst(sdram_rst),
.clk_0(sdram_clk_0),
.clk_90(sdram_clk_90),
.clk_180(sdram_clk_180),
.clk_270(sdram_clk_270));
 
// Assing outputs
// Non-DDR outputs
assign ba_pad_o = ba;
assign addr_pad_o = addr;
assign dqs_oe = dq_en;
assign cke_pad_o = cke;
assign ras_pad_o = ras;
assign cas_pad_o = cas;
assign we_pad_o = we;
assign cs_n_pad_o = cs_n;
assign ck_fb_pad_o = ck_fb;
 
`endif // `ifdef DDR_16
/versatile_mem_ctrl_ddr.v
7,7 → 7,7
// Memory controller side
tx_dat_i, rx_dat_o,
dq_en, dqm_en,
wb_rst, sdram_clk_0, sdram_clk_90, sdram_clk_180, sdram_clk_270
rst, clk_0, clk_90, clk_180, clk_270
);
 
output ck_o;
19,14 → 19,14
//input [1:0] rdqs_n_i;
//output odt_o;
input [35:0] tx_dat_i;
output [35:0] rx_dat_o;
output [31:0] rx_dat_o;
input dq_en;
input dqm_en;
input wb_rst;
input sdram_clk_0;
input sdram_clk_90;
input sdram_clk_180;
input sdram_clk_270;
input rst;
input clk_0;
input clk_90;
input clk_180;
input clk_270;
 
reg [31:0] dq_rx_reg;
wire [31:0] dq_rx;
46,8 → 46,8
// Generate clock with equal delay as data
ddr_ff_out ddr_ff_out_ck (
.Q(ck_o),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
56,8 → 56,8
 
ddr_ff_out ddr_ff_out_ck_n (
.Q(ck_n_o),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
69,8 → 69,8
for (i=0; i<2; i=i+1) begin:dqs_oddr
ddr_ff_out ddr_ff_out_dqs (
.Q(dqs_o[i]),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
83,8 → 83,8
for (i=0; i<2; i=i+1) begin:dqs_n_oddr
ddr_ff_out ddr_ff_out_dqs_n (
.Q(dqs_n_o[i]),
.C0(sdram_clk_0),
.C1(sdram_clk_180),
.C0(clk_0),
.C1(clk_180),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
142,7 → 142,7
 
 
// Data from Tx FIFO
always @ (posedge sdram_clk_270 or posedge wb_rst)
always @ (posedge clk_270 or posedge wb_rst)
if (wb_rst)
dq_tx_reg[15:0] <= 16'h0;
else
158,8 → 158,8
for (i=0; i<16; i=i+1) begin:data_out_oddr
ddr_ff_out ddr_ff_out_inst_0 (
.Q(dq_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(dq_tx[i]),
.D1(dq_tx_reg[i]),
169,7 → 169,7
endgenerate
 
// Data mask from Tx FIFO
always @ (posedge sdram_clk_270 or posedge wb_rst)
always @ (posedge clk_270 or posedge wb_rst)
if (wb_rst)
dqm_tx_reg[1:0] <= 2'b00;
else
178,7 → 178,7
else
dqm_tx_reg[1:0] <= tx_dat_i[1:0];
 
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst)
dqm_tx_reg[3:2] <= 2'b00;
else
194,8 → 194,8
for (i=0; i<2; i=i+1) begin:data_mask_oddr
ddr_ff_out ddr_ff_out_inst_1 (
.Q(dqm_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(!dqm_tx[i]),
.D1(!dqm_tx_reg[i]),
224,8 → 224,8
ddr_ff_in ddr_ff_in_inst_0 (
.Q0(dq_rx[i]),
.Q1(dq_rx[i+16]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(1'b1),
.D(dq_io[i]),
.R(wb_rst),
234,19 → 234,19
endgenerate
 
// Data to Rx FIFO
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[31:16] <= 16'h0;
else
dq_rx_reg[31:16] <= dq_rx[31:16];
 
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[15:0] <= 16'h0;
else
dq_rx_reg[15:0] <= dq_rx[15:0];
 
assign rx_dat_o = {dq_rx_reg, 4'h0};
assign rx_dat_o = dq_rx_reg;
`endif // INT_CLOCKED_DATA_CAPTURE
 
 
274,19 → 274,19
endgenerate
 
// Data to Rx FIFO
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[31:16] <= 16'h0;
else
dq_rx_reg[31:16] <= dq_rx[31:16];
 
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst)
dq_rx_reg[15:0] <= 16'h0;
else
dq_rx_reg[15:0] <= dq_rx[15:0];
 
assign rx_dat_o = {dq_rx_reg, 4'h0};
assign rx_dat_o = dq_rx_reg;
`endif // DEL_DQS_DATA_CAPTURE_1
 
342,7 → 342,7
endgenerate
// Rise & fall clocked FF
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst) begin
dq_fall_1 <= 16'h0;
dq_rise_1 <= 16'h0;
351,7 → 351,7
dq_rise_1 <= dq_iddr_rise;
end
 
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst) begin
dq_fall_2 <= 16'h0;
dq_rise_2 <= 16'h0;
361,7 → 361,7
end
// Fall sync FF
always @ (posedge sdram_clk_0 or posedge wb_rst)
always @ (posedge clk_0 or posedge wb_rst)
if (wb_rst) begin
dq_fall_3 <= 16'h0;
dq_rise_3 <= 16'h0;
371,7 → 371,6
end
// Mux
assign rx_dat_o[35:32] = 4'h0;
assign rx_dat_o[31:16] = dq_fall_1;
assign rx_dat_o[15:0] = dq_rise_1;
 
420,8 → 419,8
for (i=0; i<16; i=i+1) begin:data_out_oddr
ddr_ff_out ddr_ff_out_inst_0 (
.Q(dq_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(tx_dat_i[i+16+4]),
.D1(tx_dat_i[i+4]),
442,8 → 441,8
for (i=0; i<2; i=i+1) begin:data_mask_oddr
ddr_ff_out ddr_ff_out_inst_1 (
.Q(dqm_o[i]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(dq_en),
.D0(!dqm_tx[i+2]),
.D1(!dqm_tx[i]),
464,8 → 463,8
ddr_ff_in ddr_ff_in_inst_0 (
.Q0(dq_rx[i]),
.Q1(dq_rx[i+16]),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.C0(clk_270),
.C1(clk_90),
.CE(1'b1),
.D(dq_io[i]),
.R(wb_rst),
474,13 → 473,13
endgenerate
 
// Data to Rx FIFO
always @ (posedge sdram_clk_180 or posedge wb_rst)
always @ (posedge clk_180 or posedge wb_rst)
if (wb_rst)
dq_rx_reg <= 32'h0;
else
dq_rx_reg <= dq_rx;
 
assign rx_dat_o = {dq_rx_reg, 4'h0};
assign rx_dat_o = dq_rx_reg;
`endif // INT_CLOCKED_DATA_CAPTURE
 
`ifdef DEL_DQS_DATA_CAPTURE_1
/Makefile
37,11 → 37,11
ddr_16.v: ddr_16_generated.v
vppreproc --simple $^ > $@
 
fifo_adr_counter.v:
@echo;echo "\tThis file,"$@", doesn't exist, is it still needed?!. \n\tMake will now stop";echo
ls notexisting
#fifo_adr_counter.v:
# @echo;echo "\tThis file,"$@", doesn't exist, is it still needed?!. \n\tMake will now stop";echo
# ls notexisting
 
VERSATILE_MEM_CTRL_IP_FILES=versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v fifo_adr_counter.v ctrl_counter.v fifo.v fifo_fill.v inc_adr.v ref_counter.v ref_delay_counter.v pre_delay_counter.v burst_length_counter.v sdr_16.v ddr_16.v delay.v ddr_ff.v dcm_pll.v dff_sr.v versatile_mem_ctrl_ddr.v versatile_mem_ctrl_top.v
VERSATILE_MEM_CTRL_IP_FILES=versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v ctrl_counter.v fifo.v fifo_fill.v inc_adr.v ref_counter.v ref_delay_counter.v pre_delay_counter.v burst_length_counter.v sdr_16.v ddr_16.v fsm_wb.v delay.v ddr_ff.v dcm_pll.v dff_sr.v versatile_mem_ctrl_ddr.v versatile_mem_ctrl_top.v
 
versatile_mem_ctrl_ip.v: $(VERSATILE_MEM_CTRL_IP_FILES)
cat $^ | cat copyright.v - > $@

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