URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/rtl/verilog
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/versatile_mem_ctrl_top.v
385,14 → 385,14
wire sdram_clk_90, sdram_clk_180, sdram_clk_270; |
wire ck_fb; |
reg cke, ras, cas, we, cs_n; |
reg cke_d, ras_d, cas_d, we_d, cs_n_d; |
wire cke_d, ras_d, cas_d, we_d, cs_n_d; |
wire ras_o, cas_o, we_o, cs_n_o; |
wire [1:0] ba_o; |
wire [12:0] addr_o; |
reg [1:0] ba; |
reg [1:0] ba_d; |
wire [1:0] ba_d; |
reg [12:0] addr; |
reg [12:0] addr_d; |
wire [12:0] addr_d; |
wire dq_en, dqm_en; |
reg [15:0] dq_tx_reg; |
wire [15:0] dq_tx; |
411,7 → 411,7
wire [3:0] burst_next_cnt, burst_length; |
wire burst_mask; |
wire [12:0] cur_row; |
// new |
// |
wire [3:0] burst_adr; |
wire [2:0] tx_fifo_b_sel_i_cur; |
wire [2:0] rx_fifo_a_sel_i; |
503,110 → 503,68
// Burst Mask |
assign burst_mask = (burst_cnt >= burst_length) ? 1'b1 : 1'b0; |
|
// Control outports, DDR2 SDRAM |
always @ (posedge sdram_clk_180 or posedge sdram_rst) |
if (sdram_rst) begin |
cs_n <= 1'b0; |
cke <= 1'b0; |
ras <= 1'b0; |
cas <= 1'b0; |
we <= 1'b0; |
ba <= 2'b00; |
addr <= 13'b0000000000000; |
end |
else begin |
cs_n <= cs_n_o; |
cke <= 1'b1; |
ras <= ras_o; |
cas <= cas_o; |
we <= we_o; |
ba <= ba_o; |
addr <= addr_o; |
end |
// Delay address and control to compensate for delay in Tx FIOFs |
defparam delay0.depth=2; |
defparam delay0.width=20; |
delay delay0 ( |
.d({cs_n_o,1'b1,ras_o,cas_o,we_o,ba_o,addr_o}), |
.q({cs_n_d,cke_d,ras_d,cas_d,we_d,ba_d,addr_d}), |
.clk(sdram_clk_180), |
.rst(sdram_rst)); |
|
// Add one cycle delay to address and control to compensate for increased delay i wb fifos |
always @ (posedge sdram_clk_180 or posedge sdram_rst) |
if (sdram_rst) begin |
cs_n_d <= 1'b0; |
cke_d <= 1'b0; |
ras_d <= 1'b0; |
cas_d <= 1'b0; |
we_d <= 1'b0; |
ba_d <= 2'b00; |
addr_d <= 13'b0000000000000; |
end |
else begin |
cs_n_d <= cs_n; |
cke_d <= cke; |
ras_d <= ras; |
cas_d <= cas; |
we_d <= we; |
ba_d <= ba; |
addr_d <= addr; |
end |
|
// Assing outputs |
// Non-DDR outputs |
assign cke_pad_o = cke_d; |
assign ras_pad_o = ras_d; |
assign cas_pad_o = cas_d; |
assign we_pad_o = we_d; |
assign ba_pad_o = ba_d; |
assign addr_pad_o = addr_d; |
assign cs_n_pad_o = cs_n_d; |
|
assign cs_n_pad_o = cs_n_d; |
assign cke_pad_o = cke_d; |
assign ras_pad_o = ras_d; |
assign cas_pad_o = cas_d; |
assign we_pad_o = we_d; |
assign ba_pad_o = ba_d; |
assign addr_pad_o = addr_d; |
assign ck_fb_pad_o = ck_fb; |
assign dqs_oe = dq_en; |
|
// Read latency, delay the control signals to fit latency of the DDR2 SDRAM |
defparam delay0.depth=`CL+`AL+2; |
defparam delay0.width=4; |
delay delay0 ( |
.d({read && !burst_mask,tx_fifo_b_sel_i_cur}), |
.q({rx_fifo_we,rx_fifo_a_sel_i}), |
defparam delay1.depth=`CL+`AL+3; |
defparam delay1.width=1; |
delay delay1 ( |
.d(read && !burst_mask), |
.q(fifo_wr), |
.clk(sdram_clk_0), |
.rst(sdram_rst) |
); |
.rst(sdram_rst)); |
|
// temp assign rx_fifo_we to fifo_wr |
assign fifo_wr = rx_fifo_we; |
|
// write latency, delay the control signals to fit latency of the DDR2 SDRAM |
// defparam delay1.depth=`CL+`AL-1; |
defparam delay1.depth=`CL+`AL; |
defparam delay1.width=2; |
delay delay1 ( |
defparam delay2.depth=`CL+`AL; |
defparam delay2.width=2; |
delay delay2 ( |
.d({write, burst_mask}), |
.q({dq_en, dqm_en}), |
.clk(sdram_clk_270), |
.rst(sdram_rst) |
); |
.rst(sdram_rst)); |
|
/* // if CL>3 delay read from Tx FIFO |
defparam delay2.depth=`CL+`AL-3; |
defparam delay2.width=1; |
delay delay2 ( |
defparam delay3.depth=`CL+`AL-3; |
defparam delay3.width=1; |
delay delay3 ( |
.d(tx_fifo_re_i && !burst_mask), |
.q(tx_fifo_re), |
.clk(sdram_clk_0), |
.rst(sdram_rst) |
); |
.rst(sdram_rst)); |
*/ |
|
// if CL=3, no delay |
assign tx_fifo_re = tx_fifo_re_i && !burst_mask; |
|
|
// temp assign tx_fifo_re to fifo_rd_adr |
// assign tx_fifo_re to fifo_rd_adr |
assign fifo_rd_adr = tx_fifo_re; |
|
// New |
// |
genvar i; |
generate |
for (i=0; i < 16; i=i+1) begin : dly |
|
defparam delay10.depth=cl+2; |
defparam delay10.width=1; |
delay delay10 ( |
defparam delay4.depth=cl+2; |
defparam delay4.width=1; |
delay delay4 ( |
.d(fifo_sel_reg[i]), |
.q(fifo_sel_dly[i]), |
.clk(sdram_clk), |
614,9 → 572,9
); |
end |
|
defparam delay11.depth=cl+2; |
defparam delay11.width=2; |
delay delay11 ( |
defparam delay5.depth=cl+2; |
defparam delay5.width=2; |
delay delay5 ( |
.d(fifo_sel_domain_reg), |
.q(fifo_sel_domain_dly), |
.clk(sdram_clk), |
626,9 → 584,9
|
|
// Increment address |
defparam delay3.depth=`CL+`AL-1; |
defparam delay3.width=1; |
delay delay3 ( |
defparam delay6.depth=`CL+`AL-1; |
defparam delay6.width=1; |
delay delay6 ( |
.d({write|read}), |
.q({adr_inc}), |
.clk(sdram_clk_0), |
/versatile_mem_ctrl_ip.v
3238,14 → 3238,14
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3357,57 → 3357,17
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3414,7 → 3374,6
|
|
|
|
|
|
|
3427,13 → 3386,8
|
|
|
|
|
|
|
|
|
|
|
|
|
3441,7 → 3395,6
|
|
|
|
|
|
|
3523,11 → 3476,11
|
|
|
`line 681 "versatile_mem_ctrl_top.v" 0 |
`line 633 "versatile_mem_ctrl_top.v" 0 |
// `ifdef DDR_16 |
|
endmodule // wb_sdram_ctrl_top |
`line 684 "versatile_mem_ctrl_top.v" 2 |
`line 636 "versatile_mem_ctrl_top.v" 2 |
`timescale 1ns/1ns |
module ddr_16 ( |
output reg [14:0] a, |
5626,14 → 5579,14
wire sdram_clk_90, sdram_clk_180, sdram_clk_270; |
wire ck_fb; |
reg cke, ras, cas, we, cs_n; |
reg cke_d, ras_d, cas_d, we_d, cs_n_d; |
wire cke_d, ras_d, cas_d, we_d, cs_n_d; |
wire ras_o, cas_o, we_o, cs_n_o; |
wire [1:0] ba_o; |
wire [12:0] addr_o; |
reg [1:0] ba; |
reg [1:0] ba_d; |
wire [1:0] ba_d; |
reg [12:0] addr; |
reg [12:0] addr_d; |
wire [12:0] addr_d; |
wire dq_en, dqm_en; |
reg [15:0] dq_tx_reg; |
wire [15:0] dq_tx; |
5652,7 → 5605,7
wire [3:0] burst_next_cnt, burst_length; |
wire burst_mask; |
wire [12:0] cur_row; |
// new |
// |
wire [3:0] burst_adr; |
wire [2:0] tx_fifo_b_sel_i_cur; |
wire [2:0] rx_fifo_a_sel_i; |
5744,58 → 5697,18
// Burst Mask |
assign burst_mask = (burst_cnt >= burst_length) ? 1'b1 : 1'b0; |
|
// Control outports, DDR2 SDRAM |
always @ (posedge sdram_clk_180 or posedge sdram_rst) |
if (sdram_rst) begin |
cs_n <= 1'b0; |
cke <= 1'b0; |
ras <= 1'b0; |
cas <= 1'b0; |
we <= 1'b0; |
ba <= 2'b00; |
addr <= 13'b0000000000000; |
end |
else begin |
cs_n <= cs_n_o; |
cke <= 1'b1; |
ras <= ras_o; |
cas <= cas_o; |
we <= we_o; |
ba <= ba_o; |
addr <= addr_o; |
end |
// Delay address and control to compensate for delay in Tx FIOFs |
defparam delay0.depth=2; |
defparam delay0.width=20; |
delay delay0 ( |
.d({cs_n_o,1'b1,ras_o,cas_o,we_o,ba_o,addr_o}), |
.q({cs_n_d,cke_d,ras_d,cas_d,we_d,ba_d,addr_d}), |
.clk(sdram_clk_180), |
.rst(sdram_rst)); |
|
// Add one cycle delay to address and control to compensate for increased delay i wb fifos |
always @ (posedge sdram_clk_180 or posedge sdram_rst) |
if (sdram_rst) begin |
cke_d <= 1'b0; |
ras_d <= 1'b0; |
cas_d <= 1'b0; |
we_d <= 1'b0; |
ba_d <= 2'b00; |
addr_d <= 13'b0000000000000; |
cs_n_d <= 1'b0; |
end |
else begin |
cke_d <= cke; |
ras_d <= ras; |
cas_d <= cas; |
we_d <= we; |
ba_d <= ba; |
addr_d <= addr; |
cs_n_d <= cs_n; |
end |
|
// Assing outputs |
// Non-DDR outputs |
// assign cke_pad_o = cke; |
// assign ras_pad_o = ras; |
// assign cas_pad_o = cas; |
// assign we_pad_o = we; |
// assign ba_pad_o = ba; |
// assign addr_pad_o = addr; |
// assign cs_n_pad_o = cs_n; |
|
assign cs_n_pad_o = cs_n_d; |
assign cke_pad_o = cke_d; |
assign ras_pad_o = ras_d; |
assign cas_pad_o = cas_d; |
5802,44 → 5715,36
assign we_pad_o = we_d; |
assign ba_pad_o = ba_d; |
assign addr_pad_o = addr_d; |
assign cs_n_pad_o = cs_n_d; |
|
assign ck_fb_pad_o = ck_fb; |
assign dqs_oe = dq_en; |
|
// Read latency, delay the control signals to fit latency of the DDR2 SDRAM |
defparam delay0.depth=`CL+`AL+2; |
defparam delay0.width=4; |
delay delay0 ( |
.d({read && !burst_mask,tx_fifo_b_sel_i_cur}), |
.q({rx_fifo_we,rx_fifo_a_sel_i}), |
defparam delay1.depth=`CL+`AL+3; |
defparam delay1.width=1; |
delay delay1 ( |
.d(read && !burst_mask), |
.q(fifo_wr), |
.clk(sdram_clk_0), |
.rst(sdram_rst) |
); |
.rst(sdram_rst)); |
|
// temp assign rx_fifo_we to fifo_wr |
assign fifo_wr = rx_fifo_we; |
|
// write latency, delay the control signals to fit latency of the DDR2 SDRAM |
// defparam delay1.depth=`CL+`AL-1; |
defparam delay1.depth=`CL+`AL; |
defparam delay1.width=2; |
delay delay1 ( |
defparam delay2.depth=`CL+`AL; |
defparam delay2.width=2; |
delay delay2 ( |
.d({write, burst_mask}), |
.q({dq_en, dqm_en}), |
.clk(sdram_clk_270), |
.rst(sdram_rst) |
); |
.rst(sdram_rst)); |
|
/* // if CL>3 delay read from Tx FIFO |
defparam delay2.depth=`CL+`AL-3; |
defparam delay2.width=1; |
delay delay2 ( |
defparam delay3.depth=`CL+`AL-3; |
defparam delay3.width=1; |
delay delay3 ( |
.d(tx_fifo_re_i && !burst_mask), |
.q(tx_fifo_re), |
.clk(sdram_clk_0), |
.rst(sdram_rst) |
); |
.rst(sdram_rst)); |
*/ |
// if CL=3, no delay |
assign tx_fifo_re = tx_fifo_re_i && !burst_mask; |
5848,14 → 5753,14
// temp assign tx_fifo_re to fifo_rd_adr |
assign fifo_rd_adr = tx_fifo_re; |
|
// New |
// |
genvar i; |
generate |
for (i=0; i < 16; i=i+1) begin : dly |
|
defparam delay10.depth=cl+2; |
defparam delay10.width=1; |
delay delay10 ( |
defparam delay4.depth=cl+2; |
defparam delay4.width=1; |
delay delay4 ( |
.d(fifo_sel_reg[i]), |
.q(fifo_sel_dly[i]), |
.clk(sdram_clk), |
5863,9 → 5768,9
); |
end |
|
defparam delay11.depth=cl+2; |
defparam delay11.width=2; |
delay delay11 ( |
defparam delay5.depth=cl+2; |
defparam delay5.width=2; |
delay delay5 ( |
.d(fifo_sel_domain_reg), |
.q(fifo_sel_domain_dly), |
.clk(sdram_clk), |
5875,9 → 5780,9
|
|
// Increment address |
defparam delay3.depth=`CL+`AL-1; |
defparam delay3.width=1; |
delay delay3 ( |
defparam delay6.depth=`CL+`AL-1; |
defparam delay6.width=1; |
delay delay6 ( |
.d({write|read}), |
.q({adr_inc}), |
.clk(sdram_clk_0), |
/sdr_16.v
1357,190 → 1357,128
|
`line 4 "versatile_mem_ctrl_top.v" 0 |
|
|
|
`line 6 "versatile_mem_ctrl_top.v" 0 |
`line 1 "sdr_16_defines.v" 1 |
// |
// Specify either type of memory |
// or |
// BA_SIZE, ROW_SIZE, COL_SIZE and SDRAM_DATA_WIDTH |
// |
// either in this file or as command line option; +define+MT48LC16M16 |
// |
|
// Most of these defines have an effect on things in fsm_sdr_16.v |
|
//`define MT48LC16M16 // 32MB part |
// 8MB part |
|
|
|
|
|
|
|
|
|
|
|
|
`line 24 "sdr_16_defines.v" 0 |
// `ifdef MT48LC16M16 |
|
|
// using 1 of MT48LC4M16 |
// SDRAM data width is 16 |
|
|
|
|
|
|
// `ifdef MT48LC4M16 |
|
// LMR |
// [12:10] reserved |
// [9] WB, write burst; 0 - programmed burst length, 1 - single location |
// [8:7] OP Mode, 2'b00 |
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3 |
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved |
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page |
|
|
|
|
`line 48 "sdr_16_defines.v" 2 |
`line 6 "versatile_mem_ctrl_top.v" 0 |
|
|
module versatile_mem_ctrl_top |
( |
// wishbone side |
wb_adr_i_0, wb_dat_i_0, wb_dat_o_0, |
wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0, |
wb_adr_i_1, wb_dat_i_1, wb_dat_o_1, |
wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1, |
wb_adr_i_2, wb_dat_i_2, wb_dat_o_2, |
wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2, |
wb_adr_i_3, wb_dat_i_3, wb_dat_o_3, |
wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3, |
wb_clk, wb_rst, |
// wishbone side |
wb_adr_i_0, wb_dat_i_0, wb_dat_o_0, |
wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0, |
wb_adr_i_1, wb_dat_i_1, wb_dat_o_1, |
wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1, |
wb_adr_i_2, wb_dat_i_2, wb_dat_o_2, |
wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2, |
wb_adr_i_3, wb_dat_i_3, wb_dat_o_3, |
wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3, |
wb_clk, wb_rst, |
|
|
ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o, dq_o, dqm_pad_o, dq_i, dq_oe, cke_pad_o, |
ba_pad_o, a_pad_o, cs_n_pad_o, ras_pad_o, cas_pad_o, we_pad_o, dq_o, dqm_pad_o, dq_i, dq_oe, cke_pad_o, |
|
|
|
|
|
|
|
|
|
|
`line 29 "versatile_mem_ctrl_top.v" 0 |
`line 27 "versatile_mem_ctrl_top.v" 0 |
|
// SDRAM signals |
sdram_clk, sdram_rst |
); |
|
// number of wb clock domains |
parameter nr_of_wb_clk_domains = 1; |
// number of wb ports in each wb clock domain |
parameter nr_of_wb_ports_clk0 = 1; |
parameter nr_of_wb_ports_clk1 = 0; |
parameter nr_of_wb_ports_clk2 = 0; |
parameter nr_of_wb_ports_clk3 = 0; |
|
/* |
// Now these are defines, synthesis tool was doing strange things! jb |
parameter ba_size = 2; |
parameter row_size = 13; |
parameter col_size = 9; |
parameter [2:0] cl = 3'b010; // valid options 010, 011 used for SDR LMR |
*/ |
|
input [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_0; |
input [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_0; |
output [32*nr_of_wb_ports_clk0-1:0] wb_dat_o_0; |
input [0:nr_of_wb_ports_clk0-1] wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0; |
|
input [36*nr_of_wb_ports_clk1-1:0] wb_adr_i_1; |
input [36*nr_of_wb_ports_clk1-1:0] wb_dat_i_1; |
output [32*nr_of_wb_ports_clk1-1:0] wb_dat_o_1; |
input [0:nr_of_wb_ports_clk1-1] wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1; |
|
input [36*nr_of_wb_ports_clk2-1:0] wb_adr_i_2; |
input [36*nr_of_wb_ports_clk2-1:0] wb_dat_i_2; |
output [32*nr_of_wb_ports_clk2-1:0] wb_dat_o_2; |
input [0:nr_of_wb_ports_clk2-1] wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2; |
|
input [36*nr_of_wb_ports_clk3-1:0] wb_adr_i_3; |
input [36*nr_of_wb_ports_clk3-1:0] wb_dat_i_3; |
output [32*nr_of_wb_ports_clk3-1:0] wb_dat_o_3; |
input [0:nr_of_wb_ports_clk3-1] wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3; |
|
input [0:nr_of_wb_clk_domains-1] wb_clk; |
input [0:nr_of_wb_clk_domains-1] wb_rst; |
|
// number of wb clock domains |
parameter nr_of_wb_clk_domains = 1; |
// number of wb ports in each wb clock domain |
parameter nr_of_wb_ports_clk0 = 1; |
parameter nr_of_wb_ports_clk1 = 0; |
parameter nr_of_wb_ports_clk2 = 0; |
parameter nr_of_wb_ports_clk3 = 0; |
|
parameter ba_size = 2; |
parameter row_size = 13; |
parameter col_size = 9; |
parameter [2:0] cl = 3'b010; // valid options 010, 011 used for SDR LMR |
|
input [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_0; |
input [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_0; |
output [32*nr_of_wb_ports_clk0-1:0] wb_dat_o_0; |
input [0:nr_of_wb_ports_clk0-1] wb_stb_i_0, wb_cyc_i_0, wb_ack_o_0; |
|
input [36*nr_of_wb_ports_clk1-1:0] wb_adr_i_1; |
input [36*nr_of_wb_ports_clk1-1:0] wb_dat_i_1; |
output [32*nr_of_wb_ports_clk1-1:0] wb_dat_o_1; |
input [0:nr_of_wb_ports_clk1-1] wb_stb_i_1, wb_cyc_i_1, wb_ack_o_1; |
|
input [36*nr_of_wb_ports_clk2-1:0] wb_adr_i_2; |
input [36*nr_of_wb_ports_clk2-1:0] wb_dat_i_2; |
output [32*nr_of_wb_ports_clk2-1:0] wb_dat_o_2; |
input [0:nr_of_wb_ports_clk2-1] wb_stb_i_2, wb_cyc_i_2, wb_ack_o_2; |
|
input [36*nr_of_wb_ports_clk3-1:0] wb_adr_i_3; |
input [36*nr_of_wb_ports_clk3-1:0] wb_dat_i_3; |
output [32*nr_of_wb_ports_clk3-1:0] wb_dat_o_3; |
input [0:nr_of_wb_ports_clk3-1] wb_stb_i_3, wb_cyc_i_3, wb_ack_o_3; |
|
input [0:nr_of_wb_clk_domains-1] wb_clk; |
input [0:nr_of_wb_clk_domains-1] wb_rst; |
|
|
output [1:0] ba_pad_o; |
output [12:0] a_pad_o; |
output cs_n_pad_o; |
output ras_pad_o; |
output cas_pad_o; |
output we_pad_o; |
output reg [(16)-1:0] dq_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */; |
output [1:0] dqm_pad_o; |
input [(16)-1:0] dq_i /*synthesis syn_useioff=1 syn_allow_retiming=0 */; |
output dq_oe; |
output cke_pad_o; |
output [1:0] ba_pad_o; |
output [12:0] a_pad_o; |
output cs_n_pad_o; |
output ras_pad_o; |
output cas_pad_o; |
output we_pad_o; |
output reg [15:0] dq_o; |
output reg [1:0] dqm_pad_o; |
input [15:0] dq_i; |
output dq_oe; |
output cke_pad_o; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 105 "versatile_mem_ctrl_top.v" 0 |
`line 100 "versatile_mem_ctrl_top.v" 0 |
|
input sdram_clk, sdram_rst; |
input sdram_clk, sdram_rst; |
|
wire [0:15] fifo_empty[0:3]; |
wire current_fifo_empty; |
wire [0:15] fifo_re[0:3]; |
wire [35:0] fifo_dat_o[0:3]; |
wire [31:0] fifo_dat_i; |
wire [0:15] fifo_we[0:3]; |
wire fifo_rd_adr, fifo_rd_data, fifo_wr, idle, count0; |
|
wire [0:15] fifo_sel_i, fifo_sel_dly; |
reg [0:15] fifo_sel_reg; |
wire [1:0] fifo_sel_domain_i, fifo_sel_domain_dly; |
reg [1:0] fifo_sel_domain_reg; |
wire [0:15] fifo_empty[0:3]; |
wire current_fifo_empty; |
wire [0:15] fifo_re[0:3]; |
wire [35:0] fifo_dat_o[0:3]; |
wire [31:0] fifo_dat_i; |
wire [0:15] fifo_we[0:3]; |
wire fifo_rd_adr, fifo_rd_data, fifo_wr, idle, count0; |
|
wire [0:15] fifo_sel_i, fifo_sel_dly; |
reg [0:15] fifo_sel_reg; |
wire [1:0] fifo_sel_domain_i, fifo_sel_domain_dly; |
reg [1:0] fifo_sel_domain_reg; |
|
reg refresh_req; |
|
wire [35:0] tx_fifo_dat_o; // tmp added /MF |
|
generate |
if (nr_of_wb_clk_domains > 0) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk0)) |
wb0 |
( |
reg refresh_req; |
|
generate |
if (nr_of_wb_clk_domains > 0) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk0)) |
wb0( |
// wishbone side |
.wb_adr_i_v(wb_adr_i_0), |
.wb_dat_i_v(wb_dat_i_0), |
1561,18 → 1499,17
.sdram_fifo_we(fifo_we[0][0:nr_of_wb_ports_clk0-1]), |
.sdram_clk(sdram_clk), |
.sdram_rst(sdram_rst) ); |
end |
if (nr_of_wb_ports_clk0 < 16) begin |
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}}; |
end |
endgenerate |
end |
if (nr_of_wb_ports_clk0 < 16) begin |
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}}; |
end |
endgenerate |
|
generate |
if (nr_of_wb_clk_domains > 1) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk1)) |
wb1 |
( |
generate |
if (nr_of_wb_clk_domains > 1) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk1)) |
wb1( |
// wishbone side |
.wb_adr_i_v(wb_adr_i_1), |
.wb_dat_i_v(wb_dat_i_1), |
1593,21 → 1530,20
.sdram_fifo_we(fifo_we[1][0:nr_of_wb_ports_clk1-1]), |
.sdram_clk(sdram_clk), |
.sdram_rst(sdram_rst) ); |
if (nr_of_wb_ports_clk1 < 16) begin |
if (nr_of_wb_ports_clk1 < 16) begin |
assign fifo_empty[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b1}}; |
end |
end else begin |
assign fifo_empty[1] = {16{1'b1}}; |
assign fifo_dat_o[1] = {36{1'b0}}; |
end |
endgenerate |
end |
end else begin |
assign fifo_empty[1] = {16{1'b1}}; |
assign fifo_dat_o[1] = {36{1'b0}}; |
end |
endgenerate |
|
generate |
if (nr_of_wb_clk_domains > 2) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk1)) |
wb2 |
( |
generate |
if (nr_of_wb_clk_domains > 2) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk1)) |
wb2( |
// wishbone side |
.wb_adr_i_v(wb_adr_i_2), |
.wb_dat_i_v(wb_dat_i_2), |
1628,21 → 1564,20
.sdram_fifo_we(fifo_we[2][0:nr_of_wb_ports_clk2-1]), |
.sdram_clk(sdram_clk), |
.sdram_rst(sdram_rst) ); |
if (nr_of_wb_ports_clk2 < 16) begin |
if (nr_of_wb_ports_clk2 < 16) begin |
assign fifo_empty[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b1}}; |
end |
end else begin |
assign fifo_empty[2] = {16{1'b1}}; |
assign fifo_dat_o[2] = {36{1'b0}}; |
end |
endgenerate |
end |
end else begin |
assign fifo_empty[2] = {16{1'b1}}; |
assign fifo_dat_o[2] = {36{1'b0}}; |
end |
endgenerate |
|
generate |
if (nr_of_wb_clk_domains > 3) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk3)) |
wb3 |
( |
generate |
if (nr_of_wb_clk_domains > 3) begin |
versatile_mem_ctrl_wb |
# (.nr_of_wb_ports(nr_of_wb_ports_clk3)) |
wb3( |
// wishbone side |
.wb_adr_i_v(wb_adr_i_3), |
.wb_dat_i_v(wb_dat_i_3), |
1663,134 → 1598,117
.sdram_fifo_we(fifo_we[3][0:nr_of_wb_ports_clk3-1]), |
.sdram_clk(sdram_clk), |
.sdram_rst(sdram_rst) ); |
if (nr_of_wb_ports_clk3 < 16) begin |
if (nr_of_wb_ports_clk3 < 16) begin |
assign fifo_empty[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b1}}; |
end |
end else begin |
assign fifo_empty[3] = {16{1'b1}}; |
assign fifo_dat_o[3] = {36{1'b0}}; |
end |
endgenerate |
end |
end else begin |
assign fifo_empty[3] = {16{1'b1}}; |
assign fifo_dat_o[3] = {36{1'b0}}; |
end |
endgenerate |
|
encode encode0 |
( |
.fifo_empty_0(fifo_empty[0]), .fifo_empty_1(fifo_empty[1]), .fifo_empty_2(fifo_empty[2]), .fifo_empty_3(fifo_empty[3]), |
.fifo_sel(fifo_sel_i), .fifo_sel_domain(fifo_sel_domain_i) |
); |
encode encode0 ( |
.fifo_empty_0(fifo_empty[0]), .fifo_empty_1(fifo_empty[1]), .fifo_empty_2(fifo_empty[2]), .fifo_empty_3(fifo_empty[3]), |
.fifo_sel(fifo_sel_i), .fifo_sel_domain(fifo_sel_domain_i) |
); |
|
always @ (posedge sdram_clk or posedge sdram_rst) |
begin |
if (sdram_rst) |
{fifo_sel_reg,fifo_sel_domain_reg} <= {16'h0,2'b00}; |
else |
if (idle) |
always @ (posedge sdram_clk or posedge sdram_rst) |
begin |
if (sdram_rst) |
{fifo_sel_reg,fifo_sel_domain_reg} <= {16'h0,2'b00}; |
else |
if (idle) |
{fifo_sel_reg,fifo_sel_domain_reg} <= {fifo_sel_i,fifo_sel_domain_i}; |
end |
end |
|
decode decode0 |
( |
.fifo_sel(fifo_sel_reg), .fifo_sel_domain(fifo_sel_domain_reg), |
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3]) |
); |
decode decode0 ( |
.fifo_sel(fifo_sel_reg), .fifo_sel_domain(fifo_sel_domain_reg), |
.fifo_we_0(fifo_re[0]), .fifo_we_1(fifo_re[1]), .fifo_we_2(fifo_re[2]), .fifo_we_3(fifo_re[3]) |
); |
|
// fifo_re[0-3] is a one-hot read enable structure |
// fifo_empty should go active when chosen fifo queue is empty |
assign current_fifo_empty = (idle) ? (!(|fifo_sel_i)) : (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3])); |
// fifo_re[0-3] is a one-hot read enable structure |
// fifo_empty should go active when chosen fifo queue is empty |
assign current_fifo_empty = (idle) ? (!(|fifo_sel_i)) : (|(fifo_empty[0] & fifo_re[0])) | (|(fifo_empty[1] & fifo_re[1])) | (|(fifo_empty[2] & fifo_re[2])) | (|(fifo_empty[3] & fifo_re[3])); |
|
decode decode1 |
( |
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly), |
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3]) |
); |
decode decode1 ( |
.fifo_sel(fifo_sel_dly), .fifo_sel_domain(fifo_sel_domain_dly), |
.fifo_we_0(fifo_we[0]), .fifo_we_1(fifo_we[1]), .fifo_we_2(fifo_we[2]), .fifo_we_3(fifo_we[3]) |
); |
|
|
|
wire ref_cnt_zero; |
reg [(16)-1:0] dq_i_reg, dq_i_tmp_reg; |
reg [17:0] dq_o_tmp_reg; |
wire cmd_aref, cmd_read; |
wire ref_cnt_zero; |
reg [15:0] dq_i_reg, dq_i_tmp_reg; |
reg [17:0] dq_o_tmp_reg; |
wire cmd_aref, cmd_read; |
|
// refresch counter |
ref_counter ref_counter0( .zq(ref_cnt_zero), .rst(sdram_rst), .clk(sdram_clk)); |
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) |
refresh_req <= 1'b0; |
else |
if (ref_cnt_zero) |
refresh_req <= 1'b1; |
else if (cmd_aref) |
refresh_req <= 1'b0; |
|
// SDR SDRAM 16 FSM |
fsm_sdr_16 # ( .ba_size(ba_size), .row_size(row_size), .col_size(col_size), .init_cl(cl)) |
fsm_sdr_16( |
.adr_i({fifo_dat_o[fifo_sel_domain_reg][ba_size+row_size+col_size+6-2:6],1'b0}), |
.we_i(fifo_dat_o[fifo_sel_domain_reg][5]), |
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]), |
.fifo_empty(current_fifo_empty), .fifo_rd_adr(fifo_rd_adr), .fifo_rd_data(fifo_rd_data), |
.state_idle(idle), .count0(count0), |
.refresh_req(refresh_req), |
.cmd_aref(cmd_aref), .cmd_read(cmd_read), |
.ba(ba_pad_o), .a(a_pad_o), .cmd({ras_pad_o, cas_pad_o, we_pad_o}), .dq_oe(dq_oe), |
.sdram_clk(sdram_clk), .sdram_rst(sdram_rst) |
); |
|
// refresch counter |
ref_counter ref_counter0( .zq(ref_cnt_zero), .rst(sdram_rst), .clk(sdram_clk)); |
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) |
refresh_req <= 1'b0; |
else |
if (ref_cnt_zero) |
refresh_req <= 1'b1; |
else if (cmd_aref) |
refresh_req <= 1'b0; |
|
// SDR SDRAM 16 FSM |
fsm_sdr_16 fsm_sdr_16_0 |
( |
.adr_i({fifo_dat_o[fifo_sel_domain_reg][2+12+8+6-2:6],1'b0}), |
.we_i(fifo_dat_o[fifo_sel_domain_reg][5]), |
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]), |
.sel_i({fifo_dat_o[fifo_sel_domain_reg][3:2],dq_o_tmp_reg[1:0]}), |
.fifo_empty(current_fifo_empty), |
.fifo_rd_adr(fifo_rd_adr), |
.fifo_rd_data(fifo_rd_data), |
.state_idle(idle), |
.count0(count0), |
.refresh_req(refresh_req), |
.cmd_aref(cmd_aref), |
.cmd_read(cmd_read), |
.ba(ba_pad_o), .a(a_pad_o), |
.cmd({ras_pad_o, cas_pad_o, we_pad_o}), |
.dq_oe(dq_oe), |
.dqm(dqm_pad_o), |
.sdram_clk(sdram_clk), |
.sdram_rst(sdram_rst) |
); |
/* |
defparam fsm_sdr_16_0.ba_size = ba_size; |
defparam fsm_sdr_16_0.row_size = row_size; |
defparam fsm_sdr_16_0.col_size = col_size; |
defparam fsm_sdr_16_0.init_cl = cl; |
*/ |
assign cs_pad_o = 1'b0; |
assign cke_pad_o = 1'b1; |
assign cs_pad_o = 1'b0; |
assign cke_pad_o = 1'b1; |
|
genvar i; |
generate |
for (i=0; i < 16; i=i+1) begin : dly |
genvar i; |
generate |
for (i=0; i < 16; i=i+1) begin : dly |
|
defparam delay0.depth=3'b010+2; |
defparam delay0.width=1; |
delay delay0 ( |
.d(fifo_sel_reg[i]), |
.q(fifo_sel_dly[i]), |
.clk(sdram_clk), |
.rst(sdram_rst) |
); |
end |
|
defparam delay1.depth=3'b010+2; |
defparam delay1.width=2; |
delay delay1 ( |
.d(fifo_sel_domain_reg), |
.q(fifo_sel_domain_dly), |
.clk(sdram_clk), |
.rst(sdram_rst) |
); |
|
defparam delay2.depth=3'b010+2; |
defparam delay2.width=1; |
delay delay2 ( |
.d(cmd_read), |
.q(fifo_wr), |
.clk(sdram_clk), |
.rst(sdram_rst) |
); |
|
endgenerate |
defparam delay0.depth=cl+2; |
defparam delay0.width=1; |
delay delay0 ( |
.d(fifo_sel_reg[i]), |
.q(fifo_sel_dly[i]), |
.clk(sdram_clk), |
.rst(sdram_rst) |
); |
end |
|
defparam delay1.depth=cl+2; |
defparam delay1.width=2; |
delay delay1 ( |
.d(fifo_sel_domain_reg), |
.q(fifo_sel_domain_dly), |
.clk(sdram_clk), |
.rst(sdram_rst) |
); |
|
defparam delay2.depth=cl+2; |
defparam delay2.width=1; |
delay delay2 ( |
.d(cmd_read), |
.q(fifo_wr), |
.clk(sdram_clk), |
.rst(sdram_rst) |
); |
|
endgenerate |
|
// output registers |
assign cs_n_pad_o = 1'b0; |
assign cke_pad_o = 1'b1; |
|
always @ (posedge sdram_clk or posedge sdram_rst) |
// output registers |
assign cs_n_pad_o = 1'b0; |
assign cke_pad_o = 1'b1; |
|
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) |
{dq_i_reg, dq_i_tmp_reg} <= {16'h0000,16'h0000}; |
else |
1797,54 → 1715,25
{dq_i_reg, dq_i_tmp_reg} <= {dq_i, dq_i_reg}; |
|
assign fifo_dat_i = {dq_i_tmp_reg, dq_i_reg}; |
|
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) |
dq_o_tmp_reg <= 18'h0; |
else |
dq_o_tmp_reg <= {fifo_dat_o[fifo_sel_domain_reg][19:4],fifo_dat_o[fifo_sel_domain_reg][1:0]}; |
|
// output dq_o mux and dffs |
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) |
dq_o <= 16'h0000; |
else |
if (~count0) |
dq_o <= fifo_dat_o[fifo_sel_domain_reg][35:20]; |
else |
dq_o <= dq_o_tmp_reg[17:2]; |
|
/* |
// data mask signals should be not(sel_i) for write and 2'b00 for read |
|
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) |
dqm_pad_o <= 2'b00; |
else |
if (~count0) |
dqm_pad_o <= ~fifo_dat_o[fifo_sel_domain_reg][3:2]; |
else |
dqm_pad_o <= ~dq_o_tmp_reg[1:0]; |
*/ |
/* |
always @ (posedge sdram_clk or posedge sdram_rst) |
if (sdram_rst) begin |
{dq_o, dqm_pad_o} <= {16'h0000,2'b00}; |
|
{dq_o, dqm_pad_o} <= {16'h0000,2'b00}; |
dq_o_tmp_reg <= 18'h0; |
end else |
if (~count0) begin |
dq_o <= fifo_dat_o[fifo_sel_domain_reg][35:20]; |
dq_o_tmp_reg[17:2] <= fifo_dat_o[fifo_sel_domain_reg][19:4]; |
if (cmd_read) |
dqm_pad_o <= 2'b00; |
else |
dqm_pad_o <= ~fifo_dat_o[fifo_sel_domain_reg][3:2]; |
if (cmd_read) |
dq_o_tmp_reg[1:0] <= 2'b00; |
else |
dq_o_tmp_reg[1:0] <= ~fifo_dat_o[fifo_sel_domain_reg][1:0]; |
if (~count0) begin |
dq_o <= fifo_dat_o[fifo_sel_domain_reg][35:20]; |
dq_o_tmp_reg[17:2] <= fifo_dat_o[fifo_sel_domain_reg][19:4]; |
if (cmd_read) |
dqm_pad_o <= 2'b00; |
else |
dqm_pad_o <= ~fifo_dat_o[fifo_sel_domain_reg][3:2]; |
if (cmd_read) |
dq_o_tmp_reg[1:0] <= 2'b00; |
else |
dq_o_tmp_reg[1:0] <= ~fifo_dat_o[fifo_sel_domain_reg][1:0]; |
end else |
{dq_o,dqm_pad_o} <= dq_o_tmp_reg; |
*/ |
{dq_o,dqm_pad_o} <= dq_o_tmp_reg; |
|
|
// `ifdef SDR_16 |
1855,11 → 1744,14
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1871,16 → 1763,38
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1905,7 → 1819,6
|
|
|
|
|
|
|
1916,30 → 1829,26
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1954,26 → 1863,17
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1980,50 → 1880,66
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2034,7 → 1950,6
|
|
|
|
|
|
|
2047,7 → 1962,6
|
|
|
|
|
|
|
2066,21 → 1980,10
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 668 "versatile_mem_ctrl_top.v" 0 |
`line 633 "versatile_mem_ctrl_top.v" 0 |
// `ifdef DDR_16 |
|
endmodule // wb_sdram_ctrl_top |
`line 671 "versatile_mem_ctrl_top.v" 2 |
`line 636 "versatile_mem_ctrl_top.v" 2 |