URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/rtl
- from Rev 102 to Rev 104
- ↔ Reverse comparison
Rev 102 → Rev 104
/verilog/sdr_16_defines.v
26,13 → 26,7
// actually finished. |
//`define SDRAM_WB_SAME_CLOCKS |
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// If intending to burst write, and the wishbone clock is about 1/4 the speed |
// of the SDRAM clock, then the data may come late, and this triggers a bug |
// during write. To avoid this we can just wait a little longer for data when |
// burst reading (there's no almost_empty signal from the FIFO) |
//`define SLOW_WB_CLOCK |
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`ifdef MT48LC16M16 |
// using 1 of MT48LC16M16 |
// SDRAM data width is 16 |
/verilog/sdr_sdram_16_ctrl.v
1,5 → 1,20
`timescale 1ns/1ns |
module delay_emptyflag ( d, q, emptyflag, clk, rst); |
parameter depth = 10; |
input d; |
output q, emptyflag; |
input clk, rst; |
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reg [1:depth] dffs; |
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always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
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module sdr_sdram_16_ctrl ( |
// wisbone i/f |
dat_i, adr_i, sel_i, cti_i, bte_i, we_i, cyc_i, stb_i, dat_o, ack_o, |
34,7 → 49,7
output [31:0] dat_o; |
output ack_o; |
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output reg [1:0] ba; |
output reg [ba_size-1:0] ba; |
output reg [12:0] a; |
output reg [2:0] cmd; |
output cke, cs_n; |
91,6 → 106,18
cmd_rfr = 3'b001, |
cmd_lmr = 3'b000; |
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// LMR |
// [12:10] reserved |
// [9] WB, write burst; 0 - programmed burst length, 1 - single location |
// [8:7] OP Mode, 2'b00 |
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3 |
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved |
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page |
`define INIT_WB 1'b0 |
`define INIT_CL 3'b010 |
`define INIT_BT 1'b0 |
`define INIT_BL 3'b001 |
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// ctrl FSM |
`define FSM_INIT 3'b000 |
`define FSM_IDLE 3'b001 |
170,7 → 197,7
assign stall = state==`FSM_RW & next==`FSM_RW & ~stb_i & count0 & we_i; |
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// counter |
cnt_shreg_ce_clear # ( .length(32)) |
vl_cnt_shreg_ce_clear # ( .length(32)) |
cnt0 ( |
.cke(!stall), |
.clear(!(state==next)), |
178,7 → 205,7
.rst(rst), |
.clk(clk)); |
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dff_ce_clear |
vl_dff_ce_clear |
dff_count0 ( |
.d(!count0), |
.ce(!stall), |
271,7 → 298,7
{current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row}; |
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// refresh counter |
cnt_lfsr_zq # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_zq # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk)); |
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always @ (posedge clk or posedge rst) |
if (rst) |
283,7 → 310,7
refresh_req <= 1'b0; |
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dff # ( .width(32)) wb_dat_dff ( .d({dat_o[15:0],dq_i}), .q(dat_o), .clk(clk), .rst(rst)); |
vl_dff # ( .width(32)) wb_dat_dff ( .d({dat_o[15:0],dq_i}), .q(dat_o), .clk(clk), .rst(rst)); |
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assign ack_wr = (state==`FSM_RW & count0 & we_i); |
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