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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

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  • This comparison shows the changes necessary to convert path 
    /versatile_mem_ctrl/trunk/rtl
    from Rev 11 to Rev 13
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  •

Rev 11 → Rev 13

/verilog/ddr_16_defines.v
52,7 → 52,7
`define DLL 1'b0
`define TM 1'b0
`define CAS 1'b0
`define CL 3'b100
`define CL 3'b111
`define BT 1'b0
`define BL 3'b011
 
124,6 → 124,14
`define CMD_WRITE 3'b100
`define CMD_BT 3'b110
 
// AC Operating Specifications and Conditions
//`define TWR 4'd2 // Write recovery time, tWR/tCLK=15/8=2 (tCLK)
//`define TRFC 5'd10 // REFRESH-to-ACTIVATE/REFRESH interval (256Mb), tRFC/tCLK=75/8=10 (tCLK)
//`define TRFC 5'd14 // REFRESH-to-ACTIVATE/REFRESH interval (512Mb), tRFC/tCLK=105/8=14 (tCLK)
//`define TRFC 5'd16 // REFRESH-to-ACTIVATE/REFRESH interval (1Gb), tRFC/tCLK=127,5/8=16 (tCLK)
//`define TRFC 5'd25 // REFRESH-to-ACTIVATE/REFRESH interval (2Gb), tRFC/tCLK=197,5/8=25 (tCLK)
//`define TRCD 2'd2 // ACTIVATE-to-READ/WRITE delay, 12-15ns, tRCD/tCLK=15/8=2 (tCLK)
 
`endif // `ifdef MT47H32M16
 
 
/verilog/ref_delay_counter_defines.v
0,0 → 1,42
// module name
`define CNT_MODULE_NAME ref_delay_counter
 
// counter type = [BINARY, GRAY, LFSR]
`define CNT_TYPE_BINARY
//`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
//`define CNT_Q
// for gray type counter optional binary output
//`define CNT_Q_BIN
 
// number of CNT bins
`define CNT_LENGTH 6
 
// clear
//`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
 
// wrap around creates shorter cycle than maximum length
`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'd12
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
`define CNT_ZQ
 
/verilog/latency_counter_defines.v
0,0 → 1,42
// module name
`define CNT_MODULE_NAME latency_counter
 
// counter type = [BINARY, GRAY, LFSR]
`define CNT_TYPE_BINARY
//`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
//`define CNT_Q
// for gray type counter optional binary output
//`define CNT_Q_BIN
 
// number of CNT bins
`define CNT_LENGTH 4
 
// clear
//`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
 
// wrap around creates shorter cycle than maximum length
`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'd3
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
`define CNT_ZQ
 
/verilog/burst_length_counter_defines.v
0,0 → 1,42
// module name
`define CNT_MODULE_NAME burst_length_counter
 
// counter type = [BINARY, GRAY, LFSR]
`define CNT_TYPE_BINARY
//`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
//`define CNT_Q
// for gray type counter optional binary output
//`define CNT_Q_BIN
 
// number of CNT bins
`define CNT_LENGTH 3
 
// clear
//`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
 
// wrap around creates shorter cycle than maximum length
`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'd3
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
`define CNT_ZQ
 
/verilog/pre_delay_counter_defines.v
0,0 → 1,42
// module name
`define CNT_MODULE_NAME pre_delay_counter
 
// counter type = [BINARY, GRAY, LFSR]
`define CNT_TYPE_BINARY
//`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
//`define CNT_Q
// for gray type counter optional binary output
//`define CNT_Q_BIN
 
// number of CNT bins
`define CNT_LENGTH 4
 
// clear
//`define CNT_CLEAR
 
// async reset
`define CNT_RESET_VALUE `CNT_LENGTH'h0
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h0
 
// wrap around creates shorter cycle than maximum length
`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'd2
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
`define CNT_ZQ
 
/verilog/versatile_mem_ctrl_top.v
122,6 → 122,8
output ck_pad_o,
output ck_n_pad_o,
output cke_pad_o,
output ck_fb_pad_o,
input ck_fb_pad_i,
output cs_n_pad_o,
output ras_pad_o,
output cas_pad_o,
130,14 → 132,17
output [1:0] dm_rdqs_o,
output [1:0] ba_pad_o,
output [12:0] addr_pad_o,
input [15:0] dq_i,
output [15:0] dq_o,
output dq_oe,
input [1:0] dqs_i,
output [1:0] dqs_o,
//input [15:0] dq_i,
//output [15:0] dq_o,
inout [15:0] dq_pad_io,
//output dq_oe,
//input [1:0] dqs_i,
//output [1:0] dqs_o,
inout [1:0] dqs_pad_io,
output dqs_oe,
input [1:0] dqs_n_i,
output [1:0] dqs_n_o,
//input [1:0] dqs_n_i,
//output [1:0] dqs_n_o,
inout [1:0] dqs_n_pad_io,
input [1:0] rdqs_n_pad_i,
output odt_pad_o,
`endif
564,7 → 569,7
.bte_i(tx_fifo_dat_o[4:3]),
.cti_i(tx_fifo_dat_o[2:0]),
.init(adr_init),
.inc(adr_inc),
.inc(adr_inc | rx_fifo_we),
.adr_o(burst_adr),
.done(done),
.clk(sdram_clk_0),
586,8 → 591,8
ref_req <= 1'b1;
else if (ref_ack)
ref_req <= 1'b0;
 
 
`ifdef SDR_16
wire read;
reg [15:0] dq_i_reg, dq_i_tmp_reg;
658,29 → 663,36
 
 
`ifdef DDR_16
wire read, write;
wire read, write;
wire [15:0] dq_hi_reg, dq_lo_reg;
wire sdram_clk_180, sdram_clk_90, sdram_clk_270;
wire sdram_bufg_clk_0, sdram_bufg_clk_180, sdram_bufg_clk_90, sdram_bufg_clk_270;
reg cke_en;
reg cke, ras, cas, we, cs_n;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire sdram_clk_180, sdram_clk_90, sdram_clk_270;
wire sdram_bufg_clk_0, sdram_bufg_clk_180, sdram_bufg_clk_90, sdram_bufg_clk_270;
wire sdram_clk_ibufg;
wire ck_fb, ck_fb_bufg, ck_fb_ibufg;
reg cke_en;
reg cke, ras, cas, we, cs_n;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire [12:0] addr_o;
reg [1:0] ba;
reg [1:0] ba;
reg [12:0] addr;
wire [14:0] cke_delay_cnt;
wire dq_en, dqs_en;
wire dq_en, dqs_en;
reg [35:0] rx_fifo_dat_pipe;
reg [31:0] tx_fifo_dat_pipe;
genvar i;
wire [31:0] dq_o, dq_i;
wire ref_delay, ref_delay_ack, pre_delay, pre_delay_ack;
wire bl_en, bl_ack;
wire tx_fifo_re_i, adr_init_delay;
reg adr_init_delay_i;
genvar i;
// DDR SDRAM 16 FSM
ddr_16 ddr_16_0
(
.adr_inc(adr_inc),
.adr_inc(),
.adr_init(adr_init),
.fifo_re(tx_fifo_re),
.fifo_re(tx_fifo_re_i),
.tx_fifo_dat_o(tx_fifo_dat_o),
.burst_adr(burst_adr),
.done(done),
691,6 → 703,15
// refresh
.ref_req(ref_req),
.ref_ack(ref_ack),
.ref_delay(ref_delay),
.ref_delay_ack(ref_delay_ack),
.adr_init_delay(adr_init_delay),
//
.pre_delay(pre_delay),
.pre_delay_ack(pre_delay_ack),
// burst latency
.bl_en(bl_en),
.bl_ack(bl_ack),
// sdram
.dqm(dm_rdqs_o),
.a({ba_o,addr_o}),
717,6 → 738,33
if (cke_delay_cnt == 15'h6300)
cke_en <= 1'b1;
 
// refresh to activate/refresh delay
ref_delay_counter ref_delay_counter0
(
.cke(ref_delay),
.zq(ref_delay_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
// write recovery time
pre_delay_counter pre_delay_counter0
(
.cke(pre_delay),
.zq(pre_delay_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
// burst length
burst_length_counter burst_length_counter0
(
.cke(bl_en),
.zq(bl_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
always @ (posedge sdram_clk_180 or posedge wb_rst)
if (wb_rst) begin
cs_n <= 1'b0;
743,11 → 791,11
assign we_pad_o = we;
assign ba_pad_o = ba;
assign addr_pad_o = addr;
assign cs_n_pad_o = cs_n;
assign cs_n_pad_o = cs_n;
 
 
//
defparam delay0.depth=`CL+2;
// read latency
defparam delay0.depth=`CL+`AL+2;
delay delay0
(
.d({read,tx_fifo_b_sel_i_cur}),
756,17 → 804,39
.rst(wb_rst)
);
//
defparam delay1.depth=3;
// write latency
defparam delay1.depth=`CL+`AL-1;
delay delay1
(
.d({write, write, write, 1'b0}),
.q({dq_en, dq_oe, dqs_en, open}),
.d({write, write, write, write}),
.q({dq_en, dq_oe, dqs_en, adr_inc}),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
// TX DCM
// if CL>4 delay read from Tx FIFO
defparam delay2.depth=`CL+`AL-4;
delay delay2
(
.d({tx_fifo_re_i, tx_fifo_re_i, 2'b00}),
.q({tx_fifo_re, adr_init_delay, open, open}),
.clk(sdram_clk_0),
.rst(wb_rst)
);
/* // if CL=4, no delay
assign tx_fifo_re = tx_fifo_re_i;
always @ (posedge sdram_clk_0 or posedge wb_rst)
if (wb_rst)
adr_init_delay_i <= 1'b0;
else
adr_init_delay_i <= tx_fifo_re_i;
assign adr_init_delay = adr_init_delay_i;*/
 
// CL=3, not supported
 
 
// DCM with internal feedback
// Remove skew from internal clock
DCM #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
780,7 → 850,7
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_inst (
) DCM_internal (
.CLK0(sdram_bufg_clk_0),
.CLK180(sdram_bufg_clk_180),
.CLK270(sdram_bufg_clk_270),
794,7 → 864,7
.PSDONE(),
.STATUS(),
.CLKFB(sdram_clk_0),
.CLKIN(sdram_clk),
.CLKIN(sdram_clk_ibufg),
.DSSEN(),
.PSCLK(),
.PSEN(),
801,9 → 871,44
.PSINCDEC(),
.RST(wb_rst)
);
// DCM with external feedback
// Remove skew from external clock
DCM #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(8.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_external (
.CLK0(ck_fb_bufg),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(),
.PSDONE(),
.STATUS(),
.CLKFB(ck_fb_ibufg),
.CLKIN(sdram_clk_ibufg),
.DSSEN(),
.PSCLK(),
.PSEN(),
.PSINCDEC(),
.RST(wb_rst)
);
 
// Global buffers on DCM clock outputs
// Internal feedback to DCM
// Global buffers on DCM generated clocks
BUFG BUFG_0 (
.I (sdram_bufg_clk_0),
.O (sdram_clk_0));
816,6 → 921,17
BUFG BUFG_270 (
.I (sdram_bufg_clk_270),
.O (sdram_clk_270));
// Internal feedback to DCM
IBUFG IBUFG_clk (
.I (sdram_clk),
.O (sdram_clk_ibufg));
// External feedback to DCM
OBUF OBUF_ck_fb (
.I (ck_fb_bufg),
.O (ck_fb));
IBUFG IBUFG_ck_fb (
.I (ck_fb_pad_i),
.O (ck_fb_ibufg));
 
// Pipeline the data path from Tx FIFO to ODDR output registers
always @ (posedge sdram_clk_0 or posedge wb_rst)
845,6 → 961,42
end
endgenerate
 
assign dq_pad_io = dq_oe ? dq_o : {16{1'bz}};
// Use ODDR FF to generate clock with equal delay as data
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC"))
ODDR2_inst_1
(
.Q(ck_pad_o),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(wb_rst),
.S(1'b0)
);
 
// Use ODDR FF to generate clock with equal delay as data
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC"))
ODDR2_inst_2
(
.Q(ck_n_pad_o),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
.R(wb_rst),
.S(1'b0)
);
 
// IDDR2 (Double Data Rate Input D Flip-Flop)
generate
for (i=0; i<16; i=i+1) begin:iddr2gen
860,9 → 1012,9
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.CE(1'b1),
.D(dq_i[i]),
.D(dq_pad_io[i]),
.R(wb_rst),
.S(1'b0)
.S(1'b0)
);
end
endgenerate
877,11 → 1029,10
assign rx_fifo_dat_i = rx_fifo_dat_pipe;
 
// Assing outputs
assign ck_pad_o = sdram_clk_270;
assign ck_n_pad_o = sdram_clk_90;
assign dqs_o = dqs_en ? {sdram_clk_270, sdram_clk_270} : 2'bz;
assign dqs_n_o = dqs_en ? {sdram_clk_90, sdram_clk_90} : 2'bz;
assign dqs_oe = dqs_en;
assign dqs_pad_io = dqs_en ? {sdram_clk_270, sdram_clk_270} : 2'bz;
assign dqs_n_pad_io = dqs_en ? {sdram_clk_90, sdram_clk_90} : 2'bz;
assign dqs_oe = dqs_en;
assign ck_fb_pad_o = ck_fb;
 
`endif // `ifdef DDR_16
 
/verilog/ddr_16.fzm
1,4 → 1,4
## File last modified by Fizzim: 3:09:01 PM on 10/26/09
## File last modified by Fizzim: 9:44:02 AM on 11/6/09
<version>
8.04.05
</version>
666,6 → 666,182
-1
</page>
</cke_en>
<ref_delay_ack>
<status>
GLOBAL_FIXED
</status>
<value>
<status>
GLOBAL_VAR
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</ref_delay_ack>
<pre_delay_ack>
<status>
GLOBAL_FIXED
</status>
<value>
<status>
GLOBAL_VAR
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</pre_delay_ack>
<bl_ack>
<status>
GLOBAL_FIXED
</status>
<value>
<status>
GLOBAL_VAR
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</bl_ack>
<adr_init_delay>
<status>
GLOBAL_FIXED
</status>
<value>
<status>
GLOBAL_VAR
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</adr_init_delay>
</inputs>
<outputs>
<cs_n>
1037,7 → 1213,7
</status>
</vis>
<type>
reg
comb
<status>
GLOBAL_VAR
</status>
1108,6 → 1284,138
-1
</page>
</write>
<ref_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
comb
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
comb
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
comb
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</bl_en>
</outputs>
<state>
<name>
1594,6 → 1902,138
-1
</page>
</write>
<ref_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
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<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</read>
<write>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</write>
</attributes>
<x0>
275
</x0>
<y0>
225
</y0>
<x1>
375
</x1>
<y1>
325
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
26720,7 → 30080,7
ABS
</status>
<value>
trans100
trans99
<status>
LOCAL
</status>
26764,9 → 30124,9
ABS
</status>
<value>
1
ref_delay_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
26794,10 → 30154,10
</status>
</color>
<x2Obj>
21
35
</x2Obj>
<y2Obj>
4
-3
</y2Obj>
<page>
3
26849,40 → 30209,40
</priority>
</attributes>
<startState>
NOP20
NOP_tRFC
</startState>
<endState>
ACT_ROW
AWAIT_CMD
</endState>
<startPtX>
325.0
486.0
</startPtX>
<startPtY>
325.0
242.0
</startPtY>
<endPtX>
325.0
363.0
</endPtX>
<endPtY>
375.0
157.0
</endPtY>
<startCtrlPtX>
325.0
447.0
</startCtrlPtX>
<startCtrlPtY>
335.0
214.0
</startCtrlPtY>
<endCtrlPtY>
325.0
401.0
</endCtrlPtY>
<endCtrlPtY>
364.0
184.0
</endCtrlPtY>
<startStateIndex>
9
22
</startStateIndex>
<endStateIndex>
27
4
</endStateIndex>
<page>
3
26891,10 → 30251,10
-16777216
</color>
<pageSX>
0.0
635.0
</PageSX>
<pageSY>
0.0
275.0
</pageSY>
<pageSCX>
0.0
27134,7 → 30494,7
ABS
</status>
<value>
NOP22
NOP_tRCD
<status>
LOCAL
</status>
27152,9 → 30512,9
</status>
</type>
<comment>
ACTIVATE-to-READ/WRITE delay
<status>
GLOBAL_VAR
LOCAL
</status>
</comment>
<color>
27266,9 → 30626,9
GLOBAL_FIXED
</status>
<value>
a
15'd0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
27613,79 → 30973,8
3
</page>
</write>
</attributes>
<x0>
75
</x0>
<y0>
500
</y0>
<x1>
175
</x1>
<y1>
600
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE OBJECT
<state>
<attributes>
<name>
<ref_delay>
<status>
ABS
</status>
<value>
WRITE_ADDR
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</name>
<cs_n>
<status>
GLOBAL_FIXED
</status>
<value>
27727,60 → 31016,16
<page>
3
</page>
</cs_n>
<cmd[2:0]>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
<value>
`CMD_WRITE
1'b0
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
1
</x2Obj>
<y2Obj>
-7
</y2Obj>
<page>
3
</page>
</cmd[2:0]>
<a[14:0]>
<status>
GLOBAL_FIXED
</status>
<value>
`A_WRITE
<status>
LOCAL
</status>
</value>
<vis>
2
27810,13 → 31055,13
0
</x2Obj>
<y2Obj>
-14
0
</y2Obj>
<page>
3
</page>
</a[14:0]>
<ref_ack>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
27859,25 → 31104,52
<page>
3
</page>
</ref_ack>
<adr_init>
</bl_en>
</attributes>
<x0>
75
</x0>
<y0>
375
</y0>
<x1>
175
</x1>
<y1>
475
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE OBJECT
<state>
<attributes>
<name>
<status>
GLOBAL_FIXED
ABS
</status>
<value>
1'b0
WRITE_ADDR
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
2
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
def_type
<status>
GLOBAL_VAR
</status>
27903,15 → 31175,15
<page>
3
</page>
</adr_init>
<adr_inc>
</name>
<cs_n>
<status>
GLOBAL_FIXED
</status>
<value>
!done & !fifo_empty[fifo_sel]
1'b0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
27942,18 → 31214,18
0
</x2Obj>
<y2Obj>
-20
0
</y2Obj>
<page>
3
</page>
</adr_inc>
<fifo_re>
</cs_n>
<cmd[2:0]>
<status>
GLOBAL_FIXED
</status>
<value>
1'b1
`CMD_WRITE
<status>
LOCAL
</status>
27983,23 → 31255,23
</status>
</color>
<x2Obj>
0
1
</x2Obj>
<y2Obj>
-28
-7
</y2Obj>
<page>
3
</page>
</fifo_re>
<dqm[1:0]>
</cmd[2:0]>
<a[14:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b00
`A_WRITE
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
28030,13 → 31302,13
0
</x2Obj>
<y2Obj>
0
-14
</y2Obj>
<page>
3
</page>
</dqm[1:0]>
<read>
</a[14:0]>
<ref_ack>
<status>
GLOBAL_FIXED
</status>
28079,127 → 31351,12
<page>
3
</page>
</read>
<write>
</ref_ack>
<adr_init>
<status>
GLOBAL_FIXED
</status>
<value>
1'b1
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
1
</x2Obj>
<y2Obj>
-37
</y2Obj>
<page>
3
</page>
</write>
</attributes>
<x0>
75
</x0>
<y0>
650
</y0>
<x1>
175
</x1>
<y1>
750
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE OBJECT
<state>
<attributes>
<name>
<status>
ABS
</status>
<value>
WRITE_DATA
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
-2
</y2Obj>
<page>
3
</page>
</name>
<cs_n>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
28238,13 → 31395,13
<page>
3
</page>
</cs_n>
<cmd[2:0]>
</adr_init>
<adr_inc>
<status>
GLOBAL_FIXED
</status>
<value>
`CMD_NOP
1'b0
<status>
GLOBAL_VAR
</status>
28277,20 → 31434,20
0
</x2Obj>
<y2Obj>
0
-20
</y2Obj>
<page>
3
</page>
</cmd[2:0]>
<a[14:0]>
</adr_inc>
<fifo_re>
<status>
GLOBAL_FIXED
</status>
<value>
15'd0
1'b1
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
28321,18 → 31478,18
0
</x2Obj>
<y2Obj>
0
-22
</y2Obj>
<page>
3
</page>
</a[14:0]>
<ref_ack>
</fifo_re>
<dqm[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
2'b00
<status>
GLOBAL_VAR
</status>
28370,8 → 31527,8
<page>
3
</page>
</ref_ack>
<adr_init>
</dqm[1:0]>
<read>
<status>
GLOBAL_FIXED
</status>
28414,13 → 31571,13
<page>
3
</page>
</adr_init>
<adr_inc>
</read>
<write>
<status>
GLOBAL_FIXED
</status>
<value>
!done & !fifo_empty[fifo_sel]
1'b1
<status>
LOCAL
</status>
28453,65 → 31610,21
1
</x2Obj>
<y2Obj>
-3
-29
</y2Obj>
<page>
3
</page>
</adr_inc>
<fifo_re>
</write>
<ref_delay>
<status>
GLOBAL_FIXED
</status>
<value>
!done
1'b0
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
-5
</x2Obj>
<y2Obj>
-5
</y2Obj>
<page>
3
</page>
</fifo_re>
<dqm[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b00
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
28546,8 → 31659,8
<page>
3
</page>
</dqm[1:0]>
<read>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
28590,8 → 31703,8
<page>
3
</page>
</read>
<write>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
28626,27 → 31739,27
</status>
</color>
<x2Obj>
-2
0
</x2Obj>
<y2Obj>
-6
-37
</y2Obj>
<page>
3
</page>
</write>
</bl_en>
</attributes>
<x0>
75
</x0>
<y0>
800
525
</y0>
<x1>
175
</x1>
<y1>
900
625
</y1>
<reset>
false
28796,7 → 31909,7
</priority>
</attributes>
<startState>
NOP22
NOP_tRCD
</startState>
<endState>
WRITE_ADDR
28805,25 → 31918,25
125.0
</startPtX>
<startPtY>
600.0
475.0
</startPtY>
<endPtX>
124.0
</endPtX>
<endPtY>
650.0
525.0
</endPtY>
<startCtrlPtX>
125.0
</startCtrlPtX>
<startCtrlPtY>
610.0
485.0
</startCtrlPtY>
<endCtrlPtY>
124.0
</endCtrlPtY>
<endCtrlPtY>
639.0
514.0
</endCtrlPtY>
<startStateIndex>
9
28866,8 → 31979,8
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START LOOPBACK TRANSITION OBJECT
<transition>
## START STATE OBJECT
<state>
<attributes>
<name>
<status>
28874,13 → 31987,13
ABS
</status>
<value>
trans109
NOP30
<status>
LOCAL
</status>
</value>
<vis>
0
1
<status>
GLOBAL_VAR
</status>
28913,56 → 32026,12
3
</page>
</name>
<equation>
<cs_n>
<status>
ABS
</status>
<value>
!fifo_empty[fifo_sel]
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
69
</x2Obj>
<y2Obj>
46
</y2Obj>
<page>
3
</page>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1000
1'b0
<status>
GLOBAL_VAR
</status>
28974,7 → 32043,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
29000,73 → 32069,25
<page>
3
</page>
</priority>
</attributes>
<startState>
WRITE_DATA
</startState>
<endState>
WRITE_DATA
</endState>
<startPtX>
81.0
</startPtX>
<startPtY>
875.0
</startPtY>
<endPtX>
81.0
</endPtX>
<endPtY>
825.0
</endPtY>
<startCtrlPtX>
0.0
</startCtrlPtX>
<startCtrlPtY>
929.0
</startCtrlPtY>
<endCtrlPtY>
0.0
</endCtrlPtY>
<endCtrlPtY>
775.0
</endCtrlPtY>
<startStateIndex>
15
</startStateIndex>
<endStateIndex>
21
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
</transition>
## START LOOPBACK TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
</cs_n>
<cmd[2:0]>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
trans110
`CMD_NOP
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
0
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
output
<status>
GLOBAL_VAR
</status>
29092,60 → 32113,16
<page>
3
</page>
</name>
<equation>
</cmd[2:0]>
<a[14:0]>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
done
15'd0
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
16
</x2Obj>
<y2Obj>
-7
</y2Obj>
<page>
3
</page>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1
<status>
LOCAL
</status>
</value>
<vis>
2
29154,7 → 32131,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
29172,125 → 32149,6
</status>
</color>
<x2Obj>
30
</x2Obj>
<y2Obj>
-13
</y2Obj>
<page>
3
</page>
</priority>
</attributes>
<startState>
WRITE_DATA
</startState>
<endState>
NOP25
</endState>
<startPtX>
125.0
</startPtX>
<startPtY>
900.0
</startPtY>
<endPtX>
124.0
</endPtX>
<endPtY>
1100.0
</endPtY>
<startCtrlPtX>
125.0
</startCtrlPtX>
<startCtrlPtY>
943.0
</startCtrlPtY>
<endCtrlPtY>
124.0
</endCtrlPtY>
<endCtrlPtY>
1056.0
</endCtrlPtY>
<startStateIndex>
9
</startStateIndex>
<endStateIndex>
27
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE OBJECT
<state>
<attributes>
<name>
<status>
ABS
</status>
<value>
NOP25
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
29299,8 → 32157,8
<page>
3
</page>
</name>
<cs_n>
</a[14:0]>
<ref_ack>
<status>
GLOBAL_FIXED
</status>
29343,13 → 32201,13
<page>
3
</page>
</cs_n>
<cmd[2:0]>
</ref_ack>
<adr_init>
<status>
GLOBAL_FIXED
</status>
<value>
`CMD_NOP
1'b0
<status>
GLOBAL_VAR
</status>
29387,13 → 32245,13
<page>
3
</page>
</cmd[2:0]>
<a[14:0]>
</adr_init>
<adr_inc>
<status>
GLOBAL_FIXED
</status>
<value>
15'd0
1'b0
<status>
GLOBAL_VAR
</status>
29431,15 → 32289,15
<page>
3
</page>
</a[14:0]>
<ref_ack>
</adr_inc>
<fifo_re>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
1'b1
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
29475,13 → 32333,13
<page>
3
</page>
</ref_ack>
<adr_init>
</fifo_re>
<dqm[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
2'b00
<status>
GLOBAL_VAR
</status>
29519,8 → 32377,8
<page>
3
</page>
</adr_init>
<adr_inc>
</dqm[1:0]>
<read>
<status>
GLOBAL_FIXED
</status>
29563,15 → 32421,15
<page>
3
</page>
</adr_inc>
<fifo_re>
</read>
<write>
<status>
GLOBAL_FIXED
</status>
<value>
1'b1
1'b0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
29607,13 → 32465,13
<page>
3
</page>
</fifo_re>
<dqm[1:0]>
</write>
<ref_delay>
<status>
GLOBAL_FIXED
</status>
<value>
2'b00
1'b0
<status>
GLOBAL_VAR
</status>
29651,8 → 32509,8
<page>
3
</page>
</dqm[1:0]>
<read>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
29695,8 → 32553,8
<page>
3
</page>
</read>
<write>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
29739,19 → 32597,19
<page>
3
</page>
</write>
</bl_en>
</attributes>
<x0>
75
275
</x0>
<y0>
1100
975
</y0>
<x1>
175
375
</x1>
<y1>
1200
1075
</y1>
<reset>
false
29772,7 → 32630,7
ABS
</status>
<value>
trans111
trans119
<status>
LOCAL
</status>
29846,10 → 32704,10
</status>
</color>
<x2Obj>
0
7
</x2Obj>
<y2Obj>
-6
11
</y2Obj>
<page>
3
29901,34 → 32759,34
</priority>
</attributes>
<startState>
NOP25
NOP30
</startState>
<endState>
NOP31
NOP40
</endState>
<startPtX>
175.0
375.0
</startPtX>
<startPtY>
1150.0
1025.0
</startPtY>
<endPtX>
475.0
</endPtX>
<endPtY>
1150.0
1025.0
</endPtY>
<startCtrlPtX>
196.0
396.0
</startCtrlPtX>
<startCtrlPtY>
1150.0
1025.0
</startCtrlPtY>
<endCtrlPtY>
453.0
</endCtrlPtY>
<endCtrlPtY>
1150.0
1025.0
</endCtrlPtY>
<startStateIndex>
0
29979,7 → 32837,7
ABS
</status>
<value>
NOP30
READ_BURST
<status>
LOCAL
</status>
30287,9 → 33145,9
GLOBAL_FIXED
</status>
<value>
1'b1
1'b0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
30375,9 → 33233,9
GLOBAL_FIXED
</status>
<value>
1'b0
!bl_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
30458,51 → 33316,24
3
</page>
</write>
</attributes>
<x0>
675
</x0>
<y0>
950
</y0>
<x1>
775
</x1>
<y1>
1050
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<ref_delay>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
trans119
1'b0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
0
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
output
<status>
GLOBAL_VAR
</status>
30528,25 → 33359,25
<page>
3
</page>
</name>
<equation>
</ref_delay>
<pre_delay>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
1
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
1
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
output
<status>
GLOBAL_VAR
</status>
30564,23 → 33395,23
</status>
</color>
<x2Obj>
2
0
</x2Obj>
<y2Obj>
-5
0
</y2Obj>
<page>
3
</page>
</equation>
<priority>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
<value>
1000
!bl_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
30590,7 → 33421,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
30616,44 → 33447,23
<page>
3
</page>
</priority>
</bl_en>
</attributes>
<startState>
NOP30
</startState>
<endState>
NOP31
</endState>
<startPtX>
686.0
</startPtX>
<startPtY>
1032.0
</startPtY>
<endPtX>
563.0
</endPtX>
<endPtY>
1117.0
</endPtY>
<startCtrlPtX>
650.0
</startCtrlPtX>
<startCtrlPtY>
1058.0
</startCtrlPtY>
<endCtrlPtY>
603.0
</endCtrlPtY>
<endCtrlPtY>
1088.0
</endCtrlPtY>
<startStateIndex>
14
</startStateIndex>
<endStateIndex>
32
</endStateIndex>
<x0>
475
</x0>
<y0>
675
</y0>
<x1>
575
</x1>
<y1>
775
</y1>
<reset>
false
</reset>
<page>
3
</page>
30660,37 → 33470,10
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
</state>
## END STATE OBJECT
## START STATE OBJECT
<state>
<attributes>
<name>
<status>
30697,13 → 33480,13
ABS
</status>
<value>
trans122
NOP_tWR
<status>
LOCAL
</status>
</value>
<vis>
0
1
<status>
GLOBAL_VAR
</status>
30715,9 → 33498,9
</status>
</type>
<comment>
Write Recovery Time
<status>
GLOBAL_VAR
LOCAL
</status>
</comment>
<color>
30736,24 → 33519,24
3
</page>
</name>
<equation>
<cs_n>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
1
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
1
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
output
<status>
GLOBAL_VAR
</status>
30771,21 → 33554,21
</status>
</color>
<x2Obj>
7
0
</x2Obj>
<y2Obj>
9
0
</y2Obj>
<page>
3
</page>
</equation>
<priority>
</cs_n>
<cmd[2:0]>
<status>
GLOBAL_FIXED
</status>
<value>
1000
`CMD_NOP
<status>
GLOBAL_VAR
</status>
30797,7 → 33580,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
30823,100 → 33606,25
<page>
3
</page>
</priority>
</attributes>
<startState>
WRITE_ADDR
</startState>
<endState>
WRITE_DATA
</endState>
<startPtX>
125.0
</startPtX>
<startPtY>
750.0
</startPtY>
<endPtX>
124.0
</endPtX>
<endPtY>
800.0
</endPtY>
<startCtrlPtX>
125.0
</startCtrlPtX>
<startCtrlPtY>
760.0
</startCtrlPtY>
<endCtrlPtY>
124.0
</endCtrlPtY>
<endCtrlPtY>
789.0
</endCtrlPtY>
<startStateIndex>
9
</startStateIndex>
<endStateIndex>
27
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE OBJECT
<state>
<attributes>
<name>
</cmd[2:0]>
<a[14:0]>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
NOP27
15'd0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
1
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
output
<status>
GLOBAL_VAR
</status>
30942,8 → 33650,8
<page>
3
</page>
</name>
<cs_n>
</a[14:0]>
<ref_ack>
<status>
GLOBAL_FIXED
</status>
30986,13 → 33694,13
<page>
3
</page>
</cs_n>
<cmd[2:0]>
</ref_ack>
<adr_init>
<status>
GLOBAL_FIXED
</status>
<value>
`CMD_NOP
1'b0
<status>
GLOBAL_VAR
</status>
31030,13 → 33738,13
<page>
3
</page>
</cmd[2:0]>
<a[14:0]>
</adr_init>
<adr_inc>
<status>
GLOBAL_FIXED
</status>
<value>
15'd0
1'b0
<status>
GLOBAL_VAR
</status>
31074,8 → 33782,8
<page>
3
</page>
</a[14:0]>
<ref_ack>
</adr_inc>
<fifo_re>
<status>
GLOBAL_FIXED
</status>
31118,13 → 33826,13
<page>
3
</page>
</ref_ack>
<adr_init>
</fifo_re>
<dqm[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
2'b00
<status>
GLOBAL_VAR
</status>
31162,8 → 33870,8
<page>
3
</page>
</adr_init>
<adr_inc>
</dqm[1:0]>
<read>
<status>
GLOBAL_FIXED
</status>
31206,8 → 33914,8
<page>
3
</page>
</adr_inc>
<fifo_re>
</read>
<write>
<status>
GLOBAL_FIXED
</status>
31250,13 → 33958,13
<page>
3
</page>
</fifo_re>
<dqm[1:0]>
</write>
<ref_delay>
<status>
GLOBAL_FIXED
</status>
<value>
2'b00
1'b0
<status>
GLOBAL_VAR
</status>
31294,13 → 34002,13
<page>
3
</page>
</dqm[1:0]>
<read>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b1
!pre_delay_ack
<status>
LOCAL
</status>
31338,8 → 34046,8
<page>
3
</page>
</read>
<write>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
31382,19 → 34090,19
<page>
3
</page>
</write>
</bl_en>
</attributes>
<x0>
675
475
</x0>
<y0>
650
1125
</y0>
<x1>
775
575
</x1>
<y1>
750
1225
</y1>
<reset>
false
31415,7 → 34123,7
ABS
</status>
<value>
NOP28
WRITE_BURST
<status>
LOCAL
</status>
31723,9 → 34431,9
GLOBAL_FIXED
</status>
<value>
1'b0
!bl_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
31756,7 → 34464,7
0
</x2Obj>
<y2Obj>
0
-1
</y2Obj>
<page>
3
31811,9 → 34519,9
GLOBAL_FIXED
</status>
<value>
1'b1
1'b0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
31855,6 → 34563,50
GLOBAL_FIXED
</status>
<value>
1'b1
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
-2
</x2Obj>
<y2Obj>
-2
</y2Obj>
<page>
3
</page>
</write>
<ref_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
31893,19 → 34645,107
<page>
3
</page>
</write>
</ref_delay>
<pre_delay>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
<value>
!bl_ack
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
-4
</y2Obj>
<page>
3
</page>
</bl_en>
</attributes>
<x0>
675
75
</x0>
<y0>
800
675
</y0>
<x1>
775
175
</x1>
<y1>
900
775
</y1>
<reset>
false
31926,7 → 34766,7
ABS
</status>
<value>
trans124
trans133
<status>
LOCAL
</status>
32000,10 → 34840,10
</status>
</color>
<x2Obj>
0
8
</x2Obj>
<y2Obj>
0
9
</y2Obj>
<page>
3
32055,34 → 34895,34
</priority>
</attributes>
<startState>
NOP27
WRITE_ADDR
</startState>
<endState>
NOP28
WRITE_BURST
</endState>
<startPtX>
725.0
125.0
</startPtX>
<startPtY>
750.0
625.0
</startPtY>
<endPtX>
725.0
124.0
</endPtX>
<endPtY>
800.0
675.0
</endPtY>
<startCtrlPtX>
725.0
125.0
</startCtrlPtX>
<startCtrlPtY>
763.0
635.0
</startCtrlPtY>
<endCtrlPtY>
725.0
124.0
</endCtrlPtY>
<endCtrlPtY>
787.0
664.0
</endCtrlPtY>
<startStateIndex>
9
32133,7 → 34973,7
ABS
</status>
<value>
trans125
trans134
<status>
LOCAL
</status>
32177,9 → 35017,9
ABS
</status>
<value>
1
pre_delay_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
32207,10 → 35047,10
</status>
</color>
<x2Obj>
4
-4
</x2Obj>
<y2Obj>
-4
14
</y2Obj>
<page>
3
32262,40 → 35102,40
</priority>
</attributes>
<startState>
NOP28
NOP_tWR
</startState>
<endState>
NOP29
PRECHARGE
</endState>
<startPtX>
675.0
575.0
</startPtX>
<startPtY>
850.0
1175.0
</startPtY>
<endPtX>
575.0
675.0
</endPtX>
<endPtY>
850.0
1175.0
</endPtY>
<startCtrlPtX>
653.0
596.0
</startCtrlPtX>
<startCtrlPtY>
850.0
1175.0
</startCtrlPtY>
<endCtrlPtY>
596.0
653.0
</endCtrlPtY>
<endCtrlPtY>
850.0
1175.0
</endCtrlPtY>
<startStateIndex>
18
0
</startStateIndex>
<endStateIndex>
0
18
</endStateIndex>
<page>
3
32332,8 → 35172,8
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE OBJECT
<state>
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
32340,13 → 35180,13
ABS
</status>
<value>
NOP32
trans135
<status>
LOCAL
</status>
</value>
<vis>
1
0
<status>
GLOBAL_VAR
</status>
32379,24 → 35219,24
3
</page>
</name>
<cs_n>
<equation>
<status>
GLOBAL_FIXED
ABS
</status>
<value>
1'b0
1
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
def_type
<status>
GLOBAL_VAR
</status>
32417,18 → 35257,18
0
</x2Obj>
<y2Obj>
0
-4
</y2Obj>
<page>
3
</page>
</cs_n>
<cmd[2:0]>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
`CMD_NOP
1000
<status>
GLOBAL_VAR
</status>
32440,7 → 35280,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
32466,25 → 35306,100
<page>
3
</page>
</cmd[2:0]>
<a[14:0]>
</priority>
</attributes>
<startState>
NOP31
</startState>
<endState>
NOP_tWR
</endState>
<startPtX>
375.0
</startPtX>
<startPtY>
1175.0
</startPtY>
<endPtX>
475.0
</endPtX>
<endPtY>
1175.0
</endPtY>
<startCtrlPtX>
396.0
</startCtrlPtX>
<startCtrlPtY>
1175.0
</startCtrlPtY>
<endCtrlPtY>
453.0
</endCtrlPtY>
<endCtrlPtY>
1175.0
</endCtrlPtY>
<startStateIndex>
0
</startStateIndex>
<endStateIndex>
18
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
GLOBAL_FIXED
ABS
</status>
<value>
15'd0
trans136
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
2
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
def_type
<status>
GLOBAL_VAR
</status>
32510,25 → 35425,25
<page>
3
</page>
</a[14:0]>
<ref_ack>
</name>
<equation>
<status>
GLOBAL_FIXED
ABS
</status>
<value>
1'b0
bl_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
2
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
def_type
<status>
GLOBAL_VAR
</status>
32546,21 → 35461,21
</status>
</color>
<x2Obj>
0
19
</x2Obj>
<y2Obj>
0
-6
</y2Obj>
<page>
3
</page>
</ref_ack>
<adr_init>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
1000
<status>
GLOBAL_VAR
</status>
32572,7 → 35487,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
32598,69 → 35513,100
<page>
3
</page>
</adr_init>
<adr_inc>
</priority>
</attributes>
<startState>
WRITE_BURST
</startState>
<endState>
NOP29
</endState>
<startPtX>
163.0
</startPtX>
<startPtY>
757.0
</startPtY>
<endPtX>
286.0
</endPtX>
<endPtY>
842.0
</endPtY>
<startCtrlPtX>
200.0
</startCtrlPtX>
<startCtrlPtY>
779.0
</startCtrlPtY>
<endCtrlPtY>
243.0
</endCtrlPtY>
<endCtrlPtY>
809.0
</endCtrlPtY>
<startStateIndex>
4
</startStateIndex>
<endStateIndex>
22
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
GLOBAL_FIXED
ABS
</status>
<value>
1'b0
trans137
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</adr_inc>
<fifo_re>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
def_type
<status>
GLOBAL_VAR
</status>
32686,25 → 35632,25
<page>
3
</page>
</fifo_re>
<dqm[1:0]>
</name>
<equation>
<status>
GLOBAL_FIXED
ABS
</status>
<value>
2'b00
bl_ack
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
2
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
def_type
<status>
GLOBAL_VAR
</status>
32722,21 → 35668,21
</status>
</color>
<x2Obj>
0
-7
</x2Obj>
<y2Obj>
0
-9
</y2Obj>
<page>
3
</page>
</dqm[1:0]>
<read>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
1000
<status>
GLOBAL_VAR
</status>
32748,54 → 35694,10
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</read>
<write>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
32818,23 → 35720,44
<page>
3
</page>
</write>
</priority>
</attributes>
<x0>
800
</x0>
<y0>
1100
</y0>
<x1>
900
</x1>
<y1>
1200
</y1>
<reset>
false
</reset>
<startState>
READ_BURST
</startState>
<endState>
NOP29
</endState>
<startPtX>
486.0
</startPtX>
<startPtY>
757.0
</startPtY>
<endPtX>
363.0
</endPtX>
<endPtY>
842.0
</endPtY>
<startCtrlPtX>
459.0
</startCtrlPtX>
<startCtrlPtY>
777.0
</startCtrlPtY>
<endCtrlPtY>
405.0
</endCtrlPtY>
<endCtrlPtY>
812.0
</endCtrlPtY>
<startStateIndex>
14
</startStateIndex>
<endStateIndex>
32
</endStateIndex>
<page>
3
</page>
32841,8 → 35764,35
<color>
-16777216
</color>
</state>
## END STATE OBJECT
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE OBJECT
<state>
<attributes>
32851,7 → 35801,7
ABS
</status>
<value>
NOP33
NOP40
<status>
LOCAL
</status>
33330,127 → 36280,12
3
</page>
</write>
</attributes>
<x0>
800
</x0>
<y0>
950
</y0>
<x1>
900
</x1>
<y1>
1050
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<ref_delay>
<status>
ABS
</status>
<value>
trans126
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
1
<status>
GLOBAL_VAR
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
7
</x2Obj>
<y2Obj>
7
</y2Obj>
<page>
3
</page>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1000
1'b0
<status>
GLOBAL_VAR
</status>
33462,7 → 36297,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
33488,144 → 36323,25
<page>
3
</page>
</priority>
</attributes>
<startState>
NOP32
</startState>
<endState>
NOP33
</endState>
<startPtX>
850.0
</startPtX>
<startPtY>
1100.0
</startPtY>
<endPtX>
850.0
</endPtX>
<endPtY>
1050.0
</endPtY>
<startCtrlPtX>
850.0
</startCtrlPtX>
<startCtrlPtY>
1094.0
</startCtrlPtY>
<endCtrlPtY>
850.0
</endCtrlPtY>
<endCtrlPtY>
1055.0
</endCtrlPtY>
<startStateIndex>
27
</startStateIndex>
<endStateIndex>
9
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
</ref_delay>
<pre_delay>
<status>
ABS
GLOBAL_FIXED
</status>
<value>
trans127
1'b0
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
1
<status>
GLOBAL_VAR
</status>
</value>
<vis>
1
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
output
<status>
GLOBAL_VAR
</status>
33651,13 → 36367,13
<page>
3
</page>
</equation>
<priority>
</pre_delay>
<bl_en>
<status>
GLOBAL_FIXED
</status>
<value>
1000
1'b0
<status>
GLOBAL_VAR
</status>
33669,7 → 36385,7
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
33695,44 → 36411,23
<page>
3
</page>
</priority>
</bl_en>
</attributes>
<startState>
NOP33
</startState>
<endState>
PRECHARGE
</endState>
<startPtX>
841.0
</startPtX>
<startPtY>
950.0
</startPtY>
<endPtX>
783.0
</endPtX>
<endPtY>
499.0
</endPtY>
<startCtrlPtX>
832.0
</startCtrlPtX>
<startCtrlPtY>
861.0
</startCtrlPtY>
<endCtrlPtY>
777.0
</endCtrlPtY>
<endCtrlPtY>
602.0
</endCtrlPtY>
<startStateIndex>
26
</startStateIndex>
<endStateIndex>
8
</endStateIndex>
<x0>
475
</x0>
<y0>
975
</y0>
<x1>
575
</x1>
<y1>
1075
</y1>
<reset>
false
</reset>
<page>
3
</page>
33739,35 → 36434,8
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
</state>
## END STATE OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
33776,7 → 36444,7
ABS
</status>
<value>
trans130
trans138
<status>
LOCAL
</status>
33820,9 → 36488,9
ABS
</status>
<value>
1
adr_init_delay
<status>
GLOBAL_VAR
LOCAL
</status>
</value>
<vis>
33853,7 → 36521,7
0
</x2Obj>
<y2Obj>
-3
0
</y2Obj>
<page>
3
33905,40 → 36573,40
</priority>
</attributes>
<startState>
NOP31
NOP40
</startState>
<endState>
NOP32
NOP31
</endState>
<startPtX>
575.0
486.0
</startPtX>
<startPtY>
1150.0
1057.0
</startPtY>
<endPtX>
800.0
363.0
</endPtX>
<endPtY>
1150.0
1142.0
</endPtY>
<startCtrlPtX>
623.0
451.0
</startCtrlPtX>
<startCtrlPtY>
1150.0
1083.0
</startCtrlPtY>
<endCtrlPtY>
751.0
401.0
</endCtrlPtY>
<endCtrlPtY>
1150.0
1116.0
</endCtrlPtY>
<startStateIndex>
0
14
</startStateIndex>
<endStateIndex>
18
32
</endStateIndex>
<page>
3
/verilog/versatile_mem_ctrl_ip.v
1259,6 → 1259,274
qi <= q_next;
assign q = q_next;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile memory controller ////
//// ////
//// Description ////
//// A modular wishbone compatible memory controller with support////
//// for various types of memory configurations ////
//// ////
//// To Do: ////
//// - add support for additional SDRAM variants ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module ref_delay_counter
(
input cke,
output reg zq,
input clk,
input rst
);
parameter wrap_value = 6'd12;
reg [6:1] qi;
wire [6:1] q_next;
assign q_next =
(qi == wrap_value) ? 6'd0 :
qi + 6'd1;
always @ (posedge clk or posedge rst)
if (rst)
qi <= 6'd0;
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == 6'd0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile memory controller ////
//// ////
//// Description ////
//// A modular wishbone compatible memory controller with support////
//// for various types of memory configurations ////
//// ////
//// To Do: ////
//// - add support for additional SDRAM variants ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module pre_delay_counter
(
input cke,
output reg zq,
input clk,
input rst
);
parameter wrap_value = 4'd2;
reg [4:1] qi;
wire [4:1] q_next;
assign q_next =
(qi == wrap_value) ? 4'd0 :
qi + 4'd1;
always @ (posedge clk or posedge rst)
if (rst)
qi <= 4'd0;
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == 4'd0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile memory controller ////
//// ////
//// Description ////
//// A modular wishbone compatible memory controller with support////
//// for various types of memory configurations ////
//// ////
//// To Do: ////
//// - add support for additional SDRAM variants ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module latency_counter
(
input cke,
output reg zq,
input clk,
input rst
);
parameter wrap_value = 4'd3;
reg [4:1] qi;
wire [4:1] q_next;
assign q_next =
(qi == wrap_value) ? 4'd0 :
qi + 4'd1;
always @ (posedge clk or posedge rst)
if (rst)
qi <= 4'd0;
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == 4'd0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile memory controller ////
//// ////
//// Description ////
//// A modular wishbone compatible memory controller with support////
//// for various types of memory configurations ////
//// ////
//// To Do: ////
//// - add support for additional SDRAM variants ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module burst_length_counter
(
input cke,
output reg zq,
input clk,
input rst
);
parameter wrap_value = 3'd3;
reg [3:1] qi;
wire [3:1] q_next;
assign q_next =
(qi == wrap_value) ? 3'd0 :
qi + 3'd1;
always @ (posedge clk or posedge rst)
if (rst)
qi <= 3'd0;
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == 3'd0;
endmodule
`timescale 1ns/1ns
module sdr_16 (
output reg [14:0] a,
1627,18 → 1895,25
output reg [14:0] a,
output reg adr_inc,
output reg adr_init,
output reg bl_en,
output reg [2:0] cmd,
output reg cs_n,
output reg [1:0] dqm,
output reg fifo_re,
output reg pre_delay,
output reg read,
output reg ref_ack,
output reg ref_delay,
output reg write,
input wire adr_init_delay,
input wire bl_ack,
input wire [3:0] burst_adr,
input wire cke_en,
input wire done,
input wire [7:0] fifo_empty,
input wire [2:0] fifo_sel,
input wire pre_delay_ack,
input wire ref_delay_ack,
input wire ref_req,
input wire sdram_clk,
input wire [35:0] tx_fifo_dat_o,
1645,134 → 1920,135
input wire wb_rst
);
parameter
IDLE = 0,
ACT_ROW = 1,
AREF = 2,
AWAIT_CMD = 3,
LEMR2 = 4,
LEMR3 = 5,
LEMR_0 = 6,
LEMR_1 = 7,
LEMR_2 = 8,
LMR_0 = 9,
LMR_1 = 10,
NOP0 = 11,
NOP1 = 12,
NOP10 = 13,
NOP11 = 14,
NOP2 = 15,
NOP20 = 16,
NOP21 = 17,
NOP22 = 18,
NOP25 = 19,
NOP26 = 20,
NOP27 = 21,
NOP28 = 22,
NOP29 = 23,
NOP3 = 24,
NOP30 = 25,
NOP31 = 26,
NOP32 = 27,
NOP33 = 28,
NOP4 = 29,
NOP5 = 30,
NOP6 = 31,
NOP7 = 32,
NOP8 = 33,
NOP9 = 34,
PRE = 35,
PRECHARGE = 36,
PRE_ALL_0 = 37,
READ = 38,
READ_ADDR = 39,
REF_0 = 40,
REF_1 = 41,
WRITE_ADDR = 42,
WRITE_DATA = 43;
reg [43:0] state;
reg [43:0] nextstate;
IDLE = 0,
ACT_ROW = 1,
AREF = 2,
AWAIT_CMD = 3,
LEMR2 = 4,
LEMR3 = 5,
LEMR_0 = 6,
LEMR_1 = 7,
LEMR_2 = 8,
LMR_0 = 9,
LMR_1 = 10,
NOP0 = 11,
NOP1 = 12,
NOP10 = 13,
NOP11 = 14,
NOP2 = 15,
NOP26 = 16,
NOP29 = 17,
NOP3 = 18,
NOP30 = 19,
NOP31 = 20,
NOP4 = 21,
NOP40 = 22,
NOP5 = 23,
NOP6 = 24,
NOP7 = 25,
NOP8 = 26,
NOP9 = 27,
NOP_tRCD = 28,
NOP_tRFC = 29,
NOP_tWR = 30,
PRE = 31,
PRECHARGE = 32,
PRE_ALL_0 = 33,
READ_ADDR = 34,
READ_BURST = 35,
REF_0 = 36,
REF_1 = 37,
WRITE_ADDR = 38,
WRITE_BURST = 39;
reg [39:0] state;
reg [39:0] nextstate;
always @* begin
nextstate = 44'b00000000000000000000000000000000000000000000;
nextstate = 40'b0000000000000000000000000000000000000000;
adr_inc = 1'b0;
adr_init = 1'b0;
bl_en = 1'b0;
fifo_re = 1'b0;
pre_delay = 1'b0;
read = 1'b0;
ref_ack = 1'b0;
ref_delay = 1'b0;
write = 1'b0;
case (1'b1)
state[IDLE] : begin
state[IDLE] : begin
begin
nextstate[NOP0] = 1'b1;
end
end
state[ACT_ROW] : begin
state[ACT_ROW] : begin
if (tx_fifo_dat_o[5]) begin
nextstate[NOP22] = 1'b1;
nextstate[NOP_tRCD] = 1'b1;
end
else begin
nextstate[NOP26] = 1'b1;
end
end
state[AREF] : begin
state[AREF] : begin
ref_ack = 1'b1;
ref_delay = 1'b1;
begin
nextstate[NOP21] = 1'b1;
nextstate[NOP_tRFC] = 1'b1;
end
end
state[AWAIT_CMD] : begin
state[AWAIT_CMD] : begin
adr_init = !(&fifo_empty);
if (ref_req) begin
nextstate[AREF] = 1'b1;
end
else if (!(&fifo_empty)) begin
nextstate[NOP20] = 1'b1;
nextstate[ACT_ROW] = 1'b1;
end
else begin
nextstate[AWAIT_CMD] = 1'b1;
end
end
state[LEMR2] : begin
state[LEMR2] : begin
ref_ack = 1'b1;
begin
nextstate[NOP2] = 1'b1;
end
end
state[LEMR3] : begin
state[LEMR3] : begin
ref_ack = 1'b1;
begin
nextstate[NOP3] = 1'b1;
end
end
state[LEMR_0] : begin
state[LEMR_0] : begin
ref_ack = 1'b1;
begin
nextstate[NOP4] = 1'b1;
end
end
state[LEMR_1] : begin
state[LEMR_1] : begin
ref_ack = 1'b1;
begin
nextstate[NOP10] = 1'b1;
end
end
state[LEMR_2] : begin
state[LEMR_2] : begin
ref_ack = 1'b1;
begin
nextstate[NOP11] = 1'b1;
end
end
state[LMR_0] : begin
state[LMR_0] : begin
ref_ack = 1'b1;
begin
nextstate[NOP5] = 1'b1;
end
end
state[LMR_1] : begin
state[LMR_1] : begin
ref_ack = 1'b1;
begin
nextstate[NOP9] = 1'b1;
end
end
state[NOP0] : begin
state[NOP0] : begin
if (cke_en) begin
nextstate[PRE] = 1'b1;
end
1780,7 → 2056,7
nextstate[NOP0] = 1'b1;
end
end
state[NOP1] : begin
state[NOP1] : begin
if (ref_req) begin
nextstate[LEMR2] = 1'b1;
end
1788,7 → 2064,7
nextstate[NOP1] = 1'b1;
end
end
state[NOP10] : begin
state[NOP10] : begin
if (ref_req) begin
nextstate[LEMR_2] = 1'b1;
end
1796,7 → 2072,7
nextstate[NOP10] = 1'b1;
end
end
state[NOP11] : begin
state[NOP11] : begin
if (ref_req) begin
nextstate[AWAIT_CMD] = 1'b1;
end
1804,7 → 2080,7
nextstate[NOP11] = 1'b1;
end
end
state[NOP2] : begin
state[NOP2] : begin
if (ref_req) begin
nextstate[LEMR3] = 1'b1;
end
1812,51 → 2088,20
nextstate[NOP2] = 1'b1;
end
end
state[NOP20] : begin
if (ref_req) begin
nextstate[ACT_ROW] = 1'b1;
end
else begin
nextstate[NOP20] = 1'b1;
end
end
state[NOP21] : begin
state[NOP26] : begin
begin
nextstate[AWAIT_CMD] = 1'b1;
end
end
state[NOP22] : begin
begin
nextstate[WRITE_ADDR] = 1'b1;
end
end
state[NOP25] : begin
fifo_re = 1'b1;
begin
nextstate[NOP31] = 1'b1;
end
end
state[NOP26] : begin
begin
nextstate[READ_ADDR] = 1'b1;
end
end
state[NOP27] : begin
begin
nextstate[NOP28] = 1'b1;
state[NOP29] : begin
if (done) begin
nextstate[NOP30] = 1'b1;
end
end
state[NOP28] : begin
begin
nextstate[NOP29] = 1'b1;
else begin
nextstate[NOP29] = 1'b1;
end
end
state[NOP29] : begin
begin
nextstate[READ] = 1'b1;
end
end
state[NOP3] : begin
state[NOP3] : begin
if (ref_req) begin
nextstate[LEMR_0] = 1'b1;
end
1864,29 → 2109,20
nextstate[NOP3] = 1'b1;
end
end
state[NOP30] : begin
state[NOP30] : begin
fifo_re = 1'b1;
begin
nextstate[NOP31] = 1'b1;
nextstate[NOP40] = 1'b1;
end
end
state[NOP31] : begin
state[NOP31] : begin
adr_init = 1'b1;
pre_delay = 1'b1;
begin
nextstate[NOP32] = 1'b1;
nextstate[NOP_tWR] = 1'b1;
end
end
state[NOP32] : begin
begin
nextstate[NOP33] = 1'b1;
end
end
state[NOP33] : begin
begin
nextstate[PRECHARGE] = 1'b1;
end
end
state[NOP4] : begin
state[NOP4] : begin
if (ref_req) begin
nextstate[LMR_0] = 1'b1;
end
1894,7 → 2130,15
nextstate[NOP4] = 1'b1;
end
end
state[NOP5] : begin
state[NOP40] : begin
if (adr_init_delay) begin
nextstate[NOP31] = 1'b1;
end
else begin
nextstate[NOP40] = 1'b1;
end
end
state[NOP5] : begin
if (ref_req) begin
nextstate[PRE_ALL_0] = 1'b1;
end
1902,7 → 2146,7
nextstate[NOP5] = 1'b1;
end
end
state[NOP6] : begin
state[NOP6] : begin
if (ref_req) begin
nextstate[REF_0] = 1'b1;
end
1910,7 → 2154,7
nextstate[NOP6] = 1'b1;
end
end
state[NOP7] : begin
state[NOP7] : begin
if (ref_req) begin
nextstate[REF_1] = 1'b1;
end
1918,7 → 2162,7
nextstate[NOP7] = 1'b1;
end
end
state[NOP8] : begin
state[NOP8] : begin
if (ref_req) begin
nextstate[LMR_1] = 1'b1;
end
1926,7 → 2170,7
nextstate[NOP8] = 1'b1;
end
end
state[NOP9] : begin
state[NOP9] : begin
if (ref_req) begin
nextstate[LEMR_1] = 1'b1;
end
1934,69 → 2178,92
nextstate[NOP9] = 1'b1;
end
end
state[PRE] : begin
state[NOP_tRCD] : begin
begin
nextstate[WRITE_ADDR] = 1'b1;
end
end
state[NOP_tRFC] : begin
ref_delay = !ref_delay_ack;
if (ref_delay_ack) begin
nextstate[AWAIT_CMD] = 1'b1;
end
else begin
nextstate[NOP_tRFC] = 1'b1;
end
end
state[NOP_tWR] : begin
pre_delay = !pre_delay_ack;
if (pre_delay_ack) begin
nextstate[PRECHARGE] = 1'b1;
end
else begin
nextstate[NOP_tWR] = 1'b1;
end
end
state[PRE] : begin
ref_ack = 1'b1;
begin
nextstate[NOP1] = 1'b1;
end
end
state[PRECHARGE] : begin
state[PRECHARGE] : begin
begin
nextstate[AWAIT_CMD] = 1'b1;
end
end
state[PRE_ALL_0] : begin
state[PRE_ALL_0] : begin
ref_ack = 1'b1;
begin
nextstate[NOP6] = 1'b1;
end
end
state[READ] : begin
adr_inc = !done;
if (done) begin
nextstate[NOP30] = 1'b1;
state[READ_ADDR] : begin
bl_en = 1'b1;
read = 1'b1;
begin
nextstate[READ_BURST] = 1'b1;
end
end
state[READ_BURST] : begin
bl_en = !bl_ack;
read = !bl_ack;
if (bl_ack) begin
nextstate[NOP29] = 1'b1;
end
else begin
nextstate[READ] = 1'b1;
nextstate[READ_BURST] = 1'b1;
end
end
state[READ_ADDR] : begin
begin
nextstate[NOP27] = 1'b1;
end
end
state[REF_0] : begin
state[REF_0] : begin
ref_ack = 1'b1;
begin
nextstate[NOP7] = 1'b1;
end
end
state[REF_1] : begin
state[REF_1] : begin
ref_ack = 1'b1;
begin
nextstate[NOP8] = 1'b1;
end
end
state[WRITE_ADDR]: begin
adr_inc = !done & !fifo_empty[fifo_sel];
state[WRITE_ADDR] : begin
bl_en = 1'b1;
fifo_re = 1'b1;
write = 1'b1;
begin
nextstate[WRITE_DATA] = 1'b1;
nextstate[WRITE_BURST] = 1'b1;
end
end
state[WRITE_DATA]: begin
adr_inc = !done & !fifo_empty[fifo_sel];
fifo_re = !done;
state[WRITE_BURST]: begin
bl_en = !bl_ack;
fifo_re = !bl_ack;
write = 1'b1;
if (done) begin
nextstate[NOP25] = 1'b1;
if (bl_ack) begin
nextstate[NOP29] = 1'b1;
end
else if (!fifo_empty[fifo_sel]) begin
nextstate[WRITE_DATA] = 1'b1;
end
else begin
nextstate[WRITE_DATA] = 1'b1;
nextstate[WRITE_BURST] = 1'b1;
end
end
endcase
2003,7 → 2270,7
end
always @(posedge sdram_clk or posedge wb_rst) begin
if (wb_rst)
state <= 44'b00000000000000000000000000000000000000000001 << IDLE;
state <= 40'b0000000000000000000000000000000000000001 << IDLE;
else
state <= nextstate;
end
2013,7 → 2280,6
cmd[2:0] <= 3'b111;
cs_n <= 1'b1;
dqm[1:0] <= 2'b00;
read <= 1'b0;
end
else begin
a[14:0] <= 15'd0;
2020,131 → 2286,111
cmd[2:0] <= 3'b111;
cs_n <= 1'b0;
dqm[1:0] <= 2'b00;
read <= 1'b0;
case (1'b1)
nextstate[IDLE] : begin
nextstate[IDLE] : begin
cs_n <= 1'b1;
end
nextstate[ACT_ROW] : begin
nextstate[ACT_ROW] : begin
a[14:0] <= {tx_fifo_dat_o[28:27],tx_fifo_dat_o[26:14]};
cmd[2:0] <= 3'b011;
end
nextstate[AREF] : begin
nextstate[AREF] : begin
a[14:0] <= a;
cmd[2:0] <= 3'b001;
end
nextstate[AWAIT_CMD] : begin
nextstate[AWAIT_CMD] : begin
a[14:0] <= a;
cs_n <= 1'b1;
end
nextstate[LEMR2] : begin
nextstate[LEMR2] : begin
a[14:0] <= {2'b10,5'b00000,1'b0,7'b0000000};
cmd[2:0] <= 3'b000;
end
nextstate[LEMR3] : begin
nextstate[LEMR3] : begin
a[14:0] <= {2'b11,13'b0000000000000};
cmd[2:0] <= 3'b000;
end
nextstate[LEMR_0] : begin
nextstate[LEMR_0] : begin
a[14:0] <= {2'b01,1'b0,1'b0,1'b0,3'b000,1'b0,3'b000,1'b0,1'b0,1'b0};
cmd[2:0] <= 3'b000;
end
nextstate[LEMR_1] : begin
nextstate[LEMR_1] : begin
a[14:0] <= {2'b01,1'b0,1'b0,1'b0,3'b111,1'b0,3'b000,1'b0,1'b0,1'b0};
cmd[2:0] <= 3'b000;
end
nextstate[LEMR_2] : begin
nextstate[LEMR_2] : begin
a[14:0] <= {2'b01,1'b0,1'b0,1'b0,3'b000,1'b0,3'b000,1'b0,1'b0,1'b0};
cmd[2:0] <= 3'b000;
end
nextstate[LMR_0] : begin
nextstate[LMR_0] : begin
a[14:0] <= {2'b00,4'b0000,1'b1,8'b00000000};
cmd[2:0] <= 3'b000;
end
nextstate[LMR_1] : begin
a[14:0] <= {2'b00,1'b0,3'b001,1'b0,1'b0,1'b0,3'b100,1'b0,3'b011};
nextstate[LMR_1] : begin
a[14:0] <= {2'b00,1'b0,3'b001,1'b0,1'b0,1'b0,3'b111,1'b0,3'b011};
cmd[2:0] <= 3'b000;
end
nextstate[NOP1] : begin
nextstate[NOP1] : begin
a[14:0] <= a;
end
nextstate[NOP10] : begin
nextstate[NOP10] : begin
a[14:0] <= a;
end
nextstate[NOP11] : begin
nextstate[NOP11] : begin
a[14:0] <= a;
end
nextstate[NOP2] : begin
nextstate[NOP2] : begin
a[14:0] <= a;
end
nextstate[NOP22] : begin
nextstate[NOP3] : begin
a[14:0] <= a;
end
nextstate[NOP26] : begin
a[14:0] <= a[14:0];
end
nextstate[NOP27] : begin
read <= 1'b1;
end
nextstate[NOP28] : begin
read <= 1'b1;
end
nextstate[NOP29] : begin
read <= 1'b1;
end
nextstate[NOP3] : begin
nextstate[NOP31] : begin
a[14:0] <= a;
end
nextstate[NOP31] : begin
nextstate[NOP4] : begin
a[14:0] <= a;
end
nextstate[NOP4] : begin
nextstate[NOP5] : begin
a[14:0] <= a;
end
nextstate[NOP5] : begin
nextstate[NOP6] : begin
a[14:0] <= a;
end
nextstate[NOP6] : begin
nextstate[NOP7] : begin
a[14:0] <= a;
end
nextstate[NOP7] : begin
nextstate[NOP8] : begin
a[14:0] <= a;
end
nextstate[NOP8] : begin
nextstate[NOP9] : begin
a[14:0] <= a;
end
nextstate[NOP9] : begin
a[14:0] <= a;
end
nextstate[PRE] : begin
nextstate[PRE] : begin
a[14:0] <= {2'b00,13'b0010000000000};
cmd[2:0] <= 3'b010;
end
nextstate[PRECHARGE] : begin
nextstate[PRECHARGE] : begin
a[14:0] <= {2'b00,13'b0010000000000};
cmd[2:0] <= 3'b010;
end
nextstate[PRE_ALL_0] : begin
nextstate[PRE_ALL_0] : begin
a[14:0] <= {2'b00,13'b0010000000000};
cmd[2:0] <= 3'b010;
end
nextstate[READ] : begin
a[14:0] <= a;
end
nextstate[READ_ADDR] : begin
nextstate[READ_ADDR] : begin
a[14:0] <= {tx_fifo_dat_o[28:27],{4'b0000,tx_fifo_dat_o[13:10],burst_adr,1'b0}};
cmd[2:0] <= 3'b101;
read <= 1'b1;
end
nextstate[REF_0] : begin
nextstate[REF_0] : begin
a[14:0] <= a;
cmd[2:0] <= 3'b001;
end
nextstate[REF_1] : begin
nextstate[REF_1] : begin
a[14:0] <= a;
cmd[2:0] <= 3'b001;
end
nextstate[WRITE_ADDR]: begin
nextstate[WRITE_ADDR] : begin
a[14:0] <= {tx_fifo_dat_o[28:27],{4'b0000,tx_fifo_dat_o[13:10],burst_adr,1'b0}};
cmd[2:0] <= 3'b100;
end
2151,99 → 2397,91
endcase
end
end
reg [79:0] statename;
reg [87:0] statename;
always @* begin
case (1'b1)
state[IDLE] :
state[IDLE] :
statename = "IDLE";
state[ACT_ROW] :
state[ACT_ROW] :
statename = "ACT_ROW";
state[AREF] :
state[AREF] :
statename = "AREF";
state[AWAIT_CMD] :
state[AWAIT_CMD] :
statename = "AWAIT_CMD";
state[LEMR2] :
state[LEMR2] :
statename = "LEMR2";
state[LEMR3] :
state[LEMR3] :
statename = "LEMR3";
state[LEMR_0] :
state[LEMR_0] :
statename = "LEMR_0";
state[LEMR_1] :
state[LEMR_1] :
statename = "LEMR_1";
state[LEMR_2] :
state[LEMR_2] :
statename = "LEMR_2";
state[LMR_0] :
state[LMR_0] :
statename = "LMR_0";
state[LMR_1] :
state[LMR_1] :
statename = "LMR_1";
state[NOP0] :
state[NOP0] :
statename = "NOP0";
state[NOP1] :
state[NOP1] :
statename = "NOP1";
state[NOP10] :
state[NOP10] :
statename = "NOP10";
state[NOP11] :
state[NOP11] :
statename = "NOP11";
state[NOP2] :
state[NOP2] :
statename = "NOP2";
state[NOP20] :
statename = "NOP20";
state[NOP21] :
statename = "NOP21";
state[NOP22] :
statename = "NOP22";
state[NOP25] :
statename = "NOP25";
state[NOP26] :
state[NOP26] :
statename = "NOP26";
state[NOP27] :
statename = "NOP27";
state[NOP28] :
statename = "NOP28";
state[NOP29] :
state[NOP29] :
statename = "NOP29";
state[NOP3] :
state[NOP3] :
statename = "NOP3";
state[NOP30] :
state[NOP30] :
statename = "NOP30";
state[NOP31] :
state[NOP31] :
statename = "NOP31";
state[NOP32] :
statename = "NOP32";
state[NOP33] :
statename = "NOP33";
state[NOP4] :
state[NOP4] :
statename = "NOP4";
state[NOP5] :
state[NOP40] :
statename = "NOP40";
state[NOP5] :
statename = "NOP5";
state[NOP6] :
state[NOP6] :
statename = "NOP6";
state[NOP7] :
state[NOP7] :
statename = "NOP7";
state[NOP8] :
state[NOP8] :
statename = "NOP8";
state[NOP9] :
state[NOP9] :
statename = "NOP9";
state[PRE] :
state[NOP_tRCD] :
statename = "NOP_tRCD";
state[NOP_tRFC] :
statename = "NOP_tRFC";
state[NOP_tWR] :
statename = "NOP_tWR";
state[PRE] :
statename = "PRE";
state[PRECHARGE] :
state[PRECHARGE] :
statename = "PRECHARGE";
state[PRE_ALL_0] :
state[PRE_ALL_0] :
statename = "PRE_ALL_0";
state[READ] :
statename = "READ";
state[READ_ADDR] :
state[READ_ADDR] :
statename = "READ_ADDR";
state[REF_0] :
state[READ_BURST] :
statename = "READ_BURST";
state[REF_0] :
statename = "REF_0";
state[REF_1] :
state[REF_1] :
statename = "REF_1";
state[WRITE_ADDR]:
state[WRITE_ADDR] :
statename = "WRITE_ADDR";
state[WRITE_DATA]:
statename = "WRITE_DATA";
default :
statename = "XXXXXXXXXX";
state[WRITE_BURST]:
statename = "WRITE_BURST";
default :
statename = "XXXXXXXXXXX";
endcase
end
endmodule
2400,6 → 2638,8
output ck_pad_o,
output ck_n_pad_o,
output cke_pad_o,
output ck_fb_pad_o,
input ck_fb_pad_i,
output cs_n_pad_o,
output ras_pad_o,
output cas_pad_o,
2408,14 → 2648,17
output [1:0] dm_rdqs_o,
output [1:0] ba_pad_o,
output [12:0] addr_pad_o,
input [15:0] dq_i,
output [15:0] dq_o,
output dq_oe,
input [1:0] dqs_i,
output [1:0] dqs_o,
//input [15:0] dq_i,
//output [15:0] dq_o,
inout [15:0] dq_pad_io,
//output dq_oe,
//input [1:0] dqs_i,
//output [1:0] dqs_o,
inout [1:0] dqs_pad_io,
output dqs_oe,
input [1:0] dqs_n_i,
output [1:0] dqs_n_o,
//input [1:0] dqs_n_i,
//output [1:0] dqs_n_o,
inout [1:0] dqs_n_pad_io,
input [1:0] rdqs_n_pad_i,
output odt_pad_o,
`endif
2842,7 → 3085,7
.bte_i(tx_fifo_dat_o[4:3]),
.cti_i(tx_fifo_dat_o[2:0]),
.init(adr_init),
.inc(adr_inc),
.inc(adr_inc | rx_fifo_we),
.adr_o(burst_adr),
.done(done),
.clk(sdram_clk_0),
2864,8 → 3107,8
ref_req <= 1'b1;
else if (ref_ack)
ref_req <= 1'b0;
 
 
`ifdef SDR_16
wire read;
reg [15:0] dq_i_reg, dq_i_tmp_reg;
2936,29 → 3179,36
 
 
`ifdef DDR_16
wire read, write;
wire read, write;
wire [15:0] dq_hi_reg, dq_lo_reg;
wire sdram_clk_180, sdram_clk_90, sdram_clk_270;
wire sdram_bufg_clk_0, sdram_bufg_clk_180, sdram_bufg_clk_90, sdram_bufg_clk_270;
reg cke_en;
reg cke, ras, cas, we, cs_n;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire sdram_clk_180, sdram_clk_90, sdram_clk_270;
wire sdram_bufg_clk_0, sdram_bufg_clk_180, sdram_bufg_clk_90, sdram_bufg_clk_270;
wire sdram_clk_ibufg;
wire ck_fb, ck_fb_bufg, ck_fb_ibufg;
reg cke_en;
reg cke, ras, cas, we, cs_n;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire [12:0] addr_o;
reg [1:0] ba;
reg [1:0] ba;
reg [12:0] addr;
wire [14:0] cke_delay_cnt;
wire dq_en, dqs_en;
wire dq_en, dqs_en;
reg [35:0] rx_fifo_dat_pipe;
reg [31:0] tx_fifo_dat_pipe;
genvar i;
wire [31:0] dq_o, dq_i;
wire ref_delay, ref_delay_ack, pre_delay, pre_delay_ack;
wire bl_en, bl_ack;
wire tx_fifo_re_i, adr_init_delay;
reg adr_init_delay_i;
genvar i;
// DDR SDRAM 16 FSM
ddr_16 ddr_16_0
(
.adr_inc(adr_inc),
.adr_inc(),
.adr_init(adr_init),
.fifo_re(tx_fifo_re),
.fifo_re(tx_fifo_re_i),
.tx_fifo_dat_o(tx_fifo_dat_o),
.burst_adr(burst_adr),
.done(done),
2969,6 → 3219,15
// refresh
.ref_req(ref_req),
.ref_ack(ref_ack),
.ref_delay(ref_delay),
.ref_delay_ack(ref_delay_ack),
.adr_init_delay(adr_init_delay),
//
.pre_delay(pre_delay),
.pre_delay_ack(pre_delay_ack),
// burst latency
.bl_en(bl_en),
.bl_ack(bl_ack),
// sdram
.dqm(dm_rdqs_o),
.a({ba_o,addr_o}),
2995,6 → 3254,33
if (cke_delay_cnt == 15'h6300)
cke_en <= 1'b1;
 
// refresh to activate/refresh delay
ref_delay_counter ref_delay_counter0
(
.cke(ref_delay),
.zq(ref_delay_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
// write recovery time
pre_delay_counter pre_delay_counter0
(
.cke(pre_delay),
.zq(pre_delay_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
// burst length
burst_length_counter burst_length_counter0
(
.cke(bl_en),
.zq(bl_ack),
.clk(sdram_clk_0),
.rst(wb_rst)
);
always @ (posedge sdram_clk_180 or posedge wb_rst)
if (wb_rst) begin
cs_n <= 1'b0;
3021,11 → 3307,11
assign we_pad_o = we;
assign ba_pad_o = ba;
assign addr_pad_o = addr;
assign cs_n_pad_o = cs_n;
assign cs_n_pad_o = cs_n;
 
 
//
defparam delay0.depth=`CL+2;
// read latency
defparam delay0.depth=`CL+`AL+2;
delay delay0
(
.d({read,tx_fifo_b_sel_i_cur}),
3034,17 → 3320,39
.rst(wb_rst)
);
//
defparam delay1.depth=3;
// write latency
defparam delay1.depth=`CL+`AL-1;
delay delay1
(
.d({write, write, write, 1'b0}),
.q({dq_en, dq_oe, dqs_en, open}),
.d({write, write, write, write}),
.q({dq_en, dq_oe, dqs_en, adr_inc}),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
// TX DCM
// if CL>4 delay read from Tx FIFO
defparam delay2.depth=`CL+`AL-4;
delay delay2
(
.d({tx_fifo_re_i, tx_fifo_re_i, 2'b00}),
.q({tx_fifo_re, adr_init_delay, open, open}),
.clk(sdram_clk_0),
.rst(wb_rst)
);
/* // if CL=4, no delay
assign tx_fifo_re = tx_fifo_re_i;
always @ (posedge sdram_clk_0 or posedge wb_rst)
if (wb_rst)
adr_init_delay_i <= 1'b0;
else
adr_init_delay_i <= tx_fifo_re_i;
assign adr_init_delay = adr_init_delay_i;*/
 
// CL=3, not supported
 
 
// DCM with internal feedback
// Remove skew from internal clock
DCM #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
3058,7 → 3366,7
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_inst (
) DCM_internal (
.CLK0(sdram_bufg_clk_0),
.CLK180(sdram_bufg_clk_180),
.CLK270(sdram_bufg_clk_270),
3072,7 → 3380,7
.PSDONE(),
.STATUS(),
.CLKFB(sdram_clk_0),
.CLKIN(sdram_clk),
.CLKIN(sdram_clk_ibufg),
.DSSEN(),
.PSCLK(),
.PSEN(),
3079,9 → 3387,44
.PSINCDEC(),
.RST(wb_rst)
);
// DCM with external feedback
// Remove skew from external clock
DCM #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(8.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_external (
.CLK0(ck_fb_bufg),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(),
.PSDONE(),
.STATUS(),
.CLKFB(ck_fb_ibufg),
.CLKIN(sdram_clk_ibufg),
.DSSEN(),
.PSCLK(),
.PSEN(),
.PSINCDEC(),
.RST(wb_rst)
);
 
// Global buffers on DCM clock outputs
// Internal feedback to DCM
// Global buffers on DCM generated clocks
BUFG BUFG_0 (
.I (sdram_bufg_clk_0),
.O (sdram_clk_0));
3094,6 → 3437,17
BUFG BUFG_270 (
.I (sdram_bufg_clk_270),
.O (sdram_clk_270));
// Internal feedback to DCM
IBUFG IBUFG_clk (
.I (sdram_clk),
.O (sdram_clk_ibufg));
// External feedback to DCM
OBUF OBUF_ck_fb (
.I (ck_fb_bufg),
.O (ck_fb));
IBUFG IBUFG_ck_fb (
.I (ck_fb_pad_i),
.O (ck_fb_ibufg));
 
// Pipeline the data path from Tx FIFO to ODDR output registers
always @ (posedge sdram_clk_0 or posedge wb_rst)
3123,6 → 3477,42
end
endgenerate
 
assign dq_pad_io = dq_oe ? dq_o : {16{1'bz}};
// Use ODDR FF to generate clock with equal delay as data
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC"))
ODDR2_inst_1
(
.Q(ck_pad_o),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(wb_rst),
.S(1'b0)
);
 
// Use ODDR FF to generate clock with equal delay as data
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC"))
ODDR2_inst_2
(
.Q(ck_n_pad_o),
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
.R(wb_rst),
.S(1'b0)
);
 
// IDDR2 (Double Data Rate Input D Flip-Flop)
generate
for (i=0; i<16; i=i+1) begin:iddr2gen
3138,9 → 3528,9
.C0(sdram_clk_270),
.C1(sdram_clk_90),
.CE(1'b1),
.D(dq_i[i]),
.D(dq_pad_io[i]),
.R(wb_rst),
.S(1'b0)
.S(1'b0)
);
end
endgenerate
3155,11 → 3545,10
assign rx_fifo_dat_i = rx_fifo_dat_pipe;
 
// Assing outputs
assign ck_pad_o = sdram_clk_270;
assign ck_n_pad_o = sdram_clk_90;
assign dqs_o = dqs_en ? {sdram_clk_270, sdram_clk_270} : 2'bz;
assign dqs_n_o = dqs_en ? {sdram_clk_90, sdram_clk_90} : 2'bz;
assign dqs_oe = dqs_en;
assign dqs_pad_io = dqs_en ? {sdram_clk_270, sdram_clk_270} : 2'bz;
assign dqs_n_pad_io = dqs_en ? {sdram_clk_90, sdram_clk_90} : 2'bz;
assign dqs_oe = dqs_en;
assign ck_fb_pad_o = ck_fb;
 
`endif // `ifdef DDR_16
 
/verilog/Makefile
37,9 → 37,21
cp cke_delay_counter_defines.v versatile_counter_defines.v
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > cke_delay_counter.v
cp ref_delay_counter_defines.v versatile_counter_defines.v
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > ref_delay_counter.v
cp pre_delay_counter_defines.v versatile_counter_defines.v
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > pre_delay_counter.v
cp latency_counter_defines.v versatile_counter_defines.v
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > latency_counter.v
cp burst_length_counter_defines.v versatile_counter_defines.v
vpp versatile_counter.v > tmp1.v
vppreproc --simple tmp1.v | cat copyright.v - > burst_length_counter.v
 
versatile_mem_ctrl:
cat versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v fifo_adr_counter.v ctrl_counter.v fifo.v fifo_fill.v inc_adr.v ref_counter.v cke_delay_counter.v sdr_16.v ddr_16.v delay.v versatile_mem_ctrl_top.v | cat copyright.v - > versatile_mem_ctrl_ip.v
cat versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v fifo_adr_counter.v ctrl_counter.v fifo.v fifo_fill.v inc_adr.v ref_counter.v cke_delay_counter.v ref_delay_counter.v pre_delay_counter.v latency_counter.v burst_length_counter.v sdr_16.v ddr_16.v delay.v versatile_mem_ctrl_top.v | cat copyright.v - > versatile_mem_ctrl_ip.v
 
all: ctrl_counter dual_port_ram fifo_adr_counter fifo_fill_fsm sdr_16 ddr_16 delay_counter versatile_mem_ctrl
 

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